WO2016166822A1

WO2016166822A1 - Transmission device, reception device, and communication system

Info

Publication number: WO2016166822A1
Application number: PCT/JP2015/061518
Authority: WO
Inventors: 文大長谷川
Original assignee: 三菱電機株式会社
Priority date: 2015-04-14
Filing date: 2015-04-14
Publication date: 2016-10-20
Also published as: JP6214822B2; JPWO2016166822A1

Abstract

A transmission device 20 according to the present invention is provided with: a data symbol generation unit 1 that generates a data symbol; an addition unit 2 that carries out addition on at least some symbols from among past symbols, which are the data symbols of a past block; a symbol insertion unit 3 that multiplexes the post-addition past symbols with the data symbol generated by the data symbol generation unit; a DFT unit 5 that converts the symbols multiplexed by the symbol insertion unit to frequency-domain data; an IDFT unit 7 that converts the frequency-domain data to time-domain data formed from a plurality of samples; a sample selection unit 8 that selects, from the time-domain data, the sample at a selection target position, and inputs said sample to the addition unit; and a transmission unit 10 that transmits a block signal including the time-domain data. The addition unit 2 adds, to at least some symbols, an adjustment amount calculated on the basis of the sample inputted from the selection unit during the generation of the block signal of the previous block.

Description

Transmitting apparatus, receiving apparatus, and communication system

The present invention relates to a transmission device, a reception device, and a communication system that perform block transmission.

In a digital communication system, transmission path frequency selectivity and time variation occur due to multipath fading caused by reflection of a transmission signal on a building or the like, and Doppler fluctuation caused by movement of a terminal. In such a multipath environment, the received signal is a signal that interferes with a transmitted symbol and a symbol that arrives after a delay time.

In such a frequency selective transmission line, a single carrier (SC) block transmission system has recently attracted attention in order to obtain the best reception characteristics (for example, see Non-Patent Document 1 below). The single carrier block transmission scheme can reduce the peak power as compared with an OFDM (Orthogonal Frequency Division Multiplexing) transmission scheme (for example, see Non-Patent Document 2 below) which is a multicarrier (MC) block transmission.

In order to suppress the transmission peak power, a transmitter that performs SC block transmission generally performs DFT (Discrete Fourier Transform) processing in a precoder.

According to the conventional SC block transmission technique, it is possible to suppress transmission peak power while reducing the influence of multipath fading. However, in SC block transmission, the phase and amplitude between the SC blocks are discontinuous, so that signal components other than the desired band, such as out-of-band spectrum or out-of-band leakage, are generated. The out-of-band spectrum becomes interference to an adjacent channel or frequency band. For this reason, out-of-band spectrum suppression is required. In general, in a communication system, a spectrum mask that is an allowable range of spectrum is determined, and it is necessary to suppress an out-of-band spectrum so as to satisfy the spectrum mask.

The present invention has been made in view of the above, and an object of the present invention is to obtain a transmitter capable of suppressing out-of-band spectrum.

In order to solve the above-described problems and achieve the object, a transmission apparatus according to the present invention includes a data symbol generation unit that generates a data symbol for each block, and a past block in the data symbol generated by the data symbol generation unit. Insertion unit that inserts past symbols, which are data symbols, and generates a multiple symbol, a time-frequency conversion unit that converts the multiple symbol into frequency domain data, and an interpolation unit that performs interpolation processing on the frequency domain data And a frequency time conversion unit for converting the data after the interpolation processing into time domain data composed of a plurality of samples. In addition, the transmission apparatus includes: an addition unit that performs addition processing on at least some of the past symbols or at least some of the samples corresponding to the past symbols of the time domain data; and time domain data A selection unit that selects a sample at a position to be selected from the selection unit and inputs the sample to the addition unit, and a transmission unit that transmits a block signal including time-domain data. The addition unit adds the adjustment amount calculated based on the sample input from the selection unit in the block signal generation process of the previous block to at least some symbols or at least some samples. And

The transmission device according to the present invention has an effect that the out-of-band spectrum can be suppressed.

1 is a diagram illustrating a configuration example of a transmission device according to a first embodiment; 1 is a diagram illustrating a configuration example of a control circuit according to a first embodiment; The figure for demonstrating the definition of the term used in Embodiment 1 The figure which shows the example of arrangement | positioning of the past symbol of Embodiment 1. The flowchart which shows an example of the production | generation procedure of CP block of Embodiment 1 The figure which shows an example of the sample position considered in the addition process of Embodiment 1 The figure which shows an example of the symbol of addition processing object The figure which shows the structural example of the transmitter concerning Embodiment 2. FIG. Flowchart illustrating an example of a CP block generation processing procedure according to the second embodiment FIG. 10 is a diagram illustrating a configuration example of a receiving apparatus according to Embodiment 3 The figure which shows the structural example of the communication system concerning Embodiment 3. FIG. Flowchart illustrating an example of a reception processing procedure according to the third embodiment

Hereinafter, a transmitter, a receiver, and a communication system according to an embodiment of the present invention will be described in detail based on the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram of a configuration example of a transmission apparatus according to the first embodiment of the present invention. The transmission apparatus 20 according to the present embodiment is a transmission apparatus that performs SC block transmission. As illustrated in FIG. 1, the data symbol generation unit 1, the addition processing unit 2, the symbol insertion unit 3, the symbol selection unit 4, the DFT ( A Discrete Fourier Transform unit 5, an oversampling processing unit 6, an IDFT (Inverse DFT) unit 7, a sample selection unit 8, a CP (Cyclic Prefix) addition unit 9, a transmission unit 10 and a storage unit 11 are provided.

The data symbol generation unit 1 generates data symbols such as a PSK (Phase Shift Keying) symbol and a QAM (Quadrature Amplitude Modulation) symbol based on the information data to be transmitted. The data symbol generator 1 generates a data symbol for each block in SC block transmission, that is, in units of blocks. Note that the data symbol generation unit 1 may use data subjected to error correction coding as information data.

The addition processing unit 2 reads a past symbol that is a data symbol of a past block, that is, a data symbol of one block before and is stored in the storage unit 11, and an adjustment value for at least a part of the read past symbol It is an addition part which performs the addition process which adds. The addition process is a process performed to suppress the out-of-band spectrum. Although the details of the addition process and the adjustment value will be described later, the addition processing unit 2 performs the adjustment calculated based on the sample input from the sample selection unit 8 in the CP block generation process described later of the previous block. The quantity is added to at least some of the above symbols.

The symbol insertion unit 3 inserts the past symbol after the addition processing by the addition processing unit 2 into the data symbol generated by the data symbol generation unit 1, and the past after the addition processing with the data symbol. Multiple symbols, which are symbols for one block in which symbols are multiplexed, are generated. The symbol selection unit 4 selects a symbol to be selected from the symbols for one block output from the symbol insertion unit 3, stores the selected symbol in the storage unit 11, and is input by the symbol insertion unit 3. The symbols for one block are input to the DFT unit 5 as they are. As will be described later, for example, the symbol selection unit 4 selects a first first number of symbols and a second second number of symbols from among the symbols multiplexed by the symbol insertion unit 3, and selects the selected symbols. Is stored in the storage unit 11. The first number is K or K1 described later, and the second number is K or K2 described later. The symbols to be selected will be described later.

The DFT unit 5 is a time-frequency conversion unit that converts symbols for one block into frequency domain data by performing DFT processing on the symbols for one block input from the symbol selection unit 4. Any component that converts a time-domain signal into a frequency-domain signal can be used instead of the DFT unit 5. For example, an FFT unit that performs FFT (Fast Discrete Fourier Transform) instead of the DFT unit 5 May be used.

The oversampling processing unit 6 is an interpolation unit that performs oversampling processing, which is a kind of interpolation processing, on the data after DFT processing. In this embodiment, the oversampling rate is L. In the present embodiment, the oversampling processing unit 6 further performs a process of converting the data after the DFT processing into a desired bandwidth. The oversampling process of the present embodiment is an interpolation process that increases the sampling rate of the time domain signal, that is, narrows the sampling interval. Specifically, for example, using the signal interpolation formula described in “B. Porat,“ A Course in Digital Signal Processing ”, John Wiley and Sons Inc., 1997” (hereinafter referred to as Porat literature), etc., Oversampling processing (processing to increase the sampling rate, that is, to narrow the sampling interval) is performed, and oversampling is performed on the input signal so that there are L sampling points per symbol. In the present embodiment, the oversampling process is performed when the oversampling rate is L, and the time domain data output from the IDFT unit 7 with respect to the input sampling rate, that is, the time domain data input to the DFT unit 5. Oversampling is performed so that the sampling rate of L becomes L times. The oversampling rate is a value indicating how many times the sampling rate after oversampling is higher than the input sampling rate. As the oversampling process, for example, a technique such as zero insertion can be used. The time domain data input to the DFT unit 5 is interpolated by inserting zeros into the data after the DFT processing, which is the frequency domain data, and performing the IDFT processing on the data after the zero insertion. L need not be an integer, but may be a real number. Further, the oversampling processing unit 6 converts the data after the DFT processing into the bandwidth, assuming that the bandwidth of the data after the DFT processing is B ₁ and the desired bandwidth is B ₂ as the processing to convert to the desired bandwidth. Convert to B ₂ data. This conversion to the desired bandwidth can be realized by inserting 0 corresponding to the difference between B ₂ and B ₁ when B ₁ <B ₂ , for example. The oversampling processing unit 6 performs the above-described interpolation processing after performing processing for conversion to a desired bandwidth.

The IDFT unit 7 performs IDFT processing on the data after oversampling processing that is frequency domain data, thereby converting the data after the oversampling processing into time domain data composed of a plurality of samples. It is a time conversion unit. Instead of the IDFT unit 7, any component that converts a time domain signal into a frequency domain signal can be used. For example, instead of the IDFT unit 7, an IFFT unit that performs IFFT (Inverse FFT) is used. May be.

The sample selection unit 8 is a selection unit that selects the sample after the IDFT processing, that is, the sample at the position to be selected from the data in the time domain, and inputs the sample to the addition processing unit 2. The sample selection unit 8 selects a sample at a position to be selected from the samples after IDFT processing and inputs the selected sample to the addition processing unit 2, and also adds all samples after IDFT processing, that is, samples for one block to the CP addition unit. Output to 9. Since the sample at the position to be selected is used by the addition processing unit 2 in the processing of the next block, the sample selection unit 8 delays the selection block by a predetermined time in accordance with the processing timing of the next block. A sample at a position may be input to the addition processing unit 2. The CP adding unit 9 adds a CP to the sample output from the sample selecting unit 8 to generate a block signal. Specifically, the CP adding unit 9 copies, that is, duplicates, the last N _CP L samples in the block and arranges them at the head of the block. N _CP is a value corresponding to the number of symbols copied in the CP addition, and L is the above-described oversampling rate. The transmission unit 10 converts the block signal, which is a signal after the addition of the CP, into a signal corresponding to the transmission path and transmits the signal. When the transmission path is a wireless transmission path, the transmission unit 10 includes an analog digital circuit that converts a digital signal into an analog signal, an antenna that transmits the analog signal as a radio wave, and the transmission path is a wired transmission path. It includes an analog / digital circuit, a circuit that performs processing of a physical layer corresponding to a wired transmission path, and the like.

Note that all the components of the transmission apparatus 20 shown in FIG. 1 can be realized by hardware. The data symbol generation unit 1 is a modem or a modulator, the DFT unit 5 and the IDFT unit 7 are electronic circuits using, for example, a flip-flop circuit, a shift register, etc., the storage unit 11 is a memory, and the transmission unit 10 It is a transmitter. Each of the addition processing unit 2, symbol insertion unit 3, symbol selection unit 4, oversampling processing unit 6, sample selection unit 8, and CP addition unit 9 can also be realized as an electronic circuit. However, some of the components shown in FIG. 1 may be configured by software. When some of the components shown in FIG. 1 are realized by software, for example, the components realized by software are realized by the control circuit 200 shown in FIG. As shown in FIG. 2, the control circuit 200 includes an input unit 201 that is a reception unit that receives data input from the outside, a processor 202, a memory 203, and an output unit 204 that is a transmission unit that transmits data to the outside. With. The input unit 201 is an interface circuit that receives data input from the outside of the control circuit 200 and applies the data to the processor 202, and the output unit 204 is an interface that transmits data from the processor 202 or the memory 203 to the outside of the control circuit 200. Circuit. When at least a part of the components shown in FIG. 1 is realized by the control circuit 200 shown in FIG. 2, the processor 202 reads a program corresponding to each component of the transmission device 20 stored in the memory 203. It is realized by executing. The memory 203 is also used as a temporary memory in each process executed by the processor 202.

Next, the operation of the present embodiment will be described. First, terms and variables used in the present embodiment are defined as follows. FIG. 3 is a diagram for explaining definitions of terms used in the present embodiment. In the present embodiment, the number of data symbols for one block generated by the data symbol generator 1 is N _D. Also, let M be the number of symbols for one block of the multiplexed symbols after the data symbol and the past symbol after the addition processing are multiplexed by the symbol insertion unit 3. The DFT unit 5 receives M symbols and outputs M frequency domain data. An input unit to the DFT unit 5, that is, one point of input data is called a symbol.

The N symbols d (bold) _k in the k-th block after the past symbol and the data symbol are multiplexed by the symbol insertion unit 3 are defined as the following equation (1). B (bold) ^T represents transposition of an arbitrary matrix B (bold).

Further, the oversampling rate of oversampling performed by the oversampling processing unit 6 is L as described above. The number of data for one block output from the oversampling processing unit 6 is NL. N is a value corresponding to the desired bandwidth B ₂ described above. The IDFT unit 7 receives NL frequency domain data and outputs NL time domain data. An output unit of the IDFT unit 7, that is, one point of data output from the IDFT unit 7 is called a sample. In addition, the entire data output from the IDFT unit 7 in one IDFT process is referred to as a block sample, and the block signal that is the entire data output from the CP adding unit 9 is referred to as a CP block. Therefore, as shown in FIG. 3, one block sample is composed of NL samples. The NL samples are obtained by interpolating N symbols output from the symbol insertion unit 3, that is, N symbols. One _CP block is composed of (N + N _CP ) L samples, that is, (N + N _CP ) L samples.

Next, the arrangement of past symbols according to the present embodiment will be described. As described above, N _CP L samples of one block sample are copied by the CP adding unit 9 and arranged at the head. Therefore, after the last sample of the previous block, the first sample of the portion copied by the CP adding unit 9 is transmitted. In order to suppress the out-of-band spectrum by suppressing the discontinuity of phase and amplitude between blocks, the phase and amplitude of the last sample of the previous block and the first sample of the copied part should be as smooth as possible. It is desirable to connect.

In the present embodiment, the first symbol of the data input to the DFT unit 5, that is, the symbol multiplexed by the symbol insertion unit 3, is defined as the first position, and the first sample copied by the CP adding unit 9 is defined as the first position. The position of the corresponding symbol is defined as the second position. The second position is the M−Xth symbol from the end among the M symbols input to the DFT unit 5. X indicates the symbol number at the position corresponding to the second position of the M symbols input to the DFT unit 5.

As described in the aforementioned Porat document, due to the cyclic nature of the IDFT output, the last sample among the block samples output from the IDFT unit 7 is the last symbol and the first symbol input to the DFT unit 5. Interpolation point between Therefore, if the first symbol of the previous block is equal to the symbol at the second position, the last sample of the previous block is between the last symbol of the previous block and the first symbol. Since it is an interpolation point, the last sample of the previous block and the first sample after CP insertion are smoothly connected. As described above, the data input to the DFT unit 5 and the data output from the IDFT unit 7 are both time domain data for one block, but are interpolated by oversampling as described above. Therefore, when L is not 1, the data points are different between the two. Therefore, when the 0th symbol of the data input to the DFT unit 5 is the first position and the Xth is the second position, the data is output from the IDFT unit 7 at the first position. The corresponding sample is the 0th sample, but when L is not 1, the sample corresponding to the second position among the data output from the IDFT unit 7 is not the Xth. Hereinafter, the head position of the NL sample output from the IDFT unit 7 is A1, and the position of the sample corresponding to the second position among the NL samples output from the IDFT unit 7 is A2.

The past symbols inserted by the symbol insertion unit 3 are, for example, the first K symbols one block before and the last K symbols. That is, when the data symbol generation unit 1 generates the data symbol of the kth block and inputs the data symbol to the symbol insertion unit 3, the symbol insertion unit 3 sets the symbol insertion unit 3 when the k−1th block is generated. an output d (bold) of the _k-1, the 2K symbols _{{d k-1, MK,} d k-1, MK + 1, ..., d k-1, M-1, d k _-1,0 , d _k-1,1 ,..., D _{k-1, K-1} } are inserted as past symbols into the input data symbol. In the present embodiment, K symbols {d _{k−1, MK} , d _{k−1, M−K + 1} ,..., D to the left of d _k−1,0 , that is, before d _k−1,0. _{k-1, M-1}} the first symbol group, d _{k-1, 0} or later K symbols _{{d k-1,0, d k} -1,1, ..., d k-1, K ₋₁ } is called a second symbol group. In the present embodiment, the past symbols {d _{k−1, MK} , d _{k−1, M−K + 1} ,..., D _k−1 so that d _k−1,0 is arranged at the second position. _{, M−1} , d _k−1,0 , d _k−1 ,..., D _{k−1, K−1} }.

By performing the oversampling process and the IDFT process, it becomes an interpolation point between the last symbol of the (k−1) th block and the leading symbol of the (k−1) th block. When past symbols are arranged such that d _k−1,0 is arranged at the second position, the symbol at the kth second position is the same as the first symbol of the k−1th block. Therefore, the first sample of the k-th block after CP insertion is the sample corresponding to the A2 sample in FIG. 3, that is, the second position, and is smoothly connected to the last sample of the (k−1) -th block. Thereby, an out-of-band spectrum can be reduced.

Next, the relationship between the first position, the second position, and the positions of A1 and A2 will be described using an example shown in FIG. As shown in FIG. 3, the N _D data symbol of the k th block generated by the data symbol generator 1 g _{k, 0,} ..., defined g _k, the _ND-1. Incidentally, g _k, ND subscript portion of _ND-1 indicates the N _D. As described above, past symbols are arranged between data symbols. For this reason, the symbol insertion unit 3 includes M data symbols, a symbol group arranged on the left side of a past symbol arranged including the second position, and a past symbol arranged including the second position. It is divided into symbols arranged on the right side. As shown in FIG. 3, let g _{k, Q} be the first symbol in the symbol group arranged on the right side of the past symbol arranged including the second position.

Here, the (m, n) component of the M × M DFT matrix W (bold) _M can be expressed by the following equation (2).

The DFT process performed by the DFT unit 5, that is, the M-point DFT process, can be expressed as the following Expression (3). s (bold) _k indicates a DFT processing result, and s (bold) _k = [s _{k, 0} ,..., s _{k, M−1} ] ^T.

When M is an even number, the frequency domain signal s (bold) _{k, Z that} has been zero-inserted up to the NL point by the oversampling process in the oversampling processing unit 6 can be expressed by the following equation (4).

As shown in the above equation (4), in the oversampling process, the (NL−N) point zero is inserted at the center, that is, between _{sk, M / 2-1} and _{sk, M / 2} . The IDFT processing by the IDFT unit 7 can be expressed by the following equation (5). B (bold) ^H indicates Hermitian transpose of the matrix B (bold).

In addition, y (bold) _k can be shown by the following formula _| equation (6).

W (bold) _{M, 1} is W (bold) is a matrix obtained by extracting a row of up to M / 2-1 line from the 0 line of _M W (bold) _{M, 2} is W (bold) _M of M / This is a matrix extracted from the second row to the M−1th row. 0 (bold) _{NL-M, M} is a matrix formed by (NL-M) × M zeros. In order to simplify the notation, a matrix A (bold) shown in the following formula (7) is defined.

The first position, the second position, A1, and A2 will be described using the above-described equations. In the k-th block, the sample of A1 is y _{k, 0} and the sample of A2 is y _{k, P} when P = NL−N _CP L. The symbol at the first position is d _{k, 0} and the symbol at the second position is d _{k, X.} Here, the value of Q will be described. The value of Q depends on M in addition to N, N _CP and L described above. In other words, the value of Q depends on the number of symbols constituting the past symbol inserted by the symbol insertion unit 3. Assuming that the number of symbols constituting the past symbol inserted by the symbol insertion unit 3 is 2K, N _D = M−2K. In the M symbols in which the past symbols are inserted by the symbol insertion unit 3, the K past symbols {d _{k−1, MK} , d _{k−1, M−K + 1} ) from the Q−1th data symbol. ,..., D _{k−1, M−1} } is the second position, that is, the Xth position. Therefore, Q = X−K. The symbol insertion unit 3 divides the data symbols into the 0th to Q−1th data symbol groups and the Qth to N _D −1th data symbol groups, and the second data symbol group is preceded by the second data symbol group. A symbol group is arranged, a first symbol group and a second symbol group are arranged after the former data symbol group, and a latter data symbol group is arranged after the second symbol group.

As described above, the second position corresponding to A2 which is the head position copied as the CP can be obtained, and the insertion position of the past symbol into the data symbol can be determined.

When M symbols inputted to the DFT unit 5 at the time of generation of the k-th CP block are d (bold) _k shown in Expression (1), 2K past symbols {d _{k−1, MK} , d _{k-1, M-K + 1} ,..., _{dk-1, M-1} , _dk-1,0 , _dk-1,1 ,..., _{dk-1, K-1} } are shown in FIG. , D _k-1,0 is arranged in the symbol of the X th position shown in FIG. _1, that is, d _{k, X} and {d _{k-1, MK} , d _{k-1, M-K + 1} _{,. , M−1} , d _k−1,0 , d _k−1 ,..., D _{k−1, K−1} } are arranged so as to be continuous. That is, as shown in the following equation (8), the past symbols {d _{k−1, MK} , d _{k−1, M−K + 1} ,..., D _{k−1, M−1} , d _{k−1, 0} , d _k-1,1 ,..., D _{k-1, K-1} } are arranged.

In the above example, the number of symbols after the second position and the number of symbols before the second position are the same. However, the number of symbols after the second position and the number of symbols before the second position are the same. May be different. In this case, past symbols are arranged as shown in the following equation (9). X indicates the second position, K1 indicates the number of symbols of the past symbols after the second position, and K2 indicates the number of symbols before the symbol immediately before the second position.

For example, when N = 32, M = 24, L = 4, and N _CP = 8, P = NL−N _CP L = (N−N _CP ) L = 24 × 4 = 96. At this time, for example, if X is 16, Q is Q = 16−K. As it can be seen from FIG. 3, for exceeds the number of symbols one past symbol is copied when the above N _CP, K is the number of symbols of one past symbol is less M-X.

When generalized, each value of K, M, N, L, and N _CP can be arbitrarily determined within a range in which the relationship shown in the following formula (10) is satisfied.

For example, when N = 32, M = 24, L = 4, and N _CP = 8, X = nMN _CP L / NL = 6n, and X is a multiple of 6, for example, any value of 6, 12, 18 May be set to For example, when N = 32, M = 24, L = 4, and N _CP = 6, X = 4.5n. In this case, X = 4n or X = 5K may be set. Alternatively, an integer value corresponding to the value of X may be obtained by calculating the value of X with X = 4.5n and performing a carry-up process or a carry-down process on the calculated X value.

FIG. 4 is a diagram illustrating an arrangement example of past symbols according to the present embodiment. In FIG. 4, N = 32, M = 24, L = 4, N _CP = 8, and K = 2. j indicates the symbol number in the N symbols after the data symbol and the past symbol are multiplexed. Actually, the past symbol after the addition process is inserted into the data symbol, but in FIG. 4, the past symbol before the addition process is virtually multiplexed with the data symbol to indicate the position of the past symbol. The arrangement is shown.

Next, the overall operation and addition of this embodiment will be described. FIG. 5 is a flowchart illustrating an example of a CP block generation processing procedure according to the present embodiment. Here, the data symbol generation unit 1 generates a data symbol (step S1). The addition processing unit 2 reads the past symbol read from the storage unit 11 using the sample selected by the sample selection unit 8 in the processing of the previous block, and sets it as the symbol to be added among the read past symbols. Addition processing is performed for the above (step S2). The past symbol read from the storage unit 11 in step S2 is the symbol stored in step S4 when the previous CP block is generated.

Here, the addition processing in the addition processing unit 2 of the present embodiment will be described using equations. Addition processing unit 2, to the following as shown in equation (11), k + 1 th block is a symbol position of the addition processed in that d (bold) _{k + 1} corresponding I _G th symbol, Addition processing for adding an adjustment value ε (bold) _{k + 1,} which will be described later, is performed. The _IG- th symbol may be one or plural. That is, the number G of elements in the set of I _G is 1 or more. As will be described later, the _IG- th symbol is, for example, a symbol that continues to the second position including the second position.

The symbols after the above addition processing are normalized so that the average power is the same as that before the adjustment. Here, the addition process in the (k + 1) th block will be described. At the time when the k + 1-th block addition process is performed, the CP block of the k-th block has already been generated. The output data from the IDFT unit 7 obtained in the process of generating the CP block of the kth block is y (bold) (hat) _k . y (bold) (hat) _k is data that has been subjected to addition processing in the process of generating the CP block of the k-th block.

FIG. 6 is a diagram illustrating an example of sample positions to be considered in the addition processing of the present embodiment. In the present embodiment, as described above, the symbols of the kth block are placed around the second position so that the samples around A2 of the (k + 1) th block are equal to the samples of A1 of the kth block. insert. Thus, the samples around A2 of the (k + 1) th block and the samples around A1 in the kth block are made equal by using the circularity of Fourier transform. When P1 and P2 are integers greater than or equal to 1, the addition processing unit 2 performs P1 + P2 samples around A2 of the (k + 1) th block represented by the following equation (12) and the kth block represented by the following equation (13): A1 so that the periphery of P1 + P2 samples equal the to determine the adjustment amount to be added to the symbol position of I _G in the k + 1 th block. In the present embodiment, as shown in FIG. 6, the P1 + P2 samples around A1 are appropriately referred to as a first sample group, and the P1 + P2 samples around A2 are appropriately referred to as a second sample group. In the samples around A1 of the k-th block shown in Equation (13), P2 samples at the end of the k-th block, which are positions consecutive to A1 by being cycled by the property of Fourier transform in a finite section Including.

Specifically, in the process of the k-th CP block, the sample selection unit 8 extracts the P1 + P2 sample shown in Expression (13) centered on A1 from the input signals and outputs the sample to the addition processing unit 2 To do.

Here, I _O is symbol position I _O corresponding to P1 + P2 samples around A2 = {NL−N _CP L−P2, NL−N _CP L−P2 + 1,..., NL−N _CP L−P1-1} To do. In the matrix A (bold) defined by the equation (7), the addition processing unit 2 defines A (bold) ′ as a matrix obtained by extracting a row corresponding to I _O and a column corresponding to I _G. The size of A (bold) ′ is (P1 + P2) × G. The error η (bold) _{k + 1 at the} block boundary can be expressed by the following equation (14).

When G> P1 + P2, the adjustment value ε (bold) _{k + 1} for correcting the above error can be expressed by the following equation (15).

When G ≦ P1 + P2, the adjustment value ε (bold) _{k + 1} for correcting the error can be expressed by the following equation (16).

In order to calculate y (bold) _{k + 1, S1} , a row corresponding to I _O is extracted from the matrix A (bold), and a (P1 + P2) × N matrix is A (bold) _SUB. _{K + 1, S1} can be calculated by the following equation (17).

The addition processing unit 2 uses the samples input from the sample selection unit 8 and the P1 + P2 symbols around A2 of the k + 1-th block for the past symbols corresponding to y (bold) _{k + 1, S1.} Η (bold) _{k + 1} is obtained by (14), ε (bold) _{k + 1} is obtained using η (bold) _{k + 1} and matrix A (bold) ′, and ε (Bold) Add _{k + 1} . Then, the past symbol after the addition processing is output to the symbol insertion unit 3. Here, although the symbol subject to addition processing is described as being in the past symbol, the symbol subject to addition processing may be other than the past symbol.

Although the symbol positions of I _G can be arbitrarily selected, it is desirable to have a large Symbol impact on the A2 surrounding the sample, also to add an adjustment in the past symbols desired. Past symbols are symbols that have been transmitted even in past CP blocks, and by performing processing together with symbols transmitted in past CP blocks on the receiving side, the influence of addition processing in demodulation can be reduced. From the above, the symbol locations of the I _G is preferably a symbol near the second position.

Symbol positions of I _G may even past the whole symbol including the second position, may be part of a position past symbol is inserted. By selecting symbols around the second position, the amount of change to be added is reduced, and changes in symbols after addition and before addition are reduced. Further, symbols around the second and first positions may be selected. In general, as the number of symbols to be added increases, the adjustment amount, that is, the addition amount decreases. The number of symbols of the position of the I _G may be changed for each block. That is, the addition process can be performed adaptively. For example, when η (bold) _{k + 1} is equal to or greater than the threshold, the number of symbols to be added is G1, and when η (bold) _{k + 1} is less than the threshold, the addition is processed. Processing such as setting the number of symbols to G2 (G2 <G1) can be performed.

Returning to the description of FIG. 5, the symbol insertion unit 3 inserts the past symbol after the addition process into the data symbol input from the data symbol generation unit 1 (step S3). Specifically, as described above, the data symbols are divided into the 0th to Q−1th data symbol groups and the Qth to N _D −1th data symbol groups, and the former data symbol group The second symbol group is arranged, the first symbol group and the second symbol group are arranged after the former data symbol group, and the latter data symbol group is arranged after the second symbol group. The value of Q is calculated in advance by the procedure described above and set in the symbol insertion unit 3. The symbol insertion unit 3 may be configured so that the value of Q can be changed by an instruction from the outside. Next, the symbol selection unit 4 stores the selected symbol among the symbols output from the symbol insertion unit 3 in the storage unit 11 (step S4). This selected symbol is a symbol that is read as a past symbol when the CP block of the next block, that is, the k + 2th block is generated, assuming that the CP block to be generated is the (k + 1) th CP block. For example, as illustrated in FIG. 4, when four past symbols are inserted around the second position, the symbol selection unit 4 includes d _{k + 1} which is the first two symbols and the last two symbols. _{, 22} , d _{k + 1,23} , d _{k + 1,0} , d _{k + 1,1} are stored in the storage unit 11. D _{k + 1,22} , d _{k + 1,23} , d _{k + 1,0} , d _{k + 1,1} stored in the storage unit 11 are read in step S2 when the k + 2nd CP block is generated. Then, addition processing is performed.

Returning to the description of FIG. 5, the DFT unit 5 performs DFT processing on the data after the past symbol insertion (step S5). Next, the oversampling processing unit 6 performs oversampling processing (step S6), and inputs the processed data to the IDFT unit 7. The IDFT unit 7 performs IDFT processing on the input data (step S7), and inputs the processing result to the sample selection unit 8. The sample selection unit 8 selects P1 + P2 samples centering on A1 among the input samples (step S8), and inputs them to the addition processing unit 2. Note that P1 + P2 samples centering on A1 are referred to as a first sample group. The selected sample is used in step S3 of the next block processing. Next, the CP adding unit 9 adds a CP (step S9). A CP block is generated by the above processing.

Here, an example of the addition processing of the present embodiment will be described. FIG. 7 is a diagram illustrating an example of symbols to be added. FIG. 7 shows an example in which N = 32, M = 24, L = 4, N _CP = 8, K = 2, P1 = 1, and P2 = 1. FIG. 7 shows the positions of symbols to be added in the arrangement after symbol multiplexing. In FIG. 7, the arrangement position where the past symbols before the addition processing are symbol-multiplexed is virtually shown. j indicates the symbol number in the N symbols after the data symbol and the past symbol are multiplexed. In this case, I ₀ = {NL−N _CP L−1, NL−N _CP L} = {95, 96}. At this time, if X = 18 and symbols around the second position are selected as symbols to be added, and the past symbol shown in the above equation (8) is used, and G = 4, I _G = {16, 17, 18, 19}. When past symbols before the addition processing are virtually multiplexed with data symbols, d (bold) d _{k + 1, IG} is expressed by the following equation (18).

In practice, d (bold) _{k + 1, IG} is added by the addition processing unit 2 and input to the DFT unit 5. When d (bold) d _{k + 1, IG} after addition processing is d (bold) (hat) _{k + 1, IG} , d (bold) (hat) _{k + 1, IG} is _expressed by the following equation (19) ).

At this time, d (bold) (hat) _{k + 1, IG} can be expressed by the following equation (20).

The above equation (11), in (20), epsilon when adding (in bold) _{k + 1,} epsilon instead of (bold) _{k + 1,} c ₁ epsilon obtained by multiplying the count c ₁ for normalized (Bold) Normalization may be performed by using _{k + 1} .

As described above, in the present embodiment, past symbols that are the first and last symbols of the previous CP block are arranged around the second position, and the P1 + P2 samples around A1 of the previous block are The addition processing unit 2a adds the adjustment amount to one or more symbols in the block so that the P1 + P2 samples in the vicinity of A2 of the block to be processed are equal. For this reason, the sample and the phase and amplitude of the previous block can be made continuous, and the out-of-band spectrum can be suppressed. Further, when there is no need to make adjustments, there is no need to calculate the adjustment amount.

Embodiment 2. FIG.
FIG. 8 is a diagram of a configuration example of the transmission apparatus according to the second embodiment of the present invention. The transmission device 20a according to the present embodiment includes the addition processing unit 2a arranged at the subsequent stage of the IDFT unit 7 instead of the addition processing unit 2 of the transmission device 20 according to the first embodiment. It is the same as the device 20. Components having the same functions as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and redundant description is omitted. The addition processing unit 2a is an addition unit that performs addition processing on at least some of the samples corresponding to the past symbols in the samples output from the IDFT unit 7.

In the present embodiment, the symbol insertion unit 3 multiplexes data symbols and past symbols that have not been subjected to addition processing. The arrangement of data symbols and fixed symbol sequences is the same as in the first embodiment. As in the first embodiment, P1 + P2 samples y (bold) _{k + 1, S1} around A2 of the ( _{k + 1} ) th block shown in the following equation (21) and the kth block shown in the following equation (22) In the sample of the (k + 1) -th block output from the IDFT unit 7 such that the samples y (bold) (hat) _{k, S0} around A1 that have been circulated in FIG. implementing the addition processing with respect to the sample position of the I _{G 'is} the sample corresponding to the symbol position of _G.

In this case, y (bold) _{k + 1, S1} is the output of the IDFT unit 7. As in the first embodiment, when the error at the block boundary shown in the following equation (23) is η (bold) _{k + 1} , the above equation (15) is satisfied when G> P1 + P2, and the case where G ≦ P1 + P2 is satisfied. Ε (bold) _{k + 1} is calculated using the above equation (16). Then, the addition processing unit 2a _assumes that A (bold) _SUB2 is an NL × G ′ matrix obtained by extracting a column corresponding to _{IG ′} in the matrix A (bold), and the signal after the addition processing is expressed by the following equation (24). Is calculated.

Note that after calculating y (bold) (hat) _{k + 1} , normalization processing may be performed so that the average power becomes equal to y (bold) _{k + 1} . In the above formula (24), epsilon instead of (bold) _{k + 1,} by using the c ₂ epsilon (bold) _{k + 1} multiplied by the count c ₂ for normalization, addition processing by normalizing May be performed.

The operations of the present embodiment other than those described above are the same as those of the first embodiment. FIG. 9 is a flowchart illustrating an example of a CP block generation processing procedure according to the present embodiment. Step S1 in FIG. 9 is the same as step S1 in the first embodiment. After step S1, step S3 is performed. However, in step S3, the symbol insertion unit 3 multiplexes the past symbol and the data symbol before the addition process. Steps S4 to S7 are the same as steps S4 to S7 in the first embodiment. After step S7, the addition processing unit 2a performs addition processing on the sample to be added using the sample selected by the sample selection unit 8 in the previous block processing (step S3a). Steps S8 and S9 after step S3a are the same as steps S8 and S9 of the first embodiment.

As described above, in the present embodiment, past symbols that are the first and last symbols of one previous CP block are arranged around the second position, and the P1 + P2 samples around A1 of the previous block and the current The adjustment amount is added to one or more samples in the block after the IDFT processing so that the P1 + P2 samples in the vicinity of A2 of the block to be processed are equal. For this reason, as in the first embodiment, the sample and the phase and amplitude of the previous block can be made continuous, and the out-of-band spectrum can be suppressed.

Embodiment 3 FIG.
FIG. 10 is a diagram of a configuration example of the receiving apparatus according to the third embodiment of the present invention. FIG. 11 is a diagram illustrating a configuration example of a communication system according to the present embodiment. A receiving device 30 illustrated in FIG. 10 is a receiving device that receives a signal from the transmitting device 20 according to the first embodiment. The communication system 50 according to the present embodiment includes a transmission device 20 and a reception device 30 as shown in FIG. Although FIG. 11 shows an example in which the transmission device 20 transmits a block signal by wireless communication, the transmission device 20 may transmit the block signal by wired communication. Note that the transmission device 20a may be used instead of the transmission device 20.

As illustrated in FIG. 10, the reception device 30 includes a reception unit 31, a CP removal unit 32, a DFT unit 33, an undersampling processing unit 34, an FDE (Frequency Domain Equalizer) 35, an IDFT unit 36, a symbol selection unit 37, and a storage unit. 38 and a demodulator 39.

If encoding is performed on the transmission side, the demodulation unit 39 may be replaced with a demodulation and decoding unit, and decoding may be performed after demodulation.

Note that all the components of the receiving device 30 shown in FIG. 10 can be realized by hardware. The receiving unit 31 is a receiver, the DFT unit 33 and the IDFT unit 36 are electronic circuits using, for example, a flip-flop circuit and a shift register, and the storage unit 38 is a memory. The demodulator 39 is a modem or a demodulator and a decoder. Each of the CP removing unit 32, the FDE 35, the undersampling processing unit 34, and the symbol selecting unit 37 can be realized as an electronic circuit. However, some of the components shown in FIG. 10 may be configured by software. When some of the components shown in FIG. 10 are realized by software, for example, the components realized by software are realized by the control circuit 200 shown in FIG. As shown in FIG. 2, the control circuit 200 includes an input unit 201 that is a reception unit that receives data input from the outside, a processor 202, a memory 203, and an output unit 204 that is a transmission unit that transmits data to the outside. With. The input unit 201 is an interface circuit that receives data input from the outside of the control circuit 200 and applies the data to the processor 202, and the output unit 204 is an interface that transmits data from the processor 202 or the memory 203 to the outside of the control circuit 200. Circuit. When at least a part of the components shown in FIG. 10 is realized by the control circuit 200 shown in FIG. 2, the processor 202 stores a program corresponding to each component of the reception device 30 stored in the memory 203. This is realized by reading and executing. The memory 203 is also used as a temporary memory in each process executed by the processor 202.

In the receiving device 30 of the present embodiment, first, when the receiving unit 31 receives a block signal, that is, a signal transmitted from the transmitting device 20 as a CP block, the CP removing unit 32 removes the CP from the received signal. Next, the DFT unit 33, which is a time-frequency conversion unit, converts the received signal in the time domain into a signal in the frequency domain by performing DFT processing on the signal after CP removal. The undersampling processing unit 34 performs undersampling processing on the signal after DFT processing. The undersampling process is a process of deleting a portion in which zero is inserted in the transmission apparatus 20 when zero insertion is performed as an oversampling process in the transmission apparatus 20.

The FDE 35 performs equalization processing in the frequency domain using the frequency domain received signal after the undersampling processing. That is, the FDE 35 is an equalization processing unit that performs an equalization process on the signal in the frequency domain after the undersampling process. The frequency domain equalization process is a process used for distortion correction in the frequency domain, and any method such as the minimum mean square error (MMSE) norm FDE may be used. 1 can be used. In FDE, the channel response is obtained in the process of distortion correction in the frequency domain.

The IDFT unit 36 that is a frequency time conversion unit converts the frequency domain signal into a time domain signal by performing IDFT processing on the frequency domain signal after FDE. The demodulation unit 39 performs demodulation based on the symbol at the position where the past symbol is arranged in the transmitter 20 in the time domain signal and the block signal received in the past, and the past symbol in the time domain signal is arranged. Demodulation is performed based on symbols at positions other than the positions.

Next, demodulation processing according to the present embodiment will be described. First, the output of the IDFT unit 36 when the signal of the k-th block is received is set to q _{k, 0} , q _{k, 1} ,..., Q _{k, M−1} . Since q _{k, 0} , q _{k, 1} ,..., q _{k, M−1} are all estimated values of information data, demodulation can be performed according to the following equation (25). Note that a portion corresponding to a symbol stored as a past symbol is a symbol that has already been demodulated, and thus may not be used for demodulation. Here, d indicates a symbol candidate, and D indicates a set of symbol candidates. For example, when the information symbol is a BPSK symbol, D = {+ 1, −1}, and when the information symbol is a QPSK symbol, D = {+ 1 + j, + 1−j, −1 + j, −1−j}.

On the other hand, the transmission apparatus described in

Embodiment

1 or 2 transmits a symbol corresponding to the past symbol twice in total. For this reason, in the transmission apparatus, the k th CP block includes the _{k 1} symbols d _k-1,0 , d _k−1,1 ,..., D _k−1 as the past symbols after the second position _{. K1} and K2 symbols d _{k-1, M-K2} , d _{k-1, M-K2 + 1} ,..., D _{k-1, M-1} up to the previous second position are stored. As shown in the following equations (26) and (27), symbols transmitted as past symbols are both a received signal corresponding to the (k−1) th block and a received signal corresponding to the kth block. Demodulation processing may be performed using.

At this time, symbols other than 0 ≦ m ≦ K1, M−K2 ≦ m ≦ M−1, X−K2 ≦ m ≦ X + K1, that is, K1 <m <X−K2, X + K1 <m <M−K2 are as follows. Demodulation processing is performed according to equation (28).

Next, the operation of this embodiment will be described. FIG. 12 is a flowchart illustrating an example of a reception processing procedure according to the present embodiment. Here, a description will be given assuming that the reception process of the kth block is performed. An example will be described in which the demodulation process is performed using the above-described equations (26) and (27). In receiving apparatus 30 of the present embodiment, CP removing unit 32 removes the CP from the signal received by receiving unit 31 (step S11). Next, the DFT unit 33, which is a time-frequency conversion unit, converts the received signal in the time domain into a signal in the frequency domain by performing DFT processing on the signal after CP removal (step S12). The undersampling processing unit 34 performs undersampling processing on the signal after DFT processing (step S13).

Next, the FDE 35 performs equalization processing in the frequency domain using the frequency domain received signal after the undersampling processing (step S14). Next, the IDFT unit 36 that is a frequency time conversion unit converts the frequency domain signal into a time domain signal by performing IDFT processing on the frequency domain signal after FDE (step S15). The symbol selection unit 37 selects a symbol to be selected from the time domain signals output from the IDFT unit 36, and stores the selected symbol in the storage unit 38 (step S16). The time domain signal output from the IDFT unit 36 is a reception signal corresponding to N symbols after the past symbol is inserted by the symbol insertion unit 3 in the transmission device 20. The past symbol is a symbol of the previous block inserted in the transmission apparatus 20. The symbol to be selected is a portion to be inserted as a past symbol in the (k + 1) th block, that is, the first and last symbols of the kth block. For example, the k-th block, as the past symbols, d _{k-1, 0} is a K1 symbols after the second _{position, d k-1,1, ...,} d k-1, K1 and second Symbol selection is made up of K2 symbols d _{k-1, M-K2} , d _{k-1, M-K2 + 1} ,..., D _{k-1, M-1} up to the previous position. part _{_{37, d k, 0, d k}} , 1, ..., d k, K1 and _{d k, M-K2, d} k, M-K2 + 1, ..., d k, M-1 and the storage section 38 To store.

Next, the demodulator 39 sets a symbol to be demodulated (step S17). The symbol to be demodulated is a symbol excluding the symbol at the position stored in the storage unit 38. Next, it is determined whether or not the symbol to be demodulated is a past symbol (step S18). If the symbol to be demodulated is a past symbol (step S18, Yes), the demodulator 39 uses the symbol of the (k-1) th block stored in the storage unit 38 and the past symbol stored in the kth block. Demodulation is performed (step S19). That is, the demodulator 39 performs demodulation processing according to the above-described equation (26).

After that, the demodulator 39 determines whether or not all symbols except the symbols at the positions stored in the storage unit 38 have been demodulated in the kth block (step S21). If it is determined that all symbols excluding symbols at positions stored in the storage unit 38 have been demodulated (Yes in step S21), the reception process for the kth block is terminated.

If it is determined that there is a symbol that has not been demodulated among all symbols excluding the symbol at the position stored in the storage unit 38 (No in step S21), the process returns to step S17, and the demodulation of the symbol to be demodulated is completed in step S17. The symbols that have not been set are set, and the processes in and after step S18 are performed.

If the symbol to be demodulated is not a past symbol (No in step S18), the demodulator 39 demodulates using the symbol stored in the kth block (step S20), and proceeds to step S21. That is, in step S20, the demodulator 39 performs demodulation processing according to the above-described equation (27).

As described above, in the present embodiment, the configuration and operation of the receiving device 30 that receives a signal transmitted from the transmitting device of the first or second embodiment has been described. When addition processing is performed on past symbols, demodulation can be performed without degrading the demodulation characteristics of the past symbols by performing demodulation using the fact that past symbols are transmitted a plurality of times. For this reason, an out-of-band spectrum can be suppressed without affecting demodulation and decoding.

The configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.

1 data symbol generation unit, 2, 2a addition processing unit, 3 symbol insertion unit, 4 symbol selection unit, 5,33 DFT unit, 6 oversampling processing unit, 7, 36 IDFT unit, 8 sample selection unit, 9 CP addition unit 10, transmission unit, 11, 38 storage unit, 20, 20a transmission device, 30 reception device, 31 reception unit, 32 CP removal unit, 34 undersampling processing unit, 35 FDE, 37 symbol selection unit, 39 demodulation unit, 50 communication system.

Claims

A data symbol generator for generating a data symbol for each block;
A symbol insertion unit that generates a multiple symbol by inserting a past symbol that is the data symbol of a past block into the data symbol generated by the data symbol generation unit;
A time-frequency converter that converts the multiple symbols into frequency-domain data;
An interpolation unit that performs interpolation processing on the frequency domain data;
A frequency time conversion unit for converting the data after the interpolation processing into time domain data composed of a plurality of samples;
An adder that performs addition processing on at least some of the past symbols, or at least some of the samples corresponding to the past symbols in the time domain data;
A selection unit that selects a sample at a position to be selected from the data in the time domain and inputs the sample to the addition unit;
A transmission unit for transmitting a block signal including data in the time domain;
With
The adding unit adds the adjustment amount calculated based on the sample input from the selection unit in the block signal generation process of the previous block to the at least some symbols or the at least some samples. A transmitter characterized by adding.
The adding unit adds the adjustment amount to the at least some symbols,
The transmission apparatus according to claim 1, wherein the symbol insertion unit inserts the past symbol after the addition process into the data symbol.
The adding unit adds the adjustment amount to the at least some samples,
The transmission apparatus according to claim 1, wherein the symbol insertion unit inserts a past symbol before the addition process into the data symbol.
A storage unit;
A symbol selection unit that selects a first number of symbols at the beginning and a second number of symbols at the end of the multiple symbols, and stores the selected symbols in the storage unit;
With
The transmission device according to claim 1, wherein the adding unit uses a symbol read from the storage unit as the past symbol.
A CP adding unit that generates a block signal by adding a cyclic prefix to the time domain data;
The symbol insertion unit arranges the past symbol after the addition processing at a position including the position of the symbol corresponding to the first sample copied as a Cyclic Prefix,
When the selection unit sets P1 and P2 to integers of 1 or more, the first P1 samples of the time domain data and the last P2 samples of the time domain data are used as a first sample group. Select and input to the adder,
The adding unit includes the first sample group selected in the block signal generation process one block before, the P1 samples after the first sample copied as the cyclic prefix of the time domain data, The adjustment amount is determined so that a second sample group composed of P2 samples before the first sample copied as a cyclic prefix is equal to a second sample group. Item 5. The transmission device according to any one of Items 1 to 4.
A receiving unit for receiving a block signal transmitted from the transmission device according to any one of claims 1 to 5;
A time-frequency converter that converts the block signal into a frequency-domain signal;
An equalization processing unit for performing an equalization process on the frequency domain signal;
A frequency time conversion unit for converting the equalized signal into a time domain signal;
In the time domain signal, demodulation is performed based on a symbol at a position where a past symbol which is a symbol of a past block is arranged in the time domain signal and the block signal received in the past. A demodulator that performs demodulation based on a symbol at a position other than the position where the past symbol is arranged;
A receiving apparatus comprising:
A transmission device according to any one of claims 1 to 5;
A receiving device according to claim 6;
A communication system comprising: