JP6400033B2 - Transmitting apparatus, receiving apparatus, and communication system - Google Patents

Description

  The present invention relates to a transmission device, a reception device, and a communication system that perform single carrier transmission.

  In a digital communication system, frequency selectivity and time fluctuation of a transmission path are generated by multipath fading caused by reflection of a transmission signal on a building or the like or Doppler fluctuation caused by movement of a terminal. In such a multipath environment, the received signal is a signal that interferes with a transmitted symbol and a symbol that arrives after a delay time.

  In order to obtain the best reception characteristics in such a frequency selective transmission line, a method of adding a CP (Cyclic Prefix) using single carrier (SC) transmission has recently attracted attention. For example, see Non-Patent Document 1 below. Single carrier transmission can reduce peak power compared to OFDM (Orthogonal Frequency Division Multiplexing) transmission which is multiple carrier (MC) block transmission.

  A transmitter that performs SC transmission performs CP insertion processing as a countermeasure against multipath fading. The CP insertion process is a process of copying a rear symbol out of a certain number of symbols and adding it to the front of the certain number of symbols. The transmitter converts a block, which is data after CP insertion processing, into a time domain waveform by filtering. In this specification, the symbol interval is T in the output of transmission processing, and the unit of T is generally seconds.

  As shown in Non-Patent Document 1 below, a receiver that receives a signal transmitted from a transmitter that performs SC transmission includes reception processing including filter processing, sampling, CP removal, and FFT (Fast Fourier Transform) processing. After performing FDE (Frequency Domain Equalization) and IFFT (Inverse FFT) processing, demodulation is performed.

David Falconer, Sirikiat Lek Ariyavisitakul, Anader Benyamin-Seeyar, Brian Eidson, “Frequency Domain Equalization for Single-Carrier Broadband Wireless Systems”, IEEE Communications Magazine, Apr. 2002, pp. 58-66.

  According to the conventional SC transmission technique, the transmission peak power is suppressed. However, in the multipath transmission line, when a delay wave having a delay time of a fractional interval exists, inter-block interference occurs, and the interference cannot be removed only by frequency equalization. For this reason, the demodulation accuracy in the receiver deteriorates. Note that the delay time of the fractional interval means a delay time that is not an integral multiple of the symbol interval T.

  The present invention has been made in view of the above, and is capable of suppressing inter-block interference and suppressing deterioration in demodulation accuracy even when a delay wave having a delay time that is not an integral multiple of the symbol interval exists. The object is to obtain a device.

In order to solve the above-described problems and achieve the object, a transmission apparatus according to the present invention includes a symbol generation unit that generates a first number of data symbols per block, and a first number of data symbols in the first number of data symbols. A symbol insertion unit that inserts a first symbol group at a position 1 and inserts a second symbol group at a second position in the first number of data symbols to output a second number of symbols; A Cyclic Prefix generation unit that duplicates the third number of symbols at the end of the second number of symbols output from the symbol insertion unit and adds it to the beginning of the second number of symbols as a Cyclic Prefix, and a Cyclic Prefix is added And a transmission processing unit that performs a filtering process using a filter that satisfies the Nyquist condition for the second number of symbols after being performed . The first symbol group is the fourth number of symbols at the beginning of the first number of data symbols one block before, and the second symbol group is the end of the first number of data symbols one block before The fifth number of symbols. In addition, the first position is a position where the first symbol group starts after the insertion of the first symbol group, and the second position is the beginning of the third number of symbols copied as a Cyclic Prefix. After the insertion of the second symbol group, the end of the second symbol group is a position one before the third number of symbols to be copied as a Cyclic Prefix.

  According to the present invention, even when there is a delayed wave having a delay time that is not an integral multiple of the symbol interval, it is possible to suppress inter-block interference and suppress deterioration in demodulation accuracy.

1 is a diagram illustrating a configuration example of a transmission device according to a first embodiment; The figure which shows an example of the continuous CP block input into the transmission process part of Embodiment 1 The figure which shows the structural example of the kth block before CP of Embodiment 1 is added. The figure which shows the structural example of CP block with which CP was added to the kth block of Embodiment 1. Diagram showing an example of a multipath transmission line The figure which shows an example of the symbol which is a symbol input from the symbol production | generation part to the symbol insertion part of Embodiment 1, and comprises a kth block The figure which shows an example of the kth block after the past symbol is inserted by the symbol insertion part of Embodiment 1. The figure which shows an example of CP block after adding CP to the block shown in FIG. The figure which shows an example of CP block at the time of adding CP, without inserting the past symbol of Embodiment 1. The figure which shows an example of CP block of Embodiment 1 The figure which shows the structural example of the circuit of Embodiment 1 implement | achieved as dedicated hardware. FIG. 3 is a diagram illustrating a configuration example of a control circuit according to the first embodiment. The figure which shows an example of CP block in case all the symbols in the block of Embodiment 2 are known signals. The figure which shows the structural example of the (k-1) th CP block in case the kth CP block is the CP block shown in FIG. The figure which shows an example of CP block comprised with the CP block comprised with the known signal of Embodiment 2, and the CP block comprised with the data symbol, and a transmission sequence FIG. 9 illustrates a configuration example of a transmitter according to a second embodiment. The figure which shows the structural example of the symbol insertion part of Embodiment 2. FIG. FIG. 10 illustrates a configuration example of a receiver that is a receiving apparatus according to Embodiment 3; The figure which shows the structural example of the circuit of Embodiment 3 implement | achieved as dedicated hardware. FIG. 5 is a diagram illustrating a configuration example of a control circuit according to a third embodiment.

  Hereinafter, a transmitter, a receiver, and a communication system according to embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram of a configuration example of a transmission apparatus according to the first embodiment of the present invention. As shown in FIG. 1, a transmitter 10 which is a transmission apparatus according to the present invention includes a symbol generation unit 1, a symbol insertion unit 2, a symbol selection unit 3, a CP generation unit 4, a transmission processing unit 5, and a storage device 6. .

In this embodiment, as will be described later, a CP is added for every N symbols. N is an integer of 2 or more. When the number of symbols to be added as a CP and N _CP, the N + N _CP symbols after the CP has been added is called a CP block. N _CP is an integer of 1 or more. Further, the CP block excluding the CP portion, that is, N symbols before CP insertion is called a block. Further, as will be described later, in the present embodiment, among N symbols in a block, N _PR symbols are past symbols, specifically, symbols of the previous block. N _PR is an integer of 2 or more.

The symbol generation unit 1 generates and outputs a symbol to be transmitted based on information to be transmitted. Specifically, the symbol generator 1 generates and outputs symbols such as PSK (Phase Shift Keying) symbols, QAM (Quadrature Amplitude Modulation) symbols, and the like. Note that the symbols generated by the symbol generator 1 are not limited to PSK symbols or QAM symbols, and may be any symbols. The symbol generator 1 may generate a symbol by modulating the encoded data. The symbol generator 1 generates (N−N _PR ) symbols per block.

The symbol insertion unit 2 _adds (N−N _PR ) symbols generated by the symbol generation unit 1 according to the control signal # 1 and the control signal # 2 to the N _PR past stored in the storage device 6. Insert symbols and output. The control signal # 1 is a control signal indicating whether or not to insert a past symbol stored in the storage device 6 into the symbol generated by the symbol generation unit 1. Control signal # 2, the control signal indicating the insertion position of the previous symbol, i.e. N _PR number stored is generated by the symbol generating unit 1 in any position of the (N-N _PR) symbols in the storage device 6 Is a control signal indicating whether to insert a past symbol. Although described in detail later insertion method of the past symbols, N ₁ symbols of the N _PR-number of past symbols are arranged continuously as the top portion to be replicated in the CP insertion, N _PR number of Of the past symbols, N ₂ symbols are arranged consecutively so that the symbol immediately before the point inserted as the CP becomes the last symbol of the N ₂ symbols.

  Here, a method of performing CP insertion using past symbols described in the present embodiment, and a method of performing CP insertion using symbols of a CP block currently being processed, which are general CP insertion methods, A configuration in which any one of them can be selected and the insertion position of a past symbol can be changed will be described. Therefore, in the configuration example shown in FIG. 1, the control signal # 1 and the control signal # 2 are used. However, when only the method of performing CP insertion using the past symbols is performed, the control signal # 1 is It is unnecessary. Also, the control signal # 2 is not necessary when the past symbol insertion position is fixed. The control signal # 1 and the control signal # 2 may be transmitted from the outside of the transmitter 10, for example, or may be transmitted from a control circuit (not shown) in the transmitter 10. For example, the control circuit refers to a plurality of values stored in a storage device (not shown), selects a value based on an external input, and generates and transmits a control signal.

The symbol selection unit 3 stores the _first N ₁ symbols of one block of symbols output from the symbol insertion unit 2 in the storage device 6 according to the control signal # 3, and the block output from the symbol insertion unit 2 The last N ₂ symbols are stored in the storage device 6. The control signal # 3 is a control signal for instructing whether or not to store a symbol in the storage device 6. Information indicating the position of the symbol stored in the storage device 6 may be included in the control signal # 3. The symbols stored in the storage device 6 are used as past symbols in the symbol insertion process of the next block in the symbol insertion unit 2. Further, the symbol selection unit 3 outputs one block of symbols output from the symbol insertion unit 2 to the CP generation unit 4.

  In the present embodiment, it is possible to select whether or not to store symbols in the storage device 6 by the control signal # 3. If it is not possible to select whether or not to store the symbol in the storage device 6, the control signal # 3 is unnecessary. It is assumed that the position of the symbol stored in the storage device 6 is determined in advance. However, if the control signal # 3 includes information indicating the position of the symbol stored in the storage device 6, the storage device is controlled by the control signal # 3. 6 can designate the position of the symbol to be stored. Similarly to the control signal # 1 and the control signal # 2, the control signal # 3 may be transmitted from the outside of the transmitter 10, or may be transmitted from a control circuit (not shown) in the transmitter 10, for example. .

The CP generator 4 duplicates the last N _CP symbols of one block output from the symbol selector 3, and outputs one block output from the symbol selector 3 as the copied N _CP symbols as CP. Add to the beginning of the symbol.

  The transmission processing unit 5 performs transmission processing on the CP blocks sequentially output from the CP generation unit 4, that is, the blocks after the CP is added, generates a transmission signal, and transmits the transmission signal. The transmission processing unit 5 performs transmission processing on the CP blocks sequentially output from the CP generation unit 4, not on the CP block basis, but on continuous CP blocks. FIG. 2 is a diagram illustrating an example of continuous CP blocks input to the transmission processing unit 5. As shown in FIG. 2, CP blocks are successively input from the CP generation unit 4 such as k−1 th CP block, k th CP block, k + 1 th CP block,. k is an integer of 1 or more.

  The transmission signal transmitted by the transmission processing unit 5 may be a wireless signal or a transmission signal transmitted via a wired line. The transmission processing performed by the transmission processing unit 5 includes, for example, filter processing, digital / analog conversion processing, frequency conversion processing, and the like.

  As the filter processing performed by the transmission processing unit 5, a filter that satisfies the Nyquist condition can be used for the transmission and reception filters. The filter processing is expressed using a convolution process in the mathematical expression as described in “Yoichi Saito,“ Modulation and Demodulation of Digital Wireless Communication ”, IEICE, 2007” (hereinafter referred to as Reference Document 1). Can do. In the transmission processing of the transmission processing unit 5, “J. B. Anderson, F. Rusek and V. Owall,“ Faster-Than-Nyquist Signaling ”, Proceedings of the IEEE, vol. 101, No. 8, Aug. 2013, pp. 1817-1830. ”FtN (Faster than Nyquist) processing may be performed.

Next, CP addition and symbol insertion according to the present embodiment will be described. FIG. 3 is a diagram illustrating a configuration example of the kth block before the CP is added. FIG. 4 is a diagram illustrating a configuration example of a CP block in which a CP is added to the kth block. 3 and 4 show examples in which N = 8 and N _CP = 3. D _{a, b} represents the b-th symbol of the a-th block input to the CP generation unit 4. a and b are integers of 0 or more. In the example shown in FIG. 3, the k-th block is composed of 8 symbols from D _{k, 0} to D _{k, 7} . As shown in FIG. 4, the last three symbols shown in FIG. 3 are duplicated and placed at the beginning of the block as a CP.

  Intersymbol interference can be suppressed by using a filter that satisfies the Nyquist condition for the transmission and reception filters. However, when the symbol interval (also referred to as symbol time) is T, there is a fractional interval delay wave, that is, a delay wave having a delay time that is a non-integer multiple of the symbol interval, such as 1.3T or 3.9T. Even if a transmission / reception filter that satisfies the Nyquist condition is used, intersymbol interference occurs.

FIG. 5 is a diagram illustrating an example of a multipath transmission path. In FIG. 5, the transmission signal is assumed to be an impulse signal. In the example of FIG. 5, the signal transmitted at the timing indicated by the arrow in the left diagram of FIG. 5 is received as one preceding wave and three delayed waves on the receiving side. Of the delay waves, the first delay wave received is delayed by a delay time T _{1 with} respect to the preceding wave, and the second delay wave received is delayed by a delay time T _{2 with} respect to the preceding wave. The delayed wave received third is delayed by a delay time T _{3 with} respect to the preceding wave. For example, assuming an environment in which at least one of the delayed waves arrives at a fractional interval such as delay time T ₁ = 1.3T or T ₃ = 3.9T, Nyquist is applied to the transmission and reception filters. Even if a filter satisfying the condition is used, intersymbol interference exists. For this reason, inter-block interference also occurs, leading to degradation of demodulation and decoding accuracy on the receiving side.

Transmitter 10 of the present embodiment inserts past symbols into a block currently being processed so that interblock interference can be suppressed even when there are fractional delay waves. Specifically, the transmitter 10 copies the first symbol group, which is the first N ₁ symbols of the block immediately before the block currently being processed, as the CP of the block currently being processed. Is placed at the beginning of the first symbol group. In addition, the transmitter 10 uses the second symbol group, which is the last N ₂ symbols of the previous block, as the second symbol group that is duplicated as the CP of the block currently being processed. The second symbol group is arranged so as to be the last symbol of the symbol group.

FIG. 6 is a diagram illustrating an example of symbols that are input from the symbol generation unit 1 to the symbol insertion unit 2 and constitute the k-th block. FIG. 7 is a diagram illustrating an example of the kth block after past symbols are inserted by the symbol insertion unit 2. Further, d _{a, b} indicates a b-th symbol among (N−N _PR ) symbols constituting the a-th block input from the symbol generation unit 1 to the symbol insertion unit 2. In FIGS. 6 and 7, N = 8, N _CP = 3, N ₁ = 1, and N ₂ = 2. A portion indicated by a dotted line in FIG. 6 does not exist at the stage of input from the symbol generation unit 1 and indicates a portion where a past symbol is inserted by the symbol insertion unit 2 at the subsequent stage. Therefore, in practice, the symbol insertion unit 2 receives (N−N _PR ) = 5 symbols per block from the symbol generation unit 1. For example, five symbols from d _{k, 0} to d _{k, 4} are input to the symbol insertion unit 2 as symbols corresponding to the kth block.

In the case of the example shown in FIGS. 6 and 7, the first symbol group, which is the first N ₁ symbols of the previous block, is used as the first position where the first symbol group is copied as the first CP. In order to insert between (N−N _PR ) symbols input from the symbol generator 1, among (N−N _PR ) symbols input from the symbol generator 1, The first symbol group may be inserted before the (N−N _CP −N ₂ ) th symbol. In addition, the second symbol group, which is the N ₂ symbols at the end of the previous block, is set to be the last symbol of the second symbol group, with the symbol immediately before the portion duplicated as the CP. In order to arrange the second symbol group, after the (N−N _CP −N ₂ −1) -th symbol among the (N−N _PR ) symbols input from the symbol generator 1, the second symbol group is arranged. The symbol group may be inserted.

Therefore, for example, the symbol insertion unit 2 converts (N−N _PR ) pieces received from the symbol generation unit 1 from the 0th to the (N−N _CP −N ₂ −1) th (N−N _CP −). N ₂ ) symbols and (N _CP −N ₂ ) th to (N _CP −N ₁ ) symbols from the end to the end, and the second symbol group and the second symbol group are divided between the former and the latter. One symbol group may be inserted. In the example of FIGS. 6 and 7, since N ₁ = 1, in the process of generating the kth block, the first symbol group is the first symbol d _{k− at} the head of the k−1th block. _1,0 . In the example of FIGS. 6 and 7, since N ₂ = 2, in the process of generating the kth block, the second symbol group is the last two symbols d _{k-1 of the k−} 1th block. _{, 3} , d _k-1,4 . Since N−N _CP −N ₂ = 8−3−2 = 3, in the examples of FIGS. 6 and 7, d _k, which is the third symbol among the five symbols corresponding to the k th block _. D _k-1,0 is inserted before ₃ and N ₁ = 1 first symbol group after d _{k, 2} which is the second symbol, that is, d _k−1,3 , d _{k−1. 4} is inserted.

In the uppermost part of FIG. 7, the symbols obtained by renumbering the symbols constituting the block after the past symbol is inserted by the symbol insertion unit 2 in order from the top are shown as D _{a, b} . . _{Da, b} in FIGS. 2, 3 and 4 is the same as _{Da, b} shown in FIG.

FIG. 8 is a diagram illustrating an example of a CP block after a CP is added to the block illustrated in FIG. As shown in FIG. 8, N _CP symbols at the end of the block shown in FIG. 7 are duplicated and added as CP at the beginning. For example, in the kth block, d _k−1,0 , d _{k, 3} , d _{k, 4} are duplicated and added to the head as CP.

  Here, the principle and effect of the present invention will be described. CP is added to remove inter-block interference, and by adding CP, equalization processing on the receiving side can be simplified. In order to suppress inter-block interference using the CP, it is necessary to maintain cyclicity between the CP and the portion that is the copy source of the CP. However, when interference from adjacent symbols occurs in an environment where there is a delay wave with a fractional interval as described above, the method of simply copying and adding the last symbol in the block becomes the copy source of CP and CP. The interference component from the adjacent symbol is different from each other. For this reason, the cyclicity is not maintained between the CP and the portion from which the CP is copied, and inter-block interference occurs. When inter-block interference occurs, interference removal becomes insufficient only by equalization processing in the frequency domain on the receiving side, and demodulation accuracy deteriorates.

FIG. 9 is a diagram illustrating an example of a CP block when a CP is added without inserting a past symbol. FIG. 10 is a diagram illustrating an example of a CP block according to the present embodiment. 9 and 10, N = 8 and N _CP = 3. Further, in the example of FIG. 10, N ₁ = 1 and N ₂ = 2 are set as in the example of FIG. In the example of FIG. 9 in which past symbols are not inserted, there is a possibility that interference from d _k−1,7 and interference from d _{k, 6} leak into d _{k, 5} which is the head of the k th CP block. There is. As described above, each symbol may be influenced by interference of adjacent symbols from both sides. In FIGS. 9 and 10, interference from the front side, that is, the left side is illustrated by arrows. On the other hand, there is a possibility that the interference from d _{k, 4} and the interference from d _{k, 6} may leak into d _{k, 5} at the position where the CP is copied. As described above, since the symbol serving as an interference source differs between the CP and the portion from which the CP is copied, cyclicity is not guaranteed between the CP and the portion from which the CP is copied.

On the other hand, as shown in FIG. 10, in the present embodiment in which a past symbol is inserted and a CP is added, d _k−1,0 which is the head of the k th CP block starts from d _k−1,4. Interference and interference from d _{k, 3} may leak. In addition, interference from d _k-1,4 and interference from d _{k, 3} can also leak into the leading d _k-1,0 of the portion of the k th CP block from which the CP was copied. There is sex. As described above, in the present embodiment, since the symbols serving as interference sources are the same between the CP and the portion from which the CP is copied, the cycle between the CP and the portion from which the CP is copied is cyclic. Guarantee is guaranteed. Therefore, equalization processing can be performed by frequency domain equalization on the receiving side.

In the above example, it is assumed that interference leaks from adjacent symbols, but in reality, interference leaks not only from adjacent symbols but also from a plurality of symbols. In such a case, by increasing N ₁ and N ₂ , the influence of interference from a plurality of symbols can be made the same between the CP and the portion from which the CP is copied.

When the N symbols D _{k, b} in the k-th block numbered in order with the block head after the past symbol insertion by the symbol insertion unit 2 being 0th are used, the past symbol insertion by the symbol insertion unit 2 Can be expressed by the following equations (1) and (2). However, 1 ≦ i ≦ N ₁ and 1 ≦ j ≦ N ₂ .

For 0 ≦ b ≦ (N−N _CP −N ₂ −1), D _{k, b} = d _{k, b} , and for N−N _CP + N ₁ ≦ b ≦ (N−1), c = When b−N _PR , D _{k, b} = d _{k, c} .

Therefore, when the position of the symbol to be stored in the storage device 6 is specified by the control signal # 3, information indicating that the _first N ₁ symbols and the last N ₂ symbols are stored is the control signal # 3. Should be included. Further, in the control signal # 2, the first N ₁ symbols of the previous block stored in the storage device 6 are input from the symbol generator 1 (N−N _PR ) symbols. Among them, the instruction to insert before the (N−N _CP −N ₂ ) th symbol is given, and the N ₂ symbols at the end of the previous block are input from the symbol generator 1 (N−N _PR The information indicating insertion is included after the (N−N _CP −N ₂ −1) -th symbol among the number of symbols).

As described above, in the present embodiment, when the first number is (N−N _PR ) and the second number is N, the symbol generator 1 has the first number of data symbols per block. Is generated. Then, the symbol insertion unit 2 inserts the first symbol group at the first position in the first number of data symbols, and the second symbol group at the second position in the first number of data symbols. To output a second number of symbols. When the third number is used, the CP generation unit 4 duplicates the third number of symbols at the end of the second number of symbols output from the symbol insertion unit 2 and uses the second number as a Cyclic Prefix. Append to the beginning of the number of symbols. Assuming that the fourth number is N ₁ and the fifth number is N ₂ , as described above, the first symbol group is the fourth number at the beginning of the first number of data symbols one block before. The second symbol group is a fifth number of symbols at the end of the first number of data symbols one block before. In addition, the first position is a position where the first symbol group starts after the insertion of the first symbol group, and the second position is the beginning of the third number of symbols copied as a Cyclic Prefix. After the insertion of the second symbol group, the end of the second symbol group is a position one before the third number of symbols to be copied as a Cyclic Prefix.

  Next, the hardware configuration of the transmitter 10 of the present embodiment will be described. Of the components constituting the transmitter 10 shown in FIG. 1, the storage device 6 is realized by a memory. Each component constituting the transmitter 10 shown in FIG. 1 other than the storage device 6 is configured by a circuit. Each component constituting the transmitter 10 shown in FIG. 1 other than the storage device 6 may be realized as a dedicated circuit, or may be realized as a circuit using a processor.

  When each component configuring the transmitter 10 illustrated in FIG. 1 is realized as a dedicated circuit, each component is, for example, the circuit illustrated in FIG. 11. FIG. 11 is a diagram illustrating a configuration example of a circuit implemented as dedicated hardware. As illustrated in FIG. 11, the circuit 100 includes an input unit 101 that is a receiving unit that receives data input from the outside, a processing circuit 102, a memory 103, and a transmission processing unit that is a transmitter that transmits data to the outside. 104. The input unit 101 is an interface circuit that receives data input from the outside and applies the data to the processing circuit, and the transmission processing unit 104 is an interface circuit that transmits data from the processing circuit or the memory to the outside. In this case, the processing circuit is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination thereof. is there.

  When some of the components shown in FIG. 1 are realized by software, these components are realized by a control circuit shown in FIG. 12, for example. FIG. 12 is a diagram illustrating a configuration example of the control circuit 200. As shown in FIG. 12, the control circuit 200 includes an input unit 201 that is a receiver that receives data input from the outside, a processor 202, a memory 203, and an output unit 204 that is a transmitter that transmits data to the outside. With. The input unit 201 is an interface circuit that receives data input from the outside of the control circuit 200 and gives the data to the processor, and the output unit 204 is an interface circuit that transmits data from the processor 202 or the memory 203 to the outside of the control circuit. is there. The components realized by software among the components shown in FIG. 1 are realized by the processor 202 reading out and executing a program stored in the memory 203 and corresponding to each component realized by software. The The memory 202 is also used as a temporary memory in each process executed by the processor 202.

  The processor 202 is a CPU (Central Processing Unit, central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, processor, DSP (Digital Signal Processor)) or the like. The memory 203 is, for example, non-volatile or volatile, such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), etc. A semiconductor memory, a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, a DVD (Digital Versatile Disk), and the like are applicable.

As described above, the transmitter 10 according to the present embodiment uses the first symbol group, which is the first N ₁ symbols of the block immediately before the block currently being processed, as the CP of the block currently being processed. Are arranged so that the portion to be copied becomes the head of the first symbol group. In addition, the transmitter 10 of the present embodiment is one previous to the point where the second symbol group, which is the N ₂ symbols at the end of the previous block, is duplicated as the CP of the block currently being processed. The second symbol group is arranged so that this symbol becomes the last symbol of the second symbol group. For this reason, even when there is a delayed wave having a delay time that is not an integral multiple of the symbol interval, it is possible to suppress interblock interference and suppress degradation in demodulation accuracy.

Embodiment 2. FIG.
Next, as a second embodiment according to the present invention, a method of generating a CP block including a known signal, that is, a predetermined sequence of known symbols will be described. The known signal is generally used for channel estimation and block synchronization or frame synchronization. As the known signal, any predetermined signal can be used. When all the symbols in the block are known signals, the symbol of the last known signal in the block may be copied and added to the head as a CP. FIG. 13 is a diagram illustrating an example of a CP block when all symbols in the block are known signals. FIG. 13 is an example of N = 8 and N _CP = 3, and illustrates an example in which eight symbols from p _{k, 0} to p _{k, 7} are generated as known signals in the k-th block.

  After the CP block composed of known signals, a CP block composed of data symbols, that is, symbols generated by the symbol generator 1, or a CP block composed of known signals can be transmitted. Even when the CP block following the CP block is composed of data symbols, since the previous CP block is a known signal, a known signal is inserted as a past symbol. In this case, when the CP block following the CP block constituted by the known signal is a data symbol, the CP block generation method of the data symbol is that the content of the symbol of the previous CP block is a known signal. Other than the above, the second embodiment is the same as the first embodiment.

On the other hand, in the block immediately before the CP block composed of known signals, the symbol of the previous block is arranged as in the first embodiment, and one of the known signals is further added to the beginning and end of the block. Parts are arranged. FIG. 14 is a diagram illustrating a configuration example of the (k−1) th CP block when the kth CP block is the CP block illustrated in FIG. 13. In the example of FIG. 14, N = 8, N _CP = 3, N ₁ = 1, and N ₂ = 2, and, as in the first embodiment, the previous block at the beginning of the portion copied as CP, The (k-2) th _first N ₁ symbols are arranged. Further, N ₂ symbols at the end of the (k−2) -th block are arranged before the N ₁ symbols. Furthermore, in the present embodiment, p _{k, 5} is inserted at the beginning of the block, and p _{k, 3} , p _{k, 4} are arranged at the end of the block. That is, N ₁ known signal symbols starting from the portion copied as CP in the known signal block shown in FIG. 13 are arranged at the beginning of the (k−1) th block, and are shown in FIG. In the known signal block, N ₂ known signal symbols ending with one portion before the portion copied as CP are arranged at the end of the (k−1) th block. Thereby, in the (k−1) -th block and the k-th block shown in FIG. 13 which is the next block, it is possible to maintain the cyclicity between the CP and the portion copied as the CP.

In this case, the number of data symbols in the (k−1) th CP block is N−2N _PR . Accordingly, in the example of FIG. 14, the number of symbols in the (k−1) -th block generated by the symbol generator 1 is 8−6 = 2.

  FIG. 15 is a diagram illustrating an example of a CP block composed of known signals, a CP block composed of data symbols, and a transmission sequence. In the example of FIG. 15, the kth CP block is a CP block composed of data symbols. Specifically, since the next CP block is a CP block of a known signal, it is a CP block having the same configuration as in FIG. 14 (however, (k−1) in FIG. 14 is replaced with k).

  FIG. 16 is a diagram illustrating a configuration example of the transmitter 10a according to the present embodiment. The transmitter 10a according to the present embodiment adds the known signal generation unit 7 to the transmitter 10 according to the first embodiment, and includes the symbol insertion unit 2a instead of the symbol insertion unit 2 in the transmission according to the first embodiment. It is the same as the machine. Components having the same functions as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and redundant description is omitted.

  The known signal generation unit 7 which is a known symbol generation unit generates a known signal, that is, a known symbol, and outputs it to the symbol insertion unit 2a. The symbol insertion unit 2a outputs a past symbol stored in the storage device 6 or a known signal output from the known signal generation unit 7 from the symbol generation unit 1 in accordance with the control signal # 4 and the control signal # 5. Insert into symbol. The control signal # 4 is a signal indicating whether or not to output the known signal as it is, and whether or not a part of the known signal is inserted at the end and the top of the block as described above. The case of outputting the known signal as it is is the case of generating the CP block as shown in FIG. Control signal # 5 is a control signal indicating the past symbol insertion position, as is control signal # 2 in the first embodiment. The control signal # 4 and the control signal # 5 are generated according to the transmission sequence of the CP block as illustrated in FIG. For example, the control signal # 4 and the control signal # 5 may be transmitted from the outside of the transmitter 10a, or may be transmitted from a control circuit (not shown) in the transmitter 10a.

  FIG. 17 is a diagram illustrating a configuration example of the symbol insertion unit 2a according to the present embodiment. As shown in FIG. 17, the symbol insertion unit 2 a includes a selection device 31 and a symbol insertion processing unit 32. The selection device 31 receives a known signal and a past symbol read from the storage device 6. When the selection device 31 outputs the known signal as it is according to the control signal # 4, the selection device 31 outputs the known signal together with information indicating that the known signal is output as it is to the symbol insertion processing unit 32. In this case, the symbol insertion processing unit 32 outputs the known signal as it is. When a part of the known signal is added to the end and the head in accordance with the control signal # 4, the selection device 31 outputs the corresponding known signal and information indicating the insertion location to the symbol insertion processing unit 32. Further, the selection device 31 does not output anything to the symbol insertion processing unit 32 when no known signal is inserted in accordance with the control signal # 4. The symbol insertion processing unit 32 inserts past symbols into the symbols input from the symbol generation unit 1 according to the control signal # 5, similarly to the symbol insertion unit 2 of the first embodiment. Further, the symbol insertion processing unit 32 inserts a known signal in accordance with an instruction from the selection device 31.

As described above, the transmitter 10a according to the present embodiment includes a known symbol generation unit that generates a known symbol. Cyclic Prefix generator 4, duplicates the third number i.e. N _CP symbols of the last block consists of known symbols is added to the head of the block composed of a known symbol as Cyclic Prefix. The second number one block before the block composed of known symbols, that is, the fourth number at the beginning of N symbols, that is, N ₁ symbols, is copied as a cyclic prefix of the block composed of known symbols. N ₁ known symbols at the beginning of the position. The fifth number at the end of the N symbols one block before the block composed of known symbols, that is, N ₂ symbols, is a known symbol at a position to be duplicated as a cyclic prefix of a block composed of known symbols. N ₂ known symbols at the end.

  The hardware configuration of the transmitter 10a is the same as the hardware configuration of the transmitter 10 according to the first embodiment, and each component configuring the transmitter 10a is dedicated hardware. The circuit 100 illustrated in FIG. Or realized by the control circuit 200 shown in FIG.

  As described above, when transmitting a known signal, the transmitter 10a according to the present embodiment can maintain the past between the CP and the portion copied as the CP as in the first embodiment. Symbols and known signals are arranged. For this reason, when using a known signal, the same effect as Embodiment 1 can be produced.

Embodiment 3 FIG.
FIG. 18 is a diagram illustrating a configuration example of the receiver 20 which is the receiving apparatus according to the third embodiment of the present invention. As illustrated in FIG. 18, the receiver 20 includes a reception processing unit 21, a CP removal unit 22, a DFT unit 23, an FDE 24, an IDFT unit 25, a demodulation unit 26, and a transmission path estimation unit 27. The reception processing unit 21 performs reception processing such as frequency conversion, sampling processing, and reception filter processing. The receiver 20 of the present embodiment constitutes a communication system together with the transmitter 10 of the first embodiment or the transmitter 10a of the second embodiment, and the transmitter 10 of the first embodiment or the transmitter of the second embodiment. The signal transmitted from 10a is received.

  CP removing unit 22 removes the CP from the received signal. A DFT (Discrete Fourier Transform) unit 23 is a time-frequency conversion processing unit that converts the received signal after CP removal into a frequency domain signal by DFT and outputs it. An FDE (Frequency Domain Equalizer) 24 performs equalization processing in the frequency domain on the frequency domain signal output from the DFT unit 23 using the transmission path estimation value output from the transmission path estimation unit 27. That is, the FDE 24 is an equalization processing unit that performs equalization processing on the frequency domain signal using the result of transmission path estimation on the frequency domain signal. The equalization processing in the FDE 24 is described in Non-Patent Document 1 or “JAC Bingham,“ Multicarrier Modulation for Data Transmission: An Idea Whose Time Has Come ”, IEEE Commun. Mag., Vol. 28, No. 5, A general FDE including the method described in “May 1990, pp. 5-14” can be used.

  The transmission path estimation unit 27 performs transmission path estimation based on the received signal after CP removal, and outputs the transmission path estimation value to the FDE 24. The transmission path estimation can be performed using any general method. For example, the transmission path may be estimated using a known signal. For example, a transmission path estimation method described in Non-Patent Document 1 may be used. Further, the output of the DFT unit may be used to perform transmission path estimation using a known signal in the frequency domain.

  An IDFT (Inverse DFT) unit 25 is a frequency time conversion processing unit that converts a signal after equalization processing by the FDE 24 into a time domain signal by IDFT and outputs the signal. The demodulator 26 demodulates the signal output from the IDFT unit 25. Further, when the symbol is encoded in the transmitter 1 or the transmitter 1a, the demodulation unit 26 may perform error correction decoding after demodulation. The demodulator 26 may also demodulate the signal of the previous block included in each block in the demodulation process of each block. That is, the demodulator 26 determines a symbol (previous block) of a signal corresponding to a symbol one block previous in the time domain signal (past symbol) and a time domain signal based on a received signal corresponding to one block previous. The signal may be demodulated using a signal corresponding to a symbol other than (symbol). Alternatively, the demodulation unit 26 does not need to perform demodulation because the signal of the previous block is a symbol demodulated in the processing of the previous block.

  When the demodulation unit 26 also demodulates the signal of the previous block included in each block in the demodulation process of each block, that is, when performing demodulation again, the average as shown below is improved so as to improve the demodulation characteristics. Demodulation may be performed.

Let r _{k, m} be the m-th signal of the k-th block output from the IDFT unit 25. The k-th block output from the IDFT unit 25 is composed of N signals corresponding to N symbols. These N signals are r _{k, 0} ,..., R _{k, N−1} . Let G be a candidate for the transmitted information symbol. For example, when the transmitted symbol is a QPSK symbol, G can be expressed by the following equation (3).

Therefore, the demodulation unit 26 can perform demodulation using the following equation (4). Note that N _D = N−N _PR , and d _{a, b} (hat) indicates an estimated value of d _{a, b} .

  The control signal R indicates whether the above demodulation is performed again, or the demodulation is not performed again, that is, whether the symbol of the previous block is not demodulated. The instruction by the control signal R may not be given, and it may be fixedly determined whether the demodulation is performed again or not. The control signal R may be transmitted from the outside of the receiver 20, or may be transmitted from a control circuit (not shown) in the receiver 20, for example.

  Next, the hardware configuration of the receiver 20 of the present embodiment will be described. Each component configuring the receiver 20 illustrated in FIG. 18 is configured by a circuit. Each component constituting the receiver 20 shown in FIG. 18 may be realized as a dedicated circuit, or may be realized as a circuit using a processor.

  When each component configuring the receiver 20 illustrated in FIG. 18 is realized as a dedicated circuit, each component is, for example, the circuit illustrated in FIG. FIG. 19 is a diagram illustrating a configuration example of a circuit implemented as dedicated hardware. As illustrated in FIG. 19, the circuit 300 includes an input unit 301 that is a receiving unit that receives data input from the outside, a processing circuit 302, a memory 303, and a transmission processing unit that is a transmitter that transmits data to the outside. 304. The input unit 301 is an interface circuit that receives data input from the outside and applies the data to the processing circuit. The transmission processing unit 304 is an interface circuit that transmits data from the processing circuit 302 or the memory 303 to the outside. In this case, the processing circuit 302 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof.

  When some of the components of the receiver 20 shown in FIG. 18 are realized by software, these components are realized by, for example, the control circuit shown in FIG. FIG. 20 is a diagram illustrating a configuration example of the control circuit 400. As shown in FIG. 20, the control circuit 400 includes an input unit 401 that is a receiver that receives data input from the outside, a processor 402, a memory 403, and an output unit 404 that is a transmitter that transmits data to the outside. With. The input unit 401 is an interface circuit that receives data input from the outside of the control circuit 400 and applies the data to the processor 402. The output unit 404 is an interface circuit that transmits data from the processor 402 or the memory 403 to the outside of the control circuit. It is. Among the components of the receiver 20 shown in FIG. 18, the components realized by software read and execute the program corresponding to each component realized by software stored in the memory 403 by the processor 402. Is realized. The memory 402 is also used as a temporary memory in each process performed by the processor.

  The processor 402 is a CPU or the like. The memory 403 corresponds to, for example, a nonvolatile or volatile semiconductor memory such as a RAM, a flash memory, an EPROM, and an EEPROM, a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, and a DVD.

  As described above, the receiver 20 of the present embodiment can receive and demodulate the signal transmitted from the transmitter of the first embodiment or the second embodiment. In the transmitter of the first embodiment or the second embodiment, since the past symbols are inserted so as to suppress the inter-block interference as described above, the receiver 20 of the present embodiment has high accuracy. Demodulation can be performed.

  The configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.

  DESCRIPTION OF SYMBOLS 1 Symbol production | generation part, 2 and 2a Symbol insertion part, 3 Symbol selection part, 4 CP production | generation part, 5 Transmission process part, 6 Storage device, 7 Known signal production | generation part 10, 10a Transmitter, 20 Receiver, 21 Reception process Part, 22 CP removal part, 23 DFT part, 24 FDE, 25 IDFT part, 26 demodulation part, 27 transmission path estimation part.

Claims (4)

A symbol generator for generating a first number of data symbols per block;
A first symbol group is inserted at a first position in the first number of data symbols, and a second symbol group is inserted at a second position in the first number of data symbols. A symbol insertion unit that outputs a number of symbols;
A Cyclic Prefix generation unit that duplicates a third number of symbols at the end of the second number of symbols output from the symbol insertion unit, and adds the third number of symbols as a Cyclic Prefix to the beginning of the second number of symbols;
A transmission processing unit that performs a filtering process using a filter that satisfies a Nyquist condition for the second number of symbols after the Cyclic Prefix is added;
With
The first symbol group is a fourth number of symbols at the beginning of the first number of data symbols one block before, and the second symbol group is the first number of data symbols one block before A fifth number of symbols at the end of the data symbol,
The first position is a position where, after the insertion of the first symbol group, the head of the first symbol group is the head of the third number of symbols copied as the Cyclic Prefix. The position of 2 is a position where after the insertion of the second symbol group, the end of the second symbol group is one before the third number of symbols copied as the Cyclic Prefix. A transmitting device. A symbol generator for generating a first number of data symbols per block;
A first symbol group is inserted at a first position in the first number of data symbols, and a second symbol group is inserted at a second position in the first number of data symbols. A symbol insertion unit that outputs a number of symbols;
A Cyclic Prefix generation unit that duplicates a third number of symbols at the end of the second number of symbols output from the symbol insertion unit, and adds the third number of symbols as a Cyclic Prefix to the beginning of the second number of symbols;
A known symbol generation unit that generates a known symbol that is a predetermined symbol ; a transmission processing unit that performs a filtering process on the second number of symbols after the cyclic prefix is added;
With
The first symbol group is a fourth number of symbols at the beginning of the first number of data symbols one block before, and the second symbol group is the first number of data symbols one block before A fifth number of symbols at the end of the data symbol,
The first position is a position where, after the insertion of the first symbol group, the head of the first symbol group is the head of the third number of symbols copied as the Cyclic Prefix. The position of 2 is a position where after the insertion of the second symbol group, the end of the second symbol group is one before the third number of symbols copied as the Cyclic Prefix,
The Cyclic Prefix generation unit duplicates the third number of symbols at the end of the block composed of the known symbols and adds it as a Cyclic Prefix to the head of the block composed of the known symbols,
The fourth number of symbols at the head of the second number of symbols one block before the block composed of the known symbols is copied at the position to be duplicated as the cyclic prefix of the block composed of the known symbols. The fourth number of known symbols at the beginning, and the fifth number of symbols at the end of the second number of symbols one block before the block composed of the known symbols are composed of the known symbols send device you characterized in that said known symbols of said fifth number of the known symbol location to be replicated and tail as Cyclic Prefix of a block. A reception device that receives a signal transmitted from the transmission device according to claim 1 or 2 and includes a signal including a symbol one block before in a block as a reception signal,
A CP removing unit for removing a cyclic prefix from the received signal;
A time-frequency conversion processing unit that converts the received signal after removal of the Cyclic Prefix into a frequency domain signal;
A transmission path estimation unit that performs transmission path estimation on the received signal after the removal of the Cyclic Prefix;
An equalization processing unit that performs an equalization process on the frequency domain signal using the result of the transmission path estimation on the frequency domain signal;
A frequency time conversion processing unit for converting the equalized signal into a time domain signal;
A signal corresponding to the symbol one block before of the time domain signal, and a signal corresponding to a symbol other than the symbol one block before of the time domain signal based on the received signal corresponding to one block before A demodulator to demodulate using,
A receiving apparatus comprising: The transmission device according to claim 1 or 2,
A receiving device for receiving a signal transmitted from the transmitting device;
A communication system comprising:

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