JP2017157947A - Transmission device, reception device and communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmission device capable of suppressing deterioration of demodulation accuracy by suppressing block interference even if a delay wave of a delay time which is not an integer multiple of a symbol interval exists.SOLUTION: A transmission device comprises: a symbol generation section 1 which generates a symbol; a symbol arrangement section 3 which arranges a first symbol in such a manner that a first position and a second position within a block come to the head, arranges a second symbol group in such a manner that a third position and a fourth position within the block come to the end, and outputs the symbol groups as the block; and a CP generation section 4 by which Npieces of symbols at the end of the block are duplicated and added to the head. The first position is the head of the block, and the second position is a position to be the head of a portion that is duplicated as CP within the block. The third position is the end of the block, and the fourth position is a position which is the one before the second position.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a transmission device, a reception device, and a communication system that perform single carrier transmission.

  In a digital communication system, frequency selectivity and time fluctuation of a transmission path are generated by multipath fading caused by reflection of a transmission signal on a building or the like or Doppler fluctuation caused by movement of a terminal. In such a multipath environment, the received signal is a signal in which a transmission symbol interferes with a symbol that arrives after a delay time.

  In order to obtain the best reception characteristics in such a frequency selective transmission line, a method of adding a CP (Cyclic Prefix) using single carrier (SC) transmission has recently attracted attention. For the method of adding a CP using SC transmission, see, for example, Non-Patent Document 1 below. Single carrier transmission can reduce peak power compared to OFDM (Orthogonal Frequency Division Multiplexing) transmission which is multiple carrier (MC) block transmission.

  A transmitter that performs SC transmission performs CP insertion processing as a countermeasure against multipath fading. The CP insertion process is a process of copying a rear symbol out of a certain number of symbols and adding it to the front of the certain number of symbols. The transmitter converts a block, which is data after CP insertion processing, into a time domain waveform by filtering. In this specification, the symbol interval is T in the output of transmission processing, and the unit of T is generally seconds.

  As shown in Non-Patent Document 1 below, a receiver that receives a signal transmitted from a transmitter that performs SC transmission includes reception processing including filter processing, sampling, CP removal, and FFT (Fast Fourier Transform) processing. After performing FDE (Frequency Domain Equalization) and IFFT (Inverse FFT) processing, demodulation is performed.

David Falconer, Sirikiat Lek Ariyavisitakul, Anader Benyamin-Seeyar, Brian Eidson, “Frequency Domain Equalization for Single-Carrier Broadband Wireless Systems”, IEEE Communications Magazine, Apr. 2002, pp. 58-66.

  According to the conventional SC transmission technique, the transmission peak power is suppressed. However, in the multipath transmission line, when a delay wave having a delay time of a fractional interval exists, inter-block interference occurs, and the interference cannot be removed only by frequency equalization. For this reason, the demodulation accuracy in the receiver deteriorates. Note that the delay time of the fractional interval means a delay time that is not an integral multiple of the symbol interval T.

  The present invention has been made in view of the above, and is capable of suppressing inter-block interference and suppressing deterioration in demodulation accuracy even when a delay wave having a delay time that is not an integral multiple of the symbol interval exists. The object is to obtain a device.

  In order to solve the above-described problems and achieve the object, a transmission apparatus according to the present invention includes a data symbol generation unit that generates a first number of data symbols, and a first position and a second position in a block. Are arranged in two places so that the first symbol group is the head of the first symbol group that is a predetermined symbol group, and the third position and the fourth position in the block are respectively determined in advance. The second symbol group is arranged at two places so as to be the end of the second symbol group, which is the selected symbol group, and is located at a position other than the position where the first symbol group and the second symbol group are arranged. A symbol arrangement unit that generates and outputs a block in which a first number of data symbols are arranged, and copies a second number of symbols at the end of the block that is output from the symbol arrangement unit, , A Cyclic Prefix generator to be added to the beginning of the block Te comprises a. The first position is the beginning of the block, the second position is the position that is the beginning of the second number of symbols that are copied as the cyclic prefix in the block, and the third position is the end of the block. And the fourth position is a position immediately before the second position.

  According to the present invention, even when there is a delayed wave having a delay time that is not an integral multiple of the symbol interval, it is possible to suppress inter-block interference and suppress deterioration in demodulation accuracy.

1 is a diagram illustrating a configuration example of a transmission device according to a first embodiment; The figure which shows an example of the continuous CP block input into the transmission process part of Embodiment 1 The figure which shows the structural example of the kth block before CP of Embodiment 1 is added. The figure which shows the structural example of CP block with which CP was added to the kth block of Embodiment 1. Diagram showing an example of a multipath transmission line The figure which shows an example of the symbol which is a symbol input from the data symbol production | generation part to the symbol arrangement | positioning part of Embodiment 1, and comprises a kth block The figure which shows an example of the kth block after a fixed symbol series is arrange | positioned by the symbol arrangement | positioning part of Embodiment 1. FIG. The figure which shows an example of CP block after adding CP to the block shown in FIG. The figure which shows an example of CP block at the time of adding CP, without inserting the fixed symbol series of Embodiment 1 The figure which shows an example of CP block of Embodiment 1 The figure which shows the structural example of the circuit of Embodiment 1 implement | achieved as dedicated hardware. FIG. 3 is a diagram illustrating a configuration example of a control circuit according to the first embodiment. The figure which shows an example of CP block containing the known signal when not using a fixed symbol series The figure which shows an example of CP block containing the known signal of Embodiment 2 The figure which shows an example of CP block and transmission sequence which are comprised of CP block and the data symbol containing the known signal of Embodiment 2 FIG. 5 is a diagram illustrating a configuration example of a transmitter according to a second embodiment. FIG. 10 illustrates a configuration example of a receiver that is a receiving apparatus according to Embodiment 3; The figure which shows the structural example of the circuit of Embodiment 3 implement | achieved as dedicated hardware. FIG. 5 is a diagram illustrating a configuration example of a control circuit according to a third embodiment.

  Hereinafter, a transmitter, a receiver, and a communication system according to embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram of a configuration example of a transmission apparatus according to the first embodiment of the present invention. As shown in FIG. 1, a transmitter 10 that is a transmission apparatus according to the present invention includes a data symbol generation unit 1, a fixed sequence generation unit 2, a symbol arrangement unit 3, a CP generation unit 4, and a transmission processing unit 5.

In the present embodiment, transmitter 10 adds a CP for every N symbols, as will be described later. N is an integer of 2 or more. When the number of symbols to be added as a CP and N _CP, the N + N _CP symbols after the CP has been added is called a CP block. N _CP is an integer of 1 or more. Further, the CP block excluding the CP portion, that is, N symbols before CP insertion is called a block. As will be described later, in the present embodiment, 2N _PD symbols out of N symbols in the block are fixed symbol sequences, that is, fixed symbol sequences. _NPD is an integer of 2 or more. The transmitter 10 performs the same process for all blocks.

The data symbol generator 1 generates and outputs a symbol to be transmitted based on information to be transmitted. Specifically, the data symbol generation unit 1 generates and outputs symbols such as PSK (Phase Shift Keying) symbols, QAM (Quadrature Amplitude Modulation) symbols, and the like. Note that the symbols generated by the data symbol generator 1 are not limited to PSK symbols and QAM symbols, and may be any symbols. The data symbol generation unit 1 may generate symbols by modulating the encoded data. The data symbol generation unit 1 generates (N-2N _PD ) symbols per block.

Fixed sequence generation unit 2 generates a fixed symbol sequence is N _PD symbols predetermined outputs to the symbol arrangement unit 3. Any symbol series may be used as the fixed symbol series, and some may be 0, that is, zero symbols, or all may be zero symbols.

In accordance with the control signal # 1, the symbol arrangement unit 3 adds (N−2N _PD ) symbols generated by the data symbol generation unit 1 to 2 N _PD fixed symbols output from the fixed sequence generation unit 2 respectively. Insert it at each location and output it to the CP generator 4. The control signal # 1 is a control signal indicating whether or not to insert a fixed symbol sequence into the symbol generated by the data symbol generation unit 1, and indicating an insertion position when the fixed symbol sequence is inserted. The details of the method of inserting the fixed symbol sequence will be described later, but N ₁ symbols out of the N _PD fixed symbols are continuously arranged starting from the portion to be duplicated in CP insertion. Further, the N ₁ symbols are also arranged at the head of the block. In addition, the N ₂ symbols at the end of the N _PD fixed symbols are continuously arranged so that the symbol immediately before the portion inserted as the CP becomes the last symbol of the N ₂ symbols. . Further, the N ₂ symbols are also arranged at the end of the block.

  Here, it is possible to select one of a method for performing CP insertion including a fixed symbol sequence described in the present embodiment and a method for performing CP insertion without using a general fixed symbol sequence, A configuration in which the insertion position of the fixed symbol sequence can also be changed will be described. For this reason, the control signal # 1 is used in the configuration example shown in FIG. 1, but only the method of performing CP insertion using a fixed symbol sequence is performed, and the insertion position of the fixed symbol sequence is fixed. Does not require the control signal # 1. The control signal # 1 may be transmitted from the outside of the transmitter 10, for example, or may be transmitted from a control circuit (not shown) in the transmitter 10. For example, the control circuit refers to a plurality of values stored in a storage device (not shown), selects a value based on an external input, and generates and transmits a control signal.

The CP generation unit 4 copies or duplicates the last N _CP symbols of one block of symbols output from the symbol arrangement unit 3, and outputs the duplicated N _CP symbols as CPs from the symbol arrangement unit 3. It is added to the beginning of a block of symbols.

  The transmission processing unit 5 performs transmission processing on the CP blocks sequentially output from the CP generation unit 4, that is, the blocks after the CP is added, generates a transmission signal, and transmits the transmission signal. The transmission processing unit 5 performs transmission processing on the CP blocks sequentially output from the CP generation unit 4, not on the CP block basis, but on continuous CP blocks. FIG. 2 is a diagram illustrating an example of continuous CP blocks input to the transmission processing unit 5. As shown in FIG. 2, CP blocks are successively input from the CP generation unit 4 such as k−1 th CP block, k th CP block, k + 1 th CP block,. k is an integer of 1 or more.

  The transmission signal transmitted by the transmission processing unit 5 may be a wireless signal or a signal transmitted through a wired line. The transmission processing performed by the transmission processing unit 5 includes, for example, filter processing, digital / analog conversion processing, frequency conversion processing, and the like.

  As the filter processing performed by the transmission processing unit 5, a filter that satisfies the Nyquist condition can be used for the transmission and reception filters. The filter processing is expressed using a convolution processing in the mathematical expression as described in “Yoichi Saito,“ Modulation and Demodulation of Digital Wireless Communication ”, IEICE, 2007” (hereinafter referred to as Reference Document 1). Can do. In the transmission processing of the transmission processing unit 5, “J. B. Anderson, F. Rusek and V. Owall,“ Faster-Than-Nyquist Signaling ”, Proceedings of the IEEE, vol. 101, No. 8, Aug. 2013, pp. 1817-1830. ”FtN (Faster than Nyquist) processing may be performed.

Next, CP addition and symbol insertion according to the present embodiment will be described. FIG. 3 is a diagram illustrating a configuration example of the kth block before the CP is added. FIG. 4 is a diagram illustrating a configuration example of a CP block in which a CP is added to the kth block. 3 and 4 show examples in which N = 8 and N _CP = 3. D _{a, b} represents the b-th symbol of the a-th block input to the CP generation unit 4. a and b are integers of 0 or more. In the example shown in FIG. 3, the k-th block is composed of 8 symbols from D _{k, 0} to D _{k, 7} . As shown in FIG. 4, the last three symbols shown in FIG. 3 are duplicated and placed at the beginning of the block as a CP.

  Intersymbol interference can be suppressed by using a filter that satisfies the Nyquist condition for the transmission and reception filters. However, when the symbol interval (also referred to as symbol time) is T, there is a fractional interval delay wave, that is, a delay wave having a delay time that is a non-integer multiple of the symbol interval, such as 1.3T or 3.9T. Even if a transmission / reception filter that satisfies the Nyquist condition is used, intersymbol interference occurs.

FIG. 5 is a diagram illustrating an example of a multipath transmission path. In FIG. 5, the transmission signal is assumed to be an impulse signal. In the example of FIG. 5, the signal transmitted at the timing indicated by the arrow in the left diagram of FIG. 5 is received as one preceding wave and three delayed waves on the receiving side. Of the delay waves, the first delay wave received is delayed by a delay time T _{1 with} respect to the preceding wave, and the second delay wave received is delayed by a delay time T _{2 with} respect to the preceding wave. The delayed wave received third is delayed by a delay time T _{3 with} respect to the preceding wave. For example, assuming an environment in which at least one of a plurality of delay waves arrives at a fractional interval, such as delay time T ₁ = 1.3T or T ₃ = 3.9T, a transmission filter and reception Even if a filter that satisfies the Nyquist condition is used as the filter, intersymbol interference exists. For this reason, inter-block interference also occurs, leading to degradation of demodulation and decoding accuracy on the receiving side.

Transmitter 10 of the present embodiment inserts a fixed symbol sequence into a block so that interblock interference can be suppressed even when there are fractional delay waves. Specifically, the transmitter 10 arranges the first symbol group, which is N ₁ symbols in the fixed symbol series, so that the portion to be duplicated as the CP of the block is the head of the first symbol group. To do. Furthermore, the transmitter 10 arranges the first symbol group so that the head of the first symbol group is the head of the block. In addition, the transmitter 10 uses the first symbol group, which is N ₁ symbols in the fixed symbol series, as the last symbol of the second symbol group, the symbol immediately before the portion copied as the CP. Thus, the second symbol group is arranged. Further, the transmitter 10 arranges the second symbol group such that the end of the second symbol group is the end of the block. Thus, in the present embodiment, the first symbol group and the second symbol group are arranged in two places each.

FIG. 6 is a diagram illustrating an example of symbols that are input from the data symbol generation unit 1 to the symbol arrangement unit 3 and that constitute the k-th block. FIG. 7 is a diagram illustrating an example of the k-th block after the fixed symbol series is arranged by the symbol arrangement unit 3. Incidentally, N _PD-number of the fixed symbol sequence composed of a fixed symbol _{f -N2, f -N2 + 1,} ..., f -1, f 0, f 1, ..., and f _N1-1. In _subscripts such as f-N2, N1 and N2 represent N ₁ and N ₂ , respectively. _{f -N2, f -N2 + 1,} ..., f -1, f 0, f 1, ..., N 1 pieces of fixed symbols from f ₀ of f _N1-1 to f _N1-1, i.e., f _- The N ₁ fixed symbols on the right when the fixed symbol sequence is divided between ₁ and f ₀ are set as the first symbol group. _{f -N2, f -N2 + 1,} ..., f -1, f 0, f 1, ..., N 2 pieces of fixed symbols from f _{-N @ 2} to f _-1 of f _N1-1, i.e. f _-1 N ₂ fixed symbols on the left side when the fixed symbol series is divided between f and f ₀ are set as a second symbol group. It is assumed that N _PD ≦ N _CP is satisfied.

Further, d _{a, b} indicates the b-th symbol among the (N−2N _PD ) symbols constituting the a-th block input from the data symbol generation unit 1 to the symbol arrangement unit 3. In FIGS. 6 and 7, N = 8, N _CP = 3, N ₁ = 1, and N ₂ = 2. In FIG. 6, a portion indicated by a dotted line does not exist at the stage of input from the data symbol generation unit 1, and indicates a portion where a fixed symbol sequence is inserted by the subsequent symbol placement unit 3. Therefore, actually, (N−2N _PD ) = 2 symbols per block are input to the symbol placement unit 3 from the data symbol generation unit 1. For example, two symbols d _{k, 0} and d _{k, 1} are input to the symbol placement unit 3 as symbols corresponding to the kth block.

First, the symbol arrangement unit 3 arranges the first symbol group at the head of the block and the second symbol group at the end of the block. Further, in the block, the first symbol group is arranged so that the position of the beginning of the portion to be duplicated as CP is the beginning of the first symbol group, and one of the beginning of the portion to be duplicated as CP The second symbol group is arranged so that the previous symbol is the end of the second symbol group. A data symbol that is a symbol generated by the data symbol generator 1 is arranged after the first symbol group arranged at the head. In the example of FIG. 7, since N _PD = N _CP , no data symbol is arranged in the portion duplicated as CP. In the case of N _PD <N _CP, a data symbol is also arranged after the first symbol group of the portion duplicated as CP.

In the example of FIGS. 6 and 7, the symbol placement unit 3 places the first symbol group f ₀ at the beginning of the block and the beginning of the portion copied as the CP. The symbol placement unit 3 places the second symbol group f ₋₂ and f ₋₁ immediately before the end of the block and the portion copied as the CP. Then, data symbols d _{k, 0} and d _{k, 1} are arranged after f ₀ which is the first symbol group at the head of the block.

In FIG. 2, FIG. 3, and FIG. 4, the symbols constituting the block after the fixed symbol sequence is arranged by the symbol arrangement unit 3 shown in FIG. _{Da, b} .

FIG. 8 is a diagram illustrating an example of a CP block after a CP is added to the block illustrated in FIG. As shown in FIG. 8, the N _CP symbols at the end of the block shown in FIG. 7 are duplicated and added as a CP to the beginning of the block. In the example shown in FIG. 7, f ₀ , f ₋₂ , and f ₋₁ are duplicated and added to the head of the block as a CP.

  Here, the principle and effect of the present invention will be described. CP is added to remove inter-block interference, and by adding CP, equalization processing on the receiving side can be simplified. In order to suppress inter-block interference using the CP, it is necessary to maintain cyclicity between the CP and the portion that is the copy source of the CP. However, when interference from adjacent symbols occurs in an environment where there is a delay wave with a fractional interval as described above, the method of simply copying and adding the last symbol in the block becomes the copy source of CP and CP. The interference component from the adjacent symbol is different from each other. For this reason, the cyclicity is not maintained between the CP and the portion from which the CP is copied, and inter-block interference occurs. When inter-block interference occurs, interference removal becomes insufficient only by equalization processing in the frequency domain on the receiving side, and demodulation accuracy deteriorates.

FIG. 9 is a diagram illustrating an example of a CP block when a CP is added without using a fixed symbol sequence. FIG. 10 is a diagram illustrating an example of a CP block according to the present embodiment. 9 and 10, N = 8 and N _CP = 3. Further, in the example of FIG. 10, N ₁ = 1 and N ₂ = 2 are set as in the example of FIG. In the example of FIG. 9 in which no fixed symbol sequence is used, there is a possibility that interference from d _k−1,7 and interference from d _{k, 6} may leak into d _{k, 5} which is the head of the k th CP block. There is. In this way, each symbol may be affected by interference of adjacent symbols from both sides. 9 and 10, interference from the front side of time, that is, the left side in the figure is indicated by arrows. On the other hand, there is a possibility that the interference from d _{k, 4} and the interference from d _{k, 6} may leak into d _{k, 5} at the position where the CP is copied. As described above, since the symbol serving as an interference source differs between the CP and the portion from which the CP is copied, cyclicity is not guaranteed between the CP and the portion from which the CP is copied.

On the other hand, as shown in FIG. 10, in the present embodiment in which a CP is added using a fixed symbol sequence, f ₀ which is the head of the k-th CP block has interference from f _{−1 and} from f ₋₂ . Interference may leak. Further, interference from f ₋₁ and interference from f ₋₂ may also leak into the leading f ₀ of the portion that is the copy source of the CP of the k th CP block. As described above, in the present embodiment, since the symbols serving as interference sources are the same between the CP and the portion from which the CP is copied, the cycle between the CP and the portion from which the CP is copied is cyclic. Guarantee is guaranteed. Therefore, equalization processing can be performed by frequency domain equalization on the receiving side.

In the above example, it is assumed that interference leaks from adjacent symbols, but in reality, interference leaks not only from adjacent symbols but also from a plurality of symbols. In such a case, by increasing N ₁ and N ₂ , the influence of interference from a plurality of symbols can be made the same between the CP and the portion from which the CP is copied.

When N symbols D _{k, b} in the k-th block numbered in order with the head of the block after the fixed symbol series is arranged by the symbol arrangement unit 3 as 0th, fixed symbols by the symbol arrangement unit 3 are used. The arrangement of the series can be shown as the following formulas (1) and (2). However, 1 ≦ i ≦ N ₁ and 1 ≦ j ≦ N ₂ .

Further, data symbols are arranged in N ₁ ≦ b ≦ (N−N _CP −N ₂ −1). In the case of N _PD <N _CP , data symbols are also arranged in N−N _CP + N ₁ ≦ b ≦ (N−N ₂ −1).

  Therefore, the symbol placement unit 3 may instruct the control signal # 1 to place the fixed symbol series at the above position.

As described above, in the present embodiment, data symbol generator 1 generates the first number of data symbols per block. The first number is (N-2N _PD ). Then, the symbol placement unit 3 places the first symbol group in two places so that the first position and the second position in the block are respectively the heads of the first symbol group that is a predetermined symbol group. To place. In addition, the symbol placement unit 3 places the first symbol group in two places so that the first position and the second position in the block are at the head of the first symbol group, which is a predetermined symbol group. To place. In addition, the symbol placement unit 3 places the second symbol group in two places so that the third position and the fourth position in the block are the end of the second symbol group, which is a predetermined symbol group. And a block in which the first number of data symbols is arranged at a position other than the position where the first symbol group and the second symbol group are arranged is generated and output. The first position is the beginning of the block, the second position is the position that is the beginning of the second number of symbols that are copied as the cyclic prefix in the block, and the third position is the end of the block. And the fourth position is a position immediately before the second position. Further, the CP generation unit 4 duplicates N _CP symbols that are the second number at the end of the block output from the symbol arrangement unit 3 and adds them as a Cyclic Prefix to the head of the block.

  Next, the hardware configuration of the transmitter 10 of the present embodiment will be described. Each component configuring the transmitter 10 illustrated in FIG. 1 is configured by a circuit. Each component constituting the transmitter 10 shown in FIG. 1 may be realized as a dedicated circuit, or may be realized as a circuit using a processor.

  When each component configuring the transmitter 10 illustrated in FIG. 1 is realized as a dedicated circuit, each component is, for example, the circuit illustrated in FIG. 11. FIG. 11 is a diagram illustrating a configuration example of a circuit implemented as dedicated hardware. As shown in FIG. 11, a circuit 100 includes an input unit 101 that is a receiver that receives data input from the outside, a processing circuit 102, a memory 103, and a transmission processing circuit that is a transmitter that transmits data to the outside. 104. The input unit 101 is an interface circuit that receives data input from the outside and applies the data to the processing circuit 102, and the transmission processing circuit 104 is an interface circuit that transmits data from the processing circuit 102 or the memory 103 to the outside. In this case, the processing circuit 102 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination thereof. It is.

  When some of the components shown in FIG. 1 are realized by software, these components are realized by a control circuit shown in FIG. 12, for example. FIG. 12 is a diagram illustrating a configuration example of the control circuit 200. As shown in FIG. 12, the control circuit 200 includes an input unit 201 that is a receiver that receives data input from the outside, a processor 202, a memory 203, and an output unit 204 that is a transmitter that transmits data to the outside. With. The input unit 201 is an interface circuit that receives data input from the outside of the control circuit 200 and gives the data to the processor, and the output unit 204 is an interface circuit that transmits data from the processor 202 or the memory 203 to the outside of the control circuit 200. It is. The components realized by software among the components shown in FIG. 1 are realized by the processor 202 reading out and executing a program stored in the memory 203 and corresponding to each component realized by software. The The memory 203 is also used as a temporary memory in each process executed by the processor 202.

  The processor 202 is a CPU (Central Processing Unit, central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, processor, DSP (Digital Signal Processor)) or the like. The memory 203 is, for example, non-volatile or volatile, such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), etc. A semiconductor memory, a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, a DVD (Digital Versatile Disk), and the like are applicable.

As described above, the transmitter 10 according to the present embodiment arranges the fixed symbol sequence including the beginning of the portion to be duplicated as the CP, and further places the N ₂ symbols on the left side of the fixed symbol sequence at the end of the block. And N ₁ symbols on the right side of the fixed symbol series are arranged at the head of the block. For this reason, even when there is a delayed wave having a delay time that is not an integral multiple of the symbol interval, it is possible to suppress interblock interference and suppress degradation in demodulation accuracy.

Embodiment 2. FIG.
Next, as a second embodiment of the present invention, a CP block generation method including a known signal, that is, a known symbol sequence will be described. The known signal is generally used for channel estimation and block synchronization or frame synchronization. As the known signal, any predetermined signal can be used. When all the symbols in the block are known signals, the symbol of the last known signal in the block may be copied and added to the head as a CP. FIG. 13 is a diagram illustrating an example of a CP block when all symbols in a block are known signals when no fixed symbol sequence is arranged. FIG. 13 is an example of N = 8 and N _CP = 3, and illustrates an example in which eight symbols from p _{k, 0} to p _{k, 7} are generated as known signals in the k-th block.

  FIG. 13 shows an example in which a fixed symbol sequence is not inserted. In this embodiment, a fixed symbol sequence is also applied to a CP block including a known signal, as in the case of the data symbols described in the first embodiment. Is placed. FIG. 14 is a diagram illustrating an example of a CP block including a known signal according to the present embodiment. As shown in FIG. 14, in the CP block of the present embodiment including a known signal, a part of the known signal is arranged at the same position as the data symbol of the first embodiment, and a fixed symbol sequence Are arranged at the same position as in the first embodiment. The data symbol transmission method in the present embodiment is the same as that in the first embodiment.

  FIG. 15 is a diagram illustrating an example of a transmission sequence of a CP block including a known signal and a CP block including data symbols. In the example of FIG. 15, the kth CP block and the k + 2nd CP block are CP blocks composed of data symbols.

  FIG. 16 is a diagram illustrating a configuration example of the transmitter 10a according to the present embodiment. The transmitter 10a according to the present embodiment adds the known signal generation unit 6 to the transmitter 10 according to the first embodiment, and includes the symbol arrangement unit 3a instead of the symbol arrangement unit 3. It is the same as the machine. Components having the same functions as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and redundant description is omitted.

  The known signal generation unit 6 that is a known symbol generation unit generates a known signal, that is, a known symbol that is a predetermined symbol, and outputs it to the symbol arrangement unit 3a. Symbol placement unit 3a inserts a fixed symbol output from fixed sequence generation unit 2 or a known signal output from known signal generation unit 6 into a symbol output from data symbol generation unit 1 according to control signal # 2. To do. The control signal # 2 is a signal indicating information indicating whether to select a data symbol or a known signal and an insertion position of a fixed symbol sequence. The control signal # 2 is generated according to the CP block transmission sequence illustrated in FIG. The control signal “2” may be transmitted from the outside of the transmitter 10a, or may be transmitted from a control circuit (not shown) in the transmitter 10a, for example.

  That is, the symbol placement unit 3a according to the present embodiment allows the first symbol and the second position in the block to be at the head of the first symbol group that is a predetermined symbol group. Place the group in two places. In addition, the symbol arrangement unit 3a places the first symbol group in two places so that the first position and the second position in the block are at the head of the first symbol group, which is a predetermined symbol group. To place. In addition, the symbol arrangement unit 3a places the second symbol group in two places so that the third position and the fourth position in the block are the end of the second symbol group which is a predetermined symbol group. And a block in which a first number of known symbols are arranged at a position other than the position where the first symbol group and the second symbol group are arranged is generated and output as a known symbol block. The CP generation unit 4 duplicates the second number of symbols at the end of the known symbol block output from the symbol arrangement unit 3a as in the first embodiment, and adds it as a CP to the beginning of the known symbol block.

  As described above, the transmitter 10a according to the present embodiment includes the known signal generation unit 6 that generates known symbols. The symbol arrangement unit 3a arranges fixed symbol sequences for CP blocks including known signals as in the first embodiment.

  The hardware configuration of the transmitter 10a is the same as the hardware configuration of the transmitter 10 according to the first embodiment, and each component configuring the transmitter 10a is dedicated hardware. The circuit 100 illustrated in FIG. Or realized by the control circuit 200 shown in FIG.

  As described above, when transmitting a known signal, transmitter 10a according to the present embodiment maintains cyclicity between CP and a portion copied as CP as in the first embodiment. The fixed symbol series is arranged in the above. For this reason, when using a known signal, the same effect as Embodiment 1 can be produced.

Embodiment 3 FIG.
FIG. 17 is a diagram illustrating a configuration example of the receiver 20 which is the receiving apparatus according to the third embodiment of the present invention. As illustrated in FIG. 17, the receiver 20 includes a reception processing unit 21, a CP removal unit 22, a DFT unit 23, an FDE 24, an IDFT unit 25, a fixed sequence removal unit 26, a demodulation unit 27, and a transmission path estimation unit 28. The reception processing unit 21 performs reception processing such as frequency conversion, sampling processing, and reception filter processing. The receiver 20 of the present embodiment constitutes a communication system together with the transmitter 10 of the first embodiment or the transmitter 10a of the second embodiment, and the transmitter 10 of the first embodiment or the transmitter of the second embodiment. The signal transmitted from 10a is received.

  CP removing unit 22 removes the CP from the received signal. A DFT (Discrete Fourier Transform) unit 23 is a time-frequency conversion processing unit that converts the received signal after CP removal into a frequency domain signal by DFT and outputs it. An FDE (Frequency Domain Equalizer) 24 performs equalization processing on the frequency domain signal output from the DFT unit 23 in the frequency domain using the transmission path estimation value output from the transmission path estimation unit 28. That is, the FDE 24 is an equalization processing unit that performs equalization processing on the frequency domain signal using the result of transmission path estimation on the frequency domain signal. The equalization processing in the FDE 24 is described in Non-Patent Document 1 or “JAC Bingham,“ Multicarrier Modulation for Data Transmission: An Idea Whose Time Has Come ”, IEEE Commun. Mag., Vol. 28, No. 5, A general FDE including the method described in “May 1990, pp. 5-14” can be used.

  The transmission path estimation unit 28 performs transmission path estimation based on the received signal after CP removal, and outputs the transmission path estimation value to the FDE 24. The transmission path estimation can be performed using any general method. For example, the transmission path may be estimated using a known signal. For example, a transmission path estimation method described in Non-Patent Document 1 may be used. Further, the output of the DFT unit may be used to perform transmission path estimation using a known signal in the frequency domain.

  An IDFT (Inverse DFT) unit 25 is a frequency time conversion processing unit that converts a signal after equalization processing by the FDE 24 into a time domain signal by IDFT and outputs the signal. The fixed sequence removal unit 26 removes a signal corresponding to the fixed symbol sequence from the signal output from the IDFT unit 25 based on the control signal # 3. Control signal # 3 is a signal indicating the position where the fixed symbol sequence is inserted. The control signal # 3 may be transmitted from the outside of the receiver 20, for example, or may be transmitted from a control circuit (not shown) in the receiver 20. When the position where the fixed symbol sequence is inserted is fixed, the control signal # 3 may not be used.

  The demodulator 27 demodulates the signal after the fixed symbol sequence is removed by the fixed sequence remover 26. Further, when the symbol is encoded in the transmitter 10 or the transmitter 10a, the demodulator 27 may perform error correction decoding after demodulation.

  Next, the hardware configuration of the receiver 20 of the present embodiment will be described. Each component configuring the receiver 20 illustrated in FIG. 17 is configured by a circuit. Each component configuring the receiver 20 illustrated in FIG. 17 may be realized as a dedicated circuit, or may be realized as a circuit using a processor.

  When each component configuring the receiver 20 illustrated in FIG. 17 is realized as a dedicated circuit, each component is, for example, the circuit illustrated in FIG. FIG. 18 is a diagram illustrating a configuration example of a circuit realized as dedicated hardware. As shown in FIG. 18, a circuit 300 includes an input unit 301 that is a receiving unit that receives data input from the outside, a processing circuit 302, a memory 303, and a transmission processing circuit that is a transmitter that transmits data to the outside. 304. The input unit 301 is an interface circuit that receives data input from the outside and applies the data to the processing circuit. The transmission processing circuit 304 is an interface circuit that transmits data from the processing circuit 302 or the memory 303 to the outside. In this case, the processing circuit 302 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof.

  When there are components realized by software among the components of the receiver 20 shown in FIG. 17, these components are realized by a control circuit shown in FIG. 19, for example. FIG. 19 is a diagram illustrating a configuration example of the control circuit 400. As shown in FIG. 19, the control circuit 400 includes an input unit 401 that is a receiver that receives data input from the outside, a processor 402, a memory 403, and an output unit 404 that is a transmitter that transmits data to the outside. With. The input unit 401 is an interface circuit that receives data input from the outside of the control circuit 400 and applies the data to the processor 402. The output unit 404 is an interface circuit that transmits data from the processor 402 or the memory 403 to the outside of the control circuit. It is. Among the components of the receiver 20 shown in FIG. 17, the components realized by software read and execute the program corresponding to each component realized by software, which is stored in the memory 403 by the processor 402. Is realized. The memory 402 is also used as a temporary memory in each process performed by the processor.

  The processor 402 is a CPU or the like. The memory 403 corresponds to, for example, a nonvolatile or volatile semiconductor memory such as a RAM, a flash memory, an EPROM, and an EEPROM, a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, and a DVD.

  As described above, the receiver 20 of the present embodiment can receive and demodulate the signal transmitted from the transmitter of the first embodiment or the second embodiment. In the transmitter of Embodiment 1 or Embodiment 2, as described above, since the fixed symbol sequence is inserted so as to suppress inter-block interference, the receiver 20 of this embodiment has high accuracy. Demodulation can be performed.

  The configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.

  DESCRIPTION OF SYMBOLS 1 Data symbol production | generation part, 2 Fixed series production | generation part, 3, 3a Symbol arrangement | positioning part, 4 CP production | generation part, 5 Transmission process part, 6 Known signal production | generation part 10, 10a Transmitter, 20 Receiver, 21 Reception process part, 22 CP removal unit, 23 DFT unit, 24 FDE, 25 IDFT unit, 26 fixed sequence removal unit, 27 demodulation unit, 28 transmission path estimation unit.

Claims (4)

A data symbol generator for generating a first number of data symbols;
The first symbol group is arranged at two locations so that the first position and the second position in the block are respectively the first symbol group which is a predetermined symbol group, and the block The second symbol group is arranged in two places so that the third position and the fourth position of the second end of the second symbol group are predetermined symbol groups, respectively, and the first symbol A symbol placement unit for generating and outputting the block in which the first number of data symbols is placed at a position other than a position at which a group and the second symbol group are placed;
A Cyclic Prefix generation unit that duplicates a second number of symbols at the end of the block output from the symbol placement unit and adds the symbol as a Cyclic Prefix to the top of the block;
With
The first position is a head of the block, the second position is a position that is a head of the second number of symbols copied as the Cyclic Prefix in the block, and the third position The position is the end of the block, and the fourth position is a position immediately before the second position. A known signal generator for generating a known symbol which is a predetermined symbol;
Further comprising
The first symbol group is arranged at two positions so that the first position and the second position are respectively at the head of the first symbol group, and the third position and the fourth position are arranged. Are arranged at two places so that each of the second symbol group is the end of the second symbol group, and the second symbol group is located at a position other than the position where the first symbol group and the second symbol group are arranged. Generating and outputting a known symbol block which is a block in which the first number of known symbols are arranged;
The Cyclic Prefix generation unit duplicates the second number of symbols at the end of the known symbol block output from the symbol placement unit, and adds the second number of symbols as a Cyclic Prefix to the beginning of the known symbol block. The transmission device according to claim 1. A signal transmitted from the transmission apparatus according to claim 1 or 2, wherein a signal in which a first symbol group and a second symbol group, which are fixed symbol sequences preliminarily stored in a block, are inserted, is a received signal. As a receiving device,
A CP removing unit for removing a cyclic prefix from the received signal;
A time-frequency conversion processing unit that converts the received signal after removal of the Cyclic Prefix into a frequency domain signal;
A transmission path estimation unit that performs transmission path estimation on the received signal after the removal of the Cyclic Prefix;
An equalization processing unit that performs an equalization process on the frequency domain signal using the result of the transmission path estimation on the frequency domain signal;
A frequency time conversion processing unit for converting the equalized signal into a time domain signal;
A fixed sequence removal unit for removing a signal corresponding to a fixed symbol sequence from the time domain signal;
A demodulator that demodulates the signal after the fixed symbol sequence is removed by the fixed sequence remover;
A receiving apparatus comprising: The transmission device according to claim 1 or 2,
The receiving device according to claim 3, which receives a signal transmitted from the transmitting device;
A communication system comprising:

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