WO2016143465A1 - Current detection circuit and solenoid drive device - Google Patents

Current detection circuit and solenoid drive device Download PDF

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Publication number
WO2016143465A1
WO2016143465A1 PCT/JP2016/054337 JP2016054337W WO2016143465A1 WO 2016143465 A1 WO2016143465 A1 WO 2016143465A1 JP 2016054337 W JP2016054337 W JP 2016054337W WO 2016143465 A1 WO2016143465 A1 WO 2016143465A1
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Prior art keywords
conversion
value
moving average
detection circuit
current detection
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PCT/JP2016/054337
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French (fr)
Japanese (ja)
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清勝 佐藤
直彦 下山
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サンケン電気株式会社
清勝 佐藤
直彦 下山
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Publication of WO2016143465A1 publication Critical patent/WO2016143465A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P25/00—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details
    • H02P25/02—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details characterised by the kind of motor
    • H02P25/06—Linear motors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
    • H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
    • H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the present invention relates to a current detection circuit and a solenoid driving device that detect a current of a solenoid that operates by PWM control.
  • Patent Document 1 As a conventional current detection circuit and solenoid drive device, for example, one described in Patent Document 1 is known.
  • the current detection circuit described in Patent Document 1 relates to a PWM inverter that variably controls an electric motor.
  • the PWM inverter generates a PWM waveform from a carrier signal (saw wave) and a frequency command (sine wave), and the PWM waveform is generated.
  • On / off control of the switching element of the inverter main circuit is performed as a gate signal.
  • the current during PWM control is a sawtooth waveform
  • a method of sampling at an integer multiple of a PWM cycle and averaging a plurality of sampled sampling values every PWM cycle is used.
  • the calculation result of the average current value is converted only at every PWM cycle, there is a problem that a large difference appears between the actual current and the average current of the calculation result in a situation where the current changes.
  • the present invention provides a current detection circuit and a solenoid driving device that can reduce the amount of calculation.
  • a current detection circuit is detected by a detection unit that detects a current flowing through a solenoid, a control unit that PWM-controls a switching element for flowing a current through the solenoid at a predetermined PWM cycle, and the detection unit.
  • An A / D converter that outputs an AD conversion value n times per PWM cycle by sampling a current value at a cycle of n times the predetermined PWM cycle and performing analog-to-digital conversion, and from the A / D converter a moving average calculation unit having a FIFO buffer for storing n AD conversion values, and the moving average calculation unit is the oldest 1 from the FIFO buffer based on the addition result obtained by adding the past n AD conversion values.
  • the latest one AD conversion value from the AD conversion unit is added to the (n ⁇ 1) AD conversion values obtained by subtracting the AD conversion values for the number of times to transfer n AD conversion values. Obtain an average for the sum value, and calculates the moving average value by dividing the moving average for the total value by n.
  • the moving average calculation unit subtracts the oldest one AD conversion value from the FIFO buffer from the addition result obtained by adding the past n AD conversion values to (n ⁇ 1) times.
  • the AD conversion value is obtained, and the latest one AD conversion value from the AD conversion unit is added to the (n-1) AD conversion value to obtain the moving average sum value of the n AD conversion values.
  • the amount of calculation can be reduced.
  • FIG. 1 is a diagram showing a circuit configuration of a current detection circuit according to Embodiment 1 of the present invention.
  • the current detection circuit shown in FIG. 1 detects a current of a solenoid L that operates by PWM control, and includes a current detection resistor R1, a diode D1, a target current value input unit 11, an operational amplifier 12, an A / D converter 13, and a movement.
  • An average calculation unit 14, a comparator 15, and a control unit 16 are provided.
  • the current detection circuit and the switching element Q1 according to the first embodiment of the present invention constitute a solenoid drive device according to the first embodiment of the present invention.
  • the switching element Q1 is made of a MOSFET, the drain is connected to the positive electrode of the power supply E, and the source is connected to the solenoid L via the current detection resistor R1.
  • the controller 16 causes a current to flow through the solenoid L by performing PWM control of the switching element Q1 at a predetermined PWM cycle.
  • the solenoid L constitutes an electric motor such as a solenoid bubble or an induction motor. That is, the solenoid bubble or the motor is PWM controlled by driving the solenoid L.
  • the current detection resistor R1 corresponds to the detection unit of the present invention, and detects the current flowing through the solenoid L.
  • the operational amplifier 12 amplifies the current detected by the current detection resistor R ⁇ b> 1 and outputs the amplified current to the A / D converter 13.
  • the A / D converter 13 samples the current value detected by the current detection resistor R1 from the operational amplifier 12 a plurality of times in a short cycle that is an integer multiple n of the PWM cycle of the control unit 16 and performs analog-digital conversion, thereby converting the PWM cycle.
  • the AD conversion value is output to the moving average calculation unit 14 at a cycle of n times.
  • the moving average calculator 14 calculates a moving average value based on an AD conversion value having a period n times the PWM period from the A / D converter 13. Details of the moving average calculation unit 14 will be described later.
  • the target current value input unit 11 inputs the target current value and outputs it to the comparator 15.
  • the comparator 15 compares the moving average value calculated by the moving average calculation unit 14 with the target current value from the target current value input unit 11 to generate a PWM signal, and sends the generated PWM signal to the control unit 16. Output.
  • FIG. 2 is a diagram illustrating a hardware configuration of the moving average calculation unit according to the first embodiment.
  • the moving average calculator 14 includes a FIFO (First In First Out) buffer 141, an adder 142, an adder 143, an adder 144, a selector 145, a register 146, and a divider 147.
  • FIFO First In First Out
  • the FIFO buffer 141 stores, for example, 64 AD conversion values from the A / D converter 13 every PWM cycle.
  • One AD conversion value is 12 bits wide, for example.
  • the register 146 stores an addition result obtained by adding the past 64 AD conversion values.
  • the adder 142 corresponds to the first adder of the present invention.
  • the adder 142 reads the oldest AD conversion value from the FIFO buffer 141 and adds the 64 AD conversion values from the register 146 to calculate the FIFO.
  • One AD conversion value from the buffer 141 is subtracted, and 63 AD conversion values are output to the adder 143.
  • the adder 143 corresponds to the second adder of the present invention.
  • the adder 143 adds the latest one AD conversion value to the 63 AD conversion values from the adder 142 to obtain a moving average of 64 AD conversion values.
  • the total sum value is obtained and output to the selector 145.
  • the divider 147 obtains a moving average value of the current by dividing the addition result obtained by adding the 64 AD conversion values from the register 146 by 64.
  • the adder 144 corresponds to the third adder of the present invention, adds the AD conversion values for 64 times from the A / D converter 13, and periodically averages the AD conversion values added 64 times for each PWM cycle. The total value is output to the selector 145.
  • the divider 147 calculates the average value of the current values by dividing the AD conversion value added 64 times by 64 for each PWM cycle.
  • the selector 145 selects and outputs the addition output of the adder 143 to the register 146 at a timing other than the PWM cycle, and selects and outputs the addition output of the adder 144 to the register 146 at the timing of the PWM cycle.
  • the selector 145 constitutes a correction unit of the present invention that replaces the moving average sum value from the adder 143 with the cycle average sum value obtained by the adder 144 at the end of a predetermined PWM cycle.
  • the adder 142 reads the oldest AD conversion value for one sampling from the FIFO buffer 141, and adds the AD conversion values for 64 times from the register 146. Then, the AD conversion value for one time from the FIFO buffer 141 is subtracted to obtain the AD conversion value for 63 times.
  • the adder 143 adds the latest AD conversion value to the 63 AD conversion values from the adder 142 to obtain a moving average total value.
  • the divider 147 can obtain the moving average value by dividing the moving average total value from the adder 143 by 64, so that the amount of calculation can be reduced.
  • the selector 145 converts the moving average value based on the moving average sum calculated by the adder 143 to the average value based on the cycle average total value calculated by the adder 144 at the end of the predetermined PWM cycle. replace.
  • the abnormal moving average value is averaged every PWM period at time t3, which is the PWM period of the drive signal. Since the value is replaced, the moving average value is correct. Therefore, even if abnormal data occurs, the abnormal data is not inherited.
  • FIG. 6 shows the moving average current of the example and the average current for each conventional PWM cycle over a plurality of PWM cycles. It can be seen from FIG. 6 that the moving average current of the example is smoothly converted.
  • FIG. 4 is a diagram showing a circuit configuration of a current detection circuit according to Embodiment 2 of the present invention.
  • the current detection circuit according to the second embodiment shown in FIG. 4 has a function similar to that of the first embodiment realized by a software configuration.
  • the moving average calculation unit 14A includes a CPU (central processing unit) 148, a RAM (random access memory). 149, and a program memory 150.
  • the current detection circuit and the switching element Q1 according to the second embodiment of the present invention constitute a solenoid drive device according to the second embodiment of the present invention.
  • the program memory 150 stores a program for performing a current moving average calculation process.
  • the CPU 148 sequentially reads each instruction of the program for performing the moving average calculation process of the current stored in the program memory 150, and executes the process of each instruction (each process in the flowchart of FIG. 5). That is, the current detection circuit according to the second embodiment is characterized by performing the same process as the process of the moving average calculation unit 14 according to the first embodiment using software.
  • the configuration other than the moving average calculation unit 14A is the same as the configuration shown in FIG. 1, so here, the moving average calculation processing of the moving average calculation unit 14A is performed with reference to the flowchart of FIG. explain.
  • the cycle average total value is set to 0, the moving average total value is set to 0, the moving average value is set to 0, the AD conversion count is set to 0, and the FIFO buffer 141 is initialized to 0 (step S11).
  • the period average total value represents the total value of the results of the AD conversion values during one PWM period.
  • the moving average total value represents the total value of the past n AD conversion values including the AD conversion value at that time.
  • the moving average value represents an average value of the past n AD conversion values including the AD conversion value at that time.
  • the number of AD conversions represents the number of AD conversions from the start of PWM when the PWM period is divided into n times.
  • step S12 the event flag of the cycle start is confirmed (step S12). It is determined whether the PWM cycle has started (step S13).
  • the PWM cycle start represents the rise timing of the PWM control waveform that drives the solenoid L.
  • step S14 the event flag for starting the PWM cycle is cleared (step S14). That is, the number of AD conversions is set to 0, the PWM cycle average total value is set to 0, and the process returns to step S12.
  • step S13 When it is determined in step S13 that the PWM cycle has not started, the AD conversion completion event flag is confirmed (step S15). Next, it is determined whether AD conversion is completed (step S16). The completion of AD conversion represents the output timing of the AD conversion result. If it is determined that the AD conversion is completed, the AD conversion completion event flag is cleared, the AD conversion value is input, and the AD conversion count is incremented by 1 (step S17).
  • step S18 it is determined whether the number of AD conversions is less than n (step S18). If it is determined that the number of AD conversions is less than n, an AD conversion value is input to the FIFO buffer 141, and the moving average sum is calculated. The total value for moving average is obtained by subtracting the FIFO output value from the result of adding the AD conversion value to the value (step S19). Further, the AD conversion value is added to the cycle average total value to obtain the cycle average total value.
  • the moving average value is obtained by dividing the moving average total value by n, and the moving average value is output (step S20). Accordingly, the moving average calculation unit 14A can obtain the moving average value by dividing the moving average total value obtained in step S19 by 64, and therefore the amount of calculation can be reduced.
  • step S21 it is determined whether or not the number of AD conversions is n (step S21). If the AD conversion count is greater than n, the process returns to step S12.
  • step S22 the process proceeds to step S20.
  • the present invention can be realized with either a hardware configuration or a software configuration.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Inverter Devices (AREA)
  • Electronic Switches (AREA)

Abstract

[Problem] To provide a current detection circuit capable of reducing computation and eliminating takeover of abnormal data. [Solution] The present invention comprises: a control unit (16) that PWM controls a switching element (Q1) for applying a current to a solenoid (L) at a prescribed PWM cycle; an A/D conversion unit (13) that samples and performs analog-to-digital conversion of a current value detected by a detecting unit (R1) at a cycle which is n-fold of the prescribed PWM cycle, and that outputs n times of AD conversion values every PWM cycle; and a moving average computation unit (14) that has a FIFO buffer (141) for storing the n times of AD conversion values from the A/D conversion unit. The moving average computation unit, to (n-1) times of AD conversion values obtained by subtracting the oldest AD conversion value from the FIFO buffer from the summation result of adding past n times of AD conversion values, adds the newest AD conversion value from the AD conversion unit and obtains a moving average total value for n times of AD conversion values, and divides the moving average total value by n to compute a moving average value.

Description

電流検出回路及びソレノイド駆動装置Current detection circuit and solenoid drive device
　本発明は、ＰＷＭ制御で動作するソレノイドの電流を検出する電流検出回路及びソレノイド駆動装置に関する。 The present invention relates to a current detection circuit and a solenoid driving device that detect a current of a solenoid that operates by PWM control.
　従来の電流検出回路及びソレノイド駆動装置として、例えば、特許文献１に記載されたものが知られている。特許文献１に記載された電流検出回路は、電動機を可変制御するＰＷＭインバータに係わり、ＰＷＭインバータはキャリア信号（鋸波）と周波数指令（正弦波）とからＰＷＭ波形を生成し、このＰＷＭ波形をゲート信号としてインバータ主回路のスイッチング素子をオンオフ制御する。 As a conventional current detection circuit and solenoid drive device, for example, one described in Patent Document 1 is known. The current detection circuit described in Patent Document 1 relates to a PWM inverter that variably controls an electric motor. The PWM inverter generates a PWM waveform from a carrier signal (saw wave) and a frequency command (sine wave), and the PWM waveform is generated. On / off control of the switching element of the inverter main circuit is performed as a gate signal.
　この場合、ＰＷＭ制御中の電流は、鋸波形となるため、ソレノイドを精度良く制御するために平均電流を演算する必要がある。この手法として、ＰＷＭ周期の整数倍でサンプリングし、サンプリングされた複数のサンプリング値をＰＷＭ周期毎に平均化する手法が用いられている。この手法では、平均電流値の演算結果がＰＷＭ周期毎でしか変換しないため、電流が変化する状況では、実電流と演算結果の平均電流には大きな差が現われるという課題を有していた。 In this case, since the current during PWM control is a sawtooth waveform, it is necessary to calculate an average current in order to control the solenoid with high accuracy. As this method, a method of sampling at an integer multiple of a PWM cycle and averaging a plurality of sampled sampling values every PWM cycle is used. In this method, since the calculation result of the average current value is converted only at every PWM cycle, there is a problem that a large difference appears between the actual current and the average current of the calculation result in a situation where the current changes.
　一方、上記課題を解決する手法として、ＰＷＭ周期の整数倍でサンプリングし、サンプリング毎に直前のＰＷＭ周期分のサンプリング値で平均化処理を連続して行う方法がある。この方法は、ＰＷＭ周期の整数倍を維持したまま移動平均を算出している。 On the other hand, as a method for solving the above-described problem, there is a method in which sampling is performed at an integer multiple of a PWM cycle, and averaging processing is continuously performed with a sampling value for the immediately preceding PWM cycle for each sampling. This method calculates a moving average while maintaining an integer multiple of the PWM period.
特開２００３－２１９６９０号公報JP 2003-219690 A
　しかしながら、従来の移動平均方式では、演算量が多量であり、処理時間が長くなっていた。 However, in the conventional moving average method, the amount of calculation is large and the processing time is long.
　本発明は、演算量を少なくできる電流検出回路及びソレノイド駆動装置を提供する。 The present invention provides a current detection circuit and a solenoid driving device that can reduce the amount of calculation.
　本発明に係る電流検出回路は、ソレノイドに流れる電流を検出する検出部と、前記ソレノイドに電流を流すためのスイッチング素子を所定のＰＷＭ周期でＰＷＭ制御する制御部と、前記検出部で検出された電流値を前記所定のＰＷＭ周期のｎ倍の周期でサンプリングしアナログデジタル変換することによりＰＷＭ周期毎にｎ回のＡＤ変換値を出力するＡ／Ｄ変換部と、前記Ａ／Ｄ変換部からのｎ回のＡＤ変換値を記憶するＦＩＦＯバッファを有する移動平均演算部とを備え、前記移動平均演算部は、過去のｎ回のＡＤ変換値を加算した加算結果から前記ＦＩＦＯバッファからの最も古い１回のＡＤ変換値を減算して得られる（ｎ－１）回のＡＤ変換値に対し、前記ＡＤ変換部からの最新の１回のＡＤ変換値を加算してｎ回のＡＤ変換値の移動平均用総和値を得、当該移動平均用総和値をｎで除算することにより移動平均値を演算することを特徴とする。 A current detection circuit according to the present invention is detected by a detection unit that detects a current flowing through a solenoid, a control unit that PWM-controls a switching element for flowing a current through the solenoid at a predetermined PWM cycle, and the detection unit. An A / D converter that outputs an AD conversion value n times per PWM cycle by sampling a current value at a cycle of n times the predetermined PWM cycle and performing analog-to-digital conversion, and from the A / D converter a moving average calculation unit having a FIFO buffer for storing n AD conversion values, and the moving average calculation unit is the oldest 1 from the FIFO buffer based on the addition result obtained by adding the past n AD conversion values. The latest one AD conversion value from the AD conversion unit is added to the (n−1) AD conversion values obtained by subtracting the AD conversion values for the number of times to transfer n AD conversion values. Obtain an average for the sum value, and calculates the moving average value by dividing the moving average for the total value by n.
　本発明によれば、移動平均演算部は、過去のｎ回のＡＤ変換値を加算した加算結果から、ＦＩＦＯバッファからの最も古い１回のＡＤ変換値を減算して（ｎ－１）回のＡＤ変換値を得て、（ｎ－１）回のＡＤ変換値にＡＤ変換部からの最新の１回のＡＤ変換値を加算してｎ回のＡＤ変換値の移動平均用総和値を得るので、演算量を少なくできる。 According to the present invention, the moving average calculation unit subtracts the oldest one AD conversion value from the FIFO buffer from the addition result obtained by adding the past n AD conversion values to (n−1) times. The AD conversion value is obtained, and the latest one AD conversion value from the AD conversion unit is added to the (n-1) AD conversion value to obtain the moving average sum value of the n AD conversion values. The amount of calculation can be reduced.
本発明の実施例１に係る電流検出回路の回路構成を示す図である。It is a figure which shows the circuit structure of the current detection circuit which concerns on Example 1 of this invention. 本発明の実施例１に係る電流検出回路の移動平均演算部のハードウェア構成を示す図である。It is a figure which shows the hardware constitutions of the moving average calculating part of the electric current detection circuit which concerns on Example 1 of this invention. 本発明の実施例１に係る電流検出回路の移動平均演算部によるデータ補正処理を説明するための波形図である。It is a wave form diagram for demonstrating the data correction process by the moving average calculating part of the electric current detection circuit which concerns on Example 1 of this invention. 本発明の実施例２に係る電流検出回路の回路構成を示す図である。It is a figure which shows the circuit structure of the current detection circuit which concerns on Example 2 of this invention. 本発明の実施例２に係る電流検出回路の移動平均演算処理を示すフローチャートである。It is a flowchart which shows the moving average calculation process of the electric current detection circuit which concerns on Example 2 of this invention. 本発明の実施例の移動平均電流と従来のＰＷＭ周期毎度の平均電流を示す図である。It is a figure which shows the moving average current of the Example of this invention, and the average current of every conventional PWM period. 従来の電流検出回路の移動平均値のデータ異常が発生した様子を示す図である。It is a figure which shows a mode that the data abnormality of the moving average value of the conventional current detection circuit occurred.
　以下、本発明の実施の形態について、図面を参照しながら詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
　（実施例１）図１は、本発明の実施例１に係る電流検出回路の回路構成を示す図である。図１に示す電流検出回路は、ＰＷＭ制御で動作するソレノイドＬの電流を検出するもので、電流検出抵抗Ｒ１、ダイオードＤ１、目標電流値入力部１１、オペアンプ１２、Ａ／Ｄ変換器１３、移動平均演算部１４、比較器１５、制御部１６を備えている。本発明の実施例１に係る電流検出回路とスイッチング素子Ｑ１とは、本発明の実施例１に係るソレノイド駆動装置を構成する。 (Embodiment 1) FIG. 1 is a diagram showing a circuit configuration of a current detection circuit according to Embodiment 1 of the present invention. The current detection circuit shown in FIG. 1 detects a current of a solenoid L that operates by PWM control, and includes a current detection resistor R1, a diode D1, a target current value input unit 11, an operational amplifier 12, an A / D converter 13, and a movement. An average calculation unit 14, a comparator 15, and a control unit 16 are provided. The current detection circuit and the switching element Q1 according to the first embodiment of the present invention constitute a solenoid drive device according to the first embodiment of the present invention.
　スイッチング素子Ｑ１は、ＭＯＳＦＥＴからなり、ドレインが電源Ｅの正極に接続され、ソースが電流検出抵抗Ｒ１を介してソレノイドＬに接続されている。制御部１６は、所定のＰＷＭ周期でスイッチング素子Ｑ１をＰＷＭ制御することによりソレノイドＬに電流を流す。ソレノイドＬは、ソレノイドバブル或いは誘導電動機などの電動機を構成する。即ち、ソレノイドＬを駆動することにより、ソレノイドバブル或いは電動機をＰＷＭ制御する。 The switching element Q1 is made of a MOSFET, the drain is connected to the positive electrode of the power supply E, and the source is connected to the solenoid L via the current detection resistor R1. The controller 16 causes a current to flow through the solenoid L by performing PWM control of the switching element Q1 at a predetermined PWM cycle. The solenoid L constitutes an electric motor such as a solenoid bubble or an induction motor. That is, the solenoid bubble or the motor is PWM controlled by driving the solenoid L.
　電流検出抵抗Ｒ１は、本発明の検出部に相当し、ソレノイドＬに流れる電流を検出する。オペアンプ１２は、電流検出抵抗Ｒ１で検出された電流を増幅してＡ／Ｄ変換器１３に出力する。 The current detection resistor R1 corresponds to the detection unit of the present invention, and detects the current flowing through the solenoid L. The operational amplifier 12 amplifies the current detected by the current detection resistor R <b> 1 and outputs the amplified current to the A / D converter 13.
　Ａ／Ｄ変換器１３は、オペアンプ１２からの電流検出抵抗Ｒ１で検出された電流値を制御部１６のＰＷＭ周期の整数倍ｎの短い周期で複数回サンプリングしてアナログデジタル変換することによりＰＷＭ周期のｎ倍の周期でＡＤ変換値を移動平均演算部１４に出力する。 The A / D converter 13 samples the current value detected by the current detection resistor R1 from the operational amplifier 12 a plurality of times in a short cycle that is an integer multiple n of the PWM cycle of the control unit 16 and performs analog-digital conversion, thereby converting the PWM cycle. The AD conversion value is output to the moving average calculation unit 14 at a cycle of n times.
　移動平均演算部１４は、Ａ／Ｄ変換器１３からのＰＷＭ周期のｎ倍の周期のＡＤ変換値に基づき移動平均値を演算する。移動平均演算部１４の詳細については、後述する。 The moving average calculator 14 calculates a moving average value based on an AD conversion value having a period n times the PWM period from the A / D converter 13. Details of the moving average calculation unit 14 will be described later.
　目標電流値入力部１１は、目標電流値を入力して比較器１５に出力する。比較器１５は、移動平均演算部１４で演算された移動平均値と目標電流値入力部１１からの目標電流値とを比較してＰＷＭ信号を生成し、生成されたＰＷＭ信号を制御部１６に出力する。 The target current value input unit 11 inputs the target current value and outputs it to the comparator 15. The comparator 15 compares the moving average value calculated by the moving average calculation unit 14 with the target current value from the target current value input unit 11 to generate a PWM signal, and sends the generated PWM signal to the control unit 16. Output.
　図２は実施例１の移動平均演算部のハードウェア構成を示す図である。移動平均演算部１４は、ＦＩＦＯ（First In First Out）バッファ１４１、加算器１４２、加算器１４３、加算器１４４、セレクタ１４５、レジスタ１４６、除算器１４７を有している。 FIG. 2 is a diagram illustrating a hardware configuration of the moving average calculation unit according to the first embodiment. The moving average calculator 14 includes a FIFO (First In First Out) buffer 141, an adder 142, an adder 143, an adder 144, a selector 145, a register 146, and a divider 147.
　ここでは、ＰＷＭ周期毎に例えば６４回（整数倍ｎ＝６４）サンプリングした場合を説明する。ＦＩＦＯバッファ１４１は、ＰＷＭ周期毎にＡ／Ｄ変換器１３からの例えば６４回分のＡＤ変換値を記憶する。１回分のＡＤ変換値は、例えば１２ビット幅である。レジスタ１４６は、過去の６４回分のＡＤ変換値を加算した加算結果を記憶する。 Here, for example, a case where sampling is performed 64 times (integer multiple n = 64) for each PWM cycle will be described. The FIFO buffer 141 stores, for example, 64 AD conversion values from the A / D converter 13 every PWM cycle. One AD conversion value is 12 bits wide, for example. The register 146 stores an addition result obtained by adding the past 64 AD conversion values.
　加算器１４２は、本発明の第１の加算器に対応し、ＦＩＦＯバッファ１４１から最も古い１回分のＡＤ変換値を読み出し、レジスタ１４６からの６４回分のＡＤ変換値を加算した加算結果から、ＦＩＦＯバッファ１４１からの１回分のＡＤ変換値を減算し、６３回分のＡＤ変換値を加算器１４３に出力する。 The adder 142 corresponds to the first adder of the present invention. The adder 142 reads the oldest AD conversion value from the FIFO buffer 141 and adds the 64 AD conversion values from the register 146 to calculate the FIFO. One AD conversion value from the buffer 141 is subtracted, and 63 AD conversion values are output to the adder 143.
　加算器１４３は、本発明の第２の加算器に対応し、加算器１４２からの６３回分のＡＤ変換値に最新の１回分のＡＤ変換値を加算して６４回分のＡＤ変換値の移動平均用総和値を得て、セレクタ１４５に出力する。 The adder 143 corresponds to the second adder of the present invention. The adder 143 adds the latest one AD conversion value to the 63 AD conversion values from the adder 142 to obtain a moving average of 64 AD conversion values. The total sum value is obtained and output to the selector 145.
　除算器１４７は、レジスタ１４６からの６４回分のＡＤ変換値を加算した加算結果を６４で除算することにより電流の移動平均値を求める。 The divider 147 obtains a moving average value of the current by dividing the addition result obtained by adding the 64 AD conversion values from the register 146 by 64.
　加算器１４４は、本発明の第３の加算器に対応し、Ａ／Ｄ変換器１３からの６４回分のＡＤ変換値を加算し、ＰＷＭ周期毎に、６４回加算したＡＤ変換値を周期平均用総和値としてセレクタ１４５に出力する。 The adder 144 corresponds to the third adder of the present invention, adds the AD conversion values for 64 times from the A / D converter 13, and periodically averages the AD conversion values added 64 times for each PWM cycle. The total value is output to the selector 145.
　除算器１４７は、ＰＷＭ周期毎に、６４回加算したＡＤ変換値を６４で除算することにより、電流値の平均値を演算する。 The divider 147 calculates the average value of the current values by dividing the AD conversion value added 64 times by 64 for each PWM cycle.
　セレクタ１４５は、ＰＷＭ周期ではないタイミングでは、加算器１４３の加算出力を選択してレジスタ１４６に出力し、ＰＷＭ周期のタイミングでは、加算器１４４の加算出力を選択してレジスタ１４６に出力する。 The selector 145 selects and outputs the addition output of the adder 143 to the register 146 at a timing other than the PWM cycle, and selects and outputs the addition output of the adder 144 to the register 146 at the timing of the PWM cycle.
　即ち、セレクタ１４５は、所定のＰＷＭ周期の最後に、加算器１４３からの移動平均用総和値を加算器１４４で得られた周期平均用総和値に置き換える本発明の補正部を構成する。 That is, the selector 145 constitutes a correction unit of the present invention that replaces the moving average sum value from the adder 143 with the cycle average sum value obtained by the adder 144 at the end of a predetermined PWM cycle.
　このように実施例１の電流検出回路によれば、加算器１４２は、ＦＩＦＯバッファ１４１から最も古いサンプリング１回分のＡＤ変換値を読み出し、レジスタ１４６からの６４回分のＡＤ変換値を加算した加算結果から、ＦＩＦＯバッファ１４１からの１回分のＡＤ変換値を減算し、６３回分のＡＤ変換値を求める。加算器１４３は、加算器１４２からの６３回分のＡＤ変換値に最新の１回分のＡＤ変換値を加算して移動平均用総和値を得る。除算器１４７は、加算器１４３からの移動平均用総和値を６４で除算することで、移動平均値を求めることができるので、演算量を少なくできる。 As described above, according to the current detection circuit of the first embodiment, the adder 142 reads the oldest AD conversion value for one sampling from the FIFO buffer 141, and adds the AD conversion values for 64 times from the register 146. Then, the AD conversion value for one time from the FIFO buffer 141 is subtracted to obtain the AD conversion value for 63 times. The adder 143 adds the latest AD conversion value to the 63 AD conversion values from the adder 142 to obtain a moving average total value. The divider 147 can obtain the moving average value by dividing the moving average total value from the adder 143 by 64, so that the amount of calculation can be reduced.
　また、セレクタ１４５が、所定のＰＷＭ周期の最後に、加算器１４３で演算された移動平均用総和値に基づく移動平均値を、加算器１４４で演算された周期平均用総和値に基づく平均値に置き換える。図３に示すように、時刻ｔ２において、予期しないエラーなどにより移動平均値にデータ異常が発生しても、駆動信号のＰＷＭ周期である時刻ｔ３において、異常な移動平均値をＰＷＭ周期毎度の平均値に置き換えているので、移動平均値が正しい値となる。従って、異常データが発生しても、異常データが引き継ぎされることがなくなる。 The selector 145 converts the moving average value based on the moving average sum calculated by the adder 143 to the average value based on the cycle average total value calculated by the adder 144 at the end of the predetermined PWM cycle. replace. As shown in FIG. 3, even if a data abnormality occurs in the moving average value due to an unexpected error or the like at time t2, the abnormal moving average value is averaged every PWM period at time t3, which is the PWM period of the drive signal. Since the value is replaced, the moving average value is correct. Therefore, even if abnormal data occurs, the abnormal data is not inherited.
　また、図６に、複数のＰＷＭ周期に亙って、実施例の移動平均電流と従来のＰＷＭ周期毎度の平均電流を示した。図６から実施例の移動平均電流は滑らかに変換していることがわかる。 FIG. 6 shows the moving average current of the example and the average current for each conventional PWM cycle over a plurality of PWM cycles. It can be seen from FIG. 6 that the moving average current of the example is smoothly converted.
　（実施例２）図４は、本発明の実施例２に係る電流検出回路の回路構成を示す図である。図４に示す実施例２に係る電流検出回路は、実施例１と同様の機能をソフトウェア構成で実現したものであり、移動平均演算部１４ＡがＣＰＵ（中央処理装置）１４８、ＲＡＭ（ランダムアクセスメモリ）１４９、プログラム用メモリ１５０を備えることを特徴とする。本発明の実施例２に係る電流検出回路とスイッチング素子Ｑ１とは、本発明の実施例２に係るソレノイド駆動装置を構成する。 (Embodiment 2) FIG. 4 is a diagram showing a circuit configuration of a current detection circuit according to Embodiment 2 of the present invention. The current detection circuit according to the second embodiment shown in FIG. 4 has a function similar to that of the first embodiment realized by a software configuration. The moving average calculation unit 14A includes a CPU (central processing unit) 148, a RAM (random access memory). 149, and a program memory 150. The current detection circuit and the switching element Q1 according to the second embodiment of the present invention constitute a solenoid drive device according to the second embodiment of the present invention.
　プログラム用メモリ１５０は、電流の移動平均演算処理を行うためのプログラムを格納している。ＣＰＵ１４８は、プログラム用メモリ１５０に格納された電流の移動平均演算処理を行うためのプログラムの各命令を順番に読み出して、各命令の処理を実行する（図５のフローチャートの各処理）。即ち、実施例２に係る電流検出回路は、ソフトウェアを用いて、実施例１の移動平均演算部１４の処理と同じ処理を行うことを特徴とする。 The program memory 150 stores a program for performing a current moving average calculation process. The CPU 148 sequentially reads each instruction of the program for performing the moving average calculation process of the current stored in the program memory 150, and executes the process of each instruction (each process in the flowchart of FIG. 5). That is, the current detection circuit according to the second embodiment is characterized by performing the same process as the process of the moving average calculation unit 14 according to the first embodiment using software.
　図４において、移動平均演算部１４Ａ以外のその他の構成は、図１に示す構成と同一であるので、ここでは、図５のフローチャートを参照しながら、移動平均演算部１４Ａの移動平均演算処理を説明する。 In FIG. 4, the configuration other than the moving average calculation unit 14A is the same as the configuration shown in FIG. 1, so here, the moving average calculation processing of the moving average calculation unit 14A is performed with reference to the flowchart of FIG. explain.
　まず、周期平均用総和値を０とし、移動平均用総和値を０とし、移動平均値を０とし、ＡＤ変換回数を０とし、ＦＩＦＯバッファ１４１を０に初期化する（ステップＳ１１）。 First, the cycle average total value is set to 0, the moving average total value is set to 0, the moving average value is set to 0, the AD conversion count is set to 0, and the FIFO buffer 141 is initialized to 0 (step S11).
　ここで、周期平均用総和値は、ＰＷＭ一周期の間のＡＤ変換値の結果の総和値を表す。移動平均用総和値は、その時点のＡＤ変換値を含めた過去ｎ回のＡＤ変換値の総和値を表す。移動平均値はその時点のＡＤ変換値を含めた過去ｎ回のＡＤ変換値の平均値を表す。ＡＤ変換回数は、ＰＷＭ一周期の間をｎ回に分割した時のＰＷＭ開始からのＡＤ変換回数を表す。 Here, the period average total value represents the total value of the results of the AD conversion values during one PWM period. The moving average total value represents the total value of the past n AD conversion values including the AD conversion value at that time. The moving average value represents an average value of the past n AD conversion values including the AD conversion value at that time. The number of AD conversions represents the number of AD conversions from the start of PWM when the PWM period is divided into n times.
　次に、周期開始のイベントフラグを確認する（ステップＳ１２）。ＰＷＭ周期が開始したかどうかを判定する（ステップＳ１３）。ＰＷＭ周期開始は、ソレノイドＬを駆動するＰＷＭ制御波形の立ち上がりタイミングを表す。 Next, the event flag of the cycle start is confirmed (step S12). It is determined whether the PWM cycle has started (step S13). The PWM cycle start represents the rise timing of the PWM control waveform that drives the solenoid L.
　ＰＷＭ周期が開始したと判定された場合には、ＰＷＭ周期開始のイベントフラグをクリアする（ステップＳ１４）。即ち、ＡＤ変換回数を０にし、ＰＷＭ周期平均用総和値を０にして、ステップＳ１２の処理に戻る。 When it is determined that the PWM cycle has started, the event flag for starting the PWM cycle is cleared (step S14). That is, the number of AD conversions is set to 0, the PWM cycle average total value is set to 0, and the process returns to step S12.
　ステップＳ１３において、ＰＷＭ周期が開始していないと判定された場合には、ＡＤ変換完了イベントフラグを確認する（ステップＳ１５）。次に、ＡＤ変換が完了したかどうかを判定する（ステップＳ１６）。ＡＤ変換完了は、ＡＤ変換結果の出力タイミングを表す。ＡＤ変換が完了したと判定された場合には、ＡＤ変換完了イベントフラグをクリアし、ＡＤ変換値を入力し、ＡＤ変換回数を１だけインクリメントする（ステップＳ１７）。 When it is determined in step S13 that the PWM cycle has not started, the AD conversion completion event flag is confirmed (step S15). Next, it is determined whether AD conversion is completed (step S16). The completion of AD conversion represents the output timing of the AD conversion result. If it is determined that the AD conversion is completed, the AD conversion completion event flag is cleared, the AD conversion value is input, and the AD conversion count is incremented by 1 (step S17).
　次に、ＡＤ変換回数がｎ未満かどうかを判定し（ステップＳ１８）、ＡＤ変換回数がｎ未満であると判定された場合には、ＦＩＦＯバッファ１４１にＡＤ変換値を入力し、移動平均用総和値にＡＤ変換値を加算した結果からＦＩＦＯ出力値を減算して移動平均用総和値を求める（ステップＳ１９）。また、周期平均用総和値にＡＤ変換値を加算して周期平均用総和値を得る。 Next, it is determined whether the number of AD conversions is less than n (step S18). If it is determined that the number of AD conversions is less than n, an AD conversion value is input to the FIFO buffer 141, and the moving average sum is calculated. The total value for moving average is obtained by subtracting the FIFO output value from the result of adding the AD conversion value to the value (step S19). Further, the AD conversion value is added to the cycle average total value to obtain the cycle average total value.
　次に、移動平均用総和値をｎで除算して移動平均値を求め、移動平均値を出力する（ステップＳ２０）。従って、移動平均演算部１４Ａは、ステップＳ１９で得られた移動平均用総和値を６４で除算することで、移動平均値を求めることができるので、演算量を少なくできる。 Next, the moving average value is obtained by dividing the moving average total value by n, and the moving average value is output (step S20). Accordingly, the moving average calculation unit 14A can obtain the moving average value by dividing the moving average total value obtained in step S19 by 64, and therefore the amount of calculation can be reduced.
　一方、ステップＳ１８において、ＡＤ変換回数がｎ以上である場合には、ＡＤ変換回数がｎであるかどうかを判定する（ステップＳ２１）。ＡＤ変換回数がｎより大きい場合には、ステップＳ１２の処理に戻る。 On the other hand, if the number of AD conversions is n or more in step S18, it is determined whether or not the number of AD conversions is n (step S21). If the AD conversion count is greater than n, the process returns to step S12.
　ＡＤ変換回数がｎである場合には、即ち、ＰＷＭ周期のときに、周期平均用総和値にその時のＡＤ変換値を加算して周期平均用総和値とし、その周期平均用総和値を移動平均用総和値に置き換え（ステップＳ２２）、ステップＳ２０の処理に進む。 When the number of AD conversions is n, that is, in the PWM cycle, the AD conversion value at that time is added to the cycle average total value to obtain the cycle average total value, and the cycle average total value is converted to the moving average. The total value is replaced with the total value (step S22), and the process proceeds to step S20.
　即ち、予期しないエラーなどにより移動平均値にデータ異常が発生しても、駆動信号のＰＷＭ周期で異常な移動平均値をＰＷＭ周期毎の平均値に置き換えているので、移動平均値が正しい値となる。従って、異常データが発生しても、異常データが引き継ぎされることがなくなる。このように、本発明は、ハードウェア構成でもソフトウェア構成でも実現できる。 In other words, even if a data error occurs in the moving average value due to an unexpected error or the like, the abnormal moving average value is replaced with the average value for each PWM cycle in the PWM cycle of the drive signal. Become. Therefore, even if abnormal data occurs, the abnormal data is not inherited. Thus, the present invention can be realized with either a hardware configuration or a software configuration.
Ｑ１　スイッチング素子
Ｄ１　ダイオード
Ｒ１　電流検出抵抗
Ｅ　電源
Ｌ　ソレノイド
１１　目標電流値入力部
１２　オペアンプ
１３　Ａ／Ｄ変換部
１４，１４Ａ　移動平均演算部　
１５　比較器
１６　制御部
１４１　ＦＩＦＯバッファ
１４２，１４３，１４４　加算器
１４５　セレクタ
１４６　レジスタ
１４７　除算器
１４８　ＣＰＵ
１４９　ＲＡＭ
１５０　プログラム用メモリ Q1 Switching element D1 Diode R1 Current detection resistor E Power supply L Solenoid 11 Target current value input unit 12 Operational amplifier 13 A / D conversion unit 14, 14A Moving average calculation unit
15 Comparator 16 Control Unit 141 FIFO Buffer 142, 143, 144 Adder 145 Selector 146 Register 147 Divider 148 CPU
149 RAM
150 Program memory

Claims (7)

  1. 　ソレノイドに流れる電流を検出する検出部と、
    　前記ソレノイドに電流を流すためのスイッチング素子を所定のＰＷＭ周期でＰＷＭ制御する制御部と、
    　前記検出部で検出された電流値を前記所定のＰＷＭ周期のｎ倍の周期でサンプリングしアナログデジタル変換することによりＰＷＭ周期毎にｎ回のＡＤ変換値を出力するＡ／Ｄ変換部と、
    　前記Ａ／Ｄ変換部からのｎ回のＡＤ変換値を記憶するＦＩＦＯバッファを有する移動平均演算部と、を備え、
    　前記移動平均演算部は、過去のｎ回のＡＤ変換値を加算した加算結果から前記ＦＩＦＯバッファからの最も古い１回のＡＤ変換値を減算して得られる（ｎ－１）回のＡＤ変換値に対し、前記ＡＤ変換部からの最新の１回のＡＤ変換値を加算してｎ回のＡＤ変換値の移動平均用総和値を得、当該移動平均用総和値をｎで除算することにより移動平均値を演算することを特徴とする電流検出回路。     A detector for detecting the current flowing through the solenoid;
    A control unit that PWM-controls a switching element for causing a current to flow through the solenoid at a predetermined PWM cycle;
    An A / D converter that samples the current value detected by the detector at a period n times the predetermined PWM period and performs analog-to-digital conversion to output n AD conversion values for each PWM period;
    A moving average calculation unit having a FIFO buffer for storing n times of AD conversion values from the A / D conversion unit,
    The moving average computing unit subtracts the oldest one AD conversion value from the FIFO buffer from the addition result obtained by adding the past n AD conversion values (n−1) AD conversion values. On the other hand, the latest one AD conversion value from the AD conversion unit is added to obtain a moving average sum value of n AD conversion values, and the moving average sum value is divided by n to move. A current detection circuit characterized by calculating an average value.
  2. 　前記移動平均演算部は、
    　過去のｎ回のＡＤ変換値を加算した加算結果を記憶するレジスタを備えることを特徴とする請求項１記載の電流検出回路。     The moving average calculator is
    The current detection circuit according to claim 1, further comprising a register that stores an addition result obtained by adding the past n AD conversion values.
  3. 　前記移動平均演算部は、
    　前記レジスタからのｎ回のＡＤ変換値を加算した加算結果から、前記ＦＩＦＯバッファからの最も古い１回のＡＤ変換値を減算して（ｎ－１）回のＡＤ変換値を得る第１の加算器を備えることを特徴とする請求項２記載の電流検出回路。     The moving average calculator is
    A first addition for subtracting the oldest one AD conversion value from the FIFO buffer from the addition result obtained by adding n AD conversion values from the register to obtain an (n-1) AD conversion value The current detection circuit according to claim 2, further comprising a detector.
  4. 　前記移動平均演算部は、
    　前記第１の加算器からの（ｎ－１）回のＡＤ変換値に前記ＡＤ変換部からの最新の１回のＡＤ変換値を加算してｎ回のＡＤ変換値の移動平均用総和値を得る第２の加算器を備えることを特徴とする請求項３記載の電流検出回路。     The moving average calculator is
    The latest one AD conversion value from the AD conversion unit is added to the (n−1) AD conversion values from the first adder to obtain a moving average total value of the n AD conversion values. 4. The current detection circuit according to claim 3, further comprising a second adder to be obtained.
  5. 　前記移動平均演算部は、
    　前記第２の加算器からの移動平均用総和値をｎで除算することにより前記移動平均値を演算する除算器を備えることを特徴とする請求項４記載の電流検出回路。     The moving average calculator is
    5. The current detection circuit according to claim 4, further comprising a divider that calculates the moving average value by dividing the moving average total value from the second adder by n.
  6. 　前記所定のＰＷＭ周期毎に、前記Ａ／Ｄ変換部からのｎ回のＡＤ変換値を加算して得られた周期平均用総和値を出力する第３の加算器と、
    　前記所定のＰＷＭ周期の最後に、前記第２の加算器からの移動平均用総和値を前記第３の加算器で得られた周期平均用総和値に置き換える補正部と、
    を備えることを特徴とする請求項５記載の電流検出回路。     A third adder for outputting a periodic average total value obtained by adding n AD conversion values from the A / D converter for each predetermined PWM period;
    A correction unit that replaces the moving average sum value from the second adder with the cycle average sum value obtained by the third adder at the end of the predetermined PWM period;
    The current detection circuit according to claim 5, further comprising:
  7. 　電源と前記ソレノイドとに接続されるスイッチング素子と、
    　前記請求項１に記載される電流検出回路と、を備えることを特徴とするソレノイド駆動装置。     A switching element connected to a power source and the solenoid;
    A solenoid drive device comprising: the current detection circuit according to claim 1.
PCT/JP2016/054337 2015-03-11 2016-02-15 Current detection circuit and solenoid drive device WO2016143465A1 (en)

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