JP5233217B2 - Output current detection method of voltage type PWM inverter device - Google Patents

Description

  The present invention relates to an output current detection method for automatically controlling an output current by detecting an output current of a voltage type PWM inverter device by sampling and feeding back the detected output current value to a control circuit.

  FIG. 5 shows a configuration example of the voltage type PWM inverter device. The inverter device 1 in which semiconductor switches such as IGBTs are bridge-connected is provided with a gate signal that is an on / off signal of the semiconductor switch from the control circuit 2 based on a result of comparing the PWM carrier wave and the AC output signal wave. The voltage output of the PWM waveform is obtained. The PWM waveform detects the output current of the inverter device 1 and feeds back the detected current to the control circuit 2 to automatically control the on / off ratio of the gate signal, and automatically controls the output current according to the command value. . That is, in order to detect the output current of the inverter device 1, the detection output of the current detector 4 is sampled and held by a sample and hold circuit (sampler) 5, and converted to a digital value by an analog-digital converter (ADC) 6, This is taken into the control circuit 2.

  Since the output current of the inverter device 1 includes a ripple component caused by PWM, in order to detect the average value, as shown in the sampling timing in FIG. Sampling is performed (see, for example, Patent Document 1 and Patent Document 2).

Another technique is to improve noise resistance by sampling at a period shorter than the period of the carrier wave and obtaining the output current from the average value (see, for example, Patent Document 3).
JP 11-136950 A JP-A-9-117152 Japanese Patent Laid-Open No. 9-23658

  However, in the method of detecting the output current by sampling based on the peak of the carrier wave, the period in which the current can be detected is limited to the frequency of the carrier wave. As a result, the control period of the feedback calculation is also limited, and the control performance is reduced. There was a problem of lowering.

  In addition, the current detection system uses a current detection system that sets the delay time from the top of the carrier wave to the sampling as a fixed value as the delay time of the current detection system until the output of the current detector or current detector is input to the sample hold circuit. Since the delay time of the detector and the current detection circuit varies from device to device, it is difficult to set an optimum sampling delay time.

  The purpose of the present invention is to be able to detect current at any time without being restricted by carrier frequency and vertex timing, and to detect with improved noise resistance, and to automatically adjust the variation of the current detection system for each device An object of the present invention is to provide a method for detecting an output current of a voltage type PWM inverter device capable of performing the detected current.

In order to solve the above-mentioned problem, the present invention is based on the sampling current value, the current change in the carrier half-cycle obtained from the two sampling current values, and the half-cycle of the PWM carrier. This is an estimation of the output current after the lapse of T _ne and is characterized by the following method.

(1) An output current detection method for detecting an output current of a voltage type PWM inverter device by sampling and feeding back the detected output current value to a control circuit to automatically control the output current,
A procedure for detecting a current value sampled at the peak of the PWM carrier wave;
Based on the sampling current value, the current change in the carrier half-cycle obtained from the two consecutive sampling current values, and the PWM carrier half-cycle, the output current after the elapse of time T _ne is estimated from the sampling timing And a procedure for performing.

(2) The current value has a filter processing procedure in which the detected current is an average of a plurality of current values sampled at a symmetric time around the time of the peak of the carrier near the peak of the carrier. To do.

(3) The detection of the current value has a filtering process procedure in which an average of current values sampled over a plurality of PWM carrier wave periods is used as a detection current.

As described above, according to the present invention, the time from the sampling timing is determined based on the sampling current value, the current change in the carrier half-cycle obtained from the two consecutive sampling current values, and the PWM carrier half-cycle. to estimate the output current after T _ne course, the frequency of the carrier, it is the current detected at any time without being constrained to the vertex timing, he is possible to shorten the feedback calculation cycle, improved control performance .

  Furthermore, current detection can be performed by automatically adjusting the variation of the current detection system for each apparatus, and current detection accuracy is improved.

  Furthermore, the current value is determined by taking the average of the current values sampled multiple times at the symmetrical time around the peak time of the carrier wave as the detection current near the peak of the carrier wave, over a plurality of PWM carrier wave periods. By using the average of the sampled current values as the detection current, detection with improved noise resistance can be performed.

(Embodiment 1)
FIG. 1 is a waveform diagram of each part showing an output current detection method of a voltage type PWM inverter device. In this embodiment, output current detection that estimates the current value at the time of feedback calculation from the current value sampled at the top of the carrier wave and the on-time ratio of the gate signal so that the feedback calculation can be performed in a cycle shorter than the half cycle of the carrier wave Process. In addition, although the following description is a case where it applies to a single phase inverter apparatus, it is applicable also to the electric current detection of a three phase inverter apparatus.

  In the voltage-type PWM inverter device shown in FIG. 5, the set of semiconductor switches SW1 and SW4 and the set of SW2 and SW3 of the inverter device 1 are turned on and off at the same time, and the set of SW1 and SW4 and the set of SW2 and SW3 The description will be made assuming that the set of gate signals operate in a complementary manner. In the following text, “ON” means SW1. It is assumed that SW4 is turned on, SW2 and SW3 are turned off, and the load current IL increases.

In each waveform shown in FIG. 1, the gate signals of the switches SW1 and SW4 and the gate signals of the switches SW2 and SW3 are generated by comparing the magnitudes of the PWM carrier wave and the AC output signal wave. It is assumed that the current values I _n−1 , I _n , and I _{n + 1} sampled at the vertices t _n−1 , t _n , and t _{n + 1} of the carrier wave can detect the average value of the current.

Here, the current _Ine at time t _ne at an arbitrary sampling timing is estimated by the following method. This estimation calculation is realized by a computer resource mounted on the control circuit 2 and software that performs digital calculation using the computer resource. However, a hardware configuration may be used.

First, just before the carrier of the current value sampled at vertex I _n-1, I _n and therebetween on the time t _ne for estimating the current, from off-time, obtaining the current rate of change in on. The current that was I _n-1 at the time t _n-1 once decreased during the off period Toff _n-1 , and then increased to I _n-1 over the same time as Toff _n-1 during the on period. It becomes I _n by Ton _n-1 -Toff _{n-1 of the} remaining ON period. The current increment ΔI _n-1 is caused by Ton _n-1 −Toff _n−1 = T _n−1 −2 × Toff _n−1 . Therefore, the current change rate an _n-1 during the ON state is _{expressed by} equation (1).

a _n-1 = ΔI _n-1 / (T _n-1 -2 × Toff _n-1 ) (1)
Assuming that the on-state current change rate is the same as an _-1 during the period from time t _n to t _{n + 1} , the estimated value of the current increment ΔI _n is given by equation (2) from equation (1).

ΔI _n = a _n−1 × (T _n−1 −2 × Toff _n−1 ) (2)
Therefore, the average current estimated value I _ne at a certain time t _ne in the period from the time t _n to t _{n + 1} is expressed by Equation (3).

I _ne = I _n + ΔI _n × T _ne / T _n (3)
Therefore, the output current detection voltage-type PWM inverter apparatus, a sampling current value, a current change in the carrier wave half cycle obtained from the two sampling current values, and the half cycle of the PWM carrier, on the basis of the sampling timing The output current after elapse of time T _ne can be estimated. In feedback control based on the detected current value after the lapse of time T _ne from this sampling timing , the control performance can be improved by control with a short computation cycle without being restricted by the cycle of the carrier wave.

(Embodiment 2)
FIG. 2 is a waveform diagram of each part showing a method for adjusting the sampling delay time of the current detection system. In the present embodiment, the sampling delay time is obtained by the following procedure and the sampling timing is adjusted before the inverter device is operated.

  (Procedure 1) As the gate signals of SW1, SW4 and SW2, SW3, a gate signal having an on / off ratio of 50% is generated to operate the inverter device.

(Procedure 2) As the sampling delay time T _sd of the current detection system, the deviation I _err between the current detection values at the peak of the carrier (time t _{n-1 in} FIG. 2) and the peak of the valley (time t _{n in} FIG. 2) is calculated. .

(Step 3) I _n-1 sampled delayed by the delay time T _sd from the summit point of the Whereas decreases with a large delay time T _sd, I _n sampled by T _sd delayed root apex is T Increasing _sd increases. Therefore, the absolute value of the deviation I _err is minimized by increasing the delay time T _sd when I _n−1 > I _n and decreasing the delay time T _sd when I _n−1 <I _n. The delay time T _sd is calculated, and this delay time T _sd is set as the sampling timing.

  Therefore, in the output current detection of the voltage type PWM inverter device, in order to sample the current value in consideration of the delay of the detection system, the inverter device is operated with the gate signal having an on / off ratio of 50%. By sampling with a delay time in which the absolute value of the deviation between the current value detected at the peak of the PWM carrier wave and the current value detected at the peak of the valley is minimized, the current detection accuracy can be improved.

(Modification 1)
In the first or second embodiment, instead of the current value detected at the peak of the PWM carrier wave, the average of the current values sampled a plurality of times at the symmetrical time around the peak time of the carrier wave in the vicinity of the peak of the carrier wave Is applied to the detection current to obtain current detection with improved noise resistance.

For example, as shown in FIG. 3, around the time of the vertex of the carrier wave, an example of sampling of the odd number of times, in order to sample the average current value at time t _n, the time t _n-Ts, t _n, Current sampling is performed at a symmetrical time with respect to the peak of the carrier wave at t _{n + Ts} , and the average value is used as the current detection value.

FIG. 4 shows an example in which even-number sampling is performed. In order to sample the average current value at time t _n , current sampling is performed an even number of times at symmetrical times with respect to the top of the carrier wave at time t _n−Ts , t _n , t _{n + Ts} , and the average value Is the current detection value.

  The time Ts has a minimum value that is longer than the conversion time of the analog-digital converter (ADC), and a maximum value that is shorter than a quarter cycle of the carrier wave.

  Therefore, noise resistance in current detection can be improved by using the current value detected by sampling a plurality of times in the vicinity of the peak of the carrier wave as the sampling current value at the peak time in the first or second embodiment.

(Modification 2)
In the first embodiment or the second embodiment, as the current value detected at the peak of the PWM carrier wave, for example, the current change rate during ON calculated by the equation (1) is used only for the current detection value a _n- 1 once. Since it is easily affected by noise, the filter is obtained by taking a moving average of the current values a _n−1 , a _n−2 , a _n−3 ,... Sampled over a plurality of PWM carrier periods. The processed value is set as a current detection value.

  Therefore, as the sampling current detection value at the vertex time in the first embodiment or the second embodiment, filter processing is performed to take not only the current detection value at the vertex but also a moving average of the current values sampled over a plurality of PWM carrier wave periods. Thus, noise resistance can be improved by removing the influence of noise from the detected current.

FIG. 5 is a waveform diagram of each part showing the output current detection method of Embodiment 1 of the present invention. Each part waveform diagram which shows the delay time adjustment method of Embodiment 2 of this invention. The wave form diagram which shows the filter process of vertex current detection. The wave form diagram which shows the filter process of vertex current detection. The structural example of a voltage type PWM inverter apparatus. Conventional sampling timing.

Explanation of symbols

1 Inverter device 2 Control circuit 3 Load 4 Current detector 5 Sample hold circuit (sampler)
6 Analog-to-digital converter (ADC)

Claims (3)

An output current detection method for automatically detecting an output current of a voltage type PWM inverter device by sampling and feeding back the output current detection value to a control circuit to automatically control the output current,
A procedure for detecting a current value sampled at the peak of the PWM carrier wave;
Based on the sampling current value, the current change in the carrier half-cycle obtained from the two consecutive sampling current values, and the PWM carrier half-cycle, the output current after the elapse of time T _ne is estimated from the sampling timing And a method for detecting an output current of a voltage type PWM inverter device. 2. The filtering process according to claim 1 , wherein the current value has a filter processing procedure in which an average of current values sampled a plurality of times at the target time is used as a detected current around the time of the peak of the carrier near the peak of the carrier. The output current detection method of the voltage type PWM inverter apparatus as described in 2. 2. The output current of the voltage-type PWM inverter device according to claim 1, wherein the detection of the current value has a filtering process procedure in which an average of the sampled current values is detected current over a plurality of PWM carrier wave periods. Detection method.

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