WO2016141724A1 - 一种实时总线及其实现方法 - Google Patents

一种实时总线及其实现方法 Download PDF

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WO2016141724A1
WO2016141724A1 PCT/CN2015/093681 CN2015093681W WO2016141724A1 WO 2016141724 A1 WO2016141724 A1 WO 2016141724A1 CN 2015093681 W CN2015093681 W CN 2015093681W WO 2016141724 A1 WO2016141724 A1 WO 2016141724A1
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bus
boards
board
downlink
buses
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吕建新
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Fiberhome Telecommunication Technologies Co Ltd
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Fiberhome Telecommunication Technologies Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks

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  • the present invention relates to the field of communications technologies, and in particular, to a real-time bus and an implementation method thereof.
  • Some large-scale electronic devices in the communication field usually consist of multiple boards that are inserted into the backplane.
  • the boards are interconnected through the backplane connection, especially in large-capacity optical transmission equipment.
  • the number of boards is usually more than 30. It is very difficult to use one bus to communicate between all boards, especially for some information with low information and high real-time requirements.
  • the existing bus technology has the following problems:
  • the technical problem to be solved by the invention is to solve the complex and real-time implementation of the existing bus technology protocol.
  • Low cost, high backplane and connector cost to reduce the number and cost of signal interconnections between large numbers of boards in large devices, and to meet the real-time requirements of signals between boards.
  • the technical solution adopted by the present invention is to provide a real-time bus, including an uplink bus, a downlink bus, a system clock, and a data forwarding unit.
  • the uplink bus is composed of a plurality of first buses, each of which is connected to a plurality of boards, and each of the first buses determines a transmission rate and a time slot according to the number of boards connected thereto, and adopts Time-division multiplexing is used to transfer data of each board connected to the public board.
  • the downlink bus is composed of a plurality of second buses having the same transmission rate and content, and the second bus is in one-to-one correspondence with the first bus, and is respectively connected to the boards on the first bus;
  • the time slot of the second bus is divided according to the number of all the boards;
  • the system clock is used for synchronizing and sampling data of the bus, and is composed of a frame positioning clock and a sampling clock. Each board uses a sampling clock to transmit and receive data. The time slot segments of different boards are positioned by a frame positioning clock.
  • the data forwarding unit is located on the public board, and receives the information sent by the board on the uplink bus, and the received information is summarized and forwarded to the corresponding time slot of each board on the downlink bus. on.
  • each of the first buses is connected with m-blocks, the rate of the first bus is 1/n sampling clock frequency, n is the total number of device boards/m; the second bus The rate is equal to the sampling clock frequency.
  • the number of boards connected to each of the first buses is different, the rate of the first bus is 1/n sampling clock frequency, n is the total number of device boards / the connection on the first bus The number of boards; the rate of the second bus is equal to the sampling clock frequency.
  • each board In the real-time bus, each board outputs the information of the board in the corresponding time slot segment, and is transmitted to the data forwarding unit on the public board through each uplink bus, and the remaining period is high impedance; the data is The forwarding unit forwards the downlink data of all the boards to the downlink bus, and each board receives the corresponding downlink data in the time slot corresponding to the downlink bus.
  • the invention also provides a real-time bus implementation method, the implementation method comprising the following steps:
  • Step 201 The uplink bus is composed of a plurality of first buses, and the first bus is connected to a plurality of boards and connected to a common board;
  • Step 202 The downlink bus is composed of a plurality of second buses having the same transmission rate and content, and the second bus is in one-to-one correspondence with the first bus, and the second bus is respectively connected to a plurality of boards and The public board is connected;
  • Step 203 The boards output the information of the board in the corresponding time slot segments, and transmit the information to the data forwarding unit on the public board through the uplink bus, and the other periods are high-resistance;
  • Step 204 The data forwarding unit forwards the received information to the time slot segment corresponding to each board on the downlink bus, and forwards the downlink data of all the boards to the downlink bus. Each board receives corresponding downlink data in a time slot corresponding to the downlink bus.
  • the real-time bus synchronizes and samples the data through the system clock, and each board uses the sampling clock to perform data transmission and reception sampling, and the time slot segments of different boards are positioned by the frame positioning clock.
  • the data forwarding unit is located on the public board, receives information sent by the board on the uplink bus, and summarizes the received information and forwards the information to the downlink bus.
  • the slot segment corresponding to the board.
  • the number of boards connected to each of the first buses is different, the rate of the first bus is 1/n sampling clock frequency, n is the total number of device boards / the connection on the first bus The number of boards; the rate of the second bus is equal to the sampling clock frequency.
  • each of the first buses determines a transmission rate and a time slot division according to the number of boards connected thereto, and transmits data of each board connected to the public board in a time division multiplexing manner;
  • the time slot of each of the second buses is divided according to the number of all boards.
  • the bus is applied to complex electronic devices, in particular large-capacity communication devices.
  • the information of all the boards can be interconnected.
  • the utility model has the advantages of simple structure, simple protocol, low cost, strong real-time performance, and a large number of connected boards, which greatly simplifies the number of lines interconnected by the back board and reduces the back. Board and connector costs increase equipment reliability.
  • FIG. 1 is a structural diagram of a real-time bus according to an embodiment of the present invention
  • FIG. 2 is a flowchart of a method for implementing a real-time bus according to an embodiment of the present invention.
  • the embodiment of the invention provides a real-time bus, as shown in FIG. 1 , including an uplink bus, a downlink bus, a system clock, and a data forwarding unit.
  • the uplink bus is composed of a plurality of first buses, each of which is connected to a plurality of boards, and each of the first buses determines a transmission rate and a time slot according to the number of boards connected thereto, and adopts Time-division multiplexing transfers data from each board connected to the public board.
  • the downlink bus is composed of a plurality of second buses having the same transmission rate and content, and the second bus is in one-to-one correspondence with the first bus, and is respectively connected to the boards on the first bus;
  • the time slots of the second bus are divided according to the number of all boards.
  • Each of the first buses is connected with an m-block, the rate of the first bus is 1/n sampling clock frequency, n is the total number of device boards/m; the rate of the second bus is equal to the sampling clock frequency. .
  • the number of the boards connected to the first bus is different, the rate of the first bus is 1/n sampling clock frequency, and n is the total number of device boards/the number of boards connected to the first bus;
  • the rate of the second bus is equal to the sampling clock frequency.
  • the system clock is used for synchronizing and data sampling of the bus, and is composed of a frame positioning clock and a sampling clock.
  • Each board uses a sampling clock for data transmission and reception sampling, and the time slot segments of different boards are positioned by a frame positioning clock.
  • the data forwarding unit is located on the public board, and receives the information sent by the board on the uplink bus, and the received information is summarized and forwarded to the corresponding time slot of each board on the downlink bus. on.
  • Each board outputs the information of the board in the corresponding time slot segment, and is transmitted to the data forwarding unit on the public board through the uplink bus, and the remaining time period is high resistance; the data forwarding unit will all the boards.
  • the downlink data is forwarded to the downlink bus, and each board receives corresponding downlink data in a time slot corresponding to the downlink bus.
  • the optical transmission device is generally composed of a control board, a cross-connect board, and a service processing board.
  • the control board is a mandatory board in the device and is responsible for the management and control of the entire device. Configuration. Assume that there are 40 services, cross-boards and two control boards in the device.
  • the real-time bus of this solution can be divided into four buses according to the single-board arrangement and the driving capability of the single-board bus interface, that is, four uplink buses and four.
  • the root downlink bus, at this time n 4, hangs 10 boards on each bus.
  • the bus structure is shown in Figure 1. If the sampling clock frequency of the device is 19.44MHz, the rate of each uplink bus is 1/4 sampling clock.
  • the frequency which is 4.86 Mb/s, is equal to the sampling clock frequency, which is 19.44 Mb/s.
  • Each uplink bus is connected to 10 boards, that is, divided into 10 time slot segments, and the total number of boards connected to the downlink bus is 40, that is, divided into 40 time slot segments (excluding 2 control boards), or 42 time slot segments. (including 2 control panels).
  • the optical transmission device generally has a system clock of 19.44 MHz and a frame positioning clock of 19.44 MHz, which can be used as a synchronous clock and a frame positioning clock of the real-time bus, and a frame positioning clock is used to locate a data slot.
  • the bus is applied to a complex electronic device, in particular, a large-capacity communication device, which can realize interworking of information between all boards, has a simple structure, simple implementation protocol, low cost, strong real-time performance, and connection.
  • the number of boards is large, which greatly simplifies the number of lines interconnected by the backplane, reduces the cost of the backplane and connectors, and improves the reliability of the equipment.
  • the embodiment of the invention further provides a real-time bus implementation method. As shown in FIG. 2, the implementation method includes the following steps:
  • Step 201 The uplink bus is composed of a plurality of first buses, and the first bus is separately connected. Connect a number of boards and connect them to the public board;
  • Step 202 The downlink bus is composed of a plurality of second buses having the same transmission rate and content, and the second bus is in one-to-one correspondence with the first bus, and the second bus is respectively connected to a plurality of boards and The public board is connected;
  • Step 203 The boards output the information of the board in the corresponding time slot segments, and transmit the information to the data forwarding unit on the public board through the uplink bus, and the other periods are high-resistance;
  • Step 204 The data forwarding unit forwards the received information to the time slot segment corresponding to each board on the downlink bus, and forwards the downlink data of all the boards to the downlink bus. Each board receives corresponding downlink data in a time slot corresponding to the downlink bus.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
  • Bus Control (AREA)

Abstract

本发明公开了一种实时总线及其实现方法,包括以下步骤：上行总线由多根第一总线组成，将第一总线连接若干单板并与公共单板连接；下行总线由传输速率和内容相同的多根第二总线组成，第二总线与第一总线一一对应，将第二总线分别连接若干单板并与公共单板连接；各单板在对应的时隙段输出信息，并经上行总线传输给数据转发单元接收，其余时段高阻；数据转发单元将接收到的信息汇总在一起转发到下行总线上各单板对应的时隙段上，并将所有单板的下行数据转发到下行总线，各单板在对应的时隙段接收下行数据。本发明，具有结构简单、成本低、实时性强、连接单板数量多等优点，简化了背板互连的线数量，降低了背板和连接器成本，提高了设备可靠性。请发明人仔细审核。

Description

一种实时总线及其实现方法 技术领域
本发明涉及通信技术领域，具体涉及一种实时总线及其实现方法。
背景技术
通信领域的一些大型电子设备，通常由多块单板组成，这些单板插装在背板，单板之间通过背板连线进行信号互连，特别是在大容量光传输设备中，单板数量通常多达30块以上，采用一根总线实现所有单板之间的通信非常困难,尤其是对于一些信息量不大、实时性要求较高的信息。
现有的总线技术很多，如CAN(Controller Area Network,控制器局域网)总线和I2C总线等，这些技术在工业电子、通信设备等领域都已广泛应用，但是，存在实现协议复杂、实时性较低、背板和连接器的成本较高的缺点，对一些互连信息量不大、实时性要求高等的场合，不是很适合。通信设备中单板数量很多，要求各单板之间实时通告在位和告警等信息，通过单板之间点对点互连，连线数量太多，显然难以实现，采用CAN和I2C总线等技术互连，又存在协议复杂，实时性难以保证等问题，所以现有的总线技术不适合大数量单板之间的通信。
综上所述，现有的总线技术存在如下问题：
(1)实现协议复杂；
(2)实时性较低；
(3)背板和连接器的成本较高。
发明内容
本发明所要解决的技术问题是解决现有的总线技术实现协议复杂、实时 性较低、背板和连接器的成本较高的问题，以降低大型设备中大数量单板之间信号互连线的数量和成本，满足单板之间信号的实时性要求。
为了解决上述技术问题，本发明所采用的技术方案是提供一种实时总线，包括上行总线、下行总线、系统时钟和数据转发单元，
所述上行总线由多根第一总线组成，每根所述第一总线分别连接若干块单板，每根所述第一总线根据与其连接的单板数量确定传输速率以及时隙划分，并采用时分复用的方式将与其连接的各单板的数据传输给公共单板；
所述下行总线由传输速率和内容完全相同的多根第二总线组成，所述第二总线与所述第一总线一一对应，并分别与所述第一总线上的单板连接；每根所述第二总线的时隙根据所有单板的数量划分；
所述系统时钟用于对总线进行同步和数据采样，由帧定位时钟和采样时钟组成，各单板采用采样时钟进行数据发送和接收采样，不同单板的时隙段采用帧定位时钟定位；
所述数据转发单元位于所述公共单板上，接收所述上行总线上的单板发送的信息，并将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上。
在上述实时总线中，每根所述第一总线上连接有m块单板，所述第一总线的速率为1/n采样时钟频率，n为设备单板总数/m；所述第二总线的速率等于采样时钟频率。
在上述实时总线中，每根所述第一总线上连接的单板数量不同，所述第一总线的速率为1/n采样时钟频率，n为设备单板总数/所述第一总线上连接的单板数量；所述第二总线的速率等于采样时钟频率。
在上述实时总线中，各单板在各自对应的时隙段输出本单板的信息，并经各上行总线传输给所述公共单板上的数据转发单元接收，其余时段高阻；所述数据转发单元将所有单板的下行数据一并转发到所述下行总线，各单板在下行总线对应的时隙段接收相应的下行数据。
本发明还提供了一种实时总线的实现方法，所述实现方法包括以下步骤：
步骤201、所述上行总线由多根第一总线组成，将所述第一总线分别连接若干单板并与公共单板进行连接；
步骤202、所述下行总线由传输速率和内容完全相同的多根第二总线组成，所述第二总线与所述第一总线一一对应，将所述第二总线分别连接若干单板并于公共单板进行连接；
步骤203、各单板在各自对应的时隙段输出本单板的信息，并经各所述上行总线传输给所述公共单板上的数据转发单元接收，其余时段高阻；
步骤204、所述数据转发单元将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上，并将所有单板的下行数据一并转发到所述下行总线，各单板在下行总线对应的时隙段接收相应的下行数据。
在上述实现方法中，所述实时总线通过系统时钟对总线进行同步和数据采样，各单板采用采样时钟进行数据发送和接收采样，不同单板的时隙段采用帧定位时钟定位。
在上述实现方法中，所述数据转发单元位于所述公共单板上，接收所述上行总线上的单板发送的信息，并将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上。
在上述实现方法中，每根所述第一总线上连接的单板数量不同，所述第一总线的速率为1/n采样时钟频率，n为设备单板总数/所述第一总线上连接的单板数量；所述第二总线的速率等于采样时钟频率。
在上述实现方法中，每根所述第一总线根据与其连接的单板数量确定传输速率以及时隙划分，并采用时分复用的方式将与其连接的各单板的数据传输给公共单板；每根所述第二总线的时隙根据所有单板的数量划分。
本发明,所述总线应用于复杂的电子设备上，特别是大容量的通信设备 上，可以实现所有单板之间信息的互通，具有结构简单、实现协议简单、成本低、实时性强、连接单板数量多等优点，大大简化了背板互连的线数量，降低了背板和连接器成本，提高了设备的可靠性。
附图说明
图1为本发明实施例提供的实时总线结构图；
图2为本发明实施例提供的一种实时总线的实现方法流程图。
具体实施方式
下面结合说明书附图和具体实施方式对本发明做出详细的说明。
本发明实施例提供了一种实时总线，如图1所示，包括上行总线、下行总线、系统时钟和数据转发单元，
所述上行总线由多根第一总线组成，每根所述第一总线分别连接若干块单板，每根所述第一总线根据与其连接的单板数量确定传输速率以及时隙划分，并采用时分复用的方式将与其连接的各单板的数据传输给公共单板。
所述下行总线由传输速率和内容完全相同的多根第二总线组成，所述第二总线与所述第一总线一一对应，并分别与所述第一总线上的单板连接；每根所述第二总线的时隙根据所有单板的数量划分。
每根所述第一总线上连接有m块单板，所述第一总线的速率为1/n采样时钟频率，n为设备单板总数/m；所述第二总线的速率等于采样时钟频率。
每根所述第一总线上连接的单板数量不同，所述第一总线的速率为1/n采样时钟频率，n为设备单板总数/所述第一总线上连接的单板数量；所述第二总线的速率等于采样时钟频率。
所述系统时钟用于对总线进行同步和数据采样，由帧定位时钟和采样时钟组成，各单板采用采样时钟进行数据发送和接收采样，不同单板的时隙段采用帧定位时钟定位。
所述数据转发单元位于所述公共单板上，接收所述上行总线上的单板发送的信息，并将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上。
各单板在各自对应的时隙段输出本单板的信息，并经各上行总线传输给所述公共单板上的数据转发单元接收，其余时段高阻；所述数据转发单元将所有单板的下行数据一并转发到所述下行总线，各单板在下行总线对应的时隙段接收相应的下行数据。
下面以光传输设备举例说明，光传输设备一般由控制板、交叉板和业务处理板组成，控制板是设备中的必配单板，负责整个设备的管理和控制，其余单板可根据业务需求配置。假设设备中有40块业务、交叉单板和2块控制板，采用本方案的实时总线，可以依据单板排列和单板总线接口的驱动能力，分4根总线，即4根上行总线和4根下行总线，此时n＝4，在每根总线上挂10块单板，总线结构如图1所示，如设备采样时钟频率为19.44MHz，则每根上行总线速率为1/4采样时钟频率，即4.86Mb/s，下行总线速率等于采样时钟频率，即19.44Mb/s。每根上行总线连接10块单板，即分成10个时隙段，下行总线连接的单板总数为40，即分成40个时隙段(不包括2块控制板)，或42个时隙段(包括2块控制板)。光传输设备一般有系统时钟19.44MHz和帧定位时钟19.44MHz，可作为本实时总线的同步时钟和帧定位时钟，帧定位时钟用于定位数据时隙段。
本发明,所述总线应用于复杂的电子设备上，特别是大容量的通信设备上，可以实现所有单板之间信息的互通，具有结构简单、实现协议简单、成本低、实时性强、连接单板数量多等优点，大大简化了背板互连的线数量，降低了背板和连接器成本，提高了设备的可靠性。
本发明实施例还提供了一种实时总线的实现方法，如图2所示，所述实现方法包括以下步骤：
步骤201、所述上行总线由多根第一总线组成，将所述第一总线分别连 接若干单板并与公共单板进行连接；
步骤202、所述下行总线由传输速率和内容完全相同的多根第二总线组成，所述第二总线与所述第一总线一一对应，将所述第二总线分别连接若干单板并与公共单板进行连接；
步骤203、各单板在各自对应的时隙段输出本单板的信息，并经各所述上行总线传输给所述公共单板上的数据转发单元接收，其余时段高阻；
步骤204、所述数据转发单元将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上，并将所有单板的下行数据一并转发到所述下行总线，各单板在下行总线对应的时隙段接收相应的下行数据。
本发明不局限于上述最佳实施方式，任何人应该得知在本发明的启示下作出的结构变化，凡是与本发明具有相同或相近的技术方案，均落入本发明的保护范围之内。

Claims (9)

  1. 一种实时总线，包括上行总线、下行总线、系统时钟和数据转发单元,其特征在于，
    所述上行总线由多根第一总线组成，每根所述第一总线分别连接若干块单板，每根所述第一总线根据与其连接的单板数量确定传输速率以及时隙划分，并采用时分复用的方式将与其连接的各单板的数据传输给公共单板；
    所述下行总线由传输速率和内容完全相同的多根第二总线组成，所述第二总线与所述第一总线一一对应，并分别与所述第一总线上的单板连接；每根所述第二总线的时隙根据所有单板的数量划分；
    所述系统时钟用于对总线进行同步和数据采样，由帧定位时钟和采样时钟组成，各单板采用采样时钟进行数据发送和接收采样，不同单板的时隙段采用帧定位时钟定位；
    所述数据转发单元位于所述公共单板上，接收所述上行总线上的单板发送的信息，并将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上。
  2. 如权利要求1所述的实时总线，其特征在于，每根所述第一总线上连接有m块单板，所述第一总线的速率为1/n采样时钟频率，n为设备单板总数/m；所述第二总线的速率等于采样时钟频率。
  3. 如权利要求1所述的实时总线，其特征在于，每根所述第一总线上连接的单板数量不同，所述第一总线的速率为1/n采样时钟频率，n为设备单板总数/所述第一总线上连接的单板数量；所述第二总线的速率等于采样时钟频率。
  4. 如权利要求1所述的实时总线，其特征在于，
    各单板在各自对应的时隙段输出本单板的信息，并经各上行总线传输给所述公共单板上的数据转发单元接收，其余时段高阻；所述数据转发单元将所有单板的下行数据一并转发到所述下行总线，各单板在下行总线对应的时 隙段接收相应的下行数据。
  5. 一种实时总线的实现方法，其特征在于，所述实现方法包括以下步骤：
    步骤201、所述上行总线由多根第一总线组成，将所述第一总线分别连接若干单板并与公共单板进行连接；
    步骤202、所述下行总线由传输速率和内容完全相同的多根第二总线组成，所述第二总线与所述第一总线一一对应，将所述第二总线分别连接若干单板并与公共单板进行连接；
    步骤203、各单板在各自对应的时隙段输出本单板的信息，并经各所述上行总线传输给所述公共单板上的数据转发单元接收，其余时段高阻；
    步骤204、所述数据转发单元将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上，并将所有单板的下行数据一并转发到所述下行总线，各单板在下行总线对应的时隙段接收相应的下行数据。
  6. 如权利要求5所述的实现方法，其特征在于，所述实时总线通过系统时钟对总线进行同步和数据采样，各单板采用采样时钟进行数据发送和接收采样，不同单板的时隙段采用帧定位时钟定位。
  7. 如权利要求5所述的实现方法，其特征在于，所述数据转发单元位于所述公共单板上，接收所述上行总线上的单板发送的信息，并将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上。
  8. 如权利要求5所述的实现方法，其特征在于，每根所述第一总线上连接的单板数量不同，所述第一总线的速率为1/n采样时钟频率，n为设备单板总数/所述第一总线上连接的单板数量；所述第二总线的速率等于采样时钟频率。
  9. 如权利要求5所述的实现方法，其特征在于，每根所述第一总线根据与其连接的单板数量确定传输速率以及时隙划分，并采用时分复用的方式将与其连接的各单板的数据传输给公共单板；每根所述第二总线的时隙根据 所有单板的数量划分。
PCT/CN2015/093681 2015-03-09 2015-11-03 一种实时总线及其实现方法 Ceased WO2016141724A1 (zh)

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