WO2016132733A1

WO2016132733A1 - Host device, slave device, semiconductor interface device, and removable system

Info

Publication number: WO2016132733A1
Application number: PCT/JP2016/000781
Authority: WO
Inventors: 小野　正
Original assignee: パナソニックＩｐマネジメント株式会社
Priority date: 2015-02-16
Filing date: 2016-02-16
Publication date: 2016-08-25

Abstract

This removable system is formed from a host device, and a slave device capable of being attached to and detached from the host device. When a first power supply, a second power supply, and a clock signal from the connected host device are all detected by the slave device, the slave device controls a first signal line to a low level. When the host device detects that the first signal line is at the low level, the host device drives a second signal line at a low level. When the slave device subsequently detects that the second signal line is at the low level, the slave device stops driving the first signal line controlled to the low level and executes initialization.

Description

Host device, slave device, interface semiconductor device, and removable system

The present disclosure relates to a host device and a slave device that can be connected to each other, an interface semiconductor device that is one of the components of the host device and the slave device, and a removable system that includes the host device and the slave device.

In recent years, slave devices such as a card-shaped SD card and a memory stick, which have a large-capacity nonvolatile memory element such as a flash memory and can process data at high speed, have become popular in the market. Such slave devices are used in personal computers, smartphones, digital cameras, audio players, car navigation systems, and the like, which are host devices that can use the slave devices.

For example, Patent Document 1 discloses a technique for selecting an operating voltage from a plurality of interface voltages in a communication system using a host device and a slave device.

Patent Document 2 uses an electronic device (slave device) depending on whether the power is ON or OFF and whether a specific signal line is at a high level or a low level. A technique for determining an interface circuit to perform is disclosed.

International Publication No. 2009/107400 JP 2003-337639 A

In a communication system using a host device and a slave device, it is effective to reduce the interface voltage in order to improve the interface processing speed. Furthermore, with the recent miniaturization of semiconductor processes, there is an increasing demand for introducing a semiconductor device limited to a lower interface voltage, particularly in a host device. On the other hand, there is also a demand for maintaining interface compatibility so that existing interfaces that are popular in the market can be used continuously.

When trying to satisfy these conditions at the same time, there is a possibility that a slave device with a new interface corresponding to an interface voltage relatively lower than that of the existing interface is erroneously attached to a host device with an existing interface. Similarly, a slave device with an existing interface may be erroneously attached to a host device with a new interface corresponding to an interface voltage that is relatively lower than the existing one.

And, there is a possibility that a new interface-side device is destroyed by a relatively high interface voltage generated by the existing interface-side device.

This disclosure provides a host device, a slave device, an interface semiconductor device, and a removable system that can be used safely even if the interface voltage of the single-ended system is reduced while maintaining the compatibility of the interface.

This disclosure includes an interface unit that can be mechanically connected to any of the first slave device, the second slave device, and the third slave device as a host device. The first slave device corresponds to the first interface, the second slave device corresponds to the second interface having a different signal system from the first interface, and the third slave device corresponds to the first interface and the signal. Although the method is the same, it corresponds to the third interface having a signal voltage lower than the signal voltage of the first interface. In addition, the voltage level of the second signal line depends on the voltage level of the first signal line after supplying the first power source, the second power source, and the clock signal to the slave device connected to the interface unit. The control part which controls is provided. When the control unit detects that the voltage level of the first signal line is different from that before supplying the first power source, the second power source, and the clock signal, the control unit sets the voltage level of the second signal line. The first power source, the second power source, and the clock signal are controlled at different levels. After that, when it is detected that the voltage level of the first signal line is the same level as that before supplying the first power source, the second power source, and the clock signal, the control unit detects the second signal line. The voltage level is controlled to the same level as before supplying the first power source, the second power source, and the clock signal.

Also, the present disclosure includes an interface unit that can be mechanically connected to any of the first host device, the second host device, and the third host device as a slave device. The first host device corresponds to the first interface, the second host device corresponds to the second interface having a different signal system from the first interface, and the third host device corresponds to the first interface and the signal. Although the method is the same, it corresponds to the third interface having a signal voltage lower than the signal voltage of the first interface. In addition, a control unit that controls the voltage level of the first signal line is provided. When the control unit detects all of the first power source, the second power source, and the clock signal from the host device connected to the interface unit, the control unit sets the voltage level of the first signal line to the first power source, the second power source, and the second power source. The power is controlled to a level different from that before the clock signal is supplied. In addition, when it is detected that the voltage level of the second signal line is different from that before supplying the first power source, the second power source, and the clock signal, the control unit detects the first signal line. Is controlled to the same level as before detecting the first power source, the second power source, and the clock signal.

The present disclosure also provides a host device that can be mechanically connected to any of the first slave device, the second slave device, and the third slave device as a removable system, and the first host device and the second host device. And a slave device that can be mechanically connected to any of the third host devices. The first slave device corresponds to the first interface, the second slave device corresponds to the second interface having a different signal system from the first interface, and the third slave device corresponds to the first interface and the signal. Although the method is the same, it corresponds to the third interface having a signal voltage lower than the signal voltage of the first interface. The first host device corresponds to the first interface, the second host device corresponds to the second interface having a different signal system from the first interface, and the third host device corresponds to the first interface and the signal. Although the method is the same, it corresponds to the third interface having a signal voltage lower than the signal voltage of the first interface. In addition, in the removable system of the present disclosure, the voltage level of the first signal line and the voltage level of the second signal line are controlled. After the host device supplies the first power source, the second power source, and the clock signal to the connected slave device, the voltage level of the first signal line is changed to the first power source and the second power source. , And a level different from that before the clock signal is supplied, the voltage level of the second signal line is set to a level different from that before the first power source, the second power source, and the clock signal are supplied. To control. Further, when it is detected that the voltage level of the first signal line is the same level as before supplying the first power source, the second power source, and the clock signal, the voltage level of the second signal line is detected. Are controlled to the same level as before the first power supply, the second power supply, and the clock signal are supplied.

On the other hand, when the slave device detects all of the first power supply, the second power supply, and the clock signal from the connected host device, the voltage level of the first signal line is set to the first power supply, the second power supply, and so on. And a level different from that before supplying the clock signal. Further, when it is detected that the voltage level of the second signal line is different from the level before supplying the first power source, the second power source, and the clock signal, the voltage level of the first signal line is set. The first power source, the second power source, and the clock signal are controlled to the same level as before detection.

Also, the present disclosure includes an interface unit that can be mechanically connected to any of the first slave device, the second slave device, and the third slave device as a host device. The first slave device corresponds to the first interface, the second slave device corresponds to the second interface having a different signal system from the first interface, and the third slave device corresponds to the first interface and the signal. Although the method is the same, it corresponds to the third interface having a signal voltage lower than the signal voltage of the first interface. In addition, the voltage levels of the predetermined signal lines after supplying the first power source, the second power source, and the clock signal to the slave device connected to the interface unit are the first power source, the second power source, A control unit is provided that issues a command when it is detected that the level is different from that before the power supply and the clock signal are supplied.

Also, the present disclosure includes an interface unit that can be mechanically connected to any of the first host device, the second host device, and the third host device as a slave device. The first host device corresponds to the first interface, the second host device corresponds to the second interface having a different signal system from the first interface, and the third host device corresponds to the first interface and the signal. Although the method is the same, it corresponds to the third interface having a signal voltage lower than the signal voltage of the first interface. In addition, a control unit that controls the voltage level of a predetermined signal line is provided. When the control unit detects all of the first power source, the second power source, and the clock signal from the host device connected to the interface unit, the control unit sets the voltage level of the predetermined signal line to the first power source, the second power source, and the second power source. The level is controlled to a level different from that before supplying the power source and the clock signal. When a command is subsequently received from the host device, the voltage level of the predetermined signal line is controlled to the same level as before detecting the first power source, the second power source, and the clock signal.

The present disclosure also provides a host device that can be mechanically connected to any of the first slave device, the second slave device, and the third slave device as a removable system, and the first host device and the second host device. And a slave device that can be mechanically connected to any of the third host devices. The first slave device corresponds to the first interface, the second slave device corresponds to the second interface having a different signal system from the first interface, and the third slave device corresponds to the first interface and the signal. Although the method is the same, it corresponds to the third interface having a signal voltage lower than the signal voltage of the first interface. The first host device corresponds to the first interface, the second host device corresponds to the second interface having a different signal system from the first interface, and the third host device corresponds to the first interface and the signal. Although the method is the same, it corresponds to the third interface having a signal voltage lower than the signal voltage of the first interface. In addition, in the removable system of the present disclosure, the voltage level of a predetermined signal line is controlled. After the host device supplies the first power source, the second power source, and the clock signal to the connected slave device, the voltage level of the predetermined signal line is changed to the first power source, the second power source, A command is issued when it is detected that the level is different from that before the clock signal is supplied. On the other hand, when the slave device detects all of the first power source, the second power source, and the clock signal from the connected host device, the voltage level of the predetermined signal line is set to the first power source, the second power source, In addition, the level is controlled to be different from that before the clock signal is supplied. Further, when a command is subsequently received from the host device, the voltage level of the predetermined signal line is controlled to the same level as before detecting the first power source, the second power source, and the clock signal.

Also, the present disclosure is an interface semiconductor device including the interface unit and the control unit described above.

According to the present disclosure, a host device, a slave device, an interface semiconductor device, and a removable system that can be used safely while maintaining interface compatibility even when a single-ended interface with a reduced signal voltage is introduced. Can be provided.

FIG. 1 is a block diagram showing a configuration of a conventional removable system composed of a legacy host device and a legacy slave device. FIG. 2 is a diagram for explaining an initialization routine of a removable system composed of a legacy host device and a legacy slave device. FIG. 3A is a diagram for explaining an initialization routine in the non-UHS-I mode. FIG. 3B is a diagram for explaining an initialization routine in the UHS-I mode. FIG. 4 is a block diagram showing a configuration of a removable system including a conventional UHS-II host device and a UHS-II slave device. FIG. 5 is a diagram for explaining an initialization routine of a removable system composed of a UHS-II host device and a UHS-II slave device. FIG. 6 is a block diagram showing a configuration of a removable system including an LV-I host device in which an output signal of a conventional legacy host device is 1.8 V and a legacy slave device. FIG. 7 is a block diagram showing a configuration of a removable system composed of an LV-I host device and an LV-I slave device according to the first embodiment. FIG. 8 is a diagram for explaining an initialization routine of the removable system including the LV-I host device and the LV-I slave device according to the first embodiment. FIG. 9 is a diagram for explaining an initialization routine of a removable system including the LV-I host device and the LV-I slave device according to the second embodiment. FIG. 10 is a block diagram illustrating a configuration of a removable system including an LV-I host device and a legacy slave device according to the third embodiment. FIG. 11 is a diagram illustrating an initialization routine of a removable system composed of an LV-I host device and a legacy slave device according to the third embodiment. FIG. 12 is a block diagram illustrating a configuration of a removable system including an LV-I host device and a UHS-II slave device according to the fourth embodiment. FIG. 13 is a diagram for explaining an initialization routine of a removable system composed of an LV-I host device and a UHS-II slave device according to the fourth embodiment. FIG. 14 is a block diagram illustrating a configuration of a removable system including a legacy host device and an LV-I slave device according to the fifth embodiment. FIG. 15 is a diagram for explaining an initialization routine of a removable system composed of a legacy host device and an LV-I slave device according to the fifth embodiment. FIG. 16 is a block diagram illustrating a configuration of a removable system including a UHS-II host device and an LV-I slave device according to the sixth embodiment. FIG. 17 is a diagram for explaining an initialization routine of a removable system composed of a UHS-II host device and an LV-I slave device according to the sixth embodiment.

Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed description than necessary may be omitted. For example, detailed descriptions of already well-known matters and repeated descriptions for substantially the same configuration may be omitted. This is to avoid the following description from becoming unnecessarily redundant and to facilitate understanding by those skilled in the art.

In addition, the inventor provides the accompanying drawings and the following description in order for those skilled in the art to fully understand the present disclosure, and is not intended to limit the subject matter described in the claims. .

[1. Issues to be solved by the removable system according to the present disclosure]
First, problems to be solved by the removable system according to the present disclosure will be described with reference to FIGS. 1 to 6. Hereinafter, the interface is abbreviated as I / F as appropriate.

[1-1. Configuration of Legacy Host Device and Legacy Slave Device]
FIG. 1 is a block diagram illustrating a configuration of a removable system in which a legacy slave device 120 that can be inserted and removed is connected to a legacy host device 100 that supports a conventional single-ended I / F (hereinafter referred to as a legacy I / F). .

As shown in FIG. 1, the legacy host device 100 includes at least a power supply unit 101 and a legacy I / F semiconductor chip 102. The legacy I / F semiconductor chip 102 includes at least an I / F signal regulator 103, a host device I / F unit 104, and an I / F control unit 105. The I / F signal regulator 103 can also be arranged outside the legacy I / F semiconductor chip 102.

The legacy host device 100 and the legacy slave device 120 are mechanically connected. In addition, the legacy host device 100 is electrically connected to the legacy slave device 120 via the VDD1 line 110 that is a 3.3V power supply line.

The legacy slave device 120 includes at least a legacy I / F semiconductor chip 121 and a back-end module 125. The back-end module 125 refers to a recording medium such as a flash memory or a device such as a wireless communication module. The legacy I / F semiconductor chip 121 includes at least an I / F signal regulator 122, a slave device I / F unit 123, and an I / F control unit 124. Note that the I / F signal regulator 122 can also be disposed outside the legacy I / F semiconductor chip 121.

The host device I / F unit 104 and the slave device I / F unit 123 perform signal communication via a CLK (clock) line 111, a CMD (command) line 112, and a DAT (data) line 113. The DAT line 113 is composed of four signal lines: a DAT0 line 113a, a DAT1 line 113b, a DAT2 line 113c, and a DAT3 line 113d.

FIG. 2 is a diagram for explaining a routine after power-on in the legacy host device 100 and the legacy slave device 120. 3A and 3B are diagrams illustrating details of commands and responses in two types of legacy slave devices 120 (details will be described later).

[1-2. Detailed operation of legacy host device and legacy slave device]
The operation when the legacy slave device 120 is connected to the legacy host device 100 will be described below with reference to FIGS. 1 to 3A and 3B.

At the time of power activation, 3.3V power is supplied from the power supply unit 101 of the legacy host device 100, supplied to the legacy I / F semiconductor chip 102 and the I / F signal regulator 103, and 3.3V via the VDD1 line 110. Power is supplied to the legacy slave device 120. The I / F signal regulator 103 is a device that appropriately converts the voltage of the supplied power supply according to an instruction from the I / F control unit 105 and outputs the converted voltage. The I / F signal regulator 103 outputs the 3.3 V power as it is immediately after the power is turned on, and supplies it to the legacy I / F semiconductor chip 102 and the host device I / F unit 104. The legacy I / F semiconductor chip 102 supplies the supplied 3.3V power to all modules arranged in the legacy I / F semiconductor chip 102 so that each module can be operated. The 3.3V power supplied to the host device I / F unit 104 is the source of the 3.3V signal on the CLK line 111, the CMD line 112, and the DAT line 113 output from the host device I / F unit 104. .

On the other hand, the 3.3 V power supplied to the legacy slave device 120 via the VDD1 line 110 is supplied to the legacy I / F semiconductor chip 121 and the I / F signal regulator 122. The I / F signal regulator 122 is a device that appropriately converts the voltage of the supplied power supply according to an instruction from the I / F control unit 124 and outputs it, and is input immediately after power is supplied from the legacy host device 100. The power is output as it is and supplied to the legacy I / F semiconductor chip 121 and the slave device I / F unit 123. The legacy I / F semiconductor chip 121 supplies the supplied 3.3V power supply to every module arranged in the legacy I / F semiconductor chip 121 so that each module can be operated. The 3.3V power supplied to the slave device I / F unit 123 is a source of the 3.3V signal of the CMD line 112 and the DAT line 113 output from the slave device I / F unit 123. Further, the 3.3V power supplied to the legacy slave device 120 is also supplied to the back-end module 125.

The host device I / F unit 104 of the legacy host device 100 is connected to the slave device I / F unit 123 of the legacy slave device 120 by the CLK line 111, the CMD line 112, and the four DAT lines 113. On the CLK line 111, a single-ended clock signal is transmitted from the legacy host device 100 to the legacy slave device 120. In the CMD line 112, a command for the legacy host device 100 to control the legacy slave device 120 and a response corresponding to each command are transmitted by a single-ended method of 3.3V signal. Basically, the command is transmitted from the legacy host device 100 to the legacy slave device 120, and the response is transmitted from the legacy slave device 120 to the legacy host device 100. Therefore, the CMD line 112 is bidirectional communication.

On the other hand, the DAT line 113 is a signal line for transmitting data contents such as still images and texts at high speed, and is composed of four signal lines. The configuration of the signal line is the same as that of the CMD line 112.

After the power is turned on, the host device I / F unit 104 generates a 3.3 V signal single-ended clock by a 3.3 V (high voltage) power source supplied from the I / F signal regulator 103. Then, after 1 ms or more has elapsed after the power supply output from the power supply unit 101 has stabilized at 3.3 V, the clock is supplied to the slave device I / F unit 123. In addition, the initial state of the signal direction of the CMD line 112 and the DAT line 113 is the direction from the legacy host device 100 to the legacy slave device 120. That is, in the initial state, the terminal on the host device I / F unit 104 side is in the output state, and the terminal on the slave device I / F unit 123 side is in the input state, that is, the high impedance (Hi-Z; release) state. Although not shown, each signal line of the CMD line 112 and the DAT line 113 is connected to the output of the I / F signal regulator 103 via a pull-up resistor, so that the host device I / F unit in the output state When the terminal 104 is not driven to a low level (0) or a high level (1), the terminal transits to a high level by a 3.3V power supply.

Thereafter, the legacy host device 100 enters an initialization routine for performing characteristic confirmation and initialization of the connected legacy slave device 120. The host device I / F unit 104 sends an I / F condition check command 201a, which is a command for checking the I / F condition (for example, the corresponding power supply voltage) of the slave device connected first, to the I / F control unit 105. And transmitted to the slave device I / F unit 123 via the CMD line 112.

The I / F condition check command 201a is transmitted to the I / F control unit 124 via the slave device I / F unit 123. The I / F control unit 124 interprets the content of the command, generates a corresponding I / F condition check command response 201b, and returns it to the legacy host device 100 via the CMD line 112.

Subsequently, the legacy host device 100 transmits an initialization command 202 a to the legacy slave device 120 via the CMD line 112. As in the case of the I / F condition check command 201a, the legacy slave device 120 interprets the content of the command, generates a corresponding initialization command response 202b, and returns it to the legacy host device 100 via the CMD line 112.

Thereafter, though not described in detail, the legacy host device 100 issues a write command 203a through a predetermined initialization process. At this time, after receiving the Write command response 203 b transmitted from the legacy slave device 120, the legacy host device 100 transmits data 203 c to be written to the back-end module 125 of the legacy slave device 120 via the DAT line 113.

In the legacy I / F, there are two types of I / F, non-UHS-I and UHS-I. The non-UHS-I is an I / F of a high voltage signal (hereinafter referred to as a 3.3V signal) in which the signal voltage of the CLK line 111, the CMD line 112, and the DAT line 113 is 3.3V from start to finish. On the other hand, UHS-I uses a 3.3V signal immediately after the power is turned on, and switches to a 1.8V low voltage signal (hereinafter referred to as a 1.8V signal).

A legacy slave device that supports only non-UHS-I is called a non-UHS-I slave device, and a legacy slave device that supports UHS-I and non-UHS-I is called a UHS-I slave device. The legacy host device 100 identifies whether the connected slave device is a non-UHS-I slave device or a UHS-I slave device by the UHS-I support flag. The power supply voltage supplied to the non-UHS-I slave device and the UHS-I slave device via the power supply line is a high voltage power supply of 3.3V.

FIG. 3A and FIG. 3B are diagrams illustrating differences in initialization between a non-UHS-I slave device and a UHS-I slave device. In FIGS. 3A and 3B, the CMD line and the DAT line are shown as if they were one signal line in order to avoid complication.

The initialization command 202a described in FIG. 2 includes a UHS-I support confirmation bit for confirming whether or not a UHS-I slave device is connected. A host device supporting UHS-I can use the UHS-I Set 1 to the I support confirmation bit.

The I / F control unit 124 of the legacy slave device 120 that has received the initialization command 202a returns an initialization command response 202b including at least a UHS-I support flag and an initialization completion flag, and initializes the back-end module 125. Start. The legacy slave device 120 can accept the initialization command 202a many times until the back-end module 125 shifts to the next process during initialization and after completion of initialization. If initialization is in progress, 0 is set to the initialization completion flag of the initialization command response 202b. If initialization has been completed, 1 is set to the initialization completion flag. When the UHS-I support confirmation bit of the initialization command 202a is set to 1, the UHS-I support flag of the non-UHS-I slave device is 0, and the UHS-I support flag of the UHS-I slave device is 1

When the legacy host device 100 receives the initialization command response 202b including the initialization completion flag 1 within a predetermined time (for example, 64 clock periods) after the first initialization command 202a is issued, the legacy host device 100 It is determined that the initialization of the device 120 has been completed.

When the UHS-I support flag in the initialization command response 202b is set to 0, the legacy host device 100 determines that the connected legacy slave device 120 is a non-UHS-I slave device. In this case, between the legacy host device 100 and the legacy slave device 120, the clock transmitted via the CLK line 111, various commands and responses transmitted via the CMD line 112, and the DAT line 113 are transmitted. All of these data are realized by 3.3V signals. In FIG. 3A, the Write command 203a, the Write command response 203b, and the data (content data) 203c are all transmitted by a 3.3V signal.

The communication mode as shown in FIG. 3A is called a non-UHS-I mode.

On the other hand, when the UHS-I support flag of the initialization command response 202b is set to 1, the legacy host device 100 determines that the connected legacy slave device 120 is a UHS-I slave device.

In this case, the legacy host device 100 transmits a voltage switching command 301a to the legacy slave device 120. The I / F control unit 124 that has received the voltage switching command 301a returns a corresponding voltage switching command response 301b, sets all the terminals of the slave device I / F unit 123 to the input state, and then performs an I / F signal regulator. 122 is instructed to use a 1.8V low voltage power supply (hereinafter referred to as a 1.8V power supply).

When the I / F control unit 105 receives the voltage switching command response 301b from the legacy slave device 120, the legacy host device 100 drives all the CLK line 111, the CMD line 112, and the DAT line 113 to the low level (0). And the I / F signal regulator 103 is instructed to use a 1.8 V power supply.

Thereafter, a clock based on the 1.8V signal is transmitted to the CLK line 111, and after a predetermined procedure, the legacy host device 100 and the legacy slave device 120 use the CMD line 112 to execute various commands and responses based on the 1.8V signal, The data transmitted through the DAT line 113 is transmitted by a 1.8V signal. In FIG. 3B, the Write command 203a, the Write command response 203b, and the data 203c are all transmitted by a 1.8V signal.

The communication mode as shown in FIG. 3B is referred to as UHS-I mode.

The details of the signal voltage switching sequence accompanying the voltage switching command 301a are disclosed in Patent Document 1.

[1-3. Configuration of UHS-II Host Device and UHS-II Slave Device]
In the single-ended legacy I / F described above, the transmission speed per signal line is limited to about 200 Mbit / sec from the viewpoint of signal quality and EMI (Electro-Magnetic Interference). Therefore, in order to realize a higher transmission speed, a differential serial signal I / F called UHS-II is introduced in the SD card.

FIG. 4 is a block diagram illustrating the configuration of the removable system to which the UHS-II slave device 420 that can be inserted and removed is connected to the UHS-II host device 400. As shown in FIG. 4, the UHS-II host device 400 includes at least a first power supply unit 401, a second power supply unit 402, and a UHS-II semiconductor chip 403. The UHS-II semiconductor chip 403 includes at least an I / F signal regulator 404, a host device I / F unit 405, and an I / F control unit 406. The I / F signal regulator 404 can also be disposed outside the UHS-II semiconductor chip 403.

The UHS-II host device 400 and the UHS-II slave device 420 are mechanically connected. Further, the UHS-II host device 400 is electrically connected to the UHS-II slave device 420 via a VDD2 line 411 which is a 1.8V power supply line in addition to a VDD1 line 410 which is a 3.3V power supply line. .

The UHS-II slave device 420 includes at least a UHS-II semiconductor chip 421 and a back-end module 425. The UHS-II semiconductor chip 421 includes at least an I / F signal regulator 422, a slave device I / F unit 423, and an I / F control unit 424. The I / F signal regulator 422 can also be disposed outside the UHS-II semiconductor chip 421.

The host device I / F unit 405 and the slave device I / F unit 423 perform signal communication via an RCLK (differential reference clock) line 412, a D0 line 413, and a D1 line 414. The D0 line 413 and the D1 line 414 are used only in UHS-II. The RCLK line 412, the D0 line 413, and the D1 line 414 are all differential serial signals having a voltage amplitude of 0.4V.

The RCLK line 412 includes a DAT0 line 113a and a DAT1 line 113b in the legacy I / F.

When the legacy slave device 120 is connected to the UHS-II host device 400, or when the UHS-II slave device 420 is connected to the legacy host device 100, communication can be performed using at least the legacy I / F. Therefore, the UHS-II host device 400 and the UHS-II slave device 420 also have terminals used for the legacy I / F.

In addition, the CLK line, CMD line, DAT2 line, and DAT3 line are not used in UHS-II, but as described above, the UHS-II host device 400 or the UHS-II slave device 420 can operate in the legacy I / F. Electrically connected. On the other hand, the legacy host device 100 and the legacy slave device 120 that do not have the UHS-II function do not include the terminals of the VDD2 line 411, the D0 line 413, and the D1 line 414 that are used only in the UHS-II.

FIG. 5 is a diagram for explaining a routine after the power is turned on in the UHS-II host device 400 and the UHS-II slave device 420.

[1-4. Detailed operation of UHS-II host device and UHS-II slave device]
The operation when the UHS-II slave device 420 is connected to the UHS-II host device 400 will be described below with reference to FIGS.

At the time of power activation, 3.3V power is supplied from the first power supply unit 401 of the UHS-II host device 400 to the UHS-II slave device 420 via the VDD1 line 410. Further, the 1.8 V power supply from the second power supply unit 402 of the UHS-II host apparatus 400 is supplied to the UHS-II semiconductor chip 403 and the I / F signal regulator 404 of the UHS-II host apparatus 400 via the VDD2 line 411. Supplied to the UHS-II slave device 420.

The UHS-II semiconductor chip 403 supplies the supplied 1.8V power to all modules arranged in the UHS-II semiconductor chip 403 so that each module can be operated. The I / F signal regulator 404 is a device that appropriately converts the voltage of the supplied 1.8V power supply and outputs it. In this example, the I / F signal regulator 404 steps down the voltage to 0.4V which is the amplitude of the differential signal. This is the source of the 0.4 V differential serial signals of the RCLK line 412 and the D0 line 413 that are supplied to the unit 405 and output from the host device I / F unit 405.

On the other hand, the 3.3 V power supplied to the UHS-II slave device 420 via the VDD1 line 410 is supplied to the back-end module 425. The 1.8 V power supplied to the UHS-II slave device 420 via the VDD2 line 411 is supplied to the UHS-II semiconductor chip 421 and the I / F signal regulator 422. The UHS-II semiconductor chip 421 supplies the supplied 1.8V power to all modules arranged in the UHS-II semiconductor chip 421 so that each module can be operated. The 1.8 V power supplied to the I / F signal regulator 422 is stepped down to 0.4 V, supplied to the slave device I / F unit 423, and output from the slave device I / F unit 423. This is the source of the 414 0.4V differential serial signal.

The differential reference clock of the differential serial system is transmitted from the UHS-II host device 400 to the UHS-II slave device 420 in one direction by the RCLK line 412 (configured by two signal lines DAT0 and DAT1). In addition, by using the D0 line 413 (configured by two signal lines), a differential serial signal (a symbol composed of a command and data, as well as a specific bit string) is basically transmitted from the UHS-II host device 400 to the UHS- Is transmitted to the II slave device 420. In addition, by means of the D1 line 414 (configured by two signal lines), a differential serial type signal (a symbol composed of a specific bit string in addition to response and data) is basically transmitted from the UHS-II slave device 420 to the UHS- II is transmitted to the host device 400.

5, the UHS-II host device 400 supplies 3.3V power through the VDD1 line 410 and supplies 1.8V power to the UHS-II slave device 420 through the VDD2 line 411. Then, after 1 ms or more has elapsed since the power output from the UHS-II host device 400 has stabilized at VDD1 = 3.3V and VDD2 = 1.8V, a differential reference clock is transmitted via the RCLK line 412. Thereafter, the UHS-II host device 400 generates the STB. The L symbol 501a is transmitted to the UHS-II slave device 420 via the D0 line 413. STB. The I / F control unit 424 of the UHS-II slave device 420 that has correctly recognized the L symbol 501a can detect the STB. BT within a predetermined time T (eg, 200 μs). An L symbol 501b is generated and transmitted to the UHS-II host apparatus 400 via the D1 line 414.

The UHS-II host device 400 is connected to the STB. When the L symbol 501b can be received, it is determined that UHS-II initialization is possible (UHS-II support determination).

Thereafter, although not shown in detail, a series of various commands such as a Write command 503a, a Write command response 503b, and data 503c is passed through a predetermined UHS-II initialization process (such as an initialization command 502a and an initialization command response 502b). Execute the process.

When the UHS-II host device 400 uses the DAT0 line 113a (see FIG. 1) and the DAT1 line 113b (see FIG. 1) as the RCLK line 412, the UHS-II host device 400 disconnects these pull-up resistors and sets the low level (0) or Drive to high level (1). When the UHS-II host device 400 executes UHS-II initialization, the CMD line 112 (see FIG. 1), the DAT2 line 113c (see FIG. 1), and the DAT3 line 113d (see FIG. 1) are set to the low level (0). ) Or high level (1). Realization of the high level may be realized by setting the signal line to the Hi-Z state by a pull-up resistor, or by driving the UHS-II host device 400 to the high level.

Recently, due to miniaturization of the semiconductor process, it is becoming difficult for a semiconductor chip particularly for a host device to cope with a high voltage signal of 3.3V. For this reason, in a removable system composed of an SD card (slave device) and an SD card compatible host device, for example, it is required to introduce an I / F whose input / output is limited to a low voltage signal of 1.8V or less.

On the other hand, many removable systems consisting of SD cards and SD card-compatible host devices are already widely used, and it is the host that replaces the form factors such as signal line layout and slave device size and shape with new ones. Both the device and the slave device are not preferable from the viewpoint of design and manufacture, and it is preferable that the conventional interface can be continuously used.

Here, UHS-II has a signal amplitude that is much lower than 0.4 V and 3.3 V, and satisfies the requirement of being a low voltage signal. However, UHS-II maintains the legacy I / F while maintaining UHS. In order to support −II, it is inevitable to increase the number of terminals of the semiconductor chip of each of the host device and the slave device, which leads to an increase in the cost of the semiconductor chip, and thus the host device and the slave device. Therefore, in addition to the conventional legacy I / F and UHS-II, only the low voltage signal of 1.8V is used without using the 3.3V signal, and the protocol including initialization is the same as the legacy I / F. The introduction of this I / F (hereinafter referred to as LV-I) is desired.

From now on, it is conceivable to introduce an LV-I compatible host device in which the input / output of the legacy I / F semiconductor chip 102 is limited to the low voltage signal (1.8 V) in the legacy host device 100 shown in FIG. FIG. 6 is a block diagram illustrating a configuration of a removable system including the LV-I host device 600 and the legacy slave device 120. The LV-I host device 600 includes at least a power supply unit 601 and an LV-I semiconductor chip 602. The LV-I semiconductor chip 602 includes at least an I / F signal regulator 603, a host device I / F unit 604, and an I / F control unit 605. The difference between the legacy host device 100 of FIG. 1 and the LV-I host device of FIG. 6 is that the upper limit of the input signal withstand voltage of the LV-I semiconductor chip 602 is 1.8V.

However, the following problems occur in the removable system shown in FIG.

The output of the I / F signal regulator 603 of the LV-I host device 600 can be a 1.8V power supply instead of a 3.3V power supply after the power is turned on. On the other hand, when a legacy slave device 120 compatible with 3.3V power supply, which already has many products on the market, is connected to the LV-I host device 600, the 3.3V power supply is connected to the legacy slave device via the VDD1 line 110. 120. As described above, in the legacy slave device 120, the output of the I / F signal regulator 122 immediately after power activation is a 3.3V power supply. Therefore, the legacy slave device 120 returns an I / F condition check command response 201b of the I / F condition check command 201a received for the first time after power activation to the LV-I host device 600 with a 3.3V signal. As a result, a 3.3V signal is input to the LV-I semiconductor chip 602 of the LV-I host device 600, which causes a problem that the LV-I semiconductor chip 602 is destroyed.

This problem can be avoided by proceeding with initialization only when the slave device connected to the LV-I host device is compatible with the LV-I interface, otherwise not performing initialization.

A general method for the host device to detect the characteristics of the slave device is to read a register mounted on the slave device. However, since the register of the slave device is normally valid after the initialization command 202a or the initialization command 502a is used as a trigger, the host device needs to detect the characteristics of the slave device before the initialization is performed. This method cannot be applied to solve this problem.

In order to solve this problem, before the host device issues a command, it is necessary for the slave device to control the specific signal line to a state different from that at the time of power activation and to cause the host device to detect it. .

However, in the existing legacy host device 100 or UHS-II host device 400, there is a signal line whose state at the time of power activation is not clearly defined. For example, when the legacy host device 100 drives the DAT0 line 113a to a high level when the power is turned on, when the legacy slave device 120 drives the DAT0 line 113a to a low level, the voltage is applied from both the legacy host device 100 and the legacy slave device 120. There arises a problem that a signal collision occurs in which signals having different levels are transmitted, which adversely affects both legacy I /

F semiconductor chips

102 and 121.

On the other hand, in the newly introduced LV-I interface, a provision is made that the host device is set to the Hi-Z state without driving the DAT0 line when the power is turned on, and the LV-I slave device is set to LV. -If DAT0 is driven only when connected to the I host device, no signal collision will occur.

The inventor has recognized this problem in the process of developing a removable system and came up with a solution. The details of the solution will be specifically described below. In the following description, the first embodiment and the second embodiment will be described as examples in which the technical idea of the solving means is embodied.

[2. Configuration and Operation of Removable System According to First Embodiment]
[2-1. Constitution]
FIG. 7 is a block diagram illustrating a configuration of a removable system in which an LV-I slave device 720 that can be inserted and removed is connected to the LV-I host device 700 according to the first embodiment. As shown in FIG. 7, the LV-I host device 700 includes at least a first power supply unit 701, a second power supply unit 702, and an LV-I semiconductor chip 703. The LV-I semiconductor chip 703 includes a host device I / F unit 704 and an I / F control unit 705. The upper limit of the input signal withstand voltage of the LV-I semiconductor chip 703 of the LV-I host device 700 is 1.8V.

The LV-I host device 700 and the LV-I slave device 720 are mechanically connected. The LV-I host device 700 is electrically connected to the LV-I slave device 720 via the VDD1 line 710 and the VDD2 line 711, as in the removable system described with reference to FIG.

The LV-I slave device 720 includes at least an LV-I semiconductor chip 721 and a back-end module 724. The LV-I semiconductor chip 721 includes at least a slave device I / F unit 722 and an I / F control unit 723. Further, the slave device I / F unit 722 includes a VDD1 detection unit 722a and a VDD2 detection unit 722b. Note that the VDD1 detection unit 722a and the VDD2 detection unit 722b may be disposed outside the slave device I / F unit 722 or the LV-I semiconductor chip 721.

The host device I / F unit 704 and the slave device I / F unit 722 have a CLK (clock) line 712, a CMD (command) line 713, and a DAT (data) line 714, as in the removable system described in FIG. Signal communication. The DAT line 714 includes four signal lines, a DAT0 line 714a, a DAT1 line 714b, a DAT2 line 714c, and a DAT3 line 714d.

FIG. 8 is a diagram for explaining the operation after power-on in the removable system constituted by the LV-I host device 700 and the LV-I slave device 720 in the present embodiment.

[2-2. Detailed operation]
The operation when the LV-I slave device 720 is connected to the LV-I host device 700 will be described below with reference to FIGS.

When power is turned on, 3.3V power is supplied from the first power supply unit 701 of the LV-I host device 700 to the LV-I slave device 720 via the VDD1 line 710. In addition, 1.8V power is supplied from the second power supply unit 702 of the LV-I host device 700 to the LV-I semiconductor chip 703 and the host device I / F unit 704 of the LV-I host device 700, and further the VDD2 line 711 to the LV-I semiconductor chip 721 of the LV-I slave device 720 and the slave device I / F unit 722.

The LV-I semiconductor chip 703 supplies the supplied 1.8V power to all modules arranged in the LV-I semiconductor chip 703 so that each module can be operated. The 1.8 V power supplied to the host device I / F unit 704 is the source of the 1.8 V signal output from the host device I / F unit 704 on the CLK line 712, the CMD line 713, and the DAT line 714. Become.

On the other hand, the 3.3 V power supplied to the LV-I slave device 720 via the VDD 1 line 710 is supplied to the back-end module 724. Further, the VDD1 detection unit 722a detects the presence or absence of VDD1, and notifies the I / F control unit 723 of the result via the slave device I / F unit 722.

In addition, the 1.8V power supplied from the LV-I host device 700 via the VDD2 line is supplied to the LV-I semiconductor chip 721 and the slave device I / F unit 722. Also, the VDD2 detection unit 722b detects the presence or absence of VDD2, and notifies the I / F control unit 723 of the result via the slave device I / F unit 722.

When the VDD2 detection unit 722b detects that VDD2 is supplied, the LV-I semiconductor chip 721 supplies the supplied 1.8V power to all modules arranged in the LV-I semiconductor chip 721. Thus, each module can be operated. When the VDD2 detection unit 722b detects that VDD2 is supplied, the LV-I semiconductor chip 721 blocks the input of the 3.3V power supplied via the VDD1 line 710.

Similar to the removable system described with reference to FIG. 1, the host device I / F unit 704 of the LV-I host device 700 has a CLK line 712, a CMD line 713, and four DAT lines 714 as slaves of the LV-I slave device 720. A device I / F unit 722 is connected.

In FIG. 8, when the LV-I host device 700 tries to initialize with the LV-I, at least the DAT0 line 714a and the DAT1 line 714b are set to the Hi-Z state. At this time, the DAT0 line 714a and the DAT1 line 714b are both set to the high level (1) by pull-up resistors of the signal lines (not shown).

The LV-I host device 700 supplies 3.3V power via the VDD1 line and supplies 1.8V power to the LV-I slave device 720 via the VDD2 line. The order in which the LV-I host device 700 starts up VDD1 and VDD2 does not matter. Then, after 1 ms or more has elapsed after the power output from the LV-I host device 700 has stabilized at VDD1 = 3.3V and VDD2 = 1.8V, the LV-I host device 700 receives 1 through the CLK line 712. .8V single-ended clock is transmitted to the LV-I slave device 720.

The LV-I slave device 720 detects VDD1 (3.3V power supply) by the VDD1 detection unit 722a, detects VDD2 (1.8V power supply) by the VDD2 detection unit 722b, and detects the CLK line by the slave device I / F unit 722. When the 712 1.8 V single-ended clock is detected, the detection result is supplied to the I / F control unit 723. At this time, the I / F control unit 723 determines that the host device is trying to initialize with the LV-I interface, and sets the DAT0 line 714a to the low level (0) with respect to the slave device I / F unit 722. The drive is instructed (timing 801 in FIG. 8).

After the LV-I host device 700 supplies VDD1, VDD2, and 1.8V single-ended clocks, the host device I / F unit 704 detects that the DAT0 line 714a is at a low level by a predetermined time. This is notified to the I / F control unit 705. Therefore, the I / F control unit 705 determines that the LV-I slave device 720 corresponding to LV-I is connected, and drives the DAT1 line 714b to the low level (0) with respect to the host device I / F unit 704. (Timing 802 in FIG. 8).

When the slave device I / F unit 722 of the LV-I slave device 720 detects that the DAT1 line 714b is at a low level, it notifies the I / F control unit 723 of this. Therefore, the I / F control unit 723 instructs the slave device I / F unit 722 to stop driving the DAT0 line 714a. As a result, the DAT0 line 714a transits to a high level (1) due to the pull-up resistor on the LV-I host device 700 side (timing 803 in FIG. 8).

When the host device I / F unit 704 of the LV-I host device 700 detects that the DAT0 line 714a is at a high level, it notifies the I / F control unit 705 of this. Therefore, the I / F control unit 705 detects that the DAT0 line 714a is not driven by the LV-I slave device 720, and sets the DAT1 that has been set to the low level (0) to the host device I / F unit 704. An instruction is given to stop driving the line 714b (timing 804 in FIG. 8). Subsequently, an I / F condition check command 805a is transmitted to the LV-I slave device 720 via the CMD line 713 in order to perform initialization processing. The I / F condition check command 805a is multiplexed with a parameter including a check bit indicating whether or not it corresponds to at least a 1.8V signal.

Upon receiving the I / F condition check command 805a, the LV-I slave device 720 confirms the parameters multiplexed in the I / F condition check command 805a and then transmits the corresponding I / F condition via the CMD line 713. A check command response 805b is transmitted to the LV-I host device 700. After this process, initialization at the LV-I interface and data exchange by the data 806 are performed.

[2-3. effect]
According to the present embodiment, the LV-I host apparatus 700 supplies the 3.3V power supply VDD1, the 1.8V power supply VDD2, and the 1.8V single-ended clock almost simultaneously. The LV-I slave device 720 that has detected this drives the DAT0 line 714a to a low level, so that the LV-I host device 700 detects that communication by the LV-I interface is possible.

Note that VDD1, VDD2, and a single-ended clock are supplied simultaneously to the LV-I host device 700 at the time of power activation. Since the LV-I host device 700 sets the DAT0 line 714a to the Hi-Z state, even if the LV-I slave device 720 drives the DAT0 line 714a to the low level at the timing 801 in FIG. There is no adverse effect on the I / F unit 704 or the slave device I / F unit 722. Further, by driving the DAT0 line 714a to a low level, it is possible to notify the LV-I host device 700 that the LV-I slave device 720 supports the LV-I interface.

On the other hand, the LV-I host device 700 that has detected that the DAT0 line 714a is at the low level detects that the slave device is the LV-I slave device 720. As a result, it is guaranteed that the response received via the CMD line 713 and the data received via the DAT line 714 are all 1.8V signals. Therefore, even if the LV-I host device 700 continues the subsequent processing, the 3.3V high voltage signal is not supplied to the LV-I host device 700, so the upper limit of the input signal withstand voltage is 1.8V. The host device I / F unit 704 is not destroyed.

In the description of the present embodiment, it is assumed that the DAT0 line 714a and the DAT1 line 714b are connected by a predetermined power source and a pull-up resistor and are at a high level in the Hi-Z state. In addition, when the DAT0 line 714a and the DAT1 line 714b are connected to the ground by a pull-down resistor, and the LV-I host device 700 is in the Hi-Z state, the LV-I slave device detects all of VDD1, VDD2, and CLK. 720 drives the DAT0 line 714a high. The LV-I host device 700 that detects that the DAT0 line 714a is at the high level may drive the DAT1 line 714b to the high level.

[3. Configuration and Operation of Removable System According to Second Embodiment]
[3-1. Constitution]
The configuration is the same as the removable system shown in FIG. 7 described in the first embodiment.

FIG. 9 is a diagram for explaining the operation after power-on in the removable system constituted by the LV-I host device 700 and the LV-I slave device 720 in the present embodiment.

[3-2. Detailed operation]
Hereinafter, the operation when the LV-I slave device 720 is connected to the LV-I host device 700 will be described with reference to FIGS. 7 and 9, particularly different parts from the first embodiment.

In FIG. 9, when the LV-I host device 700 tries to initialize with the LV-I, at least the DAT0 line 714a is set to the Hi-Z state. At this time, the DAT0 line 714a becomes high level by the pull-up resistor.

After the LV-I slave device 720 detects all of VDD1, VDD2, and CLK and drives the DAT0 line 714a to the low level (timing 801 in FIG. 9), the timing at which the I / F condition check command 805a is received (in FIG. 9) At timing 901), the LV-I slave device 720 stops driving the DAT0 line 714a. Subsequent operations are the same as those in the first embodiment.

[3-3. effect]
According to the present embodiment, as in the first embodiment, the LV-I host device 700 generates a VDD1 which is a 3.3V power supply, a VDD2 which is a 1.8V power supply, and a 1.8V single-ended clock. Supply almost simultaneously. The LV-I slave device 720 that has detected this drives the DAT0 line 714a to a low level, so that the LV-I host device 700 detects that communication by the LV-I interface is possible. In the first embodiment, the LV-I host device 700 uses the DAT1 line 714b to notify the timing when the LV-I slave device 720 stops driving the DAT0 line 714a, which has been set to the low level (0). However, the present embodiment is different in that the notification is made by transmission of the I / F condition check command 805a instead of the DAT1 line 714b.

The reason that this embodiment can be implemented is that the host device or slave device uses the DAT line 714 until the exchange of the I / F condition check command 805a and the I / F condition check command response 805b is completed. This is because no transmission is performed.

[4. Configuration and Operation of Removable System According to Third Embodiment]
The LV-I host device and the LV-I slave device described in the third and subsequent embodiments will be described as operating based on the contents described in the first embodiment. It is effective even when it operates based on the contents described in 1.

[4-1. Constitution]
FIG. 10 is a block diagram illustrating a configuration of a removable system in which the legacy slave device 120 that can be inserted and removed is connected to the LV-I host device 700 according to the third embodiment. The configurations of the LV-I host device 700 and the legacy slave device 120 are the same as those described so far.

The LV-I host device 700 and the legacy slave device 120 are mechanically connected. On the other hand, the LV-I host device 700 supplies power via the VDD1 line 1010 and the VDD2 line 1011. However, since the legacy slave device 120 does not have a terminal for the VDD2 line, as a result, only the VDD1 line 1010 is electrically connected. Connected to.

The host device I / F unit 704 and the slave device I / F unit 123 perform signal communication via the CLK line 1012, the CMD line 1013, and the DAT line 1014. The DAT line 1014 includes four signal lines including a DAT0 line 1014a, a DAT1 line 1014b, a DAT2 line 1014c, and a DAT3 line 1014d.

FIG. 11 is a diagram for explaining the operation after power-on in the removable system composed of the LV-I host device 700 and the legacy slave device 120 in this embodiment.

[4-2. Detailed operation]
The operation when the legacy slave device 120 is connected to the LV-I host device 700 will be described below with reference to FIGS.

When power is turned on, 3.3V power is supplied from the first power supply unit 701 of the LV-I host device 700 and supplied to the legacy slave device 120 via the VDD1 line 1010. In addition, 1.8V power is supplied from the second power supply unit 702 of the LV-I host device 700 to the LV-I semiconductor chip 703 and the host device I / F unit 704 of the LV-I host device 700. The 1.8V power is also supplied to the VDD2 line 1011. However, since the legacy slave device 120 does not have the terminal of the VDD2 line 1011, VDD2 is not supplied to the legacy slave device 120 as a result.

The 3.3V power supplied to the legacy slave device 120 via the VDD1 line 1010 is supplied to the legacy I / F semiconductor chip 121 and the back-end module 125, and becomes operable.

In the present embodiment, when the power is turned on, the DAT0 line 1014a and the DAT1 line 1014b of the LV-I host device 700 are in the Hi-Z state, so that each signal line becomes high level (1) by the pull-up resistor. Yes.

After 1 ms or more has elapsed after the power output from the LV-I host device 700 has stabilized at VDD1 = 3.3V and VDD2 = 1.8V, the LV-I host device 700 receives 1.8V via the CLK line 1012. A single-ended clock is transmitted to the legacy slave device 120.

By the way, unlike the LV-I slave device 720 shown in FIG. 7, the legacy slave device 120 does not have a function of driving the DAT0 line 1014a to a low level when all of VDD1, VDD2, and CLK are detected. Therefore, the LV-I host device 700 does not detect that the DAT0 line 1014a is at a low level.

When the LV-I host device 700 does not detect that the DAT0 line 1014a is at the low level by a predetermined time, the LV-I host device 700 does not indicate that the slave device is the LV-I slave device 720, that is, It is determined that the LV-I interface is not supported, and the initialization on the LV-I interface is stopped.

[4-3. effect]
According to the present embodiment, the legacy slave device 120 does not drive the DAT0 line 1014a to a low level immediately after activation. Therefore, the LV-I host device 700 monitors the DAT0 line 1014a and detects that the slave device does not support LV-I if it does not detect a low level by a predetermined time. Do not perform the initialization process. Thus, since a 3.3V high voltage signal is not supplied to the LV-I host device 700 from a slave device that is not the LV-I slave device 720, the upper limit of the input signal withstand voltage is 1.8V. The I / F unit 704 is not destroyed.

[5. Configuration and Operation of Removable System According to Fourth Embodiment]
[5-1. Constitution]
FIG. 12 is a block diagram illustrating a configuration of a removable system in which a UHS-II slave device 420 that can be inserted and removed is connected to the LV-I host device 700 according to the fourth embodiment. The configurations of the LV-I host device 700 and the UHS-II slave device 420 are the same as described above.

The LV-I host device 700 and the UHS-II slave device 420 are mechanically connected. The LV-I host device 700 is electrically connected to the UHS-II slave device 420 via the VDD1 line 1210 and the VDD2 line 1211.

The host device I / F unit 704 and the slave device I / F unit 423 perform signal communication via the CLK line 1212, the CMD line 1213, and the DAT line 1214. The DAT line 1214 includes four signal lines including a DAT0 line 1214a, a DAT1 line 1214b, a DAT2 line 1214c, and a DAT3 line 1214d.

FIG. 13 is a diagram for explaining the operation after the power is turned on in the removable system including the LV-I host device 700 and the UHS-II slave device 420.

[5-2. Detailed operation]
The operation when the UHS-II slave device 420 is connected to the LV-I host device 700 will be described below with reference to FIGS.

At the time of power activation, 3.3V power is supplied from the first power supply unit 701 of the LV-I host device 700 and supplied to the UHS-II slave device 420 via the VDD1 line 710. In addition, 1.8V power is supplied from the second power supply unit 702 of the LV-I host device 700 to the LV-I semiconductor chip 703 and the host device I / F unit 704 of the LV-I host device 700, and further the VDD2 line 1211 is supplied to the UHS-II slave device 420.

In the present embodiment, when the power is turned on, the DAT0 line 1214a and the DAT1 line 1214b of the LV-I host device 700 are in the Hi-Z state, so that each signal line becomes high level (1) by the pull-up resistor. Yes.

After 1 ms or more has elapsed after the power supply output from the LV-I host device 700 has stabilized at VDD1 = 3.3V and VDD2 = 1.8V, the LV-I host device 700 receives 1.8V via the CLK line 1212. A single-ended clock is transmitted to the UHS-II slave device 420.

Similar to the legacy slave device 120 described in the third embodiment, the UHS-II slave device 420 also has a function of driving the DAT0 line 1214a to a low level when all of VDD1, VDD2, and CLK are detected. Absent. Therefore, the LV-I host device 700 does not detect that the DAT0 line 1214a is at a low level.

Similar to the third embodiment, when the LV-I host device 700 does not detect that the DAT0 line 1214a is at a low level by a predetermined time, the LV-I host device 700 is a slave device. It is determined that LV-I is not supported, and initialization at the LV-I interface is stopped.

[5-3. effect]
According to the fourth embodiment, the UHS-II slave device 420 does not drive the DAT0 line 1214a to a low level immediately after activation. Therefore, the LV-I host device 700 monitors the DAT0 line 1214a and detects that the slave device does not support LV-I if it does not detect a low level by a predetermined time. Do not perform the initialization process. Further, since a 3.3V high voltage signal is not supplied to the LV-I host device 700, the host device I / F unit 704 whose upper limit of the input signal withstand voltage is 1.8V is not destroyed.

[6. Configuration and Operation of Removable System According to Fifth Embodiment]
[6-1. Constitution]
FIG. 14 is a block diagram illustrating the configuration of a removable system to which the LV-I slave device 720 according to the fifth embodiment that can be inserted into and removed from the legacy host device 100 is connected. The configurations of the legacy host device 100 and the LV-I slave device 720 are the same as those described so far. It is assumed that the LV-I slave device 720 of this embodiment does not support legacy I / F.

The legacy host device 100 and the LV-I slave device 720 are mechanically connected. In addition, the legacy host device 100 is electrically connected to the legacy slave device 120 via the VDD1 line 110 that is a 3.3V power supply line.

On the other hand, since the legacy host device 100 does not have a terminal for supplying 1.8 V power, 1.8 V power is not supplied to the LV-I slave device 720. Therefore, the VDD2 detection unit 722b cannot detect VDD2. On the other hand, since the VDD1 detection unit 722a detects VDD1, when VDD2 cannot be detected, the 3.3V signal supplied via the VDD1 line 1410 is supplied to the LV-I semiconductor chip 721.

Generally, it is known that if a signal is supplied to a semiconductor chip in a state where power is not supplied, the semiconductor chip is adversely affected, and such a situation should be avoided. In the present embodiment, when 1.8V power is not supplied to the LV-I semiconductor chip 721 via VDD2, the 3.3V signal supplied via VDD1 is used instead of the LV-I semiconductor chip 721 and the slave. This is supplied to the device I / F unit 722.

The host device I / F unit 104 and the slave device I / F unit 722 perform signal communication via the CLK line 1411, the CMD line 1412, and the DAT line 1413. The DAT line 1413 is composed of four signal lines: a DAT0 line 1413a, a DAT1 line 1413b, a DAT2 line 1413c, and a DAT3 line 1413d.

FIG. 15 is a diagram for explaining the operation after power-on in the removable system composed of the legacy host device 100 and the LV-I slave device 720.

[6-2. Detailed operation]
The operation when the LV-I slave device 720 is connected to the legacy host device 100 will be described below with reference to FIGS.

At power-on, 3.3V power is supplied from the power supply unit 101 of the legacy host device 100 to the LV-I slave device 720 via the VDD1 line 1410.

The DAT1 line 1413b of the legacy host device 100 is in the Hi-Z state, but the state of the DAT0 line 1413a is undefined. That is, the state of the DAT0 line 1413a is
(1) Hi-Z state, resulting in high level (2) Driven to low level by legacy host device 100 (3) Either driven to high level by legacy host device 100 It is.

After 1 ms or more has elapsed after the power supply output from the legacy host device 100 has stabilized at VDD1 = 3.3 V, the legacy host device 100 sends a 3.3 V single-ended clock to the LV-I slave device via the CLK line 1411. To 720.

The LV-I slave device 720 detects VDD1 by the VDD1 detection unit 722a and detects CLK by the slave device I / F unit 722, but does not detect VDD2. At this time, the LV-I slave device 720 determines that the legacy I / F has been initialized, and notifies the I / F control unit 723 accordingly. Since it is determined that the LV-I is not initialized, the DAT0 line 1413a is not driven low.

Meanwhile, the legacy host device 100 transmits the I / F condition check command 1501a to the LV-I slave device 720 without particularly checking the level of the DAT0 line 1413a. The I / F control unit 723 of the LV-I slave device 720 that has received the I / F condition check command 1501a interprets the content of the command, and the LV-I slave device 720 of this embodiment supports the legacy I / F. Therefore, the corresponding I / F condition check command response 1501b is not transmitted. If the legacy host device 100 does not receive the I / F condition check command response 1501b even after a predetermined time has elapsed after transmitting the I / F condition check command 1501a, the slave device does not support the legacy I / F. Judgment is made and the subsequent processing is stopped.

[6-3. effect]
According to the present embodiment, when the LV-I slave device 720 is connected to the legacy host device 100, the legacy host device 100 does not supply VDD2, so that the LV-I slave device 720 is supplied with VDD1, VDD2, CLK Cannot detect everything. At this time, the LV-I slave device 720 determines that the LV-I interface is not initialized, and does not drive the DAT0 line 1413a to a low level.

If the legacy host device 100 is driving the DAT0 line 1413a to a high level, and the LV-I slave device 720 drives the DAT0 line 1413a to a low level, the host device and the slave device will receive signals having different voltage levels. A signal collision occurs between the two semiconductor chips, which adversely affects both semiconductor chips.

However, if the LV-I slave device 720 in this embodiment determines that the LV-I interface is not initialized, it does not drive the DAT0 line 1413a to a low level, so the legacy host device 100 determines which DAT0 line 1413a is Even in such a state, the above signal collision never occurs.

In the present embodiment, the description has been made on the assumption that the LV-I slave device 720 does not support the legacy I / F, but the same effect can be obtained even if it supports. When the LV-I slave device 720 supports legacy I / F, the LV-I slave device 720 confirms the contents of the I / F condition check command 1501a and then responds to the corresponding I / F condition check command response. 1501b is generated and returned to the legacy host device 100 via the CMD line 1412. After this process, initialization at the legacy interface and data exchange are performed.

[7. Configuration and Operation of Removable System According to Sixth Embodiment]
[7-1. Constitution]
FIG. 16 is a block diagram illustrating the configuration of a removable system to which the LV-I slave device 720 according to the sixth embodiment that can be inserted into and removed from the UHS-II host device 400 is connected. The configurations of the UHS-II host device 400 and the LV-I slave device 720 are the same as described above. It is assumed that the LV-I slave device 720 of this embodiment does not support UHS-II.

The UHS-II host device 400 and the LV-I slave device 720 are mechanically connected. Further, the UHS-II host device 400 is electrically connected to the LV-I slave device 720 via a VDD1 line 1610 which is a 3.3V power supply line. The UHS-II host device 400 is electrically connected to the LV-I slave device 720 via a VDD2 line 1611 which is a 1.8V power supply line in addition to the VDD1 line 1610. As in the first embodiment, since VDD2 is detected by the VDD2 detector 722b, the LV-I semiconductor chip 721 cuts off the input of the 3.3V power supplied via the VDD1 line 1610.

The host device I / F unit 405 and the slave device I / F unit 722 are connected by an RCLK (differential reference clock) line 1612. The UHS-II host device 400 has terminals of the D0 line 1613 and the D1 line 1614, whereas the LV-I slave device 720 does not have the terminals of the D0 line 1613 and the D1 line 1614. Signal transmission using the line 1613 and the D1 line 1614 is impossible.

The CLK line, CMD line 1612e, DAT2 line 1612c, and DAT3 line 1612d are not used in the UHS-II, but the UHS-II host device 400 or the LV-I slave device 720 is a legacy I / F or LV as described above. It is in an electrically connected state so that it can operate even with -I.

FIG. 17 is a diagram for explaining a routine after power-on in the UHS-II host device 400 and the LV-I slave device 720.

[7-2. Detailed operation]
Hereinafter, the operation when the LV-I slave device 720 is connected to the UHS-II host device 400 will be described with reference to FIGS. 16 and 17.

At the time of power activation, 3.3V power is supplied from the first power supply unit 401 of the UHS-II host device 400 to the LV-I slave device 720 via the VDD1 line 1610. In addition, 1.8V power is supplied from the second power supply unit 402 of the UHS-II host device 400 to the LV-I slave device 720 via the VDD2 line 1611.

The states of the five signal lines of the UHS-II host apparatus 400, that is, the DAT0 line 1612a, the DAT1 line 1612b, the DAT2 line 1612c, the DAT3 line 1612d, and the CMD line 1612e are not defined. That is,
(1) Hi-Z state, resulting in high level (2) Driven to low level by UHS-II host device 400 (3) Driven to high level by UHS-II host device 400 One of them.

In FIG. 17, the UHS-II host device 400 supplies 3.3V power to the LV-I slave device 720 via the VDD1 line and 1.8V power via the VDD2 line.

At this time, the LV-I slave device 720 detects VDD1 and VDD2, but does not detect CLK. At this time, the LV-I slave device 720 determines that the LV-I is not initialized, and notifies the I / F control unit 723 accordingly. Since it is determined that the LV-I is not initialized, the DAT0 line 1612a is not driven low.

On the other hand, the UHS-II host device 400 does not particularly check the level of the DAT0 line 1612a, and does not check the level of the STB. The L symbol 1701a is transmitted. However, since the LV-I slave device 720 of this embodiment does not support UHS-II, the STB. The L symbol 1701b cannot be transmitted. The UHS-II host device 400 transmits the STB. When the L symbol 1701b cannot be received, it is determined that the slave device does not support UHS-II, and the UHS-II initialization is stopped.

[7-3. effect]
According to the present embodiment, when the LV-I slave device 720 is connected to the UHS-II host device 400, the UHS-II host device 400 does not supply CLK. , VDD2, and CLK cannot be detected. At this time, the LV-I slave device 720 determines that the LV-I interface is not initialized, and does not drive the DAT0 line 1612a to a low level.

If the UHS-II host device 400 is driving the DAT0 line 1612a to a high level and the LV-I slave device 720 drives the DAT0 line 1612a to a low level, the voltage level differs from both the host device and the slave device. A signal collision occurs in which signals are transmitted to each other, which adversely affects both semiconductor chips.

Further, there is a possibility that the RCLK line 1612 (DAT0 line 1612a and DAT1 line 1612b) is transmitted from the UHS-II host device 400 at the timing when the LV-I slave device 720 detects VDD1 and VDD2. At this time, even if the UHS-II host device 400 does not drive the DAT0 line 1612a to the high level in the initial state, if the LV-I slave device 720 drives the DAT0 line 1612a to the low level, a signal collision with RCLK occurs. There is a risk of waking up.

However, if the LV-I slave device 720 in this embodiment determines that the LV-I interface is not initialized, it does not drive the DAT0 line 1612a to a low level, so the UHS-II host device 400 does not drive the DAT0 line 1612a. No matter what the state is, the above signal collision never occurs.

In the present embodiment, the description has been made on the assumption that the LV-I slave device 720 does not support UHS-II. At this time, the LV-I slave device 720 has terminals of the D0 line 1613 and the D1 line 1614, and the STB. When the L symbol 1701a is received, the STB. The L symbol 1701b is transmitted. STB. The UHS-II host apparatus 400 that has received the L symbol 1701b continues the UHS-II initialization.

[8. Addendum]
In the present disclosure, in addition to legacy I / F and UHS-II, which are existing interfaces between an SD card and a corresponding host device, when LV-I is newly introduced, an LV-I host device and an LV-I slave The method (the first embodiment and the second embodiment) in which the apparatuses identify each other that the other party supports LV-I has been described. In addition, a method (third to sixth embodiments) that does not adversely affect at least the existing host device and the existing slave device is described.

As for the former, among the legacy host device, UHS-II host device, and LV-I host device, VDD1, VDD2, and CLK are supplied only to the LV-I host immediately after the power is turned on. Therefore, since the LV-I slave device can easily identify the LV-I host device and the LV-I host device is in the Hi-Z state when the power is turned on, the LV-I slave device is in the DAT0 line. This is characterized in that the LV-I host device can detect the LV-I slave device by driving the LV-I to a low level.

And for the latter,
(1) LV-I host device and legacy slave device (2) LV-I host device and UHS-II slave device (3) Legacy host device and LV-I slave device (4) UHS-II host device and LV-I Considering the four types of slave devices, the LV-I host device with a signal withstand voltage of 1.8V does not receive the 3.3V signal, and the host device and the slave device drive signals at different voltage levels. It was confirmed that initialization was canceled without causing

As described in the fifth embodiment, the LV-I slave device of the present disclosure may be connected to a legacy host device. After startup, the legacy host device transmits an I / F condition check command with a 3.3V signal without detecting the characteristics of the connected slave device. Therefore, the input signal withstand voltage of the LV-I semiconductor chip of the LV-I slave device of the present disclosure needs to be 3.3 V or more.

It is also possible to notify the LV-I host device that the LV-I slave device of the present disclosure supports LV-I using a specific signal line other than DAT0. Since the UHS-II host device may have all the signal lines of the DAT line and CMD line driven to a high level, the LV-I slave device is connected to the LV-I host device as disclosed. Only when the specific signal line is driven to a low level, the method is effective.

In addition, the LV-I host device of the present disclosure is designed to make power supply to a back-end module such as a flash memory more efficient, and a legacy slave device that does not have a terminal corresponding to the VDD2 line is not supplied with power. In order not to adversely affect the reception of the signal, it is preferable to supply a power supply of 3.3V via the VDD1 line.

In addition, the LV-I host device of the present disclosure makes it possible to easily detect that the LV-I slave device is connected to the LV-I host device, and the 1.8V signal used in the LV-I interface. In order to generate efficiently, it is preferable to supply 1.8V power via the VDD2 line. Note that the VDD2 line can be shared with the UHS-II interface, and an increase in the number of terminals of the host device and the slave device can be suppressed.

Also, the signal line used in the LV-I of the present disclosure is equivalent to the legacy I / F. Accordingly, there is an effect that it is not necessary to increase the number of terminals of the LV-I semiconductor chip of the host device and the slave device.

In this embodiment, the high voltage signal or the power supply voltage is 3.3 V, and the low voltage signal or the power supply voltage is 1.8 V. However, as long as the voltage relationship is maintained, It may be a voltage value.

Note that the LV-I slave device of the present disclosure preferably includes a legacy I / F so that the legacy host device can operate. At this time, if the low-voltage signal voltage is 1.8 V, it becomes the same as the UHS-I mode signal voltage, and the mounting of the LV-I semiconductor chip becomes easy.

Further, in the LV-I interface, the power supply voltage supplied on the VDD2 line is set to 1.8 V, so that the host device I / F unit and the slave device I / F unit that generate the LV-I signal have VDD2 The 1.8V power supplied from the line can be supplied as it is, and the power supply can be made more efficient.

The present disclosure can be applied to a slave device including an SD card, a corresponding host device, an interface semiconductor device, and a removable system including the host device and the slave device.

100 Legacy Host Device 101 Power Supply Unit 102 Legacy I / F Semiconductor Chip 103 I / F Signal Regulator 104 Host Device I / F Unit 105 I / F Control Unit 110 VDD1 Line 111 CLK Line 112 CMD Line 113 DAT Line 113a DAT0 Line

113b DAT1 line

113c DAT2 line

113d DAT3 line 120 Legacy slave device 121 Legacy I / F semiconductor chip 122 I / F signal regulator 123 Slave device I / F unit 124 I / F control unit 125 Back-end module 201a I / F condition check command 201b I / F condition check command response 202a initialization command 202b initialization command response 203a Write command 203b Wr te command response 203c data 301a voltage switching command 301b voltage switching command response 400 UHS-II host device 401 first power supply unit 402 second power supply unit 403 UHS-II semiconductor chip 404 I / F signal regulator 405 host device I / F Unit 406 I / F control unit 410 VDD1 line 411 VDD2 line 412 RCLK line 413 D0 line 414 D1 line 420 UHS-II slave device 421 UHS-II semiconductor chip 422 I / F signal regulator 423 Slave device I / F unit 424 I / F control unit 425 backend module 501a STB. L symbol 501b STB. L symbol 502a Initialization command 502b Initialization command response 503a Write command 503b Write command response 503c Data 600 LV-I host device 601 Power supply unit 602 LV-I semiconductor chip 603 I / F signal regulator 604 Host device I / F unit 605 I / F control unit 700 LV-I host device 701 First power supply unit 702 Second power supply unit 703 LV-I semiconductor chip 704 Host device I / F unit 705 I / F control unit 710 VDD1 line 711 VDD2 line 712 CLK Line 713 CMD line 714 DAT line 714a DAT0 line 714b DAT1 line 714c DAT2 line 714d DAT3 line 720 LV-I slave device 721 LV- Semiconductor chip 722 Slave device I / F unit 722a VDD1 detection unit 722b VDD2 detection unit 723 I / F control unit 724 Backend module 801, 802, 803, 804, 901 Timing 805a I / F condition check command 805b I / F condition check Command response 806 Data 1010 VDD1 line 1011 VDD2 line 1012 CLK line 1013 CMD line 1014 DAT line 1014a DAT0 line 1014b DAT1 line 1014c DAT2 line 1014d DAT3 line 1210 VDD1 line 1211 VDD2 line 1213 CLK2 line 1212 CLK line 14 13 DAT1 line 1214c D T2 line 1214d DAT3 line 1410 VDD1 line 1411 CLK line 1412 CMD line 1413 DAT line 1413a DAT0 line 1413b DAT1 line 1413c DAT2 line 1413d DAT3 line 1501a I / F condition check command 1501b I / F condition check command 1501b I / F condition check line 1616 1612 RCLK line 1612a DAT0 line 1612b DAT1 line 1612c DAT2 line 1612d DAT3 line 1612e CMD line 1613 D0 line 1614 D1 line 1701a STB. L symbol 1701b STB. L symbol

Claims

The first slave device corresponding to the first interface, the second slave device corresponding to the second interface having a different signal system from the first interface, and the signal system of the first interface are the same. An interface unit mechanically connectable to any of the third slave devices corresponding to the third interface having a signal voltage lower than the signal voltage of the first interface;
After supplying the first power supply, the second power supply, and the clock signal to the slave device connected to the interface unit, the voltage level of the first signal line is changed to the first power supply, the second power supply, and the second power supply. When it is detected that the power level is different from that before supplying the clock signal, the voltage level of the second signal line is supplied to the first power source, the second power source, and the clock signal. Control to a different level than before
Thereafter, when it is detected that the voltage level of the first signal line is the same level as that before supplying the first power source, the second power source, and the clock signal, the second signal line And a control unit that controls the voltage level of the first power source, the second power source, and the same level as before the clock signal is supplied.
The interface unit is not logically connectable to the first slave device or the second slave device, but is logically connectable to the third slave device. The host device described in 1.
The first signal line and the second signal line are connected to a predetermined power supply line by a pull-up resistor before supplying the first power supply, the second power supply, and the clock signal. 3. The host device according to claim 1, wherein the host device is connected to a ground and a pull-down resistor and is released by the control unit.
After supplying the first power supply, the second power supply, and the clock signal to the connected slave device, the voltage level of the first signal line is changed to the first power supply, the second power supply, and When it is detected that the level is different from the level before the clock signal is supplied, the voltage level of the second signal line is the level before the first power source, the second power source, and the clock signal are supplied. Control to different levels,
Thereafter, when it is detected that the voltage level of the first signal line is the same level as that before supplying the first power source, the second power source, and the clock signal, the second signal line Is controlled to the same level as before the first power supply, the second power supply, and the clock signal are supplied.
The first host device corresponding to the first interface, the second host device corresponding to the second interface having a different signal system from the first interface, and the signal system of the first interface are the same. An interface unit mechanically connectable to any of the third host devices corresponding to the third interface having a signal voltage lower than the signal voltage of the first interface;
When all of the first power source, the second power source, and the clock signal are detected from the host device connected to the interface unit, the voltage level of the first signal line is set to the first power source, the second power source, and the second power source. Control to a level different from that before supplying the power supply and the clock signal,
When it is detected that the voltage level of the second signal line is different from that before the first power supply, the second power supply, and the clock signal are supplied, the voltage of the first signal line is A slave device comprising: a first power supply; a second power supply; and a control unit that controls the level to the same level as before detecting the clock signal.
6. The interface unit does not control the first signal line when at least one of the first power source, the second power source, and the clock signal is not detected. The slave device described in 1.
The first signal line and the second signal line are released by the control unit before the first power supply, the second power supply, and the clock signal are supplied. Item 7. The slave device according to any one of Items 5 and 6.
When all of the first power supply, the second power supply, and the clock signal supplied from the connected host device are detected, the voltage level of the first signal line is set to the first power supply and the second power supply. And a level different from that before supplying the clock signal,
When it is detected that the voltage level of the second signal line is different from that before the first power supply, the second power supply, and the clock signal are supplied, the voltage of the first signal line is An interface semiconductor device that controls a level to the same level as before detecting the first power source, the second power source, and the clock signal.
A removable system formed of a host device and a slave device detachably attached to the host device,
The host device includes a first slave device corresponding to a first interface, a second slave device corresponding to a second interface having a different signal system from the first interface, and the first interface. Although the signal system is the same, it can be mechanically connected to any of the third slave devices corresponding to the third interface which is a signal voltage lower than the signal voltage of the first interface,
The slave device includes a first host device corresponding to a first interface, a second host device corresponding to a second interface having a different signal system from the first interface, and the first interface. Although the signal system is the same, it can be mechanically connected to any of the third host devices corresponding to the third interface having a signal voltage lower than the signal voltage of the first interface,
After the host device supplies the first power source, the second power source, and the clock signal to the connected slave device,
When it is detected that the voltage level of the first signal line is different from that before supplying the first power source, the second power source, and the clock signal, the voltage level of the second signal line is set to , Controlling the first power source, the second power source, and the level before the clock signal is supplied,
Thereafter, when it is detected that the voltage level of the first signal line is the same level as that before supplying the first power source, the second power source, and the clock signal, the second signal line Is controlled to the same level as before supplying the first power source, the second power source, and the clock signal,
On the other hand, when the slave device detects all of the first power source, the second power source, and the clock signal from the connected host device, the voltage level of the first signal line is set to the first power source, the first power source, and the second power source. 2 power supply and control to a level different from that before supplying the clock signal,
When it is detected that the voltage level of the second signal line is different from that before the first power supply, the second power supply, and the clock signal are supplied, the voltage of the first signal line is A removable system that controls a level to the same level as before detecting the first power source, the second power source, and the clock signal.
The first slave device corresponding to the first interface, the second slave device corresponding to the second interface having a different signal system from the first interface, and the signal system of the first interface are the same. An interface unit mechanically connectable to any of the third slave devices corresponding to the third interface having a signal voltage lower than the signal voltage of the first interface;
After supplying the first power source, the second power source, and the clock signal to the slave device connected to the interface unit, the voltage level of a predetermined signal line is changed to the first power source, the second power source, and the second power source. A host device comprising: a power supply; and a control unit that issues a command when it is detected that the level is different from that before supplying the clock signal.
The interface unit is not logically connectable to the first slave device or the second slave device, but is logically connectable to the third slave device. The host device described in 1.
The predetermined signal line is connected to a predetermined power supply line by a pull-up resistor or a ground and a pull-down resistor before supplying the first power source, the second power source, and the clock signal. The host device according to claim 10, wherein the host device is released by the control unit.
After supplying the first power supply, the second power supply, and the clock signal to the connected slave device, the voltage level of a predetermined signal line is changed to the first power supply, the second power supply, and the An interface semiconductor device that issues a predetermined command when it is detected that the level is different from that before supplying a clock signal.
The first host device corresponding to the first interface, the second host device corresponding to the second interface having a different signal system from the first interface, and the signal system of the first interface are the same. An interface unit mechanically connectable to any of the third host devices corresponding to the third interface having a signal voltage lower than the signal voltage of the first interface;
When all of the first power source, the second power source, and the clock signal are detected from the host device connected to the interface unit, the voltage level of a predetermined signal line is set to the first power source and the second power source. And a level different from that before supplying the clock signal,
Thereafter, when a command is received from the host device, the control unit controls the voltage level of the predetermined signal line to the same level as before detecting the first power source, the second power source, and the clock signal; Slave device with
The interface unit does not control the predetermined signal line when at least one of the first power source, the second power source, and the clock signal is not detected. The slave device described.
16. The device according to claim 14, wherein the predetermined signal line is released by the control unit before the first power source, the second power source, and the clock signal are supplied. The slave device described in 1.
When all of the first power supply, the second power supply, and the clock signal are detected from the connected host device, the voltage level of a predetermined signal line is changed to the first power supply, the second power supply, and the clock. Control to a different level than before supplying the signal,
Thereafter, when a command is received from the host device, the voltage level of the predetermined signal line is controlled to the same level as before detecting the first power source, the second power source, and the clock signal. apparatus.
A removable system formed of a host device and a slave device detachably attached to the host device,
The host device includes a first slave device corresponding to a first interface, a second slave device corresponding to a second interface having a different signal system from the first interface, and the first interface. Although the signal system is the same, it can be mechanically connected to any of the third slave devices corresponding to the third interface which is a signal voltage lower than the signal voltage of the first interface,
The slave device includes a first host device corresponding to a first interface, a second host device corresponding to a second interface having a different signal system from the first interface, and the first interface. Although the signal system is the same, it can be mechanically connected to any of the third host devices corresponding to the third interface having a signal voltage lower than the signal voltage of the first interface,
After the host device supplies the first power source, the second power source, and the clock signal to the connected slave device,
A command is issued when it is detected that the voltage level of a predetermined signal line is different from the level before supplying the first power source, the second power source, and the clock signal,
On the other hand, when the slave device detects all of the first power source, the second power source, and the clock signal from the connected host device, the voltage level of the predetermined signal line is set to the first power source, the first power source, and the second power source. 2 power supply and control to a level different from that before supplying the clock signal,
Thereafter, when the command is received from the host device, the voltage level of the predetermined signal line is controlled to the same level as before detecting the first power source, the second power source, and the clock signal. .
The signal system of the first interface and the third interface is a single-ended system, and the signal system of the second interface is a differential serial system whose signal voltage is lower than that of the first interface signal. The host device according to claim 1.
The host device according to claim 19, wherein the signal voltage of the first interface is 3.3V, and the signal voltage of the third interface is 1.8V.
The signal system of the first interface and the third interface is a single-ended system, and the signal system of the second interface is a differential serial system whose signal voltage is lower than that of the first interface signal. The slave device according to claim 5.
The slave device according to claim 21, wherein the signal voltage of the first interface is 3.3V, and the signal voltage of the third interface is 1.8V.