WO2016127871A1 - 检测装置、系统及单板 - Google Patents

检测装置、系统及单板 Download PDF

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Publication number
WO2016127871A1
WO2016127871A1 PCT/CN2016/073206 CN2016073206W WO2016127871A1 WO 2016127871 A1 WO2016127871 A1 WO 2016127871A1 CN 2016073206 W CN2016073206 W CN 2016073206W WO 2016127871 A1 WO2016127871 A1 WO 2016127871A1
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Prior art keywords
service
cfp
board
tested
socket
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PCT/CN2016/073206
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English (en)
French (fr)
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徐新发
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中兴通讯股份有限公司
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Publication of WO2016127871A1 publication Critical patent/WO2016127871A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems

Definitions

  • the present invention relates to the field of hardware, and in particular, to a detection device, a system, and a board.
  • the Optical Transport Network is a transport network that organizes networks in the optical layer based on wavelength division multiplexing.
  • OTN is currently developing rapidly and has a wide range of applications.
  • the types of services that OTN needs to support are also increasing.
  • OTN mainly supports fixed rate services, such as ODUk, and k is equal to 0/1/2/3/4.
  • the bandwidth of the customer service is getting larger and larger, the bandwidth of the OTN service board is gradually increasing.
  • the 100G service board is gradually being used in a large scale.
  • the 40G and 100G service board customer side optical modules are CFP modules, which support hot swap and are more expensive.
  • the general CFP module of the service table is connected to the service board and then crosses the backplane to other service boards. This method requires dozens of CFP modules to verify the board service and test. High cost.
  • the present invention provides a detection device, a system, and a board, and the main purpose thereof is to solve the technical problem of high test cost when testing a service board.
  • the present invention provides a detecting apparatus including an EPLD logic control unit, a high speed signal loopback unit, and a CFP socket, wherein the CFP socket is connected to the high speed signal loopback unit, and the high speed a signal loopback unit is connected to the EPLD logic control unit, and the CFP socket is connected to the EPLD logic control unit;
  • the CFP socket is configured to connect a service main board to be tested and the detecting device
  • the high-speed signal loopback unit is configured to receive a high-speed signal sent by the service board to be tested through the CFP socket, and loop the high-speed signal through the CFP socket to the service board to be tested.
  • the detecting, by the service board, the high-speed channel of the service board to be tested is normal according to the received high-speed signal after the loopback;
  • the EPLD logic control unit is configured to send a control signal to the high-speed signal loopback unit, and receive a low-speed signal sent by the service board to be tested through the CFP socket, and detect the to-be-suppressed according to the low-speed signal. Check if the low speed channel of the service board is normal;
  • the control signal is used to drive the high speed signal loopback unit to operate.
  • the detecting device further includes a frequency divider, and the CFP socket passes through the frequency divider Connected to the EPLD logic control unit:
  • the frequency divider is configured to reduce the frequency of the high-speed clock signal sent by the main board of the service to be tested, and send the reduced low-speed clock to the EPLD logic control unit for detection.
  • the detecting device further includes a plug-and-pick recording unit, and the plug-and-pick recording unit is connected to the EPLD logic control unit;
  • the insertion and removal times recording unit is configured to record the number of times the detecting device is inserted into the service main board to be tested.
  • the detecting device further comprises a power supply unit, the power supply unit being connected to the CFP socket.
  • the CFP socket is a 148 pin socket.
  • the present invention also provides a veneer comprising the detecting device as described above.
  • the present invention further provides a detection system, which includes a service meter, a service board to be tested with a CFP module, a cross board, and at least one service board to be tested with a detection device. ;
  • the service main board to be tested with the CFP module is connected to the cross board, and the cross board and the at least one service main board to be tested with the detecting device.
  • the embodiment of the present invention implements detection of a high-speed signal channel and a low-speed signal channel of a service motherboard to be tested by using an EPLD logic control unit, a high-speed signal loopback unit, and a CFP socket detection device, and replaces the service board with a service board with a detection device.
  • a service board with a CFP module reduces the cost of the original test board business.
  • FIG. 1 is a schematic diagram of functional modules of a first embodiment of a detecting device
  • FIG. 2 is a schematic diagram of functional modules of a second embodiment of the detecting device
  • FIG. 3 is a schematic diagram of functional modules of a third embodiment of the detecting device.
  • FIG. 4 is a schematic diagram of functional modules of a fourth embodiment of the detecting device.
  • FIG. 5 is a schematic diagram of functional modules of a first embodiment of a single board
  • FIG. 6 is a schematic diagram of functional modules of a first embodiment of a detection system
  • FIG. 7 is a schematic diagram of functional modules of a detection system provided by the prior art.
  • the invention provides a detection device.
  • FIG. 1 is a schematic diagram of functional modules of a first embodiment of a detecting device.
  • the detecting device 100 includes:
  • the EPLD logic control unit 101, the high-speed signal loopback unit 102, and the CFP socket 103 are connected to the high-speed signal loopback unit 102, and the high-speed signal loopback
  • the unit 102 is connected to the Electronic Programmable Logic Device (EPLD) 101
  • the CFP socket 103 is connected to the EPLD logic control unit 101.
  • EPLD Electronic Programmable Logic Device
  • the CFP socket 103 is configured to connect a service main board to be tested and the detecting device 100;
  • the high-speed signal loopback unit 102 is configured to receive a high-speed signal sent by the service motherboard to be tested through the CFP socket 103, and loop the high-speed signal through the CFP socket 103 to the to-be-tested device.
  • the service board is configured to enable the service board to be tested to detect whether the high-speed channel of the service board to be tested is normal according to the received high-speed signal after the loopback;
  • the EPLD logic control unit 101 is configured to send a control signal to the high-speed signal loopback unit 102, and receive a low-speed signal sent by the service motherboard to be tested through the CFP socket 103, and detect according to the low-speed signal. Whether the low speed channel of the service board to be tested is normal;
  • the control signal is used to drive the high speed signal loopback unit 102 to operate.
  • the EPLD logic control unit 101 may be configured to implement an MDIO interface by simulating a Management Data Interface (MDIO) timing, and the EPLD logic control unit 101 may send a control signal to the high-speed loopback unit, where the control signal is used.
  • MDIO Management Data Interface
  • the high speed loopback unit can be operated normally.
  • the detecting device 100 is implemented by the following methods:
  • the detection of the high-speed channel of the service board to be tested is performed by the CFP socket 103 receiving the high-speed service signal sent by the service board to be tested, and passing the high-speed loopback unit in the detecting device 100, and looping back the high-speed service signal.
  • the service board to be tested can detect whether the high-speed channel of the service board to be tested is working normally according to the received high-speed service signal of the loopback.
  • the detection of the low-speed channel of the service board to be tested is performed by the CFP socket 103 receiving the low-speed service signal sent by the service board to be tested, and detecting whether the low-speed service signal is normal through the EPLD logic control unit 101 in the detecting device 100, thereby detecting Whether the low speed channel of the service motherboard to be tested is working normally.
  • the CFP socket 103 is a 148 pin socket.
  • the embodiment of the present invention implements the detection of the high-speed signal channel and the low-speed signal channel of the service motherboard to be tested by the detection device 100 including the EPLD logic control unit 101, the high-speed signal loopback unit 102, and the CFP socket 103.
  • the service board with the detection device 100 replaces the service board with the CFP module, thereby reducing the cost of the original test board business.
  • FIG. 2 is a schematic diagram of functional modules of a second embodiment of the detecting apparatus 100.
  • the detecting apparatus 100 further includes:
  • the frequency divider 104 is connected to the EPLD logic control unit 101 by the frequency divider:
  • the frequency divider 104 is configured to reduce the frequency of the high-speed clock signal sent by the main board of the service to be tested, and send the reduced low-speed clock to the EPLD logic control unit 101 for detection.
  • the frequency divider is added to the EPLD logic control unit 101 to divide the frequency to a low frequency.
  • the frequency divider functions to: transmit the service main board to the high frequency of the loopback detecting device 100.
  • the clock signal is down-converted, and then the down-converted low-frequency clock signal is sent to the EPLD.
  • the EPLD implements the clock frequency detection function, and the detection result is stored in the EPLD register, and can be fed back to the CPU of the service motherboard to be tested through the MDIO interface.
  • the CFP socket 103 is a 148 pin socket.
  • the embodiment of the present invention implements the detection of the high-speed signal channel and the low-speed signal channel of the service motherboard to be tested by the detection device 100 including the EPLD logic control unit 101, the high-speed signal loopback unit 102, and the CFP socket 103, and the detection device 100 is provided.
  • the service board replaces the service board with the CFP module, thereby reducing the cost of the original test board business.
  • FIG. 3 is a schematic diagram of functional modules of a third embodiment of the detecting apparatus 100.
  • the detecting apparatus 100 further includes:
  • plug-and-pick record unit 105 the plug-and-pick record unit is connected to the EPLD logic control unit 101;
  • the insertion and removal times recording unit is configured to record the number of times the detecting device 100 detects the service main board to be tested.
  • the CFP socket 103 is a 148 pin socket.
  • the high-speed connector since the high-speed connector has a certain service life, the number of insertions and removals is required, so an EEPROM is built in the daughter card for storing the number of insertions and removals.
  • the embodiment of the present invention implements the detection of the high-speed signal channel and the low-speed signal channel of the service motherboard to be tested by the detection device 100 including the EPLD logic control unit 101, the high-speed signal loopback unit 102, and the CFP socket 103, and the detection device 100 is provided.
  • the service board replaces the service board with the CFP module, thereby reducing the cost of the original test board business.
  • FIG. 4 is a schematic diagram of functional modules of a fourth embodiment of the detecting apparatus 100.
  • the detecting apparatus 100 further includes:
  • the power supply unit 106 is connected to the CFP socket 103.
  • the CFP socket 103 is a 148 pin socket.
  • the power supply unit introduces 3.3V into the loopback detecting device 100 through a 148 pin socket, and the loopback detecting device 100 internally has a voltage required for the power unit to be converted into other loopback detecting devices 100.
  • the embodiment of the present invention implements the detection of the high-speed signal channel and the low-speed signal channel of the service motherboard to be tested by the detection device 100 including the EPLD logic control unit 101, the high-speed signal loopback unit 102, and the CFP socket 103, and the detection device 100 is provided.
  • the service board replaces the service board with the CFP module, thereby reducing the cost of the original test board business.
  • the invention provides a veneer.
  • FIG. 5 is a schematic diagram of functional modules of a first embodiment of a single board.
  • the single board includes the detecting device 100100 described in FIGS. 1 to 5.
  • the embodiment of the present invention implements the detection of the high-speed signal channel and the low-speed signal channel of the service motherboard to be tested by the detection device 100 including the EPLD logic control unit 101, the high-speed signal loopback unit 102, and the CFP socket 103, and the detection device 100 is provided.
  • the service board replaces the service board with the CFP module, thereby reducing the cost of the original test board business.
  • the present invention provides a detection system.
  • Figure 6 is a schematic diagram of the functional modules of the first embodiment of the detection system.
  • the detection system includes a service meter, a service board 601 with a CFP module to be tested, a cross board 602, and at least one service board 603 with a detection device 100 to be tested;
  • the service main board 601 with the CFP module is connected to the cross board 602, and the cross board 602 and the at least one service main board 603 with the detecting device 100 to be tested.
  • the first service board connected to the service table is inserted into the CFP module to access the service.
  • the business boards 2, which need to be cascaded, are inserted into the detecting device 100100, respectively.
  • the service connected to service board 1 is crossed to the other service boards to be tested. According to the capacity of the service board, categorize as many service boards as possible, and achieve the purpose of using a service table and a CFP module to detect or aging multiple service boards.
  • FIG. 7 is a schematic diagram of functional modules of a detection system provided by the prior art.
  • the detection system includes a service meter, a service board 701 with a CFP module to be tested, a cross board 702, and at least one service board 703 with a CFP module to be tested;
  • the service main board 701 with the CFP module to be tested is connected to the cross board 702, and the cross board 702 And the at least one service main board 703 to be tested with the CFP module.
  • the general CFP module of the service table is generally connected to the service board, and then crosses the backplane to other service boards to implement a light meter to test dozens of service boards.
  • the method requires dozens of CFP optical modules to verify the board business, and the testing cost is high.
  • the high-speed signal channel and the low-speed signal channel of the service motherboard to be tested are detected by the detection device including the EPLD logic control unit, the high-speed signal loopback unit, and the CFP socket.
  • the service board of the detection device replaces the service board with the CFP module, thereby reducing the cost of the original test board business.

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  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
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Abstract

一种检测装置(100)，所述检测装置(100)包括EPLD逻辑控制单元(101)、高速信号环回单元(102)、CFP插座(103)，所述CFP插座(103)与所述高速信号环回单元(102)连接，所述高速信号环回单元(102)与所述EPLD逻辑控制单元(101)连接，所述CFP插座(103)与所述EPLD逻辑控制单元(101)连接。一种单板、检测系统，实现对待测的业务主板的高速信号通道以及低速信号通道的检测，通过带有检测装置(100)的业务主板代替带有CFP模块的业务主板，从而降低原有的测试单板业务的成本。

Description

检测装置、系统及单板 技术领域
本发明涉及硬件领域，尤其涉及一种检测装置、系统及单板。
背景技术
光传送网(Optical Transport Network，OTN)是以波分复用技术为基础、在光层组织网络的传送网。OTN目前发展比较迅速，应用范围广泛。OTN需要支持的业务类型也不断增加。OTN主要支持固定速率的业务，如ODUk，k等于0/1/2/3/4。
随着客户业务带宽越来越大，OTN业务板带宽也逐渐增大，目前100G业务板也逐渐开始大范围使用。40G和100G业务板客户侧光模块均是CFP模块，支持热插拔，价格比较昂贵。在生产线测试业务板及高温老化时，一般是业务表通用CFP模块接入业务到业务板，然后通过背板交叉到其他业务板，这种方式需要几十个CFP模块来验证单板业务，测试成本很高。
发明内容
本发明提供一种检测装置、系统及单板，主要目的在于解决测试业务板时的测试成本较高的技术问题。
为实现上述目的，本发明提供的一种检测装置，所述检测装置包括EPLD逻辑控制单元、高速信号环回单元、CFP插座，所述CFP插座与所述高速信号环回单元连接，所述高速信号环回单元与所述EPLD逻辑控制单元连接，所述CFP插座与所述EPLD逻辑控制单元连接；
所述CFP插座，设置为连接待测的业务主板和所述检测装置；
所述高速信号环回单元，设置为接收所述待测的业务主板通过所述CFP插座发送的高速信号，并将所述高速信号通过所述CFP插座环回到所述待测的业务主板，以使得所述待测的业务主板根据接收到的环回后的高速信号检测所述待测的业务主板的高速通道是否正常；
所述EPLD逻辑控制单元，设置为向所述高速信号环回单元发送控制信号，并且通过所述CFP插座接收所述待测的业务主板发送的低速信号，并根据所述低速信号检测所述待测业务主板的低速通道是否正常；
所述控制信号用于驱动所述高速信号环回单元工作。
在本发明的实施例中，所述检测装置还包括分频器，所述CFP插座通过所述分频器 与所述EPLD逻辑控制单元连接：
所述分频器，设置为降低所述待测业务主板发送的高速时钟信号频率，将降低后的低速时钟送给EPLD逻辑控制单元来检测。
在本发明的实施例中，所述检测装置还包括插拔次数记录单元，所述插拔次数记录单元与所述EPLD逻辑控制单元连接；
所述插拔次数记录单元，设置为记录所述检测装置插入所述待测业务主板的次数。
在本发明的实施例中，所述检测装置还包括电源单元，所述电源单元与所述CFP插座连接。
在本发明的实施例中，所述CFP插座为148pin的插座。
此外，为实现上述目的，本发明还提供一种单板，所述单板包括如上所述的检测装置。
此外，为实现上述目的，本发明还提供一种检测系统，所述检测系统包括业务仪表、带有CFP模块的待测的业务主板、交叉板以及至少一个带有检测装置的待测的业务主板；
所述带有CFP模块的待测的业务主板与所述交叉板连接，所述交叉板与所述至少一个带有检测装置的待测的业务主板。
本发明实施例通过包括EPLD逻辑控制单元、高速信号环回单元、CFP插座的检测装置，实现对待测的业务主板的高速信号通道以及低速信号通道的检测，通过带有检测装置的业务主板代替带有CFP模块的业务主板，从而降低原有的测试单板业务的成本。
附图说明
图1为检测装置第一实施例的功能模块示意图；
图2为检测装置第二实施例的功能模块示意图；
图3为检测装置第三实施例的功能模块示意图；
图4为检测装置第四实施例的功能模块示意图；
图5为单板第一实施例的功能模块示意图；
图6为检测系统第一实施例的功能模块示意图；
图7为现有技术提供的一种检测系统的功能模块示意图。
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明提供一种检测装置。
参照图1，图1为检测装置第一实施例的功能模块示意图。
在第一实施例中，该检测装置100包括：
包括EPLD逻辑控制单元101、高速信号环回单元102、光模块(Centum Form-factor Pluggable，CFP)插座103，所述CFP插座103与所述高速信号环回单元102连接，所述高速信号环回单元102与所述电子逻辑控制单元(Electrically Programmable Logic Device，EPLD)101连接，所述CFP插座103与所述EPLD逻辑控制单元101连接；
所述CFP插座103，设置为连接待测的业务主板和所述检测装置100；
所述高速信号环回单元102，设置为接收所述待测的业务主板通过所述CFP插座103发送的高速信号，并将所述高速信号通过所述CFP插座103环回到所述待测的业务主板，以使得所述待测的业务主板根据接收到的环回后的高速信号检测所述待测的业务主板的高速通道是否正常；
所述EPLD逻辑控制单元101，设置为向所述高速信号环回单元102发送控制信号，并且通过所述CFP插座103接收所述待测的业务主板发送的低速信号，并根据所述低速信号检测所述待测业务主板的低速通道是否正常；
所述控制信号用于驱动所述高速信号环回单元102工作。
其中，所述EPLD逻辑控制单元101可以设置为模拟管理数据接口(Management Data Interface，MDIO)时序实现MDIO接口，所述EPLD逻辑控制单元101可以向高速环回单元发送控制信号，所述控制信号用于驱动所述高速环回单元能正常工作。
为了实现对待测的业务主板的高速通道以及低速通道的检测，检测装置100分别通过以下方式实现：
对待测的业务主板的高速通道的检测，是通过CFP插座103接收待测的业务主板发送的高速业务信号，并通过检测装置100中的高速环回单元后，将所述高速业务信号环回输出给所述待测的业务主板，所述待测的业务主板可以根据接收到的环回的高速业务信号检测所述待测的业务主板的高速通道是否正常工作；
对待测的业务主板的低速通道的检测，是通过CFP插座103接收待测的业务主板发送的低速业务信号，并通过检测装置100中的EPLD逻辑控制单元101检测该低速业务信号是否正常，从而检测所述待测的业务主板的低速通道是否正常工作。
所述CFP插座103为148pin的插座。
本发明实施例通过包括EPLD逻辑控制单元101、高速信号环回单元102、CFP插座103的检测装置100，实现对待测的业务主板的高速信号通道以及低速信号通道的检测， 通过带有检测装置100的业务主板代替带有CFP模块的业务主板，从而降低原有的测试单板业务的成本。
参照图2，图2为检测装置100第二实施例的功能模块示意图。
在第一实施例的基础上，该检测装置100还包括：
分频器104，所述CFP插座103通过所述分频器与所述EPLD逻辑控制单元101连接：
所述分频器104，设置为降低所述待测业务主板发送的高速时钟信号频率，将降低后的低速时钟送给EPLD逻辑控制单元101来检测。
具体的，检测装置100插在100G的待测的业务主板上时，会有时钟输入，对于以太网协议，此时钟频率为644.53125M，对于波分系统来说，此频率为698.8125M。由于逻辑不支持如此高的输入频率，在EPLD逻辑控制单元101前增加分频器，分频到低频，同时，分频器作用是：将所述业务主板发送给环回检测装置100的高频时钟信号降频，然后将降频后的低频时钟信号送给EPLD，EPLD来实现时钟频率检测功能，并将检测结果存在EPLD的寄存器中，可通过MDIO接口反馈给待测的业务主板的CPU。
所述CFP插座103为148pin的插座。
本发明实施例通过包括EPLD逻辑控制单元101、高速信号环回单元102、CFP插座103的检测装置100，实现对待测的业务主板的高速信号通道以及低速信号通道的检测，通过带有检测装置100的业务主板代替带有CFP模块的业务主板，从而降低原有的测试单板业务的成本。
参照图3，图3为检测装置100第三实施例的功能模块示意图。
在第一实施例的基础上，该检测装置100还包括：
插拔次数记录单元105，所述插拔次数记录单元与所述EPLD逻辑控制单元101连接；
所述插拔次数记录单元，设置为记录所述检测装置100检测所述待测的业务主板的次数。
所述CFP插座103为148pin的插座。
具体的，由于高速连接器有一定的使用寿命，插拔次数有要求，所以在子卡上内置一个EEPROM，用于存放插拔次数。
本发明实施例通过包括EPLD逻辑控制单元101、高速信号环回单元102、CFP插座103的检测装置100，实现对待测的业务主板的高速信号通道以及低速信号通道的检测，通过带有检测装置100的业务主板代替带有CFP模块的业务主板，从而降低原有的测试单板业务的成本。
参照图4，图4为检测装置100第四实施例的功能模块示意图。
在第一实施例的基础上，该检测装置100还包括：
电源单元106，所述电源单元106与所述CFP插座103连接。
所述CFP插座103为148pin的插座。
所述电源单元为通过148pin插座引入3.3V到环回检测装置100，环回检测装置100内部有电源单元转换为其他环回检测装置100需要的电压。
本发明实施例通过包括EPLD逻辑控制单元101、高速信号环回单元102、CFP插座103的检测装置100，实现对待测的业务主板的高速信号通道以及低速信号通道的检测，通过带有检测装置100的业务主板代替带有CFP模块的业务主板，从而降低原有的测试单板业务的成本。
本发明提供一种单板。
参照图5，图5为单板第一实施例的功能模块示意图。
在第一实施例中，该单板包括图1至图5所述的检测装置100100。
本发明实施例通过包括EPLD逻辑控制单元101、高速信号环回单元102、CFP插座103的检测装置100，实现对待测的业务主板的高速信号通道以及低速信号通道的检测，通过带有检测装置100的业务主板代替带有CFP模块的业务主板，从而降低原有的测试单板业务的成本。
本发明提供一种检测系统。
参照图6，图6为检测系统第一实施例的功能模块示意图。
所述检测系统包括业务仪表、带有CFP模块的待测的业务主板601、交叉板602以及至少一个带有检测装置100的待测的业务主板603；
所述带有CFP模块的待测的业务主板601与所述交叉板602连接，所述交叉板602与所述至少一个带有检测装置100的待测的业务主板603。
将与业务表连接的第一块业务板插上CFP模块，接入业务，业务板1背板交叉自环业务通。将需要级联的业务板2…..业务板n分别插入检测装置100100。通过网管设置交叉，将业务板1接入的业务分别交叉到待测试的其他业务板。根据业务板能力，尽可能级联更多的业务板，达到使用一块业务表和一个CFP模块，检测或高温老化多块业务板的目的。
参照图7，图7为现有技术提供的一种检测系统的功能模块示意图。
所述检测系统包括业务仪表、带有CFP模块的待测的业务主板701、交叉板702以及至少一个带有CFP模块的待测的业务主板703；
所述带有CFP模块的待测的业务主板701与所述交叉板702连接，所述交叉板702 与所述至少一个带有CFP模块的待测的业务主板703。
具体的，在生产线测试业务板及高温老化时，一般是业务表通用CFP模块接入业务到业务板，然后通过背板交叉到其他业务板，实现一块光表来测试几十块业务板，这种方式需要几十个CFP光模块来验证单板业务，测试成本很高。
通过比较图6和图7，可发现通过使用该检测装置100，可大大减少测试所需CFP模块的数量，极大的降低测试成本；而且采用检测装置100后也不需要加入光钎自环，提高测试效率。
以上仅为本发明的优选实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。
工业实用性
基于本发明实施例提供的上述技术方案，通过包括EPLD逻辑控制单元、高速信号环回单元、CFP插座的检测装置，实现对待测的业务主板的高速信号通道以及低速信号通道的检测，通过带有检测装置的业务主板代替带有CFP模块的业务主板，从而降低原有的测试单板业务的成本。

Claims (7)

  1. 一种检测装置，所述检测装置包括EPLD逻辑控制单元、高速信号环回单元、CFP插座，所述CFP插座与所述高速信号环回单元连接，所述高速信号环回单元与所述EPLD逻辑控制单元连接，所述CFP插座与所述EPLD逻辑控制单元连接；
    所述CFP插座，设置为连接待测的业务主板和所述检测装置；
    所述高速信号环回单元，设置为接收所述待测的业务主板通过所述CFP插座发送的高速信号，并将所述高速信号通过所述CFP插座环回到所述待测的业务主板，以使得所述待测的业务主板根据接收到的环回后的高速信号检测所述待测的业务主板的高速通道是否正常；
    所述EPLD逻辑控制单元，设置为向所述高速信号环回单元发送控制信号，并且通过所述CFP插座接收所述待测的业务主板发送的低速信号，并根据所述低速信号检测所述待测业务主板的低速通道是否正常；
    所述控制信号用于驱动所述高速信号环回单元工作。
  2. 根据权利要求1所述的检测装置，其中，所述检测装置还包括分频器，所述CFP插座通过所述分频器与所述EPLD逻辑控制单元连接：
    所述分频器，设置为降低所述待测业务主板发送的高速时钟信号频率，将降低后的低速时钟送给EPLD逻辑控制单元来检测。
  3. 根据权利要求1所述的检测装置，其中，所述检测装置还包括插拔次数记录单元，所述插拔次数记录单元与所述EPLD逻辑控制单元连接：
    所述插拔次数记录单元，设置为记录所述检测装置插入所述待测业务主板的次数。
  4. 根据权利要求1所述的检测装置，其中，所述检测装置还包括电源单元，所述电源单元与所述CFP插座连接。
  5. 根据权利要求1至4任意一项所述的检测装置，其中，所述CFP插座为148pin的插座。
  6. 一种单板，所述单板包括权利要求1至5任意一项所述的检测装置。
  7. 一种检测系统，所述检测系统包括业务仪表、带有CFP模块的待测的业务主板、交叉板以及至少一个带有检测装置的待测的业务主板；
    所述带有CFP模块的待测的业务主板与所述交叉板连接，所述交叉板与所述至少一个带有检测装置的待测的业务主板。
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