WO2016123756A1 - Threshold compensation rectification circuit - Google Patents

Threshold compensation rectification circuit Download PDF

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Publication number
WO2016123756A1
WO2016123756A1 PCT/CN2015/072205 CN2015072205W WO2016123756A1 WO 2016123756 A1 WO2016123756 A1 WO 2016123756A1 CN 2015072205 W CN2015072205 W CN 2015072205W WO 2016123756 A1 WO2016123756 A1 WO 2016123756A1
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Prior art keywords
complementary mos
output
rectifying unit
stage
unit
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PCT/CN2015/072205
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French (fr)
Chinese (zh)
Inventor
刘昱
刘欣
张海英
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中国科学院微电子研究所
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Priority to PCT/CN2015/072205 priority Critical patent/WO2016123756A1/en
Publication of WO2016123756A1 publication Critical patent/WO2016123756A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

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  • the present invention relates to the field of integrated circuit design technology, and in particular, to a threshold compensation rectifier circuit.
  • a typical RF energy harvesting system consists of a receiving antenna, an impedance matching circuit, a rectifier circuit, a boost converter circuit, and an energy storage unit, as shown in Figure 1.
  • the antenna receives the RF energy signal of the surrounding environment, and transmits the RF energy signal to the rectifier circuit through the impedance matching network, and the rectifier circuit converts the RF signal into an available DC voltage signal, and raises the voltage to the voltage through the boost conversion circuit.
  • the expected value is finally passed to the energy storage unit, and the generated electrical energy is stored to supply power to the subsequent application circuit.
  • Power conversion efficiency refers to the ratio of output power to input power.
  • Receive sensitivity refers to the minimum power that an energy harvesting system can receive an energy signal.
  • the receiving sensitivity is determined by the rectifier circuit, that is, the threshold voltage of the rectifier device is limited. The lower the threshold voltage of the rectifier device, the lower the minimum input power required, the system The receiving sensitivity is higher. Therefore, in order to improve the power conversion efficiency and receiving sensitivity of the RF energy harvesting system, it is necessary to design a high efficiency, low threshold voltage rectifier circuit.
  • Figure 2 presents a simple threshold-compensating rectifier circuit that uses a MOS transistor with adjustable voltage between the gate and drain as a rectifying unit instead of a conventional gate-drain directly connected MOS diode.
  • the voltage of each node gradually rises from input to output, and the gate of the rectification MOS transistor can be connected to different nodes of the rectification link (Fig. 2 provides the gate to the next stage node). That is, the compensation branch length is 2), the gate leakage voltage is adjustable, and the advantage of this is that the threshold compensation of the rectifying device can be realized without an additional compensation circuit and special process, and the threshold is effectively reduced.
  • the circuit has the disadvantage that the MOS transistor rectifying unit with the compensation voltage between the gate and the drain has large reverse leakage, especially in the RF energy harvesting system with extremely low input power, the power conversion efficiency of the rectifier circuit will be If the reverse leakage of the rectifier unit can be reduced on this basis, the efficiency of the rectifier circuit will be greatly improved.
  • the rectification circuit used in the RF energy harvesting system in the prior art has a problem that the reverse leakage current of the rectifying device is large and the efficiency of the rectifying circuit is low.
  • the object of the present invention is to provide a threshold compensation rectifying circuit to realize a low threshold and high efficiency rectifying circuit. Improve the receiving sensitivity and efficiency of the RF energy harvesting system.
  • the threshold compensation rectifier circuit provided by the invention comprises:
  • a complementary MOS rectifying unit of a first stage to an Nth stage a complementary MOS output rectifying unit, and a load capacitor and a load resistor;
  • Each of the complementary MOS rectifying units of the first to Nth stages of the complementary MOS rectifying unit has a first input end, a second input end, and an output end; the first input end of the current stage complementary MOS rectifying unit The output end of the first-stage complementary MOS rectifying unit is connected, the second input end is connected to the first input signal or the second input signal, and the output end is connected to the first input end of the next-stage complementary MOS rectifying unit; the first-stage complementary MOS rectification The first input end of the unit is connected to the ground; the output end of the last stage complementary MOS rectifying unit is connected to the input end of the complementary MOS output rectifying unit;
  • the complementary MOS output rectifying unit has an input end and an output end; wherein an output end of the complementary MOS output rectifying unit is connected to an output signal;
  • One end of the load capacitor is connected to the output signal, and the other end is connected to the ground;
  • One end of the load resistor is connected to the output signal and the other end is connected to the ground.
  • each of the complementary MOS rectifying units includes: a PMOS transistor, an NMOS transistor, a first bias voltage source, a second bias voltage source, and a coupling capacitor.
  • the source of the PMOS transistor is connected to the negative terminal of the second bias voltage source, and is connected together to the first input end of the complementary MOS rectifying unit of the stage, the gate of the PMOS transistor and the first a negative voltage terminal of the bias voltage source is connected, the drain of the PMOS transistor is connected to the substrate, and is connected to the drain of the NMOS transistor and the substrate;
  • the source of the NMOS transistor is connected to the positive terminal of the first bias voltage source, and is connected together to the output end of the complementary MOS rectifier unit of the stage, the gate of the NMOS transistor and the second bias Connect the positive terminal of the voltage source;
  • the one end of the coupling capacitor is connected to the output end of the complementary MOS rectifying unit of the stage, and the other end is connected to the second input end of the complementary MOS rectifying unit of the stage.
  • the complementary MOS output rectifying unit comprises: a PMOS transistor and an NMOS transistor;
  • the source of the PMOS transistor is connected to the gate of the NMOS transistor and is connected together with the input end of the complementary MOS output rectifying unit, the gate of the PMOS transistor is connected to the source of the NMOS transistor, and Together with the output of the complementary MOS output rectifying unit, the drain of the PMOS transistor is connected to the substrate and is connected to the drain of the NMOS transistor and the substrate.
  • the threshold compensation rectifier circuit provided by the embodiment of the invention performs high-efficiency rectification on the weak input RF signal through the N-stage complementary MOS rectifying unit and the complementary MOS output rectifying unit, and outputs the required straight Current voltage.
  • the complementary MOS rectifying unit forms a rectifying unit by using complementary PMOS and NMOS symmetric cross-connections on the basis of the existing threshold compensation technology.
  • both the PMOS and the NMOS exhibit the reverse turn-off characteristic of the MOS transistor, that is, the reverse current is very small, which greatly reduces the reverse leakage of the rectifying unit;
  • Due to the threshold compensation technique it is characterized by a forward-passing MOS transistor characteristic, that is, the forward voltage drop is very low, and the equivalent threshold voltage of the rectifying unit is lowered. Therefore, the threshold compensation rectifier circuit provided by the present invention not only has a lower threshold voltage, but also its reverse leakage is effectively suppressed, so that the receiving sensitivity and the conversion efficiency of the rectifier circuit are improved.
  • FIG. 1 is a schematic structural view of a typical RF energy harvesting system
  • FIG. 2 is a circuit schematic diagram of a prior art threshold compensation rectifier circuit
  • FIG. 3 is a schematic structural diagram of a threshold compensation rectifier circuit according to an embodiment of the present invention.
  • FIG. 4 is a circuit schematic diagram of a threshold compensation rectifier circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic circuit diagram of a threshold compensation rectifier circuit with a compensation branch length of 2 according to an embodiment of the present invention
  • Figure 6 is a waveform diagram of the transient simulation of the input voltage and output current of the rectifier circuit.
  • Embodiments of the present invention provide a threshold compensation rectification circuit, wherein the rectification unit not only has a lower threshold but also has a smaller reverse leakage, and can be used in an RF energy harvesting system to improve the receiving sensitivity and efficiency of the system.
  • FIG. 3 is a schematic structural diagram of a threshold compensation rectifier circuit according to the present invention.
  • the threshold compensation rectifier circuit includes complementary MOS rectification units 301, 302, 303, 304, and 305 of the first stage to the Nth stage, a complementary MOS output rectification unit 306, a load capacitance C L , and a load resistance R. L , and two differential input RF signals RF in +, RF in - and an output DC voltage signal V out ;
  • Each of the complementary MOS rectifying units 301, 302, 303, 304, and 305 of the complementary MOS rectifying units of the first to N stages has a first input terminal, a second input terminal, and an output terminal.
  • the first input end of the current-stage complementary MOS rectifying unit is connected to the output end of the complementary MOS rectifying unit of the previous stage, and the second input end is connected to the first input signal RF in + or the second input signal RF in -, the output end and the lower end
  • the first input end of the first-stage complementary MOS rectifying unit is connected; the first input end of the first-stage complementary MOS rectifying unit 301 is connected to the ground; the output end of the last-stage complementary MOS rectifying unit 305 and the input of the complementary MOS output rectifying unit 306 Connected to each other;
  • Rectifying said complementary MOS output unit 306 having an input terminal and an output terminal; wherein the complementary MOS output rectifying means connected to the output terminal 306 and an output signal V out;
  • One end of the load capacitor C L is connected to the output signal V out and the other end is connected to the ground;
  • One end of the load resistor R L is connected to the output signal V out and the other end is connected to the ground.
  • the threshold compensation rectifier circuit includes complementary MOS rectification units 401, 402, 403, 404, and 405 of the first stage to the Nth stage, a complementary MOS output rectification unit 406, a load capacitance C L , and a load resistance R. L , and two differential input RF signals RF in +, RF in - and an output DC voltage signal V out .
  • the connection relationship between them is the same as that described in FIG. 3, and details are not described herein again, and only the components and connection relationships inside each unit will be described in detail.
  • the first-stage complementary MOS rectifying unit 401 includes a PMOS transistor M p1 , an NMOS transistor M n1 , two bias voltage sources V cp and V cn , and a coupling capacitor C.
  • the source of the PMOS transistor M p1 is connected to the negative terminal of the bias voltage source V cn and is connected together to the first input terminal of the complementary MOS rectifying unit 401 of the stage, the gate and the bias of the PMOS transistor M p1 a negative terminal of the voltage source V cp is connected, a drain of the PMOS transistor M p1 is connected to the substrate, and is connected to a drain of the NMOS transistor Mn1 and a substrate; a source of the NMOS transistor Mn1 Connected to the positive terminal of the bias voltage source V cp and connected together to the output terminal of the complementary MOS rectifying unit 401 of the stage, the gate of the NMOS transistor Mn1 is connected to the positive terminal of the bias voltage source V cn ;
  • the circuit composition and connection mode of the second-stage complementary MOS rectifying unit 402, the third-stage complementary MOS rectifying unit 403, the N-1-th complement MOS rectifying unit 404, and the N-th complement MOS rectifying unit 405 are the same as the first stage. The same is true for the complementary MOS rectifying unit 401, and details are not described herein again.
  • the complementary MOS output rectifying unit 406 includes: a PMOS transistor M p-out and an NMOS transistor M n-out .
  • the source of the PMOS transistor M p-out is connected to the gate of the NMOS transistor Mn -out and is connected together with the input terminal of the complementary MOS output rectifying unit 406.
  • the gate and NMOS of the PMOS transistor M p-out The sources of the transistors Mn -out are connected and connected together with the output of the complementary MOS output rectifying unit 406, the drain of the PMOS transistor Mp -out is connected to the substrate, and the NMOS transistor Mn -out The drain is connected to the substrate.
  • FIG. 5 shows a specific circuit implementation of the bias voltage sources V cp and V cn of Figure 4.
  • the gates of the PMOS and NMOS transistors in the complementary MOS rectifier unit of each stage in FIG. 4 can be connected to different nodes of the rectification link instead of the ideal.
  • the embodiment provided in FIG. 5 is to connect the gate voltage of the PMOS transistor of the current stage rectifying unit to the first input end of the rectifier unit of the previous stage, and connect the gate voltage of the NMOS transistor to the rectifier unit of the subsequent stage.
  • the output that is, the case where the length of the compensation branch is 2.
  • One problem with this implementation is that the gate of the PMOS transistor of the first stage rectification unit and the gate of the NMOS transistor of the last stage rectification unit have no nodes on the rectification link to provide their required compensation voltage. Therefore, an NMOS compensation unit needs to be added between the first-stage rectifying unit and the ground to provide a required compensation voltage for the gate of the first-stage rectifying unit PMOS transistor, and is added between the last-stage rectifying unit and the output rectifying unit.
  • a PMOS compensation unit provides the required compensation voltage for the gate of the NMOS transistor of the last stage rectification unit.
  • the length of the compensation branch will be determined according to the specific situation, or it may be 4, 6, or 8, and the number of transistors of the corresponding NMOS and PMOS compensation units will also change accordingly.
  • the specific circuit implementation method of FIG. 5 will be described in detail below.
  • the threshold compensation rectifier circuit includes: first to Nth stages of complementary MOS rectification units 501, 502, 503, 504, and 505, complementary MOS output rectification unit 506, NMOS compensation unit 507, and PMOS compensation.
  • Unit 508 load capacitance C L , load resistance R L , and two differential input RF signals RF in +, RF in - and an output DC voltage signal V out ;
  • Each of the complementary MOS rectifying units 501, 502, 503, 504, and 505 of the complementary MOS rectifying units of the first to N stages has a first input terminal, a second input terminal, and a first bias voltage terminal. a second bias voltage terminal and an output terminal;
  • the first input end of the current-stage complementary MOS rectifying unit is connected to the output end of the complementary MOS rectifying unit of the previous stage, and the second input end is connected to the first input signal RF in + or the second input signal RF in -, the output end and the lower end
  • the first input end of the first complementary MOS rectifying unit is connected, the first bias voltage end is connected to the first input end of the complementary MOS rectifying unit of the previous stage, and the output of the second bias voltage end and the complementary MOS rectifying unit of the latter stage Connected to each other;
  • the first input end of the first-stage complementary MOS rectifying unit 501 is connected to the output end of the NMOS compensating unit 507, and the first bias voltage end is connected to the first input end of the NMOS compensating unit 507, and is connected to the ground together;
  • the output of the last stage complementary MOS rectifying unit 505 is connected to the first input of the PMOS compensation unit 508, and is connected together to the input of the complementary MOS output rectifying unit 506, and the output of the second bias voltage terminal and the PMOS compensating unit 508. Connected to each other;
  • the complementary MOS output rectifying unit 506 has an input terminal and an output terminal. Wherein the output terminal is connected and the output signal V out;
  • the NMOS compensation unit 507 has a first input terminal, a second input terminal, a bias voltage terminal and an output terminal; wherein the second input terminal is connected to the second input signal RF in -, and the bias voltage terminal is connected to the first stage The output ends of the complementary MOS rectifying unit 501 are connected;
  • the PMOS compensation unit 508 has a first input terminal, a second input terminal, a bias voltage terminal and an output terminal; wherein the second input terminal is connected to the first input signal RF in + , and the bias voltage terminal is complementary to the last level The first input end of the MOS rectifying unit 505 is connected;
  • One end of the load capacitor C L is connected to the output signal V out and the other end is connected to the ground;
  • One end of the load resistor R L is connected to the output signal V out and the other end is connected to the ground.
  • the first-stage complementary MOS rectifying unit 501 includes: a PMOS transistor M p1 , an NMOS transistor M n1 and a coupling capacitor C;
  • the source of the PMOS transistor M p1 is connected to the first input terminal of the complementary MOS rectifying unit 501 of the stage, the gate is connected to the first bias voltage terminal of the complementary MOS rectifying unit 501 of the stage, and the drain and the substrate are connected Together, and connected to the drain of the NMOS transistor Mn1 and the substrate;
  • the source of the NMOS transistor M n1 is connected to the output terminal of the complementary MOS rectifying unit 501 of the stage, and the gate is connected to the second bias voltage terminal of the complementary MOS rectifying unit 501 of the stage; one end of the coupling capacitor C and the complementary MOS rectification of the stage The output end of the unit 501 is connected, and the other end is connected to the second input end of the complementary MOS rectifying unit 501 of the stage;
  • the circuit composition and connection mode of the second-stage complementary MOS rectifying unit 502, the third-stage complementary MOS rectifying unit 503, the N-1-th complement MOS rectifying unit 504, and the N-th complement MOS rectifying unit 505 are the same as the first stage.
  • the complementary MOS output rectifying unit 506 includes: a PMOS transistor M p-out and an NMOS transistor M n-out ; the source of the PMOS transistor M p-out is connected to the gate of the NMOS transistor Mn -out , and Together with the input of the complementary MOS output rectifying unit 506, the gate is connected to the source of the NMOS transistor Mn -out , and is connected together with the output of the complementary MOS output rectifying unit 506, and the drain and the substrate are connected together. And connected to the drain of the NMOS transistor Mn -out and the substrate;
  • the NMOS compensation unit 507 includes: an NMOS transistor M nd1 and a coupling capacitor C; a source of the NMOS transistor M nd1 is connected to an output end of the NMOS compensation unit 507, and a bias voltage terminal of the gate and NMOS compensation unit 507 Connected, the drain and the substrate are connected together and connected together with the first input of the NMOS compensation unit 507; one end of the coupling capacitor C is connected to the output of the NMOS compensation unit 507, and the other end is connected to the second of the NMOS compensation unit 507. Inputs are connected;
  • the PMOS compensation unit 508 includes: a PMOS transistor M pd1 and a coupling capacitor C; a source of the PMOS transistor M pd1 is connected to a first input end of the PMOS compensation unit 508 , and a bias of the gate and PMOS compensation unit 508
  • the voltage terminals are connected, the drain and the substrate are connected together, and are connected together with the output end of the PMOS compensation unit 508; one end of the coupling capacitor C is connected to the output end of the PMOS compensation unit 508, and the other end is connected to the second end of the PMOS compensation unit 508.
  • the inputs are connected.
  • MOS transistor In order to reduce the reverse leakage of the rectifier unit, based on the existing threshold compensation technology, complementary As a rectifying unit, MOS transistor can not only reduce the threshold voltage of the rectifying unit, but also effectively suppress its reverse leakage. When it is applied to the RF energy harvesting system, it can improve the receiving sensitivity and power conversion efficiency of the system.
  • the rectifier circuit when the input is a differential RF signal, the rectifier circuit rectifies the positive and negative half cycles of the input signal simultaneously, and each rectifier unit is only in the half cycle of the input signal. Internal conduction.
  • Figure 6 shows the transient simulation waveform of the input voltage and output current during the operation of the rectifier circuit. It can be seen that a sinusoidal period of the input signal can be divided into three working areas:
  • Subthreshold region 0 ⁇ V in ⁇ V th , where V in is the amplitude of the input signal, and V th is the threshold voltage of the rectifying unit.
  • V in is the amplitude of the input signal
  • V th is the threshold voltage of the rectifying unit.
  • the output current is exponentially related to the input voltage, and the input voltage is small. The output current is also small;
  • Leakage zone The negative half cycle of the input voltage during which the output current is reverse leakage current.
  • the existing threshold compensation technique only reduces the threshold of the rectifying unit and increases the inversion time, but does not suppress the reverse leakage.
  • the invention adopts a complementary MOS rectifying unit based on the threshold compensation technology. Not only the low threshold voltage is realized, but also the reverse leakage is effectively suppressed, and the conversion efficiency of the rectifier circuit is improved.
  • the complementary MOS rectifying unit provided by the present invention is described by taking the second-stage complementary MOS rectifying unit in FIG. 5 as an example.
  • the rectifying unit is forward biased, due to the threshold compensation technique, the voltage of each node in the Dickson multi-stage rectification circuit is gradually increased from input to output, that is, V 0 ⁇ V 1 ⁇ V 2 ⁇ V 3 , M
  • Both p2 and Mn2 behave as the forward conduction characteristics of the MOS transistor, so that its forward voltage drop is much smaller than the forward voltage drop (the threshold voltage of the diode) of the conventional diode as a rectifying device, that is, equivalent to a rectifying device.
  • the threshold voltage is lowered.
  • the rectifying unit of the threshold compensation rectifying circuit provided by the embodiment of the present invention exhibits a forward conduction characteristic of the MOS transistor when forward biased, and has a lower conduction voltage drop, which is equivalent to lowering the threshold voltage of the rectifying unit; When reverse biased, it appears as the reverse cut-off characteristic of the MOS transistor, which greatly reduces the reverse leakage of the rectifying unit. Thereby, not only a lower threshold voltage is achieved, but also reverse leakage is effectively suppressed, and power conversion efficiency is improved. When applied to an RF energy harvesting system, the receiving sensitivity and efficiency of the RF collection system are improved.

Abstract

A threshold compensation rectification circuit comprises complementary MOS rectification units on N levels, complementary MOS output rectification units, load capacitors, and load resistors. Each complementary MOS rectification unit on each level is provided with a first input end, a second input end, and an output end. A first input end of the complementary MOS rectification unit on a current level is connected to an output end of the complementary MOS rectification unit on a previous level, a second input end is connected to a first input signal or a second input signal, and an output end is connected to a first input end of the complementary MOS rectification unit one a next level. A first input end of the complementary MOS rectification unit on a first level is connected to the ground. An output end of the complementary MOS rectification unit on a last level is connected to an input end of the corresponding complementary MOS output rectification unit. The complementary MOS output rectification unit is provided with an input end and an output end, and the output end is connected to an output signal. One end of each load capacitor is connected to an output signal, and the other end is connected to the ground. One end of each load resistor is connected to an output signal, and the other end is connected to the ground.

Description

阈值补偿整流电路Threshold compensation rectifier circuit 技术领域Technical field
本发明涉及集成电路设计技术领域，尤其涉及一种阈值补偿整流电路。The present invention relates to the field of integrated circuit design technology, and in particular, to a threshold compensation rectifier circuit.
背景技术Background technique
近年来，能量收集技术的关注度不断增高，尤其是在无电池供电的无线传感网中，需要一个射频能量收集系统为传感器节点供电，解决无线传感器的供电问题，延长其在低维护环境中的工作寿命。In recent years, the focus of energy harvesting technology has increased, especially in wireless battery-free wireless sensor networks, which require an RF energy harvesting system to power sensor nodes, solve the problem of wireless sensor power supply, and extend its low maintenance environment. Working life.
一个典型的射频能量收集系统由接收天线、阻抗匹配电路、整流电路、升压转换电路和储能单元组成，如图1所示。其中天线接收到周围环境的射频能量信号，经过阻抗匹配网络把射频能量信号传递给整流电路，整流电路将射频信号转换成一个可用的直流电压信号，并经过升压转换电路将该电压升高到期望值，最后传递给储能单元，将所得的电能储存起来，给后续应用电路供电。A typical RF energy harvesting system consists of a receiving antenna, an impedance matching circuit, a rectifier circuit, a boost converter circuit, and an energy storage unit, as shown in Figure 1. The antenna receives the RF energy signal of the surrounding environment, and transmits the RF energy signal to the rectifier circuit through the impedance matching network, and the rectifier circuit converts the RF signal into an available DC voltage signal, and raises the voltage to the voltage through the boost conversion circuit. The expected value is finally passed to the energy storage unit, and the generated electrical energy is stored to supply power to the subsequent application circuit.
衡量射频能量收集系统的两个重要指标是功率转换效率和接收灵敏度，功率转换效率指的是输出功率与输入功率的比值。为了提高系统的功率转换效率，系统的每个组成单元都应进行效率优化设计。接收灵敏度指的是能量收集系统所能接收到能量信号的最小功率。对基于Dickson多级整流电路的射频能量收集系统而言，接收灵敏度由整流电路来决定，即受到整流器件的阈值电压限制，整流器件的阈值电压越低，所需的最小输入功率越低，系统的接收灵敏度就越高。因此，为了提高射频能量收集系统的功率转换效率和接收灵敏度，需要设计一个高效率、低阈值电压的整流电路。Two important indicators for measuring RF energy harvesting systems are power conversion efficiency and receiver sensitivity. Power conversion efficiency refers to the ratio of output power to input power. In order to improve the power conversion efficiency of the system, each component of the system should be optimized for efficiency. Receive sensitivity refers to the minimum power that an energy harvesting system can receive an energy signal. For an RF energy harvesting system based on Dickson multi-stage rectifier circuit, the receiving sensitivity is determined by the rectifier circuit, that is, the threshold voltage of the rectifier device is limited. The lower the threshold voltage of the rectifier device, the lower the minimum input power required, the system The receiving sensitivity is higher. Therefore, in order to improve the power conversion efficiency and receiving sensitivity of the RF energy harvesting system, it is necessary to design a high efficiency, low threshold voltage rectifier circuit.
图2提出了一个简单的阈值补偿整流电路，该电路采用栅漏之间电压可调的MOS晶体管作为整流单元代替传统的栅漏直接连接的MOS二极管，根据 Dickson多级整流电路中各节点电压从输入到输出逐渐升高的特点，可把整流MOS晶体管的栅极接到整流链路不同节点上(图2提供的是栅极接到后一级节点上，即补偿支路长度为2的情况)，实现栅漏电压可调，这样做的优点是无需额外的补偿电路和特殊工艺，就可实现对整流器件的阈值补偿，有效的降低阈值。但是该电路的缺点是，这种栅漏之间具有补偿电压的MOS晶体管整流单元，反向漏电较大，尤其在输入功率极低的射频能量收集系统中，整流电路的功率转换效率会因此而下降，如果能在此基础上减小整流单元的反向漏电，那么会使整流电路的效率大大提升。Figure 2 presents a simple threshold-compensating rectifier circuit that uses a MOS transistor with adjustable voltage between the gate and drain as a rectifying unit instead of a conventional gate-drain directly connected MOS diode. In the Dickson multi-stage rectifier circuit, the voltage of each node gradually rises from input to output, and the gate of the rectification MOS transistor can be connected to different nodes of the rectification link (Fig. 2 provides the gate to the next stage node). That is, the compensation branch length is 2), the gate leakage voltage is adjustable, and the advantage of this is that the threshold compensation of the rectifying device can be realized without an additional compensation circuit and special process, and the threshold is effectively reduced. However, the circuit has the disadvantage that the MOS transistor rectifying unit with the compensation voltage between the gate and the drain has large reverse leakage, especially in the RF energy harvesting system with extremely low input power, the power conversion efficiency of the rectifier circuit will be If the reverse leakage of the rectifier unit can be reduced on this basis, the efficiency of the rectifier circuit will be greatly improved.
综上所述，可知先前技术中用于射频能量收集系统的整流电路存在整流器件反向漏电较大、整流电路效率较低的问题。In summary, it can be seen that the rectification circuit used in the RF energy harvesting system in the prior art has a problem that the reverse leakage current of the rectifying device is large and the efficiency of the rectifying circuit is low.
发明内容Summary of the invention
为克服上述现有技术存在的整流器件反向漏电较大、整流电路效率较低的问题，本发明的目的在于提供一种阈值补偿整流电路，以实现一种低阈值、高效率的整流电路，提高射频能量收集系统的接收灵敏度和效率。In order to overcome the problem that the reverse leakage current of the rectifying device is large and the efficiency of the rectifying circuit is low, the object of the present invention is to provide a threshold compensation rectifying circuit to realize a low threshold and high efficiency rectifying circuit. Improve the receiving sensitivity and efficiency of the RF energy harvesting system.
本发明提供的阈值补偿整流电路，包括：The threshold compensation rectifier circuit provided by the invention comprises:
第一级至第N级的互补MOS整流单元、互补MOS输出整流单元以及负载电容和负载电阻；a complementary MOS rectifying unit of a first stage to an Nth stage, a complementary MOS output rectifying unit, and a load capacitor and a load resistor;
所述第一级至第N级的互补MOS整流单元的每一级互补MOS整流单元都具有第一输入端、第二输入端和输出端；当前级互补MOS整流单元的第一输入端与前一级互补MOS整流单元的输出端相连，第二输入端与第一输入信号或第二输入信号相连，输出端与下一级互补MOS整流单元的第一输入端相连；第一级互补MOS整流单元的第一输入端与地相连；最后一级互补MOS整流单元的输出端与互补MOS输出整流单元的输入端相连； Each of the complementary MOS rectifying units of the first to Nth stages of the complementary MOS rectifying unit has a first input end, a second input end, and an output end; the first input end of the current stage complementary MOS rectifying unit The output end of the first-stage complementary MOS rectifying unit is connected, the second input end is connected to the first input signal or the second input signal, and the output end is connected to the first input end of the next-stage complementary MOS rectifying unit; the first-stage complementary MOS rectification The first input end of the unit is connected to the ground; the output end of the last stage complementary MOS rectifying unit is connected to the input end of the complementary MOS output rectifying unit;
所述互补MOS输出整流单元具有一个输入端和一个输出端；其中，所述互补MOS输出整流单元的输出端与输出信号相连；The complementary MOS output rectifying unit has an input end and an output end; wherein an output end of the complementary MOS output rectifying unit is connected to an output signal;
所述负载电容的一端与输出信号相连，另一端与地相连；One end of the load capacitor is connected to the output signal, and the other end is connected to the ground;
所述负载电阻的一端与输出信号相连，另一端与地相连。One end of the load resistor is connected to the output signal and the other end is connected to the ground.
进一步的，所述每一级互补MOS整流单元包括：一个PMOS晶体管、一个NMOS晶体管、第一偏置电压源、第二偏置电压源和一个耦合电容。Further, each of the complementary MOS rectifying units includes: a PMOS transistor, an NMOS transistor, a first bias voltage source, a second bias voltage source, and a coupling capacitor.
其中，所述PMOS晶体管的源极与所述第二偏置电压源的负端相连，并一起连接到该级互补MOS整流单元的第一输入端，所述PMOS晶体管的栅极与所述第一偏置电压源的负端相连，所述PMOS晶体管的漏极和衬底连接在一起，并与所述NMOS晶体管的漏极和衬底相连；The source of the PMOS transistor is connected to the negative terminal of the second bias voltage source, and is connected together to the first input end of the complementary MOS rectifying unit of the stage, the gate of the PMOS transistor and the first a negative voltage terminal of the bias voltage source is connected, the drain of the PMOS transistor is connected to the substrate, and is connected to the drain of the NMOS transistor and the substrate;
其中，所述NMOS晶体管的源极与所述第一偏置电压源的正端相连，并一起连接到该级互补MOS整流单元的输出端，所述NMOS晶体管的栅极与所述第二偏置电压源的正端相连；The source of the NMOS transistor is connected to the positive terminal of the first bias voltage source, and is connected together to the output end of the complementary MOS rectifier unit of the stage, the gate of the NMOS transistor and the second bias Connect the positive terminal of the voltage source;
其中，所述耦合电容的一端与该级互补MOS整流单元的输出端相连，另一端与该级互补MOS整流单元的第二输入端相连。The one end of the coupling capacitor is connected to the output end of the complementary MOS rectifying unit of the stage, and the other end is connected to the second input end of the complementary MOS rectifying unit of the stage.
进一步的，所述互补MOS输出整流单元包括：一个PMOS晶体管和一个NMOS晶体管；Further, the complementary MOS output rectifying unit comprises: a PMOS transistor and an NMOS transistor;
其中，所述PMOS晶体管的源极与所述NMOS晶体管的栅极相连，并一起与互补MOS输出整流单元的输入端相连，所述PMOS晶体管的栅极与所述NMOS晶体管的源极相连，并一起与互补MOS输出整流单元的输出端相连，所述PMOS晶体管的漏极和衬底连接在一起，并与所述NMOS晶体管的漏极和衬底相连。Wherein the source of the PMOS transistor is connected to the gate of the NMOS transistor and is connected together with the input end of the complementary MOS output rectifying unit, the gate of the PMOS transistor is connected to the source of the NMOS transistor, and Together with the output of the complementary MOS output rectifying unit, the drain of the PMOS transistor is connected to the substrate and is connected to the drain of the NMOS transistor and the substrate.
本发明实施例提供的阈值补偿整流电路，通过N级互补MOS整流单元和互补MOS输出整流单元，对较微弱的输入射频信号进行高效整流，输出所需的直 流电压。所述互补MOS整流单元在现有阈值补偿技术的基础上，采用互补的PMOS和NMOS对称交叉连接构成整流单元。该结构的整流单元在反向偏置时，PMOS和NMOS都表现为MOS晶体管反向截止特性，即反向电流非常小，大大减小了整流单元的反向漏电；而在正向偏置时，由于采用阈值补偿技术，使其表现为一个正向导通的MOS晶体管特性，即正向导通压降很低，等效为整流单元的阈值电压被降低。因此，本发明所提供的阈值补偿整流电路不仅具有较低的阈值电压，而且其反向漏电也被有效的抑制，使得整流电路的接收灵敏度和转换效率都得到提高。The threshold compensation rectifier circuit provided by the embodiment of the invention performs high-efficiency rectification on the weak input RF signal through the N-stage complementary MOS rectifying unit and the complementary MOS output rectifying unit, and outputs the required straight Current voltage. The complementary MOS rectifying unit forms a rectifying unit by using complementary PMOS and NMOS symmetric cross-connections on the basis of the existing threshold compensation technology. When the rectifying unit of the structure is reverse biased, both the PMOS and the NMOS exhibit the reverse turn-off characteristic of the MOS transistor, that is, the reverse current is very small, which greatly reduces the reverse leakage of the rectifying unit; Due to the threshold compensation technique, it is characterized by a forward-passing MOS transistor characteristic, that is, the forward voltage drop is very low, and the equivalent threshold voltage of the rectifying unit is lowered. Therefore, the threshold compensation rectifier circuit provided by the present invention not only has a lower threshold voltage, but also its reverse leakage is effectively suppressed, so that the receiving sensitivity and the conversion efficiency of the rectifier circuit are improved.
附图说明DRAWINGS
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单的介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any inventive labor.
图1为典型射频能量收集系统的结构示意图；1 is a schematic structural view of a typical RF energy harvesting system;
图2为现有技术阈值补偿整流电路的电路原理图；2 is a circuit schematic diagram of a prior art threshold compensation rectifier circuit;
图3为本发明实施例提供的阈值补偿整流电路的结构示意图；3 is a schematic structural diagram of a threshold compensation rectifier circuit according to an embodiment of the present invention;
图4为本发明实施例提供的阈值补偿整流电路的电路原理图；4 is a circuit schematic diagram of a threshold compensation rectifier circuit according to an embodiment of the present invention;
图5为本发明实施例提供的补偿支路长度为2的阈值补偿整流电路的电路原理图；FIG. 5 is a schematic circuit diagram of a threshold compensation rectifier circuit with a compensation branch length of 2 according to an embodiment of the present invention; FIG.
图6为整流电路的输入电压和输出电流瞬态仿真波形图。Figure 6 is a waveform diagram of the transient simulation of the input voltage and output current of the rectifier circuit.
具体实施方式detailed description
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是 全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, instead of All embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
本发明实施例提供一种阈值补偿整流电路，其中的整流单元不仅具有较低的阈值，而且具有较小的反向漏电，可用于射频能量收集系统中，提高系统的接收灵敏度和效率。Embodiments of the present invention provide a threshold compensation rectification circuit, wherein the rectification unit not only has a lower threshold but also has a smaller reverse leakage, and can be used in an RF energy harvesting system to improve the receiving sensitivity and efficiency of the system.
图3为本发明所述的阈值补偿整流电路的结构示意图。如图3所示，所述阈值补偿整流电路包括第一级至第N级的互补MOS整流单元301、302、303、304和305、互补MOS输出整流单元306、负载电容CL、负载电阻RL、以及两个差分输入射频信号RFin+、RFin-和一个输出直流电压信号Vout；FIG. 3 is a schematic structural diagram of a threshold compensation rectifier circuit according to the present invention. As shown in FIG. 3, the threshold compensation rectifier circuit includes complementary MOS rectification units 301, 302, 303, 304, and 305 of the first stage to the Nth stage, a complementary MOS output rectification unit 306, a load capacitance C L , and a load resistance R. L , and two differential input RF signals RF in +, RF in - and an output DC voltage signal V out ;
所述第一级至第N级的互补MOS整流单元的每一级互补MOS整流单元301、302、303、304和305都具有第一输入端、第二输入端和输出端。当前级互补MOS整流单元的第一输入端与前一级互补MOS整流单元的输出端相连，第二输入端与第一输入信号RFin+或第二输入信号RFin-相连，输出端与下一级互补MOS整流单元的第一输入端相连；第一级互补MOS整流单元301的第一输入端与地相连；最后一级互补MOS整流单元305的输出端与互补MOS输出整流单元306的输入端相连；Each of the complementary MOS rectifying units 301, 302, 303, 304, and 305 of the complementary MOS rectifying units of the first to N stages has a first input terminal, a second input terminal, and an output terminal. The first input end of the current-stage complementary MOS rectifying unit is connected to the output end of the complementary MOS rectifying unit of the previous stage, and the second input end is connected to the first input signal RF in + or the second input signal RF in -, the output end and the lower end The first input end of the first-stage complementary MOS rectifying unit is connected; the first input end of the first-stage complementary MOS rectifying unit 301 is connected to the ground; the output end of the last-stage complementary MOS rectifying unit 305 and the input of the complementary MOS output rectifying unit 306 Connected to each other;
所述互补MOS输出整流单元306具有一个输入端和一个输出端；其中，所述互补MOS输出整流单元306的输出端与输出信号Vout相连；Rectifying said complementary MOS output unit 306 having an input terminal and an output terminal; wherein the complementary MOS output rectifying means connected to the output terminal 306 and an output signal V out;
所述负载电容CL的一端与输出信号Vout相连，另一端与地相连；One end of the load capacitor C L is connected to the output signal V out and the other end is connected to the ground;
所述负载电阻RL的一端与输出信号Vout相连，另一端与地相连。One end of the load resistor R L is connected to the output signal V out and the other end is connected to the ground.
图4为图3所示的阈值补偿整流电路的电路原理图。如图4所示，所述阈值补偿整流电路包括第一级至第N级的互补MOS整流单元401、402、403、404和405、互补MOS输出整流单元406、负载电容CL、负载电阻RL、以及两个差分 输入射频信号RFin+、RFin-和一个输出直流电压信号Vout。它们之间的连接关系与图3中所描述的相同，在此不再赘述，只对各单元内部的组成和连接关系进行详细说明。4 is a circuit schematic diagram of the threshold compensation rectifier circuit shown in FIG. As shown in FIG. 4, the threshold compensation rectifier circuit includes complementary MOS rectification units 401, 402, 403, 404, and 405 of the first stage to the Nth stage, a complementary MOS output rectification unit 406, a load capacitance C L , and a load resistance R. L , and two differential input RF signals RF in +, RF in - and an output DC voltage signal V out . The connection relationship between them is the same as that described in FIG. 3, and details are not described herein again, and only the components and connection relationships inside each unit will be described in detail.
其中，第一级互补MOS整流单元401包括：PMOS晶体管Mp1、NMOS晶体管Mn1、两个偏置电压源Vcp和Vcn以及耦合电容C。所述PMOS晶体管Mp1的源极与偏置电压源Vcn的负端相连，并一起连接到该级互补MOS整流单元401的第一输入端，所述PMOS晶体管Mp1的栅极与偏置电压源Vcp的负端相连，所述PMOS晶体管Mp1的漏极和衬底连接在一起，并与所述NMOS晶体管Mn1的漏极和衬底相连；所述NMOS晶体管Mn1的源极与偏置电压源Vcp的正端相连，并一起连接到该级互补MOS整流单元401的输出端，所述NMOS晶体管Mn1的栅极与偏置电压源Vcn的正端相连；耦合电容C的一端与该级互补MOS整流单元401的输出端相连，另一端与该级互补MOS整流单元401的第二输入端相连；The first-stage complementary MOS rectifying unit 401 includes a PMOS transistor M p1 , an NMOS transistor M n1 , two bias voltage sources V cp and V cn , and a coupling capacitor C. The source of the PMOS transistor M p1 is connected to the negative terminal of the bias voltage source V cn and is connected together to the first input terminal of the complementary MOS rectifying unit 401 of the stage, the gate and the bias of the PMOS transistor M p1 a negative terminal of the voltage source V cp is connected, a drain of the PMOS transistor M p1 is connected to the substrate, and is connected to a drain of the NMOS transistor Mn1 and a substrate; a source of the NMOS transistor Mn1 Connected to the positive terminal of the bias voltage source V cp and connected together to the output terminal of the complementary MOS rectifying unit 401 of the stage, the gate of the NMOS transistor Mn1 is connected to the positive terminal of the bias voltage source V cn ; One end of C is connected to the output end of the complementary MOS rectifying unit 401 of the stage, and the other end is connected to the second input end of the complementary MOS rectifying unit 401 of the stage;
同样的，第二级互补MOS整流单元402、第三级互补MOS整流单元403、第N-1级互补MOS整流单元404和第N级互补MOS整流单元405的电路组成和连接方式与第一级互补MOS整流单元401的相同，在此不再赘述。Similarly, the circuit composition and connection mode of the second-stage complementary MOS rectifying unit 402, the third-stage complementary MOS rectifying unit 403, the N-1-th complement MOS rectifying unit 404, and the N-th complement MOS rectifying unit 405 are the same as the first stage. The same is true for the complementary MOS rectifying unit 401, and details are not described herein again.
其中，互补MOS输出整流单元406包括：一个PMOS晶体管Mp-out和一个NMOS晶体管Mn-out。所述PMOS晶体管Mp-out的源极与NMOS晶体管Mn-out的栅极相连，并一起与互补MOS输出整流单元406的输入端相连，所述PMOS晶体管Mp-out的栅极与NMOS晶体管Mn-out的源极相连，并一起与互补MOS输出整流单元406的输出端相连，所述PMOS晶体管Mp-out的漏极和衬底连接在一起，并与NMOS晶体管Mn-out的漏极和衬底相连。The complementary MOS output rectifying unit 406 includes: a PMOS transistor M p-out and an NMOS transistor M n-out . The source of the PMOS transistor M p-out is connected to the gate of the NMOS transistor Mn -out and is connected together with the input terminal of the complementary MOS output rectifying unit 406. The gate and NMOS of the PMOS transistor M p-out The sources of the transistors Mn -out are connected and connected together with the output of the complementary MOS output rectifying unit 406, the drain of the PMOS transistor Mp -out is connected to the substrate, and the NMOS transistor Mn -out The drain is connected to the substrate.
图5示出了图4中偏置电压源Vcp和Vcn的具体电路实现。根据Dickson多级整流电路中各节点电压从输入到输出逐渐升高的特点，可把图4中各级互补MOS 整流单元中PMOS和NMOS晶体管的栅极连接到整流链路不同节点上，代替理想偏置电压源，实现阈值补偿。图5所提供的实施例是把当前级整流单元的PMOS晶体管的栅极电压接到其前一级整流单元的第一输入端，把NMOS晶体管的栅极电压接到其后一级整流单元的输出端，即补偿支路长度为2的情况。这种实施方法存在一个问题是第一级整流单元的PMOS晶体管的栅极和最后一级整流单元的NMOS晶体管的栅极在整流链路上没有节点可提供其所需的补偿电压。因此，需要在第一级整流单元与地之间加入一个NMOS补偿单元，为第一级整流单元PMOS晶体管的栅极提供所需的补偿电压，在最后一级整流单元与输出整流单元之间加入一个PMOS补偿单元，为最后一级整流单元NMOS晶体管的栅极提供所需的补偿电压。当然，在实际设计时，会根据具体情况，决定补偿支路的长度，也可以是4、6、8等情况，同时对应的NMOS和PMOS补偿单元的晶体管个数也会相应的发生变化。下面对图5的具体电路实施方法进行详细描述。Figure 5 shows a specific circuit implementation of the bias voltage sources V cp and V cn of Figure 4. According to the characteristics that the voltage of each node in the Dickson multi-stage rectifier circuit is gradually increased from input to output, the gates of the PMOS and NMOS transistors in the complementary MOS rectifier unit of each stage in FIG. 4 can be connected to different nodes of the rectification link instead of the ideal. Bias voltage source for threshold compensation. The embodiment provided in FIG. 5 is to connect the gate voltage of the PMOS transistor of the current stage rectifying unit to the first input end of the rectifier unit of the previous stage, and connect the gate voltage of the NMOS transistor to the rectifier unit of the subsequent stage. The output, that is, the case where the length of the compensation branch is 2. One problem with this implementation is that the gate of the PMOS transistor of the first stage rectification unit and the gate of the NMOS transistor of the last stage rectification unit have no nodes on the rectification link to provide their required compensation voltage. Therefore, an NMOS compensation unit needs to be added between the first-stage rectifying unit and the ground to provide a required compensation voltage for the gate of the first-stage rectifying unit PMOS transistor, and is added between the last-stage rectifying unit and the output rectifying unit. A PMOS compensation unit provides the required compensation voltage for the gate of the NMOS transistor of the last stage rectification unit. Of course, in actual design, the length of the compensation branch will be determined according to the specific situation, or it may be 4, 6, or 8, and the number of transistors of the corresponding NMOS and PMOS compensation units will also change accordingly. The specific circuit implementation method of FIG. 5 will be described in detail below.
如图5所示，所述阈值补偿整流电路包括：第一级至第N级的互补MOS整流单元501、502、503、504和505、互补MOS输出整流单元506、NMOS补偿单元507、PMOS补偿单元508、负载电容CL、负载电阻RL、以及两个差分输入射频信号RFin+、RFin-和一个输出直流电压信号Vout；As shown in FIG. 5, the threshold compensation rectifier circuit includes: first to Nth stages of complementary MOS rectification units 501, 502, 503, 504, and 505, complementary MOS output rectification unit 506, NMOS compensation unit 507, and PMOS compensation. Unit 508, load capacitance C L , load resistance R L , and two differential input RF signals RF in +, RF in - and an output DC voltage signal V out ;
所述第一级至第N级的互补MOS整流单元的每一级互补MOS整流单元501、502、503、504和505都具有第一输入端、第二输入端、第一偏置电压端、第二偏置电压端和输出端；Each of the complementary MOS rectifying units 501, 502, 503, 504, and 505 of the complementary MOS rectifying units of the first to N stages has a first input terminal, a second input terminal, and a first bias voltage terminal. a second bias voltage terminal and an output terminal;
当前级互补MOS整流单元的第一输入端与前一级互补MOS整流单元的输出端相连，第二输入端与第一输入信号RFin+或第二输入信号RFin-相连，输出端与下一级互补MOS整流单元的第一输入端相连，第一偏置电压端与前一级互补MOS整流单元的第一输入端相连，第二偏置电压端与后一级互补MOS整流单元的输 出端相连；The first input end of the current-stage complementary MOS rectifying unit is connected to the output end of the complementary MOS rectifying unit of the previous stage, and the second input end is connected to the first input signal RF in + or the second input signal RF in -, the output end and the lower end The first input end of the first complementary MOS rectifying unit is connected, the first bias voltage end is connected to the first input end of the complementary MOS rectifying unit of the previous stage, and the output of the second bias voltage end and the complementary MOS rectifying unit of the latter stage Connected to each other;
第一级互补MOS整流单元501的第一输入端与NMOS补偿单元507的输出端相连，第一偏置电压端与NMOS补偿单元507的第一输入端相连，并一起连接到地；The first input end of the first-stage complementary MOS rectifying unit 501 is connected to the output end of the NMOS compensating unit 507, and the first bias voltage end is connected to the first input end of the NMOS compensating unit 507, and is connected to the ground together;
最后一级互补MOS整流单元505的输出端与PMOS补偿单元508的第一输入端相连，并一起连接到互补MOS输出整流单元506的输入端，第二偏置电压端与PMOS补偿单元508的输出端相连；The output of the last stage complementary MOS rectifying unit 505 is connected to the first input of the PMOS compensation unit 508, and is connected together to the input of the complementary MOS output rectifying unit 506, and the output of the second bias voltage terminal and the PMOS compensating unit 508. Connected to each other;
所述互补MOS输出整流单元506具有一个输入端和一个输出端。其中，输出端和输出信号Vout相连；The complementary MOS output rectifying unit 506 has an input terminal and an output terminal. Wherein the output terminal is connected and the output signal V out;
所述NMOS补偿单元507具有第一输入端、第二输入端、偏置电压端和输出端；其中，第二输入端与第二输入信号相连RFin-相连，偏置电压端与第一级互补MOS整流单元501的输出端相连；The NMOS compensation unit 507 has a first input terminal, a second input terminal, a bias voltage terminal and an output terminal; wherein the second input terminal is connected to the second input signal RF in -, and the bias voltage terminal is connected to the first stage The output ends of the complementary MOS rectifying unit 501 are connected;
所述PMOS补偿单元508具有第一输入端、第二输入端、偏置电压端和输出端；其中，第二输入端与第一输入信号RFin+相连，偏置电压端与最后一级互补MOS整流单元505的第一输入端相连；The PMOS compensation unit 508 has a first input terminal, a second input terminal, a bias voltage terminal and an output terminal; wherein the second input terminal is connected to the first input signal RF in + , and the bias voltage terminal is complementary to the last level The first input end of the MOS rectifying unit 505 is connected;
所述负载电容CL的一端与输出信号Vout相连，另一端与地相连；One end of the load capacitor C L is connected to the output signal V out and the other end is connected to the ground;
所述负载电阻RL的一端与输出信号Vout相连，另一端与地相连。One end of the load resistor R L is connected to the output signal V out and the other end is connected to the ground.
其中，第一级互补MOS整流单元501包括：一个PMOS晶体管Mp1、一个NMOS晶体管Mn1和一个耦合电容C；The first-stage complementary MOS rectifying unit 501 includes: a PMOS transistor M p1 , an NMOS transistor M n1 and a coupling capacitor C;
所述PMOS晶体管Mp1的源极与该级互补MOS整流单元501的第一输入端相连，栅极与该级互补MOS整流单元501的第一偏置电压端相连，漏极和衬底连接在一起，并与NMOS晶体管Mn1的漏极和衬底相连；The source of the PMOS transistor M p1 is connected to the first input terminal of the complementary MOS rectifying unit 501 of the stage, the gate is connected to the first bias voltage terminal of the complementary MOS rectifying unit 501 of the stage, and the drain and the substrate are connected Together, and connected to the drain of the NMOS transistor Mn1 and the substrate;
NMOS晶体管Mn1的源极和该级互补MOS整流单元501的输出端相连，栅极与 该级互补MOS整流单元501的第二偏置电压端相连；耦合电容C的一端与该级互补MOS整流单元501的输出端相连，另一端与该级互补MOS整流单元501的第二输入端相连；The source of the NMOS transistor M n1 is connected to the output terminal of the complementary MOS rectifying unit 501 of the stage, and the gate is connected to the second bias voltage terminal of the complementary MOS rectifying unit 501 of the stage; one end of the coupling capacitor C and the complementary MOS rectification of the stage The output end of the unit 501 is connected, and the other end is connected to the second input end of the complementary MOS rectifying unit 501 of the stage;
同样的，第二级互补MOS整流单元502、第三级互补MOS整流单元503、第N-1级互补MOS整流单元504和第N级互补MOS整流单元505的电路组成和连接方式与第一级互补MOS整流单元501的相同，在此不再赘述；Similarly, the circuit composition and connection mode of the second-stage complementary MOS rectifying unit 502, the third-stage complementary MOS rectifying unit 503, the N-1-th complement MOS rectifying unit 504, and the N-th complement MOS rectifying unit 505 are the same as the first stage. The same is true of the complementary MOS rectifying unit 501, and details are not described herein again;
其中，互补MOS输出整流单元506包括：一个PMOS晶体管Mp-out和一个NMOS晶体管Mn-out；所述PMOS晶体管Mp-out的源极与NMOS晶体管Mn-out的栅极相连，并一起与互补MOS输出整流单元506的输入端相连，栅极与NMOS晶体管Mn-out的源极相连，并一起与互补MOS输出整流单元506的输出端相连，漏极和衬底连接在一起，并与NMOS晶体管Mn-out的漏极和衬底相连；The complementary MOS output rectifying unit 506 includes: a PMOS transistor M p-out and an NMOS transistor M n-out ; the source of the PMOS transistor M p-out is connected to the gate of the NMOS transistor Mn -out , and Together with the input of the complementary MOS output rectifying unit 506, the gate is connected to the source of the NMOS transistor Mn -out , and is connected together with the output of the complementary MOS output rectifying unit 506, and the drain and the substrate are connected together. And connected to the drain of the NMOS transistor Mn -out and the substrate;
其中，NMOS补偿单元507包括：一个NMOS晶体管Mnd1和一个耦合电容C；所述NMOS晶体管Mnd1的源极与NMOS补偿单元507的输出端相连，栅极与NMOS补偿单元507的偏置电压端相连，漏极和衬底连接在一起，并一起与NMOS补偿单元507的第一输入端相连；耦合电容C的一端与NMOS补偿单元507的输出端相连，另一端与NMOS补偿单元507的第二输入端相连；The NMOS compensation unit 507 includes: an NMOS transistor M nd1 and a coupling capacitor C; a source of the NMOS transistor M nd1 is connected to an output end of the NMOS compensation unit 507, and a bias voltage terminal of the gate and NMOS compensation unit 507 Connected, the drain and the substrate are connected together and connected together with the first input of the NMOS compensation unit 507; one end of the coupling capacitor C is connected to the output of the NMOS compensation unit 507, and the other end is connected to the second of the NMOS compensation unit 507. Inputs are connected;
其中，PMOS补偿单元508包括：一个PMOS晶体管Mpd1和一个耦合电容C；所述PMOS晶体管Mpd1的源极与PMOS补偿单元508的第一输入端相连，栅极与PMOS补偿单元508的偏置电压端相连，漏极和衬底连接在一起，并一起与PMOS补偿单元508的输出端相连；耦合电容C的一端与PMOS补偿单元508的输出端相连，另一端与PMOS补偿单元508的第二输入端相连。The PMOS compensation unit 508 includes: a PMOS transistor M pd1 and a coupling capacitor C; a source of the PMOS transistor M pd1 is connected to a first input end of the PMOS compensation unit 508 , and a bias of the gate and PMOS compensation unit 508 The voltage terminals are connected, the drain and the substrate are connected together, and are connected together with the output end of the PMOS compensation unit 508; one end of the coupling capacitor C is connected to the output end of the PMOS compensation unit 508, and the other end is connected to the second end of the PMOS compensation unit 508. The inputs are connected.
本发明实施例提供的阈值补偿整流电路的工作原理为：The working principle of the threshold compensation rectifier circuit provided by the embodiment of the present invention is:
为了减小整流单元的反向漏电，在现有阈值补偿技术基础上，采用了互补 MOS晶体管作为整流单元，不仅可以降低整流单元的阈值电压，而且可以有效的抑制其反向漏电，当其应用于射频能量收集系统时，可以提高系统的接收灵敏度和功率转换效率。In order to reduce the reverse leakage of the rectifier unit, based on the existing threshold compensation technology, complementary As a rectifying unit, MOS transistor can not only reduce the threshold voltage of the rectifying unit, but also effectively suppress its reverse leakage. When it is applied to the RF energy harvesting system, it can improve the receiving sensitivity and power conversion efficiency of the system.
具体的，结合图5，根据Dickson多级整流电路的工作原理，当输入为差分的射频信号时，整流电路对输入信号的正负半周同时整流，每个整流单元只在输入信号的半个周期内导通。Specifically, in combination with FIG. 5, according to the working principle of the Dickson multi-stage rectifier circuit, when the input is a differential RF signal, the rectifier circuit rectifies the positive and negative half cycles of the input signal simultaneously, and each rectifier unit is only in the half cycle of the input signal. Internal conduction.
为了更清晰的说明整流电路的工作原理，图6给出了整流电路工作时输入电压和输出电流的瞬态仿真波形图。可以看出，输入信号的一个正弦周期，可分为3个工作区域：In order to more clearly explain the working principle of the rectifier circuit, Figure 6 shows the transient simulation waveform of the input voltage and output current during the operation of the rectifier circuit. It can be seen that a sinusoidal period of the input signal can be divided into three working areas:
亚阈值区：0≤Vin≤Vth，其中Vin为输入信号的幅度，Vth为整流单元的阈值电压，在这个范围内输出电流与输入电压呈指数关系，此时输入电压较小，输出电流也较小；Subthreshold region: 0 ≤ V in ≤ V th , where V in is the amplitude of the input signal, and V th is the threshold voltage of the rectifying unit. In this range, the output current is exponentially related to the input voltage, and the input voltage is small. The output current is also small;
反型区：Vth≤Vin≤Vin,max，其中Vin,max为输入信号幅度的最大值，在这个范围内输出电流与输入电压呈平方关系，此时整流单元完全导通，对负载电容进行充电，并在Vin＝Vin,max处，输出电流达到峰值；Inversion zone: V th ≤V in ≤V in,max , where V in,max is the maximum value of the input signal amplitude, in which the output current is squared with the input voltage, and the rectifying unit is fully turned on, The load capacitor is charged, and at V in =V in,max , the output current reaches a peak value;
漏电区：输入电压的负半周，在这段时间内的输出电流为反向漏电流。Leakage zone: The negative half cycle of the input voltage during which the output current is reverse leakage current.
因此，可以看出，在输入信号的每个正弦周期内，只有反型区是在给电容充电，而大部分时间都处在亚阈值区和漏电区。若要提高整流电路的转换效率，应设法增大反型区的时间，同时减小反向漏电的大小。Thus, it can be seen that during each sinusoidal period of the input signal, only the inversion region is charging the capacitor, and most of the time is in the subthreshold region and the drain region. To improve the conversion efficiency of the rectifier circuit, try to increase the time of the inversion zone while reducing the magnitude of the reverse leakage.
现有阈值补偿技术只是减小了整流单元的阈值，增大了反型区时间，但是并没有对反向漏电进行抑制，本发明在阈值补偿技术的基础上，采用了互补型MOS整流单元，不仅实现了低阈值电压，而且有效的抑制了反向漏电，使整流电路的转换效率得到提高。 The existing threshold compensation technique only reduces the threshold of the rectifying unit and increases the inversion time, but does not suppress the reverse leakage. The invention adopts a complementary MOS rectifying unit based on the threshold compensation technology. Not only the low threshold voltage is realized, but also the reverse leakage is effectively suppressed, and the conversion efficiency of the rectifier circuit is improved.
具体的，本发明所提供的互补MOS整流单元，以图5中第二级互补MOS整流单元为例进行说明。当整流单元正向偏置时，由于采用了阈值补偿技术，根据Dickson多级整流电路中各节点电压从输入到输出逐渐升高的特点，即V0<V1<V2<V3，Mp2和Mn2都表现为MOS晶体管的正向导通特性，这样其正向导通压降比传统二极管作为整流器件的正向导通压降(二极管的阈值电压)小得多，即等效为整流器件的阈值电压被降低。当整流单元反向偏置时，Mp2和Mn2的源极出现在二者相互连接处，即Mp2和Mn2都具有负的Vgs，工作在非常弱的反型区，表现为MOS晶体管的反向截止特性，与现有的单纯的阈值补偿技术(图2)相比，整流单元的反向电流被有效的抑制住，使得反向漏电大大的被降低。Specifically, the complementary MOS rectifying unit provided by the present invention is described by taking the second-stage complementary MOS rectifying unit in FIG. 5 as an example. When the rectifying unit is forward biased, due to the threshold compensation technique, the voltage of each node in the Dickson multi-stage rectification circuit is gradually increased from input to output, that is, V 0 <V 1 <V 2 <V 3 , M Both p2 and Mn2 behave as the forward conduction characteristics of the MOS transistor, so that its forward voltage drop is much smaller than the forward voltage drop (the threshold voltage of the diode) of the conventional diode as a rectifying device, that is, equivalent to a rectifying device. The threshold voltage is lowered. When the rectifying unit is reverse biased, the sources of M p2 and M n2 appear at the mutual connection, that is, both M p2 and M n2 have negative V gs , and work in a very weak inversion region, which is expressed as MOS. The reverse turn-off characteristic of the transistor, compared with the existing simple threshold compensation technique (Fig. 2), the reverse current of the rectifying unit is effectively suppressed, so that the reverse leakage is greatly reduced.
本发明实施例提供的阈值补偿整流电路的整流单元在正向偏置时表现为MOS晶体管的正向导通特性，具有较低的导通压降，等效为降低了整流单元的阈值电压；在反向偏置时表现为MOS晶体管的反向截止特性，大大减小了整流单元的反向漏电。从而，不仅实现了较低的阈值电压，而且有效的抑制了反向漏电，提高了功率转换效率。使其应用于射频能量收集系统时，对射频收集系统的接收灵敏度和效率都有提高。The rectifying unit of the threshold compensation rectifying circuit provided by the embodiment of the present invention exhibits a forward conduction characteristic of the MOS transistor when forward biased, and has a lower conduction voltage drop, which is equivalent to lowering the threshold voltage of the rectifying unit; When reverse biased, it appears as the reverse cut-off characteristic of the MOS transistor, which greatly reduces the reverse leakage of the rectifying unit. Thereby, not only a lower threshold voltage is achieved, but also reverse leakage is effectively suppressed, and power conversion efficiency is improved. When applied to an RF energy harvesting system, the receiving sensitivity and efficiency of the RF collection system are improved.
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。 The above is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. All should be covered by the scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims (3)

  1. 一种阈值补偿整流电路，其特征在于，包括：A threshold compensation rectifier circuit, comprising:
    第一级至第N级的互补MOS整流单元、互补MOS输出整流单元以及负载电容和负载电阻；a complementary MOS rectifying unit of a first stage to an Nth stage, a complementary MOS output rectifying unit, and a load capacitor and a load resistor;
    所述第一级至第N级的互补MOS整流单元的每一级互补MOS整流单元都具有第一输入端、第二输入端和输出端；当前级互补MOS整流单元的第一输入端与前一级互补MOS整流单元的输出端相连，第二输入端与第一输入信号或第二输入信号相连，输出端与下一级互补MOS整流单元的第一输入端相连；第一级互补MOS整流单元的第一输入端与地相连；最后一级互补MOS整流单元的输出端与互补MOS输出整流单元的输入端相连；Each of the complementary MOS rectifying units of the first to Nth stages of the complementary MOS rectifying unit has a first input end, a second input end, and an output end; the first input end of the current stage complementary MOS rectifying unit The output end of the first-stage complementary MOS rectifying unit is connected, the second input end is connected to the first input signal or the second input signal, and the output end is connected to the first input end of the next-stage complementary MOS rectifying unit; the first-stage complementary MOS rectification The first input end of the unit is connected to the ground; the output end of the last stage complementary MOS rectifying unit is connected to the input end of the complementary MOS output rectifying unit;
    所述互补MOS输出整流单元具有一个输入端和一个输出端；其中，所述互补MOS输出整流单元的输出端与输出信号相连；The complementary MOS output rectifying unit has an input end and an output end; wherein an output end of the complementary MOS output rectifying unit is connected to an output signal;
    所述负载电容的一端与输出信号相连，另一端与地相连；One end of the load capacitor is connected to the output signal, and the other end is connected to the ground;
    所述负载电阻的一端与输出信号相连，另一端与地相连。One end of the load resistor is connected to the output signal and the other end is connected to the ground.
  2. 根据权利要求1所述的阈值补偿整流电路，其特征在于，所述每一级互补MOS整流单元包括：一个PMOS晶体管、一个NMOS晶体管、第一偏置电压源、第二偏置电压源和一个耦合电容。The threshold compensation rectifying circuit according to claim 1, wherein each of the complementary MOS rectifying units comprises: a PMOS transistor, an NMOS transistor, a first bias voltage source, a second bias voltage source, and a Coupling capacitor.
    所述PMOS晶体管的源极与所述第二偏置电压源的负端相连，并一起连接到该级互补MOS整流单元的第一输入端，所述PMOS晶体管的栅极与所述第一偏置电压源的负端相连，所述PMOS晶体管的漏极和衬底连接在一起，并与所述NMOS晶体管的漏极和衬底相连；a source of the PMOS transistor is connected to a negative terminal of the second bias voltage source, and is connected together to a first input end of the complementary MOS rectifying unit of the stage, a gate of the PMOS transistor and the first bias The negative terminal of the voltage source is connected, the drain of the PMOS transistor is connected to the substrate, and is connected to the drain of the NMOS transistor and the substrate;
    所述NMOS晶体管的源极与所述第一偏置电压源的正端相连，并一起连接到该级互补MOS整流单元的输出端，所述NMOS晶体管的栅极与所述第二偏置电压 源的正端相连；a source of the NMOS transistor is coupled to a positive terminal of the first bias voltage source and is coupled together to an output of the complementary MOS rectifier unit of the stage, a gate of the NMOS transistor and the second bias voltage The positive ends of the sources are connected;
    所述耦合电容的一端与该级互补MOS整流单元的输出端相连，另一端与该级互补MOS整流单元的第二输入端相连。One end of the coupling capacitor is connected to the output end of the complementary MOS rectifying unit of the stage, and the other end is connected to the second input end of the complementary MOS rectifying unit of the stage.
  3. 根据权利要求1所述的阈值补偿整流电路，其特征在于，所述互补MOS输出整流单元包括：一个PMOS晶体管和一个NMOS晶体管；The threshold compensation rectifying circuit according to claim 1, wherein the complementary MOS output rectifying unit comprises: a PMOS transistor and an NMOS transistor;
    所述PMOS晶体管的源极与所述NMOS晶体管的栅极相连，并一起与互补MOS输出整流单元的输入端相连，所述PMOS晶体管的栅极与所述NMOS晶体管的源极相连，并一起与互补MOS输出整流单元的输出端相连，所述PMOS晶体管的漏极和衬底连接在一起，并与所述NMOS晶体管的漏极和衬底相连。 a source of the PMOS transistor is connected to a gate of the NMOS transistor, and is connected together with an input end of a complementary MOS output rectifying unit, a gate of the PMOS transistor is connected to a source of the NMOS transistor, and together The output of the complementary MOS output rectifying unit is connected, and the drain of the PMOS transistor is connected to the substrate and connected to the drain of the NMOS transistor and the substrate.
PCT/CN2015/072205 2015-02-04 2015-02-04 Threshold compensation rectification circuit WO2016123756A1 (en)

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US8326256B1 (en) * 2008-07-15 2012-12-04 Impinj, Inc. RFID tag with MOS bipolar hybrid rectifier
CN103023114A (en) * 2012-12-08 2013-04-03 河南师范大学 Integrated rechargeable battery device
CN203217613U (en) * 2013-04-19 2013-09-25 浙江师范大学 UHF RFID passive label chip power supply circuit
CN104269946A (en) * 2014-10-30 2015-01-07 桂林电子科技大学 Radio frequency energy collector
CN204103611U (en) * 2014-10-30 2015-01-14 桂林电子科技大学 A kind of radio frequency energy collector

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8326256B1 (en) * 2008-07-15 2012-12-04 Impinj, Inc. RFID tag with MOS bipolar hybrid rectifier
CN103023114A (en) * 2012-12-08 2013-04-03 河南师范大学 Integrated rechargeable battery device
CN203217613U (en) * 2013-04-19 2013-09-25 浙江师范大学 UHF RFID passive label chip power supply circuit
CN104269946A (en) * 2014-10-30 2015-01-07 桂林电子科技大学 Radio frequency energy collector
CN204103611U (en) * 2014-10-30 2015-01-14 桂林电子科技大学 A kind of radio frequency energy collector

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