WO2016112511A1 - 一种数据混洗的装置及方法 - Google Patents

一种数据混洗的装置及方法 Download PDF

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Publication number
WO2016112511A1
WO2016112511A1 PCT/CN2015/070767 CN2015070767W WO2016112511A1 WO 2016112511 A1 WO2016112511 A1 WO 2016112511A1 CN 2015070767 W CN2015070767 W CN 2015070767W WO 2016112511 A1 WO2016112511 A1 WO 2016112511A1
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data
address
shuffling
shuffled
module
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PCT/CN2015/070767
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English (en)
French (fr)
Inventor
柴守刚
梁文亮
王文会
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华为技术有限公司
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Priority to PCT/CN2015/070767 priority Critical patent/WO2016112511A1/zh
Priority to CN201580049773.1A priority patent/CN106716384A/zh
Publication of WO2016112511A1 publication Critical patent/WO2016112511A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures

Definitions

  • the present invention relates to the field of computers, and in particular, to an apparatus and method for data shuffling.
  • the shuffling process refers to reordering the elements in a set.
  • the array ⁇ a, b, c, d, e ⁇ can be arbitrarily exchanged by array elements through different specified shuffling operations. Get a new array, such as: ⁇ b,e,d,a,c ⁇ .
  • the central processing unit reads data that needs to be shuffled from the memory;
  • the CPU calls the shuffling function to complete the shuffling operation
  • the CPU writes the data of the shuffle operation back to the memory.
  • the inventor of the present invention found in the research and practice of the above prior art that since the shuffling operation is realized by the CPU, it occupies the computing resources of the CPU, and the memory starts and ends respectively. Operation, so when the amount of data to be shuffled is large, it takes a long time for data transfer, and it is necessary to open up the cache array space. When the internal cache space of the CPU is not enough, the cache array needs to be put into the memory. It will increase the number of reads and writes of memory, further increasing the processing delay of the entire operation.
  • Embodiments of the present invention provide a device and method for data shuffling, which can implement a shuffling process in a processor other than the shuffling device, save a large amount of computing resources in the processor, and reduce data processing delay.
  • a first aspect of the present invention provides a device for data shuffling, the device being applied to a buffer chip of a memory, the memory further comprising a memory chip, the device comprising: a cache module and a shuffling module;
  • the cache module is communicatively coupled to the shuffling module
  • the cache module is configured to cache a first address of each data in the data set to be shuffled and an address offset of each data;
  • the shuffling module is configured to calculate, according to the first address of each data and an address offset of each data, a second address of each of the data, where the second address is used to indicate a mix a storage location of each of the washed data in the memory chip;
  • the shuffling module is configured to perform data interaction with the storage chip according to the second address, to implement adjustment of a data sequence in the data group to be shuffled, and obtain a data set after shuffling.
  • the cache module is an address cache module, the address cache module is communicatively coupled to the shuffling module, and the address cache module is configured to cache data to be shuffled.
  • the cache module includes an address cache module and a control cache module, the address cache module is configured to cache a first address of each data in the data set to be shuffled, and the control cache module is configured to cache an address of each of the data. Offset; or,
  • the cache module includes an address cache module and an offset cache module, the address cache module is configured to cache a first address of each data in the data set to be shuffled, and the offset cache module is configured to cache each of the data.
  • the address offset is configured to cache a first address of each data in the data set to be shuffled.
  • the shuffling module is configured to perform data interaction with the storage chip according to the second address, to implement The data sequence in the data set to be shuffled is adjusted to obtain a data set after shuffling, which may include:
  • the shuffling module is configured to transmit the to-be-shuffled data set and the second address of each of the data to the memory chip, so that the memory chip according to the second address of each of the data
  • the data to be shuffled is written into a storage location corresponding to the second address of each data, so that the data sequence in the data set to be shuffled is adjusted to obtain a data set after shuffling.
  • the shuffling module is configured to perform data interaction with the memory chip according to the second address, to implement The data sequence in the data set to be shuffled is adjusted to obtain a data set after shuffling, which may include:
  • the shuffling module is configured to transmit a second address of each of the data to the memory chip, so that the memory chip follows the second address of each data, from the second address of each data Reading, by the corresponding storage location, each of the data to achieve a sequence of data in the data set to be shuffled Adjust to get the data set after shuffling.
  • the shuffling module may include: a mode selection register,
  • the mode selection register is configured to acquire a shuffling switch control word, and the shuffling switch control word is used to indicate that the data shuffling function is turned on or off;
  • the mode selection register is configured to acquire an address offset of each of the data from the cache module when the shuffle switch control word indicates that the data shuffling function is turned on.
  • the address offset of each data in the data to be shuffled The absolute value is less than the size of the total storage space for storing each of the data, and the sum of the address offsets of each of the data is zero.
  • the memory further includes a bus, where a configuration line connected to the mode selection register is configured in the bus,
  • One end of the configuration line is connected to the mode selection register, and the other end is connected to a chip other than the memory through a slot of the memory;
  • the mode selection register is used to acquire a shuffle switch control word, including:
  • the mode select register is configured to receive the shuffle switch control word configured by a user through the configuration line.
  • the shuffling module is configured to use the first address according to each of the data And calculating, by the address offset of each data, a second address of each of the data, including:
  • the shuffling module is configured to invoke an address mapping function to calculate a second address of each of the data, where the address mapping function is a second address of each of the data and a first address of each of the data A mapping relationship between the sum of the address offsets of each of the data.
  • a second aspect of the present invention provides a data shuffling method, the method is applied to a buffer chip of a memory, and the memory further includes a memory chip, including:
  • the data is exchanged with the memory chip according to the second address, and the data sequence in the data group to be shuffled is adjusted to obtain a shuffle.
  • the storage location corresponding to the second address of each data is used to adjust the order of the data in the data set to be shuffled to obtain a data set after shuffling.
  • the data is exchanged with the memory chip according to the second address, and the data sequence in the data group to be shuffled is adjusted to obtain a shuffle.
  • the address offset can include:
  • the shuffling switch control word is used to indicate that the data shuffling function is turned on or off;
  • the first address and each of the data according to the The address offset of the data, and the second address of each of the data is calculated, which may include:
  • an address mapping function to calculate a second address of each of the data, the address mapping function being a second address of each of the data and a first address of each of the data and each of the data The mapping relationship between the sum of the address offsets.
  • a third aspect of the present invention provides an apparatus for data shuffling, comprising:
  • An obtaining module configured to acquire a first address of each data in the data group to be shuffled and an address offset of each data
  • a calculating module configured to calculate, according to the first address of each data and an address offset of each of the data, a second address of each data, where the second address is used to indicate after shuffling a storage location of each of the data in the memory chip;
  • an adjusting module configured to perform data interaction with the storage chip according to the second address, to implement adjustment of a data sequence in the data group to be shuffled, and obtain a data set after shuffling.
  • the adjusting module may include:
  • a first transmission unit configured to transmit, to the memory chip, the to-be-mixed data set and a second address of each of the data, so that the memory chip according to the second address of each of the data
  • the data to be shuffled is written into a storage location corresponding to the second address of each data, so that the data sequence in the data set to be shuffled is adjusted to obtain a data set after shuffling.
  • the adjusting module includes:
  • a second transmission unit configured to transmit a second address of each of the data to the memory chip, so that the memory chip follows the second address of each data, from the second address of each data
  • the corresponding storage location reads the data, and implements adjustment of the data sequence in the dataset to be shuffled to obtain a data set after shuffling.
  • the acquiring module may include:
  • a first acquiring unit configured to acquire a shuffling switch control word, where the shuffling switch control word is used to indicate that the data shuffling function is turned on or off;
  • a second acquiring unit configured to acquire a first address of each data and an address offset of each of the data when the shuffling switch control word indicates that the data shuffling function is turned on.
  • the calculating module may include:
  • a calculating unit configured to call an address mapping function, to calculate a second address of each of the data, the address mapping function is a second address of each of the data and a first address of each of the data and the The mapping relationship between the sum of the address offsets of each data.
  • the device in the data buffering device application and the memory buffer chip provided, only the buffer chip in the memory needs to be improved, instead of the entire memory structure, so that the implementation is more simple and convenient, and at the same time, the device is
  • the shuffling function is implemented in hardware through the memory, and the process of reading and writing data is performed at the same time. It is not necessary to use the processor outside the memory to complete the above process, which can largely save the computing resources of the processor, especially It reduces the workload of the CPU, and also greatly reduces the delay of data processing. When the amount of data is large, the advantage of short data transmission time is further reflected.
  • FIG. 1 is a schematic diagram of a memory in an embodiment of the present invention.
  • FIG. 2 is a schematic diagram showing the internal structure of a memory chip in an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a newly added shuffling module in a buffer chip according to an embodiment of the present invention.
  • FIG. 4 is a structure of a shuffling module in an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a function control word of a mode selection register in an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a process of data shuffling and writing performed by a device for data shuffling in an embodiment of the present invention
  • FIG. 7 is a schematic diagram of a process of data shuffling and reading performed by a device for data shuffling in an embodiment of the present invention
  • FIG. 8 is a schematic diagram of an embodiment of a method for data shuffling in an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of an embodiment of a device for data shuffling in an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of another embodiment of a device for data shuffling in an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of another embodiment of a device for data shuffling in an embodiment of the present invention.
  • FIG. 12 is a schematic diagram of another embodiment of a device for data shuffling in an embodiment of the present invention.
  • FIG. 13 is a schematic diagram of another embodiment of a device for data shuffling in an embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram of an apparatus for data shuffling according to an embodiment of the present invention.
  • the embodiment of the invention provides a data shuffling method, which can save a large amount of computing resources in the processor and reduce data processing delay.
  • Embodiments of the present invention also provide corresponding apparatus for data shuffling. The details are described below separately.
  • FIG. 1 is a schematic diagram of a memory. Referring to FIG. 1, the data shuffling process in the embodiment of the present invention is performed in a memory.
  • the memory consists of several memory chips and one buffer chip.
  • FIG. 1 the eight memory chips in FIG. 1 are only one schematic. In practical applications, the number of memory chips is not specifically limited.
  • Memory is a channel that connects the CPU and other devices, and functions as a buffer and data exchange.
  • the CPU When the CPU is working, it needs to read data from an external memory such as a hard disk, but because of the large storage capacity of the external memory and the distance from the CPU. The location is far away, so the speed of transferring data will slow down, resulting in lower CPU efficiency.
  • memory is built between the external memory and the CPU, and the memory depends on the memory, and the contents of all the external memory. All need to pass through the memory to make a difference.
  • Some routine programs such as Windows XP, typing software, and game software, are usually installed on external storage such as hard disks, but they cannot be used. They must be loaded into memory to run. Really realize its function, so usually store a large amount of data to be permanently saved in external memory, and put some temporary or small amount of data and programs in memory.
  • FIG. 2 is a schematic diagram of an internal structure of a memory chip.
  • a memory chip is located in a memory.
  • Each of the storage chips is composed of a plurality of storage arrays, each of which is a two-dimensional storage array composed of a plurality of rows and a plurality of columns, and each storage array corresponds to one row of buffers.
  • the storage size of the line buffer corresponds to the storage size of each row in the storage array, and each storage array further includes a data cache module and an address cache module corresponding to the external interface of the memory chip, and the data cache module is used to put some data.
  • the bit width of the data buffer module is usually much smaller than the bit width of the line buffer. This is because the bit width of the data bus is limited.
  • the data bus is responsible for the transfer of data between the components in the computer.
  • the data bus width refers to the inside of each chip. The width of the data transfer, and the data bus width determines the amount of information transferred between the CPU and the L2 cache, memory, and input or output devices. For example, if the data bus width of the CPU is 64 bits, it can transmit data at a time. The maximum value is 64 bits, that is, 8 bytes can be processed at a time.
  • FIG. 2 the two storage arrays in FIG. 2 are one schematic. In practical applications, the number of storage arrays in the storage chip is not specifically limited.
  • the data information and the address information enter the data cache module and the address cache module of the corresponding storage array through an interface outside the storage chip;
  • the data of the entire line buffer is flushed to the corresponding row according to the row information in the address information.
  • the present invention proposes a scheme for directly implementing data shuffling in the memory of the computer, that is, adding a shuffling module to the buffer chip of the memory to realize the shuffling function during data reading and writing.
  • FIG 3 is a schematic diagram of a new shuffling module in the buffer chip, see Figure 3, the buffer chip package
  • the bus interface module, the data cache module, the control cache module, the address cache module, and the shuffling module are included.
  • the cache chip may further include an offset cache module.
  • the bus interface module is used for inter-association between different devices, a common set of lines, configured with appropriate interface circuits, connected with various components and peripheral devices, and a common path for transmitting information between the various components is called a bus.
  • the bus of the computer can be divided into a data bus (DB, Data Bus), a control bus (CB, Control Bus) and an address bus (AB, Address Bus).
  • the main function of the buffer chip is to buffer the signals of DB, CB and AB. Plastic surgery.
  • control cache module mainly functions to buffer control signals and timing signals. Some of the control signals are sent to the memory and the input/output device interface circuit, such as read or write signals.
  • the chip select signal or the interrupt response signal is also fed back to the CPU by other components, such as the interrupt request signal, the reset signal, the bus request signal, or the ready ready signal. There may be other control signals, and the specific use depends on the CPU. Demand.
  • connection form is related to the circuit design, so the connection form is not used here. Make a limit.
  • the shuffling module can be connected to the address caching module, or can be connected to the address caching module and the control cache module, and can also be connected to the address caching module and the offset caching module, and the connection mode is a communication connection.
  • the shuffling process does not change the data itself, but is related to the control signal and the address signal, so the shuffling module is mainly used to send and receive the signal stream transmitted from the data buffer module and the control buffer module. It should be noted that, in this solution, only the buffer chip on the memory is modified, and the memory chip on the memory is not modified, so the present invention does not change much for the memory.
  • FIG 4 is a schematic diagram of the structure of the shuffling module.
  • the function of the shuffling is to realize the rearrangement of the data in the memory, that is, the address of the data after the shuffling changes, so as long as each data is known
  • the shuffle function is implemented by swapping the original address with the new address and then swapping each data from the original address to the new address.
  • it is necessary to know the offset of the new address of each data relative to the original address. Assuming the original address is addr_old and the address offset is shift, the new address is addr_new addr_old+shift.
  • the shuffling module can be an address conversion module.
  • an embodiment of the present invention further provides an application programming interface (API, Application).
  • API is a call interface left by the operating system to the application.
  • the application causes the operating system to execute the command or action of the application by calling the API of the operating system.
  • the API is a predefined function to provide the application. The ability of a program and developer to access a set of routines based on a piece of software or hardware without having to access the source code or understand the details of the internal workings.
  • An API can be used as a specification that specifies the intersection between two software. The way data is exchanged.
  • a unified API which encapsulates the memory-based shuffling function, that is, the properties and implementation details of the object are hidden in the program, and only the public is disclosed.
  • the interface controls the access level of attribute reading and modification in the program, and combines the abstracted data and functions to form an organic whole, that is, organically combines the data with the source code of the operation data to form a "class".
  • the data and functions are members of the "class". The user only needs to call the interface function to implement the shuffling operation.
  • API function of the writing process can be defined as:
  • the expression (1) indicates that the memory is shuffling while the data is being written
  • Data1 refers to the data to be written
  • size1 refers to the bit width of each data element to be written
  • shift1 is an array representing each The address offset corresponding to the data.
  • the expression (2) indicates that the memory performs the data shuffling operation while reading the data
  • ShuffledData indicates the data after the shuffling operation
  • Data2 refers to the data before the shuffling
  • size2 refers to the bit width of the data element to be read.
  • Shift2 is an array representing the address offset corresponding to each data.
  • the mode selection register acquires an address offset of a user-configured data to be shuffled through an API, and stores a user-configured address offset. .
  • the user can configure the mode select register as needed.
  • the shuffling module further includes a mode selection register for obtaining a shuffling switch control word, the shuffling switch control word is used to indicate to turn the data shuffling function on or off, when the shuffling switch control word
  • the mode selection register can obtain the address offset corresponding to each data from the cache module, and the absolute value of each address offset is smaller than the total storage space for storing each data.
  • the function implemented by the shuffling module is to add the original address and address offset to get the new address.
  • the original address is transferred from the processor through the address bus, such as a CPU or a microprocessor.
  • the address offset is extracted from the mode selection register, and the memory uses the calculated new address to read or write data, thereby The original address is changed to the new address, and the shuffling function is finally completed.
  • S_on is the size indicating the size of each data element, and usually the bit width of the downlink buffer is larger than the bit width of the data element, so there is enough space in the line buffer to store each data, which will not cause The overflow of data.
  • shift_0 indicates the address offset of the data corresponding thereto
  • shift_1 indicates the address offset of the data corresponding to -3
  • the address offset of each corresponding data is sequentially set. Ding, through the data shuffling between multiple lines, but also achieve the purpose of data shuffling between multiple columns.
  • opening up space you can open up a large space. If the space is large, you can store the data written next time. If you write it multiple times, you should open up a large space first, and then write the data multiple times. Mix with and fill these spaces.
  • the memory also includes a bus in which one or more configuration lines connected to the mode selection register are arranged, and one end of the configuration line is connected to the mode selection register, and the other end is a slot and memory through the memory.
  • Other chips are connected.
  • the chip outside the memory may be a CPU chip, a north bridge chip, or other chips that implement address offset input or output.
  • the North Bridge chip is an important part of the main board chipset, also known as the main bridge.
  • the name of the chipset is named after the name of the Northbridge chip.
  • the Northbridge chip of the Intel 845E chipset is 82845E.
  • the north bridge chip of the 875P chipset is 82875P.
  • the north bridge chip is responsible for contacting the CPU and controlling the memory to provide the front side bus frequency for the CPU type, the main frequency and the system.
  • the user can write the register control word through this dedicated configuration line, and these written control words are used to enable or disable the data shuffling function, set the data corresponding address offset, or write other information according to user requirements.
  • Control word and then the data shuffling device obtains the user through a dedicated configuration
  • the information of the line configuration is used for data shuffling. This method needs to modify the hardware interface of the memory.
  • mode selection register there are other ways to configure the mode selection register. For example, using the existing control lines in the memory, modifying the protocol of the control line, increasing the transmission process of the register control word, and then modifying the protocol by the data shuffling device. Get user-configured information that does not require modifying the hardware interface of the memory. There may be other ways of implementation, and thus are not limited herein.
  • FIG. 6 is a schematic diagram of a process of data shuffling and writing performed by a data shuffling apparatus according to an embodiment of the present invention. Referring to FIG. 6, a schematic diagram of a data shuffling writing process is shown.
  • the data shuffling device is applied to the buffer chip of the memory, and the memory further includes a memory chip.
  • the device includes a cache module and a shuffling module, and the communication connection between them is used, and the cache module is used for buffering to be mixed.
  • the first address is used to indicate the storage location of each data before the shuffling in the memory chip, and the shuffling module according to each The first address of the data and the address offset of each data, the second address of each data is calculated, and the second address is used to indicate the storage location of each data after the shuffling in the storage chip, the shuffling module Then, according to the second address and the memory chip for data interaction, the data sequence in the shuffle data set is adjusted, and the shuffled data set is obtained.
  • the cache module may be an address cache module, an address cache module and a control cache module, or an address cache module and an offset cache module.
  • the composition of the cache module is not limited herein.
  • the shuffling module can transmit the data set to be shuffled and the second of each data to the memory chip.
  • the address is such that the memory chip writes the data to be shuffled to the storage location corresponding to the second address of each data according to the second address of each data, thereby realizing the adjustment of the data sequence in the data group to be shuffled, and obtaining the shuffled Data collection.
  • the first address is not manually allocated and written, but is uniformly allocated and managed by the operating system, and the first address in the address cache module may also be discontinuous under special circumstances. In this case, the selection and arrangement of the first address are not limited here.
  • the CPU writes the first address of the data into the address cache module, the first addresses are 50, 51, 52, 53, 54, 55, and the data a, b, c, d, e, f are written into the data cache module.
  • Address offset 0, -3, -6, 2, 7, -1 are written into the control cache, where the data and address offsets are set by the programmer, and the first address is automatically assigned by the system;
  • the shuffling module calls the address mapping function void MemShuffleWrt (&Data1, size1, shift1), and calculates the second address of each data.
  • the address mapping function is the second address of each data and the first address and each data of each data. a mapping relationship between the sum of address offsets;
  • the second addresses are calculated to be 50, 48, 46, 55, 61, 54 respectively, so the data in the data buffer module is written into the line buffer according to the second address, and then a memory refresh operation is performed, and the line buffer is used.
  • the data brush is returned to the storage array to complete the data writing and shuffling operations.
  • the address may be inserted and not inserted.
  • the first address is continuous, and the second address is not continuous; when not inserted, the first address It is continuous, and the second address is also continuous, except that the order corresponding to the address has changed.
  • the sum of the address offsets is not necessarily zero. This is because there is no limit to the address offset when the space is inserted. When it is zero, the data written can be left or right. It can be other ways, and in most cases it is not zero.
  • FIG. 7 is a schematic diagram showing the process of data shuffling and reading performed by the data shuffling apparatus in the embodiment of the present invention. Referring to FIG. 7, a schematic diagram of the data shuffling reading process is shown.
  • a method of data shuffling readout process is provided, and a device for performing data shuffling of the method is also provided, and the device is identical to the device described in the embodiment corresponding to FIG. 6 above. Therefore, it is not described here.
  • the shuffling module transmits a second address of each data to the memory chip, so that the memory chip is in accordance with each The second address of the data reads each data from the storage location corresponding to the second address of each data, and adjusts the order of the data in the shuffled data set to obtain a shuffled data set.
  • the CPU writes the first address of the data to the address cache module, and the first addresses are 50, 51, 52, respectively. 53,54,55, and these addresses must be consecutive segments, writing address offsets 1, 1, 1, 1, 1, and -5 into the control cache, where the data and address offsets are set by the programmer.
  • the first address is automatically assigned by the system;
  • the address mapping function is the second address of each data and the first address of each data and the address of each data. a mapping relationship between the sum of offsets;
  • the calculated second addresses are 51, 52, 53, 54, 55, 50 respectively. It can be seen that the data is cyclically shifted right after shuffling, and then the row of the storage array where the second address corresponds to the data is refreshed to the row. In the buffer, finally, the data corresponding to the second address in the line buffer is downloaded into the data buffer module and the data is read out through the data bus, and the data reading and shuffling operations are completed.
  • the data shuffling device needs to call an address mapping function, and the second address of each data is calculated by the function, and the address mapping function is the first of each data.
  • the data shuffling device of the present invention can be applied to a mobile phone memory, a random access memory (RAM) or an embedded system due to its quick configuration function, and can also be applied to a base station system.
  • a base station system For example, in a multi-antenna multi-user mobile communication data processing, it takes about 100 us to perform a shuffling operation, and the data shuffling device proposed by the present invention directly implements data shuffling in the memory, and only requires a few clocks. The cycle can be completed. Assuming that the clock frequency of the memory module is 1600MHz, the shuffling operation can be time in the order of ns. Therefore, the apparatus for data shuffling proposed by the present invention is suitable for use in a storage device.
  • the device in the data buffering device application and the memory buffer chip provided, only the buffer chip in the memory needs to be improved, instead of the entire memory structure, so that the implementation is more simple and convenient, and at the same time, the device is
  • the shuffling function is implemented in hardware through the memory, and the process of reading and writing data is performed at the same time. It is not necessary to use the processor outside the memory to complete the above process, which can largely save the computing resources of the processor, especially It reduces the workload of the CPU, and also greatly reduces the delay of data processing. When the amount of data is large, the data transmission time is further reflected. Short advantage.
  • an embodiment of a data shuffling method according to an embodiment of the present invention includes:
  • the data shuffling device acquires a first address of each data in the data group to be shuffled, and the first address is used to indicate a storage location in the memory chip before each data shuffling, and at the same time, the data is mixed.
  • the washed device also obtains the address offset corresponding to each data.
  • the data shuffling device calculates a second address corresponding to each data according to the first address of each data and the address offset of each data, and the second address is used to indicate each after shuffling.
  • the data shuffling device performs data interaction with the memory chip according to the calculated second address, and can adjust the data sequence in the shuffle data set to obtain a shuffled data set.
  • the data shuffling device obtains the first address of each data in the data to be shuffled and the corresponding address offset, and obtains a second address corresponding to each data by calculation, according to the second address and storage.
  • the data interaction of the chip realizes the order adjustment of the data to be shuffled, and the data after shuffling is obtained, and the above process is applied to the cache chip of the memory, and the shuffling is not required in the reprocessor, thereby saving the processor to a large extent. Computing resources while reducing the processing latency of the data.
  • data interaction is performed according to the second address and the storage chip to implement mixing
  • the data sequence in the data collection is adjusted to obtain a shuffled data set, including:
  • the data to be shuffled is written to the storage location corresponding to the second address of each data according to the second address of each data, and the order of the data in the data mixture to be shuffled is adjusted to obtain a data set after shuffling.
  • the data shuffling device transmits the data address to be shuffled and the second address of each data to the memory chip, and the memory chip first writes into the line buffer according to the second address corresponding to each data, and then performs the second time.
  • the memory refresh operation refreshes the data in the line buffer back to the storage array, that is, the storage location corresponding to the second address of each data.
  • the memory refresh operation must refresh the dynamic random access memory (DRAM) within a few milliseconds, otherwise the data may be lost, and the DRAM refresh mode may be various. It can be performed separately for the normal read or write operation and the refresh operation.
  • the refresh is centralized in the centralized mode, but there will be a period of time after the read is stopped, which is applicable to the high speed memory; or a cycle of the storage system can be divided.
  • the normal read or write operation and the refresh operation are decentralized, but the speed of the system operation will be reduced; it can also be an asynchronous type that combines the first two methods and refreshes every once in a while. Ensure that the entire memory chip is refreshed in the refresh cycle. Therefore, the specific refresh mode is not limited here.
  • the data shuffling and data writing can be completed in the memory, which saves a large amount of processing time. At the same time, the program is more practical.
  • a second optional embodiment of the data shuffling method provided by the embodiment of the present invention, data interaction is performed according to the second address and the storage chip to implement mixing
  • the data sequence in the data collection is adjusted to obtain a shuffled data set, including:
  • the data shuffling device transmits a second address of each data to the memory chip, so that the memory chip reads out each of the storage locations corresponding to the second address of each data according to the second address of each data. Data, complete reading and shuffling of data.
  • the manner in which the data shuffling device transmits the second address to the memory chip may be through one or more transmission protocols, such as a transmission control protocol (TCP, Transmission Control). Protocol), or User Datagram Protocol (UDP), may also transmit information of the second address to the memory chip through the address bus. Therefore, the specific transmission mode is not limited herein.
  • TCP Transmission Control protocol
  • UDP User Datagram Protocol
  • the data shuffling and data reading can be completed in the memory, and the data writing process is performed in the process of implementing the shuffling operation.
  • the reverse process is similar, which saves a lot of processing time. At the same time, it can flexibly grasp the corresponding data in a continuous address, which is convenient for research and use, and further increases the practicability of the solution.
  • the third embodiment of the data shuffling method provided by the embodiment of the present invention is provided on the basis of the foregoing embodiment, the first optional embodiment, and the second optional embodiment.
  • obtaining the first address of each data in the data to be shuffled and the address offset of each data includes:
  • the data shuffling device when the data shuffling device includes a mode selection register, the data shuffling device can acquire the shuffling switch control word, and the shuffling switch control word is used to indicate that the data shuffling function is turned on or off.
  • the shuffling switch control word indicates that the data shuffling function is turned on, the data shuffling device acquires the first address of each data.
  • the mode selection register when the user configures the mode selection register, it can be configured through a dedicated configuration line added by the memory.
  • the configuration line is added in the bus, but this method needs to modify the hardware interface of the memory, and can also pass through the memory.
  • the device for data shuffling includes a mode selection register, and the user can set the address offset of the data by configuring the mode selection register, and other control words such as the bit width of the data, in practice.
  • the setting of the address offset can realize the left shift of the data loop, the right shift of the loop, or any other new arrangement such as any exchange, so the flexibility and practicality of the scheme are improved, and the operability is also improved. improved.
  • the data provided by the embodiment of the present invention is provided on the basis of any one of the foregoing embodiment, the first optional embodiment, the second optional embodiment, and the third optional embodiment.
  • the second address of each data is calculated based on the first address of each data and the address offset of each data, including:
  • the address mapping function is called to calculate a second address of each data, and the address mapping function is a mapping relationship between the second address of each data and the sum of the first address of each data and the address offset of each data.
  • the data shuffling device calls an address mapping function, and the second address of each data is calculated by the function, and the address mapping function is the second address of each data and the first address and each of each data.
  • the mapping relationship between the sum of the address offsets of the data is the mapping relationship between the sum of the address offsets of the data.
  • the adjustment such as the item of increasing the data bandwidth, is set to bps1, so the expression of the specific address mapping function is not limited in this embodiment.
  • the data shuffling device calls the address mapping function set by the user, and the second address is mapped according to the first address and the address offset of the data, and the address mapping of the function is implemented.
  • Functions can be compiled through the API, and the use of encoding is relatively simple. The process of the entire shuffle conversion is transparent to the user. The user can change the form of the address mapping function as needed, which fully demonstrates the flexibility of the solution. Good, and at the same time a wide range of features.
  • the technician compiles the write function and the read function separately through the API interface, and the write function is as follows:
  • Data refers to the data to be read or written
  • size refers to the bit width of each data element
  • shift refers to the address offset corresponding to each data in an array
  • the corresponding mapping is determined according to the above functional relationship. result.
  • the data shuffling device obtains the data to be shuffled from the data buffer in the memory chip as A, B, C, D, E, F, G, H, I, J, K, L, and obtains from the address cache.
  • the shuffled data will be placed in the new address, specifically data B is located at address 4, data C is at address 7, data D is at address 10, data E is at address 2, and data F is at address 5.
  • the data G is located at address 8, the data H is at address 11, the data I is at address 3, the data J is at address 6, the data K is at address 9, the data L is at address 12, and the data shuffling process ends.
  • the shuffled data is migrated to the line buffer, and all corresponding data of the new address addr_new can be downloaded into the data cache, and the data can be read out by the technician to analyze the data for smoother data.
  • the foundation of the transmission The foundation of the transmission.
  • an embodiment of the data shuffling apparatus in the embodiment of the present invention includes :
  • the obtaining module 901 is configured to acquire a first address of each data in the data set to be shuffled and an address offset of each data;
  • the calculating module 902 is configured to calculate, according to the first address of each data and the address offset of each data, a second address of each data, where the second address is used to indicate shuffling a storage location of each subsequent data in the memory chip;
  • the adjusting module 903 is configured to perform data interaction with the memory chip according to the second address, and implement an adjustment of a data sequence in the data group to be shuffled to obtain a data set after shuffling.
  • the obtaining module 901 acquires a first address of each data in the data to be shuffled and an address offset of each data, and the calculating module 902 is biased according to the first address of each data and the address of each data.
  • the second address is used to calculate the storage address of each data after the shuffling, and the adjustment module 903 performs data interaction with the memory chip according to the second address to implement the processing.
  • the data sequence in the shuffle data set is adjusted to obtain a shuffled data set.
  • the data shuffling device obtains the first address of each data in the data to be shuffled and the corresponding address offset, and obtains a second address corresponding to each data by calculation, according to the second address and storage.
  • the data interaction of the chip realizes the order adjustment of the data to be shuffled, and the data after shuffling is obtained, and the above process is applied to the cache chip of the memory, and the shuffling is not required in the reprocessor, thereby saving the processor to a large extent. Computing resources while reducing the processing latency of the data.
  • another embodiment of the apparatus for data shuffling in the embodiment of the present invention includes:
  • the obtaining module 1001 is configured to acquire a first address of each data in the data set to be shuffled and an address offset of each data;
  • the calculating module 1002 is configured to calculate, according to the first address of each data acquired by the obtaining module 1001 and the address offset of each data, a second address of each data, the second address Used to indicate a storage location of each data after shuffling in the memory chip;
  • the adjusting module 1003 is configured to perform data interaction with the storage chip according to the second address calculated by the calculating module 1002, so as to implement adjustment of the data sequence in the data group to be shuffled, Data mixture after shuffling;
  • the adjustment module 1003 may further include:
  • a first transmission unit 10031 configured to transmit, to the memory chip, the to-be-mixed data set and a second address of each of the data, so that the storage chip follows the second address of each of the data
  • the shuffling data is written into a storage location corresponding to the second address of each data, so that the data sequence in the data group to be shuffled is adjusted to obtain a shuffled data set.
  • the data shuffling and data writing can be completed in the memory, which saves a large amount of processing time. At the same time, the program is more practical.
  • another embodiment of the apparatus for data shuffling in the embodiment of the present invention includes:
  • the obtaining module 1101 is configured to obtain a first address of each data in the data set to be shuffled and an address offset of each data;
  • the calculation module 1102 is configured to calculate, according to the first address of each data acquired by the obtaining module 1101 and the address offset of each data, a second address of each data, the second address Used to indicate a storage location of each data after shuffling in the memory chip;
  • the adjusting module 1103 is configured to perform data interaction with the storage chip according to the second address calculated by the calculating module 1102, to implement adjustment of the data sequence in the data group to be shuffled, and obtain a data set after shuffling;
  • the adjustment module 1103 may further include:
  • a second transmission unit 11031 configured to transmit, to the memory chip, a second address of each of the data, so that the memory chip follows the second address of each data, from the second of each data
  • the storage location corresponding to the address reads the data, and implements adjustment of the data sequence in the dataset to be shuffled to obtain a data set after shuffling.
  • the data shuffling and data reading can be completed in the memory, and the data writing process is performed in the process of implementing the shuffling operation.
  • the reverse process is similar, which saves a lot of processing time. At the same time, it can flexibly grasp the corresponding data in a continuous address, which is convenient for research and use, and further increases the practicability of the solution.
  • another embodiment of the apparatus for data shuffling in the embodiment of the present invention includes:
  • the obtaining module 1201 is configured to acquire a first address and each of each data in the data set to be shuffled The address offset of the data;
  • the calculating module 1202 is configured to calculate, according to the first address of each data acquired by the acquiring module 1201 and the address offset of each data, a second address of each data, the second address Used to indicate a storage location of each data after shuffling in the memory chip;
  • the adjusting module 1203 is configured to perform data interaction with the storage chip according to the second address calculated by the calculating module 1202, to implement adjustment of the data sequence in the data group to be shuffled, and obtain a data set after shuffling;
  • the obtaining module 1201 may further include:
  • a first obtaining unit 12011 configured to acquire a shuffling switch control word, where the shuffling switch control word is used to indicate that the data shuffling function is turned on or off;
  • a second obtaining unit 12012 configured to acquire, when the shuffling switch control word acquired by the first acquiring unit 12011 indicates that the data shuffling function is turned on, acquiring the first address of each data and each of the data Address offset.
  • the adjusting module 1203 may further include:
  • a second transmission unit 12031 configured to transmit, to the memory chip, a second address of each data, so that the memory chip follows the second address of each data, from the second of each data
  • the storage location corresponding to the address reads the data, and implements adjustment of the data sequence in the dataset to be shuffled to obtain a data set after shuffling.
  • the device for data shuffling includes a mode selection register, and the user can set the address offset of the data by configuring the mode selection register, and other control words such as the bit width of the data, in practice.
  • the setting of the address offset can realize the left shift of the data loop, the right shift of the loop, or any other new arrangement such as any exchange, so the flexibility and practicality of the scheme are improved, and the operability is also improved. improved.
  • FIG. 13 another embodiment of an apparatus for data shuffling in an embodiment of the present invention includes:
  • the obtaining module 1301 is configured to obtain a first address of each data in the data set to be shuffled and an address offset of each data;
  • the calculating module 1302 is configured to calculate, according to the first address of each data acquired by the acquiring module 1301 and the address offset of each data, a second address of each data, the second address Used to indicate a storage location of each data after shuffling in the memory chip;
  • the adjusting module 1303 is configured to perform data interaction with the storage chip according to the second address calculated by the calculating module 1302, to implement adjustment of the data sequence in the data group to be shuffled, and obtain a data set after shuffling;
  • the obtaining module 1301 may further include:
  • a first obtaining unit 13011 configured to acquire a shuffling switch control word, where the shuffling switch control word is used to indicate that the data shuffling function is turned on or off;
  • a second obtaining unit 13012 configured to acquire, when the shuffling switch control word acquired by the first acquiring unit 13011, the first data of the data and the data Address offset.
  • the calculating module 1302 can further include:
  • the calculating unit 13021 is configured to invoke an address mapping function, and calculate a second address of each of the data, where the address mapping function is a second address of each of the data and a first address and location of each of the data A mapping relationship between the sum of the address offsets of each data.
  • the adjustment module 1303 may further include:
  • a second transmission unit 13031 configured to transmit, to the memory chip, a second address of each of the data, so that the memory chip follows the second address of each data, from the second of each data
  • the storage location corresponding to the address reads the data, and implements adjustment of the data sequence in the dataset to be shuffled to obtain a data set after shuffling.
  • the data shuffling device calls the address mapping function set by the user, and the second address is mapped according to the first address and the address offset of the data, and the address mapping of the function is implemented.
  • Functions can be compiled through the API, and the use of encoding is relatively simple. The process of the entire shuffle conversion is transparent to the user. The user can change the form of the address mapping function as needed, which fully demonstrates the flexibility of the solution. Good, and at the same time a wide range of features.
  • the data shuffling device 1400 may have a relatively large difference due to different configurations or performances, and may include one or more central processing units 1422 ( For example, one or more processors) and memory 1432, one or more storage media 1430 that store application 1442 or data 1444 (eg, one or one storage device in Shanghai).
  • the memory 1432 and the storage medium 1430 may be temporarily stored.
  • the program stored on storage medium 1430 may include one or more modules (not shown), each of which may include a series of instruction operations in the server.
  • central processor 1422 can be configured to communicate with storage medium 1430, executing a series of instruction operations in storage medium 1430 on server 1400.
  • the central processor 1422 is used to:
  • the data shuffling device obtains the first address of each data in the data to be shuffled and the corresponding address offset, and obtains a second address corresponding to each data by calculation, according to the second address and storage.
  • the data interaction of the chip realizes the order adjustment of the data to be shuffled, and the data after shuffling is obtained, and the above process is applied to the cache chip of the memory, and the shuffling is not required in the reprocessor, thereby saving the processor to a large extent. Computing resources while reducing the processing latency of the data.
  • the central processing unit 1422 is further configured to transmit, to the memory chip, the to-be-mixed data set and the second address of each of the data, so that the memory chip follows each of The second address of the data is used to write the data to be shuffled to a storage location corresponding to the second address of each data, so as to adjust the order of the data in the data set to be shuffled, and obtain a data set after shuffling. .
  • the data shuffling and data writing can be completed in the memory, which saves a large amount of processing time. At the same time, the program is more practical.
  • the central processing unit 1422 is further configured to transmit, to the memory chip, a second address of each of the data, so that the memory chip follows the second address of each of the data.
  • Each of the data is read by a storage location corresponding to the second address of each data, and the data sequence in the dataset to be shuffled is adjusted to obtain a data set after shuffling.
  • the data shuffling device is in the process of implementing the shuffling operation.
  • the data shuffling and data reading can be completed in the memory, which is similar to the reverse process of the data writing process, which saves a lot of processing time and can flexibly grasp the corresponding one in a continuous address.
  • the data is easy to study and use, further increasing the practicality of the program.
  • the central processing unit 1422 is further configured to acquire a shuffling switch control word, where the shuffling switch control word is used to indicate that the data shuffling function is turned on or off;
  • the device for data shuffling includes a mode selection register, and the user can set the address offset of the data by configuring the mode selection register, and other control words such as the bit width of the data, in practice.
  • the setting of the address offset can realize the left shift of the data loop, the right shift of the loop, or any other new arrangement such as any exchange, so the flexibility and practicality of the scheme are improved, and the operability is also improved. improved.
  • the central processing unit 1422 is further configured to invoke an address mapping function to calculate a second address of each of the data, where the address mapping function is a second address of each of the data and the A mapping relationship between the first address of each data and the sum of the address offsets of each of the data.
  • the data shuffling device calls the address mapping function set by the user, and the second address is mapped according to the first address and the address offset of the data, and the address mapping of the function is implemented.
  • Functions can be compiled through the API, and the use of encoding is relatively simple. The process of the entire shuffle conversion is transparent to the user. The user can change the form of the address mapping function as needed, which fully demonstrates the flexibility of the solution. Good, and at the same time a wide range of features.
  • the data shuffling device 1400 can also include one or more power sources 1426, one or more wired or wireless network interfaces 1450, one or more input and output interfaces 1458, and/or one or more operating systems 1441, such as Windows. ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM and more.
  • the steps performed by the apparatus for data shuffling in the above embodiment may be based on the apparatus structure of the data shuffling shown in FIG.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present invention which is essential or contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

Abstract

本发明实施例公开了一种数据混洗的装置，包括：缓存模块和混洗模块；缓存模块与混洗模块通信连接；缓存模块用于缓存待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量；混洗模块用于根据每个数据的第一地址和每个数据的地址偏移量，计算得到每个数据的第二地址，第二地址用于指示混洗后的每个数据在存储芯片中的存储位置；混洗模块用于根据第二地址与存储芯片进行数据交互，实现对待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。本发明实施例还提供一种数据混洗的方法。本发明实施例能够直接在内存中进行数据混洗操作，节省了处理器中大量的计算资源，降低数据处理时延。

Description

一种数据混洗的装置及方法 技术领域
本发明涉及计算机领域，尤其涉及一种数据混洗的装置及方法。
背景技术
随着技术的不断进步，在大多数领域内要求多核多线程并行的处理技术也随之发展，在并行处理中由于各个步骤之间在并行的粒度或维度上不同，因此通常需要对内存中的数据进行混洗，混洗处理是指对一个集合中的元素进行重新排序，例如将数组{a，b，c，d，e}通过不同的指定混洗操作，实现数组元素任意交换的功能，得到新数组，如：{b，e，d，a，c}。
现有技术中，实现混洗操作过程大致如下所述：
1、中央处理器(CPU，Central Processing Unit)从内存中读取需要进行混洗操作的数据；
2、CPU调用混洗函数完成混洗操作；
3、CPU将进行过shuffle操作的数据写回内存中。
本发明的发明人在对上述现有技术的研究和实践过程中发现，由于混洗操作是通过CPU来实现的，会占用CPU的计算资源，而混洗开始和结束分别要进行内存的读写操作，因此当混洗的数据量很大时，则要较长的数据传输时间，并且需要开辟缓存数组空间，当CPU内部的高速缓存空间不够用时，则需要将缓存数组放入内存中，这样会增加内存的读写次数，进一步增加了整个操作的处理时延。
发明内容
本发明实施例提供了一种数据混洗的装置及方法，可以不需要在混洗装置外的处理器中实现混洗过程，节省了处理器中大量的计算资源，降低数据处理时延。
本发明第一方面提供了一种数据混洗的装置，所述装置应用于内存的缓冲芯片，所述内存还包括存储芯片，所述装置包括：缓存模块和混洗模块；
所述缓存模块与所述混洗模块通信连接；
所述缓存模块用于缓存待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量；
所述混洗模块用于根据所述每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每个数据的第二地址，所述第二地址用于指示混洗后的每个数据在所述存储芯片中的存储位置；
所述混洗模块用于根据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
结合第一方面，在第一种可能的实现方式中，所述缓存模块为地址缓存模块，所述地址缓存模块与所述混洗模块通信连接，所述地址缓存模块用于缓存待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量；或者，
所述缓存模块包括地址缓存模块和控制缓存模块，所述地址缓存模块用于缓存待混洗数据集合中每个数据的第一地址，所述控制缓存模块用于缓存所述每个数据的地址偏移量；或者，
所述缓存模块包括地址缓存模块和偏移缓存模块，所述地址缓存模块用于缓存待混洗数据集合中每个数据的第一地址，所述偏移缓存模块用于缓存所述每个数据的地址偏移量。
结合第一方面或第一方面第一种可能的实现方式，在第二种可能的实现方式中，所述混洗模块用于根据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合，可以包括：
所述混洗模块用于向所述存储芯片传输所述待混洗数据集合和所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址将所述待混洗数据写入所述每个数据的第二地址对应的存储位置，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
结合第一方面或第一方面第一种可能的实现方式，在第三种可能的实现方式中，所述混洗模块用于根据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合，可以包括：
所述混洗模块用于向所述存储芯片传输所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址，从所述每个数据的第二地址对应的存储位置读出所述每个数据，实现对所述待混洗数据集合中数据顺序的 调整，得到混洗后的数据集合。
结合第一方面或第一方面第一种至第三种任一种可能的实现方式，在第四种可能的实现方式中，所述混洗模块可以包括：模式选择寄存器，
所述模式选择寄存器用于获取混洗开关控制字，所述混洗开关控制字用于指示开启或关闭数据混洗功能；
当所述混洗开关控制字指示开启所述数据混洗功能时，所述模式选择寄存器用于从所述缓存模块获取所述每个数据的地址偏移量。
结合第一方面或第一方面第一种至第四种任一种可能的实现方式，在第五种可能的实现方式中，所述待混洗数据集合中每个数据的地址偏移量的绝对值都小于用于存储所述每个数据的总存储空间的大小，且所述每个数据的地址偏移量之和为零。
结合第一方面第四种可能的实现方式，在第六种可能的实现方式中，所述内存还包括总线，所述总线中配置有与所述模式选择寄存器连接的配置线，
所述配置线一端与所述模式选择寄存器相连，另一端通过所述内存的插槽与所述内存以外的芯片相连；
所述模式选择寄存器用于获取混洗开关控制字，包括：
所述模式选择寄存器用于通过所述配置线接收用户配置的所述混洗开关控制字。
结合第一方面或第一方面第一种至第六种任一种可能的实现方式，在第七种可能的实现方式中，所述混洗模块用于根据所述每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每个数据的第二地址，包括：
所述混洗模块用于调用地址映射函数，计算得到所述每个数据的第二地址，所述地址映射函数为所述每个数据的第二地址与所述每个数据的第一地址与所述每个数据的地址偏移量之和的映射关系。
本发明第二方面提供一种数据混洗的方法，所述方法应用于内存的缓冲芯片，所述内存还包括存储芯片，包括：
获取待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量；
根据所述每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每个数据的第二地址，所述第二地址用于指示混洗后的每个数据在所述 存储芯片中的存储位置；
根据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
结合第二方面，在第一种可能的实现方式中，所述根据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合，可以包括：
向所述存储芯片传输所述待混洗数据集合和所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址将所述待混洗数据写入所述每个数据的第二地址对应的存储位置，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
结合第二方面，在第二种可能的实现方式中，所述根据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合，可以包括：
向所述存储芯片传输所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址，从所述每个数据的第二地址对应的存储位置读出所述每个数据，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
结合第二方面，第二方面第一种或第二种可能的实现方式，在第三种可能的实现方式中，所述获取待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量可以包括：
获取混洗开关控制字，所述混洗开关控制字用于指示开启或关闭数据混洗功能；
当所述混洗开关控制字指示开启所述数据混洗功能时，获取所述每个数据的第一地址和所述每个数据的地址偏移量。
结合第二方面，第二方面第一种至第三种任一种可能的实现方式，在第四种可能的实现方式中，所述根据所述每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每个数据的第二地址，可以包括：
调用地址映射函数，计算得到所述每个数据的第二地址，所述地址映射函数为所述每个数据的第二地址与所述每个数据的第一地址与所述每个数据 的地址偏移量之和的映射关系。
本发明第三方面提供一种数据混洗的装置，包括：
获取模块，用于获取待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量；
计算模块，用于根据所述每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每个数据的第二地址，所述第二地址用于指示混洗后的每个数据在所述存储芯片中的存储位置；
调整模块，用于根据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
结合本发明实施例的第三方面，在第一种可能的实现方式中，所述调整模块可以包括：
第一传输单元，用于向所述存储芯片传输所述待混洗数据集合和所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址将所述待混洗数据写入所述每个数据的第二地址对应的存储位置，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
结合本发明实施例的第三方面，在第二种可能的实现方式中，所述调整模块包括：
第二传输单元，用于向所述存储芯片传输所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址，从所述每个数据的第二地址对应的存储位置读出所述每个数据，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
结合第三方面，第三方面第一种或第二种可能的实现方式，在第三种可能的实现方式中，所述获取模块可以包括：
第一获取单元，用于获取混洗开关控制字，所述混洗开关控制字用于指示开启或关闭数据混洗功能；
第二获取单元，用于当所述混洗开关控制字指示开启所述数据混洗功能时，获取所述每个数据的第一地址和所述每个数据的地址偏移量。
结合第三方面，第三方面第一种至第三种任一种可能的实现方式，在第四种可能的实现方式中，所述计算模块可以包括：
计算单元，用于调用地址映射函数，计算得到所述每个数据的第二地址，所述地址映射函数为所述每个数据的第二地址与所述每个数据的第一地址与所述每个数据的地址偏移量之和的映射关系。
从以上技术方案可以看出，本发明实施例具有以下优点：
本发明实施例中，提供的数据混洗的装置应用与内存的缓存芯片中，需要改进的只有内存中的缓冲芯片，而不是整个内存的构造，因此实现起来更加的简易，同时，该装置的混洗功能是在内存中通过硬件实现的，又伴随着数据读写的过程同时进行，不需要通过内存外的处理器来完成上述过程，这样可以很大程度上节省处理器的计算资源，尤其减轻了CPU的工作负担，还在很大程度上降低了数据处理的时延，当数据量较大的时候，进一步体现了数据传输时间短的优势。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例中内存示意图；
图2是本发明实施例中存储芯片的内部结构示意图；
图3是本发明实施例中缓冲芯片内新增的混洗模块示意图；
图4是本发明实施例中混洗模块的结构；
图5是本发明实施例中模式选择寄存器的功能控制字示意图；
图6是本发明实施例中数据混洗的装置所执行数据混洗与写入的过程示意图；
图7是本发明实施例中数据混洗的装置所执行数据混洗与读出的过程示意图；
图8是本发明实施例中数据混洗的方法一个实施例示意图；
图9是本发明实施例中数据混洗的装置一个实施例示意图；
图10是本发明实施例中数据混洗的装置另一个实施例示意图；
图11是本发明实施例中数据混洗的装置另一个实施例示意图；
图12是本发明实施例中数据混洗的装置另一个实施例示意图；
图13是本发明实施例中数据混洗的装置另一个实施例示意图；
图14为本发明实施例中数据混洗的装置一个结构示意图。
具体实施方式
本发明实施例提供一种数据混洗的方法，可以节省处理器中大量的计算资源，降低数据处理时延。本发明实施例还提供了相应的数据混洗的装置。以下分别进行详细说明。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1为内存示意图，请参阅图1，本发明实施例中的数据混洗过程在内存中进行。内存由若干个存储芯片和一个缓冲芯片组成。
需要说明的是，图1中的8个存储芯片只是一个示意，在实际应用中，对存储芯片的个数不做具体限定。
内存是连接CPU和其他设备的通道，并且起到缓冲以及数据交换的作用，当CPU工作时，需要从硬盘等外部存储器上读取数据，但是由于外部存储器的存储容量较大，而且距离CPU的位置较远，因此传输数据的速度就会减慢，导致CPU的工作效率降低，为了解决这个问题，于是在外部存储器与CPU之间建立了内存，而内存依赖于内存，所有外部存储器上的内容都需要通过内存才能发挥作用。
一些日常使用的程序，例如，Windows XP系统、打字软件和游戏软件等，一般都是安装在硬盘等外部存储器上的，但仅此是不能使用其功能的，必须将它们调入内存中运行才能真正实现其功能，因此通常把要永久保存的大量数据存储在外部存储器中，而把一些临时的或少量的数据和程序放在内存中。
图2为存储芯片的内部结构示意图，请参阅图2，本发明实施例中存储芯片位于内存中。其中每个存储芯片是由若干个存储阵列组成，每个存储阵列是由多个行与多个列组成的二维存储阵列，且每个存储阵列对应一个行缓 冲器，行缓冲器的存储大小正好对应存储阵列中每一行的存储大小，同时每个存储阵列还包括了存储芯片外接接口对应的数据缓存模块和地址缓存模块，数据缓存模块用于将一些数据暂时性的保存起来以供读取和再读取，而地址缓存模块将数据对应的地址暂时保存起来，可以用于调用。数据缓存模块的位宽通常远小于行缓冲器的位宽，这是由于数据总线的位宽有限，数据总线负责计算机中数据在各组成部分之间的传送，数据总线宽度是指在各芯片内部数据传送的宽度，而数据总线宽度则决定了CPU与二级缓存、内存以及输入或输出设备之间一次数据传输的信息量，例如，CPU的数据总线宽度就是64位，则它一次可以传送数据的最大值为64位，即一次能处理8个字节。
需要说明的是，图2中的2个存储阵列是一个示意，在实际应用中，对存储芯片中的存储阵列个数不做具体限定。
存储芯片在读取数据时的过程如下：
根据地址信息中的行信息确定对应的存储阵列中对应行的位置，并将整行的数据写入行缓冲器中；
根据地址信息中的列信息确定对应的行缓冲器中对应列的位置，确定存储位置后，将其中的数据放入数据缓存模块；
从数据缓存模块输出到存储芯片之外。
存储芯片在写入数据时的过程如下：
数据信息和地址信息通过存储芯片外的接口进入对应存储阵列的数据缓存模块和地址缓存模块中；
根据地址信息中的列信息，刷新行缓冲器中相应列的数据，
根据地址信息中的行信息，将整个行缓冲器的数据刷新至对应的行中。
由上可见，存储阵列的读写每次都是以一整行为单位进行读写的，到了行缓冲器后才根据具体的列地址进行具体存储单元的读写。
根据内存的结构特点，本发明提出一种在计算机的内存中直接实现数据混洗的方案，即在内存的缓冲芯片上增加一个混洗模块，实现数据读写时的混洗功能。
图3为缓冲芯片内新增的混洗模块示意图，请参阅图3，缓冲芯片中包 括总线接口模块、数据缓存模块、控制缓存模块、地址缓存模块和混洗模块，实际上，缓存芯片还可以包括偏移缓存模块。其中，总线接口模块用于不同设备之间实现相互关联，常用一组线路，配置以适当的接口电路，与各部件和外围设备连接，而各个部件之间传送信息的公共通路被称为总线，计算机的总线可以划分为数据总线(DB，Data Bus)、控制总线(CB，Control Bus)与地址总线(AB，Address Bus)，缓冲芯片主要作用是实现对DB、CB以及AB的信号进行缓存和整形。
需要说明的是，上述提及的控制缓存模块其主要作用是缓存控制信号和时序信号的，控制信号中，有的是微处理器送往存储器和输入输出设备接口电路的，如读或写的信号，片选信号或中断响应信号，也有是其它部件反馈给CPU的，如中断申请信号、复位信号、总线请求信号或限备就绪信号，还可以有其他控制信号，具体用途的选择取决于CPU对它的需求。
可以理解的是，上述各个模块之间存在各自分别对应的硬件电路，这些电路之间通过传输线在缓冲芯片中进行关联性的相接，具体的连接形式与电路设计相关，故此处不对连接的形式做限定。
混洗模块可以与地址缓存模块相连，也可以与地址缓存模块和控制缓存模块相连，还可以与地址缓存模块和偏移缓存模块相连，且连接方式为通信连接。混洗过程并不会改变数据本身，但是与控制信号和地址信号有关，因此混洗模块主要用于收发从数据缓存模块与控制缓存模块传递过来的信号流。需要说明的是，本方案中只修改了内存上的缓冲芯片，并没有修改内存上的存储芯片，因此本发明对内存来说改变并不大。
图4是混洗模块的结构示意图，请参阅图4，混洗的功能是实现数据在内存中位置的重新排列，也就是说混洗后数据的地址会发生变化，因此只要知道了每个数据的原始地址和新地址，然后将每个数据从原始地址交换到新地址就实现了混洗功能。为了计算出新地址，需要知道每个数据的新地址相对于原始地址的偏移量，假设原始地址为addr_old，地址偏移量为shift，则新地址为addr_new＝addr_old+shift。综上可见，混洗模块可以是一个地址换算模块。
可选地，本发明实施例还提供一种应用程序编程接口(API，Application  Programming Interface)，API是操作系统留给应用程序的一个调用接口，应用程序通过调用操作系统的API而使操作系统去执行应用程序的命令或动作，API是一些预先定义的函数，目的是提供应用程序与开发人员基于某软件或硬件访问一组例程的能力，而又无需访问源码，或理解内部工作机制的细节，一个API可以当作一个规范，它规定了两个软件之间交了与数据交换的方式。
而本发明实施例中，为了方便用户的编程使用，提出了一种统一的API，将基于内存的混洗功能进行封装，也就是说，在程序上隐蔽对象的属性和实现细节，仅对外公开接口，控制程序中属性读和修改的访问级别，将抽象得到的数据和功能相结合，形成一个有机的整体，也就是将数据与操作数据的源代码进行有机的结合，形成一个“类”，其中数据和函数都是“类”的成员。用户只需要调用该接口函数，即可实现混洗操作。
为了方便使用和简化控制字，我们对数据的读写过程分别定义了一个API函数，写入过程的API函数可以定义为：
void MemShuffleWrt(&Data1,size1,shift1)   (1)
而对数据的读出过程定义一个API函数可以为：
ShuffledData＝MemShuffleRd(&Data2,size2,shift2)   (2)
其中，表达式(1)表示内存在写入数据的同时进行数据混洗操作，Data1是指待写入的数据，size1是指待写入每个数据元素的位宽，shift1是一个数组表示每个数据对应的地址偏移量。表达式(2)表示内存在读取数据的同时进行数据混洗操作，ShuffledData表示进行混洗操作后的数据，Data2是指混洗前的数据，size2是指待读出数据元素的位宽，shift2是一个数组表示每个数据对应的地址偏移量。
图5是本发明实施例中模式选择寄存器的功能控制字示意图，请参阅图5，模式选择寄存器通过API获取用户配置的待混洗数据的地址偏移量，并且存储用户配置的地址偏移量。用户可根据需要，对模式选择寄存器进行配置。
可选地，混洗模块还包括模式选择寄存器，它用于获取混洗开关控制字，这些混洗开关控制字用于指示开启或关闭数据混洗功能，当混洗开关控制字 指示开启数据混洗功能时，模式选择寄存器可以从缓存模块获取每个数据对应的地址偏移量，每个地址偏移量的绝对值都要小于存储每个数据的总存储空间的大小。
混洗模块实现的功能是将原地址和地址偏移量相加得到新地址。其中原地址是通过地址总线从处理器传递过来的，例如CPU或微处理器，地址偏移量是从模式选择寄存器中提取的，内存利用计算出来的新地址去读或写数据，从而将数据从原始地址变换到了新地址，最终完成混洗功能。
本发明中，假设S_on为第一值，表示开启数据混洗功能，S_on为第二值，表示关闭数据混洗功能，如S_on＝1表示开启数据混洗功能，S_on＝0表示关闭数据混洗功能，S_on后是表示每个数据元素位宽大小的size，而通常情况下行缓冲器的位宽大于数据元素的位宽，因此在行缓冲器中有足够的空间存放每个数据，不会导致数据的溢出。其余的控制字，例如：shift_0表示与之对应的数据的地址偏移量0，shift_1表示与之对应的数据的地址偏移量-3，依次对每个对应的数据的地址偏移量进行设定，通过多行之间的数据混洗，同时也实现了对多列之间数据混洗的目的。在开辟空间的时候可以开辟较大的空间，如果开辟的空间大了可存放下一次写入的数据，如果多次写入的话往往先开辟较大的空间，然后分多次进行数据的写入与混洗，并填满这些空间。
与此同时，内存中还包括了总线，在总线中配置有一条或多条与模式选择寄存器相连的配置线，而配置线一端与模式选择寄存器相连，另一端则是通过内存的插槽与内存以外的芯片相连。内存以外的芯片可以是CPU芯片，也可以是北桥芯片，还可以是其他实现地址偏移量输入或者输出的芯片。其中，北桥芯片是主板芯片组中起主导作用的重要组成部分，也称为主桥，通常，芯片组的名称就是以北桥芯片的名称来命名的，如英特尔845E芯片组的北桥芯片是82845E，875P芯片组的北桥芯片是82875P，北桥芯片负责与CPU联系，并且控制内存，提供对CPU类型、主频和系统的前端总线频率。
用户可以通过这条专用配置线实现寄存器控制字的写入，而这些写入的控制字用于开启或关闭数据混洗功能，设定数据对应地址偏移量，也可以根据用户需求写入其他控制字，再由数据混洗的装置获取该用户通过专用配置 线配置的信息，用于进行数据混洗，该方法需要修改内存的硬件接口。
需要说明的是，还存在其他配置模式选择寄存器的方式，例如，利用内存中已有的控制线，修改控制线的协议，增加寄存器控制字的传输过程，再由数据混洗的装置通过修改协议获取用户配置的信息，该方法不需要修改内存的硬件接口。还可以有其他实现的方式，故此处不作限定。
图6是本发明实施例中数据混洗的装置所执行数据混洗与写入的过程示意图，请参阅图6，数据混洗写入过程示意图如图所示。
本实施例中，数据混洗的装置应用于内存的缓冲芯片，而且内存中还包括了存储芯片，该装置包括了缓存模块和混洗模块，它们之间通信连接，缓存模块用于缓存待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量，第一地址则是用于指示混洗前的每个数据在存储芯片中的存储位置的，混洗模块根据每个数据的第一地址和每个数据的地址偏移量，计算得到每个数据的第二地址，第二地址用于指示混洗后的每个数据在存储芯片中的存储位置，混洗模块再根据第二地址与存储芯片进行数据交互，实现对待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
需要说明的是，缓存模块可以为地址缓存模块，也可以是地址缓存模块和控制缓存模块，还可以是地址缓存模块和偏移缓存模块，此处不对缓存模块的组成做限定。
当把一段在地址上连续的数据写入内存，同时又需要在写入的过程中赋予这些数据新的地址时，混洗模块可以向存储芯片传输待混洗数据集合和每个数据的第二地址，以使存储芯片按照每个数据的第二地址将待混洗数据写入每个数据的第二地址对应的存储位置，实现对待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
可以理解的是，实际应用中，第一地址不是人为分配和写入的，而是由操作系统统一分配和管理的，而且地址缓存模块中的第一地址在特殊情况下也可以出现不连续的情况，故此处不对第一地址的选取和排列情况作限定。
具体实现过程可以如下：
CPU将数据的第一地址写入地址缓存模块，第一地址分别为50，51，52，53，54，55，将数据a，b，c，d，e，f写入数据缓存模块中，将地址偏移量 0，-3，-6，2，7，-1写入控制缓存中，其中数据和地址偏移量是程序员设定的，而第一地址是系统自动分配的；
混洗模块调用地址映射函数void MemShuffleWrt(&Data1,size1,shift1)，计算得到每个数据的第二地址，地址映射函数为每个数据的第二地址与每个数据的第一地址与每个数据的地址偏移量之和的映射关系；
计算得到第二地址分别为50，48，46，55，61，54，于是将数据缓存模块中的数据按照第二地址写入行缓冲器中，再进行一次内存刷新操作，将行缓冲器中数据刷回到存储阵列中，完成数据的写入与混洗的操作。
可以理解的是，地址偏移量为零时，则是将数据写入第一地址，没有进行混洗操作，当地址偏移量不为零时，通过混洗模块获得第二地址，数据会写入第二地址中，在写入的过程中进行了混洗操作。
然而在写入的过程中涉及到地址可能会出现插空与不插空的情况，当插空时，第一地址是连续的，而第二地址不连续；当不插空时，第一地址是连续的，且第二地址也是连续的，只是地址对应的次序发生了变化。如果插空时，地址偏移量之和不一定为零，这是因为插空的情况下，对地址偏移量没有限制，为零时，写入的数据可以为循环左移或循环右移，也可以是其他方式，而大多数情况下是不为零的。
图7是本发明实施例中数据混洗的装置所执行数据混洗与读出的过程示意图示意图，请参阅图7，数据混洗读出过程示意图如图所示。
本实施例中，提供了数据混洗读出过程的一种方法，同时也提供了一种可以实现该方法的数据混洗的装置，且该装置与上述图6对应的实施例描述的装置一致，故此处不作赘述。
当需要读取内存中一段连续的数据，同时又需要在读取的过程中赋予这些数据新的地址时，混洗模块向存储芯片传输每个数据的第二地址，以使存储芯片按照每个数据的第二地址，从每个数据的第二地址对应的存储位置读出每个数据，实现对待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
具体实现过程可以如下：
CPU将数据的第一地址写入地址缓存模块，第一地址分别为50，51，52， 53，54，55，且这些地址必须为连续的一段地址，将地址偏移量1，1，1，1，1，-5写入控制缓存中，其中数据和地址偏移量是程序员设定的，而第一地址是系统自动分配的；
混洗模块调用ShuffledData＝MemShuffleRd(&Data2,size2,shift2)，计算得到每个数据的第二地址，地址映射函数为每个数据的第二地址与每个数据的第一地址与每个数据的地址偏移量之和的映射关系；
计算得到第二地址分别为51，52，53，54，55，50，可以看出混洗后实现了数据的循环右移，再将第二地址对应数据所在的存储阵列的那一行刷新至行缓冲器中，最后将行缓冲器中第二地址对应的数据下载待数据缓存模块中并通过数据总线读出这些数据，完成数据的读出与混洗的操作。
相对于写入的过程，读取时不存在插空的情况，因此读取时的地址偏移量之和一定为零。
可选地，在读取数据或写入数据的过程中，数据混洗的装置需要调用地址映射函数，通过这个函数来计算得到每个数据的第二地址，地址映射函数是每个数据的第二地址与每个数据的第一地址与每个数据的地址偏移量之和的映射关系。
介于上述介绍，本发明中数据混洗的装置由于具有快速配置的功能，可以应用于手机内存、随机存储器(RAM，random access memory)或者嵌入式系统，也可以应用与基站系统。如在多天线多用户的移动通信数据处理中，进行一次混洗操作大概需要100us的时间，而利用本发明提出的数据混洗的装置在内存中直接实现数据的混洗，只需要几个时钟周期即可完成，假设内存模块的时钟频率为1600MHz，那么混洗操作可以在ns量级的时间内时间。因此本发明提出的数据混洗的装置应用在存储装置是合理的。
本发明实施例中，提供的数据混洗的装置应用与内存的缓存芯片中，需要改进的只有内存中的缓冲芯片，而不是整个内存的构造，因此实现起来更加的简易，同时，该装置的混洗功能是在内存中通过硬件实现的，又伴随着数据读写的过程同时进行，不需要通过内存外的处理器来完成上述过程，这样可以很大程度上节省处理器的计算资源，尤其减轻了CPU的工作负担，还在很大程度上降低了数据处理的时延，当数据量较大的时候，进一步体现了数据传输时间 短的优势。
下面对本发明中的数据混洗的方法进行详细描述，请参阅图8，本发明实施例提供的一种数据混洗的方法实施例包括：
801、获取待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量；
本实施例中，数据混洗的装置获取待混洗数据集合中每个数据的第一地址，第一地址是用于指示每个数据混洗前在存储芯片内的存储位置，同时，数据混洗的装置也获取每个数据对应的地址偏移量。
802、根据每个数据的第一地址和每个数据的地址偏移量，计算得到每个数据的第二地址，第二地址用于指示混洗后的每个数据在存储芯片中的存储位置；
本实施例中，数据混洗的装置根据每个数据的第一地址和每个数据的地址偏移量，计算得到每个数据对应的第二地址，第二地址用于指示混洗后的每个数据在存储芯片中的存储位置。
803、根据第二地址与存储芯片进行数据交互，实现对待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
本实施例中，数据混洗的装置根据计算得到的第二地址与存储芯片进行数据交互，可以实现对待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
本发明实施例中，数据混洗的装置获取待混洗数据中每个数据的第一地址和对应的地址偏移量，通过计算得到每个数据对应的第二地址，根据第二地址与存储芯片的数据交互实现待混洗数据的顺序调整，得到混洗后的数据，而上述过程应用于内存的缓存芯片中，不需要再处理器中实现混洗，因此很大程度上节省了处理器的计算资源，同时降低了数据的处理时延。
可选地，在上述图8对应的实施例的基础上，本发明实施例提供的数据混洗方法的第一个可选实施例中，根据第二地址与存储芯片进行数据交互，实现对待混洗数据集合中数据顺序的调整，得到混洗后的数据集合，包括：
向存储芯片传输待混洗数据集合和每个数据的第二地址，以使存储芯片 按照每个数据的第二地址将待混洗数据写入每个数据的第二地址对应的存储位置，实现对待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
本实施例中，数据混洗的装置向存储芯片传输待混洗数据集合与每个数据的第二地址，存储芯片按照每个数据对应的第二地址先写入行缓冲器中，再进行一次内存刷新操作，将行缓冲器中的数据刷新回存储阵列中，即每个数据第二地址对应的存储位置中。
需要说明的是，内存刷新操作一般情况下，必须在数毫秒之内对动态随机存取存储器(DRAM，Dynamic Random Access Memory)刷新一次，否则数据就可能会丢失，而DRAM的刷新方式有多种，可以为正常读取或写入操作与刷新操作分开进行，刷新集中完成的集中式，但是会存在一段停止读取后写入的时间，适用与高速存储器；也可以为将一个存储系统周期分为两个时间，分别进行正常读取或写入操作和刷新操作的分散式，但是系统运行的速度会降低；还可以为将前面两种方式结合，每隔一段时间就刷新一次的异步式，保证在刷新周期内对整个存储芯片刷新一遍，故此处不对具体的刷新方式做限定。
其次，本发明实施例中，数据混洗的装置在实现混洗操作的过程中，伴随着数据的写入，使得数据混洗与数据写入可以都在内存中完成，节省了大量的处理时间，同时令方案的实用性更强。
可选地，在上述图8对应的实施例的基础上，本发明实施例提供的数据混洗方法的第二个可选实施例中，根据第二地址与存储芯片进行数据交互，实现对待混洗数据集合中数据顺序的调整，得到混洗后的数据集合，包括：
向存储芯片传输每个数据的第二地址，以使存储芯片按照每个数据的第二地址，从每个数据的第二地址对应的存储位置读出每个数据，实现对待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
本实施例中，数据混洗的装置向存储芯片传输每个数据的第二地址，使得存储芯片按照每个数据的第二地址，从每个数据的第二地址对应的存储位置中读出每个数据，完成数据的读出和混洗。
需要说明的是，数据混洗的装置向存储芯片传输第二地址的方式可以是通过一种或多种传输协议，例如传输控制协议(TCP，Transmission Control  Protocol)，或者用户数据包协议(UDP，User Datagram Protocol)，也可以是通过地址总线向存储芯片传递第二地址的信息，故此处不对具体传输方式做限定。
其次，本发明实施例中，数据混洗的装置在实现混洗操作的过程中，伴随着数据的读取，使得数据混洗与数据读取可以都在内存中完成，与数据写入过程的逆过程相似，节省了大量的处理时间，同时可以灵活的掌握一段连续地址中对应的数据，便于研究与使用，进一步增加了方案的实用性。
可选地，上述图8对应的实施例、第一个可选实施例以及第二个可选实施例中任一项的基础上，本发明实施例提供的数据混洗方法的第三个可选实施例中，获取待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量包括：
获取混洗开关控制字，混洗开关控制字用于指示开启或关闭数据混洗功能；
当混洗开关控制字指示开启数据混洗功能时，获取每个数据的第一地址和每个数据的地址偏移量。
本实施例中，当数据混洗的装置包括模式选择寄存器时，则数据混洗的装置可以获取混洗开关控制字，而混洗开关控制字是用于指示开启或者关闭数据混洗功能的，当混洗开关控制字指示开启数据混洗功能时，数据混洗的装置获取每个数据的第一地址。
需要说明的是，用户对模式选择寄存器进行配置的时候，可以通过内存增加的专用配置线进行配置，该配置线添加在总线中，但是这种方法需要修改内存的硬件接口，还可以通过内存中已有的控制线，修改控制线的协议，增加寄存器控制字的传输过程，而这种方法不需要修改内存的硬件接口，故此处不对具体配置模式选择寄存器的方法做限定。
再次，本发明实施例中，数据混洗的装置包括了模式选择寄存器，用户可以通过配置模式选择寄存器来设定数据的地址偏移量，还有数据的位宽大小等其他控制字，在实际应用中，对地址偏移量的设置可以实现数据循环左移，循环右移，或者任意交换等其他的新排列方式，因此该方案的灵活性和实践性都得以提升，同时，可操作性也增强了。
可选地，上述图8对应的实施例、第一个可选实施例、第二个可选实施例以及第三个可选实施例中任一项的基础上，本发明实施例提供的数据混洗方法的第四个可选实施例中，根据每个数据的第一地址和每个数据的地址偏移量，计算得到每个数据的第二地址，包括：
调用地址映射函数，计算得到每个数据的第二地址，地址映射函数为每个数据的第二地址与每个数据的第一地址与每个数据的地址偏移量之和的映射关系。
本实施例中，数据混洗的装置调用地址映射函数，通过这个函数来计算得到每个数据的第二地址，地址映射函数是每个数据的第二地址与每个数据的第一地址与每个数据的地址偏移量之和的映射关系。
需要说明的是，地址映射函数可以通过API对其进行编译，该函数可以为上述实施例中提及的写入函数：void MemShuffleWrt(&Data1,size1,shift1)，也可以是读出函数：ShuffledData＝MemShuffleRd(&Data2,size2,shift2)，而在实际应用中，也可以对函数表达式中元素的位置进行改变，例如&Data1、size1与shift1的次序发生改变，还可以是对函数表达式中的元素项目进行调整，例如增加数据带宽的项目，设定为bps1，因此本实施例中不对具体地址映射函数的表达式做限定。
更进一步地，本发明实施例中，数据混洗的装置调用用户设定的地址映射函数，可以根据数据的第一地址与地址偏移量，映射出第二地址，而实现这个功能的地址映射函数可以通过API进行编译，且编码的使用比较简单，整个混洗转换的过程对用户而言也是透明的，用户可以根据需要对地址映射函数的形式进行更改，充分的体现了本方案的灵活性好，同时应用范围广的特点。
为便于理解，下面以一个具体应用场景对本发明中一种数据混洗的方法进行详细描述，具体为：
甲楼中有多家用户同时进行语音传输、收发电子邮件、网页浏览、在线看视频与拨打可视电话的操作，于是需要有多天线支持信号的收发，甲楼中有用户1、用户2和用户3，而用户1、用户2与用户3都使用天线1、天线2、天线3和天线4，此时在多天线多用户的移动通信数据处理中，需在短时 间内进行一次数据混洗操作，使得以天线作为单位进行数据处理。
技术员通过API接口分别编译了写入函数与读出函数，其写入函数如下：
Void MemShuffleWrt(&Data,size,shift)
而对数据的读出过程定义一个API函数如下：
ShuffledData＝MemShuffleRd(&Data,size,shift)
Data是指待读出或写入的数据，size是指每个数据元素的位宽，shift是指一个数组中每个数据对应的地址偏移量，根据上述的函数关系确定与之对应的映射结果。
此时用户通过修改控制线协议来增加寄存器控制字的传输过程，并且设定为地址偏移量shift1＝0，shift2＝2，shift3＝4，shift4＝6，shift5＝-3，shift6＝-1，shift7＝1，shift8＝3，shift9＝-6，shift10＝-4，shift11＝-2，shift12＝0。
数据混洗的装置从存储芯片中的数据缓存中获取待混洗数据为A、B、C、D、E、F、G、H、I、J、K、L，并且从地址缓存中获取了对应的12个地址的原地址addr_odd分别为addr_odd1＝1至addr_odd12＝12。
接着在数据混洗的装置的地址映射模块中开始进行原地址与新地址之间的映射，调用读出函数ShuffledData＝MemShuffleRd(&Data,size,shift)，根据该函数的关系代入以下数据，例如：Data＝A，size＝2Byte，shift1＝0，其对应原地址为addr_odd1所对应的1，通过相应的映射关系，可以得到待混洗数据A的新地址addr_new1＝addr_odd1+shift1，即addr_new1＝1+0＝1。
依次类推可以得到新地址：addr_new2＝4、addr_new3＝7、addr_new4＝10、addr_new5＝2、addr_new6＝5、addr_new7＝8、addr_new8＝11、addr_new9＝3、addr_new10＝6、addr_new11＝9和addr_new12＝12，而相应的，混洗后的数据会被置于新地址中，具体为数据B位于地址4，数据C位于地址7，数据D位于地址10，数据E位于地址2，数据F位于地址5，数据G位于地址8，数据H位于地址11，数据I位于地址3，数据J位于地址6，数据K位于地址9，数据L位于地址12，数据混洗的过程结束。
最后，这些混洗后的数据迁移到行缓冲器中，新地址addr_new所有对应的数据可以下载到数据缓存中，并读出这些数据，技术人员可对这些数据进行分析，为实现更流畅的数据传输奠定基础。
上面对本发明实施例中的数据混洗方法进行了描述，下面对本发明实施例中的数据混洗的装置进行描述，请参阅图9，本发明实施例中的数据混洗的装置一个实施例包括：
获取模块901，用于获取待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量；
计算模块902，用于根据所述每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每个数据的第二地址，所述第二地址用于指示混洗后的每个数据在所述存储芯片中的存储位置；
调整模块903，用于根据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
本实施例中，获取模块901获取待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量，计算模块902根据每个数据的第一地址和每个数据的地址偏移量，计算得到每个数据的第二地址，第二地址用于指示混洗后的每个数据在存储芯片中的存储位置，调整模块903根据第二地址与存储芯片进行数据交互，实现对待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
本发明实施例中，数据混洗的装置获取待混洗数据中每个数据的第一地址和对应的地址偏移量，通过计算得到每个数据对应的第二地址，根据第二地址与存储芯片的数据交互实现待混洗数据的顺序调整，得到混洗后的数据，而上述过程应用于内存的缓存芯片中，不需要再处理器中实现混洗，因此很大程度上节省了处理器的计算资源，同时降低了数据的处理时延。
请参阅图10，本发明实施例中数据混洗的装置的另一个实施例包括：
获取模块1001，用于获取待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量；
计算模块1002，用于根据所述获取模块1001获取的每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每个数据的第二地址，所述第二地址用于指示混洗后的每个数据在所述存储芯片中的存储位置；
调整模块1003，用于根据所述计算模块1002计算的第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到 混洗后的数据集合；
所述调整模块1003可以进一步包括：
第一传输单元10031，用于向所述存储芯片传输所述待混洗数据集合和所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址将所述待混洗数据写入所述每个数据的第二地址对应的存储位置，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
其次，本发明实施例中，数据混洗的装置在实现混洗操作的过程中，伴随着数据的写入，使得数据混洗与数据写入可以都在内存中完成，节省了大量的处理时间，同时令方案的实用性更强。
请参阅图11，本发明实施例中数据混洗的装置的另一个实施例包括：
获取模块1101，用于获取待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量；
计算模块1102，用于根据所述获取模块1101获取的每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每个数据的第二地址，所述第二地址用于指示混洗后的每个数据在所述存储芯片中的存储位置；
调整模块1103，用于根据所述计算模块1102计算的第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合；
所述调整模块1103可以进一步包括：
第二传输单元11031，用于向所述存储芯片传输所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址，从所述每个数据的第二地址对应的存储位置读出所述每个数据，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
其次，本发明实施例中，数据混洗的装置在实现混洗操作的过程中，伴随着数据的读取，使得数据混洗与数据读取可以都在内存中完成，与数据写入过程的逆过程相似，节省了大量的处理时间，同时可以灵活的掌握一段连续地址中对应的数据，便于研究与使用，进一步增加了方案的实用性。
请参阅图12，本发明实施例中数据混洗的装置的另一个实施例包括：
获取模块1201，用于获取待混洗数据集合中每个数据的第一地址和每个 数据的地址偏移量；
计算模块1202，用于根据所述获取模块1201获取的每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每个数据的第二地址，所述第二地址用于指示混洗后的每个数据在所述存储芯片中的存储位置；
调整模块1203，用于根据所述计算模块1202计算的第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合；
所述获取模块1201可以进一步包括：
第一获取单元12011，用于获取混洗开关控制字，所述混洗开关控制字用于指示开启或关闭数据混洗功能；
第二获取单元12012，用于当所述第一获取单元12011获取的混洗开关控制字指示开启所述数据混洗功能时，获取所述每个数据的第一地址和所述每个数据的地址偏移量。
所述调整模块1203可以进一步包括：
第二传输单元12031，用于向所述存储芯片传输所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址，从所述每个数据的第二地址对应的存储位置读出所述每个数据，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
再次，本发明实施例中，数据混洗的装置包括了模式选择寄存器，用户可以通过配置模式选择寄存器来设定数据的地址偏移量，还有数据的位宽大小等其他控制字，在实际应用中，对地址偏移量的设置可以实现数据循环左移，循环右移，或者任意交换等其他的新排列方式，因此该方案的灵活性和实践性都得以提升，同时，可操作性也增强了。
请参阅图13，本发明实施例中数据混洗的装置的另一个实施例包括：
获取模块1301，用于获取待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量；
计算模块1302，用于根据所述获取模块1301获取的每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每个数据的第二地址，所述第二地址用于指示混洗后的每个数据在所述存储芯片中的存储位置；
调整模块1303，用于根据所述计算模块1302计算的第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合；
所述获取模块1301可以进一步包括：
第一获取单元13011，用于获取混洗开关控制字，所述混洗开关控制字用于指示开启或关闭数据混洗功能；
第二获取单元13012，用于当所述第一获取单元13011获取的混洗开关控制字指示开启所述数据混洗功能时，获取所述每个数据的第一地址和所述每个数据的地址偏移量。
所述计算模块1302可以进一步包括：
计算单元13021，用于调用地址映射函数，计算得到所述每个数据的第二地址，所述地址映射函数为所述每个数据的第二地址与所述每个数据的第一地址与所述每个数据的地址偏移量之和的映射关系。
所述调整模块1303可以进一步包括：
第二传输单元13031，用于向所述存储芯片传输所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址，从所述每个数据的第二地址对应的存储位置读出所述每个数据，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
更进一步地，本发明实施例中，数据混洗的装置调用用户设定的地址映射函数，可以根据数据的第一地址与地址偏移量，映射出第二地址，而实现这个功能的地址映射函数可以通过API进行编译，且编码的使用比较简单，整个混洗转换的过程对用户而言也是透明的，用户可以根据需要对地址映射函数的形式进行更改，充分的体现了本方案的灵活性好，同时应用范围广的特点。
图14是本发明实施例提供的一种数据混洗的装置结构示意图，该数据混洗的装置1400可因配置或性能不同而产生比较大的差异，可以包括一个或一个以上中央处理器1422(例如，一个或一个以上处理器)和存储器1432，一个或一个以上存储应用程序1442或数据1444的存储介质1430(例如一个或一个以上海量存储设备)。其中，存储器1432和存储介质1430可以是短暂存 储或持久存储。存储在存储介质1430的程序可以包括一个或一个以上模块(图示没标出)，每个模块可以包括对服务器中的一系列指令操作。更进一步地，中央处理器1422可以设置为与存储介质1430通信，在服务器1400上执行存储介质1430中的一系列指令操作。
中央处理器1422用于：
获取待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量；
根据所述每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每个数据的第二地址，所述第二地址用于指示混洗后的每个数据在所述存储芯片中的存储位置；
根据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
本发明实施例中，数据混洗的装置获取待混洗数据中每个数据的第一地址和对应的地址偏移量，通过计算得到每个数据对应的第二地址，根据第二地址与存储芯片的数据交互实现待混洗数据的顺序调整，得到混洗后的数据，而上述过程应用于内存的缓存芯片中，不需要再处理器中实现混洗，因此很大程度上节省了处理器的计算资源，同时降低了数据的处理时延。
作为一种可选的方式，中央处理器1422还用于向所述存储芯片传输所述待混洗数据集合和所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址将所述待混洗数据写入所述每个数据的第二地址对应的存储位置，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
其次，本发明实施例中，数据混洗的装置在实现混洗操作的过程中，伴随着数据的写入，使得数据混洗与数据写入可以都在内存中完成，节省了大量的处理时间，同时令方案的实用性更强。
作为一种可选的方式，中央处理器1422还用于向所述存储芯片传输所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址，从所述每个数据的第二地址对应的存储位置读出所述每个数据，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
其次，本发明实施例中，数据混洗的装置在实现混洗操作的过程中，伴 随着数据的读取，使得数据混洗与数据读取可以都在内存中完成，与数据写入过程的逆过程相似，节省了大量的处理时间，同时可以灵活的掌握一段连续地址中对应的数据，便于研究与使用，进一步增加了方案的实用性。
作为一种可选的方式，中央处理器1422还用于获取混洗开关控制字，所述混洗开关控制字用于指示开启或关闭数据混洗功能；
当所述混洗开关控制字指示开启所述数据混洗功能时，获取所述每个数据的第一地址和所述每个数据的地址偏移量。
再次，本发明实施例中，数据混洗的装置包括了模式选择寄存器，用户可以通过配置模式选择寄存器来设定数据的地址偏移量，还有数据的位宽大小等其他控制字，在实际应用中，对地址偏移量的设置可以实现数据循环左移，循环右移，或者任意交换等其他的新排列方式，因此该方案的灵活性和实践性都得以提升，同时，可操作性也增强了。
作为一种可选的方式，中央处理器1422还用于调用地址映射函数，计算得到所述每个数据的第二地址，所述地址映射函数为所述每个数据的第二地址与所述每个数据的第一地址与所述每个数据的地址偏移量之和的映射关系。
更进一步地，本发明实施例中，数据混洗的装置调用用户设定的地址映射函数，可以根据数据的第一地址与地址偏移量，映射出第二地址，而实现这个功能的地址映射函数可以通过API进行编译，且编码的使用比较简单，整个混洗转换的过程对用户而言也是透明的，用户可以根据需要对地址映射函数的形式进行更改，充分的体现了本方案的灵活性好，同时应用范围广的特点。
数据混洗的装置1400还可以包括一个或一个以上电源1426，一个或一个以上有线或无线网络接口1450，一个或一个以上输入输出接口1458，和/或，一个或一个以上操作系统1441，例如Windows ServerTM，Mac OS XTM，UnixTM,LinuxTM，FreeBSDTM等等。
上述实施例中由数据混洗的装置所执行的步骤可以基于该图14所示的数据混洗的装置结构。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有 详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上对本发明所提供的一种数据混洗的方法进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本发明实施例的思想，在具体实施方式及应用范围上均会有改变之处， 综上所述，本说明书内容不应理解为对本发明的限制。

Claims (18)

  1. 一种数据混洗的装置，其特征在于，所述装置应用于内存的缓冲芯片，所述内存还包括存储芯片，所述装置包括：缓存模块和混洗模块；
    所述缓存模块与所述混洗模块通信连接；
    所述缓存模块用于缓存待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量；
    所述混洗模块用于根据所述每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每个数据的第二地址，所述第二地址用于指示混洗后的每个数据在所述存储芯片中的存储位置；
    所述混洗模块用于根据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
  2. 根据权利要求1所述的装置，其特征在于，
    所述缓存模块为地址缓存模块，所述地址缓存模块与所述混洗模块通信连接，所述地址缓存模块用于缓存待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量；或者，
    所述缓存模块包括地址缓存模块和控制缓存模块，所述地址缓存模块用于缓存待混洗数据集合中每个数据的第一地址，所述控制缓存模块用于缓存所述每个数据的地址偏移量；或者，
    所述缓存模块包括地址缓存模块和偏移缓存模块，所述地址缓存模块用于缓存待混洗数据集合中每个数据的第一地址，所述偏移缓存模块用于缓存所述每个数据的地址偏移量。
  3. 根据权利要求1或2所述的装置，其特征在于，所述混洗模块用于根据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合，包括：
    所述混洗模块用于向所述存储芯片传输所述待混洗数据集合和所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址将所述待混洗数据写入所述每个数据的第二地址对应的存储位置，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
  4. 根据权利要求1或2所述的装置，其特征在于，所述混洗模块用于根 据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合，包括：
    所述混洗模块用于向所述存储芯片传输所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址，从所述每个数据的第二地址对应的存储位置读出所述每个数据，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
  5. 根据权利要求1-4任一所述的装置，其特征在于，所述混洗模块包括：模式选择寄存器，
    所述模式选择寄存器用于获取混洗开关控制字，所述混洗开关控制字用于指示开启或关闭数据混洗功能；
    当所述混洗开关控制字指示开启所述数据混洗功能时，所述模式选择寄存器用于从所述缓存模块获取所述每个数据的地址偏移量。
  6. 根据权利要求1-5任一所述的装置，其特征在于，所述待混洗数据集合中每个数据的地址偏移量的绝对值都小于用于存储所述每个数据的总存储空间的大小，且所述每个数据的地址偏移量之和为零。
  7. 根据权利要求5所述的装置，其特征在于，所述内存还包括总线，所述总线中配置有与所述模式选择寄存器连接的配置线，
    所述配置线一端与所述模式选择寄存器相连，另一端通过所述内存的插槽与所述内存以外的芯片相连；
    所述模式选择寄存器用于获取混洗开关控制字，包括：
    所述模式选择寄存器用于通过所述配置线接收用户配置的所述混洗开关控制字。
  8. 根据权利要求1至7中任一所述的装置，其特征在于，所述混洗模块用于根据所述每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每个数据的第二地址，包括：
    所述混洗模块用于调用地址映射函数，计算得到所述每个数据的第二地址，所述地址映射函数为所述每个数据的第二地址与所述每个数据的第一地址与所述每个数据的地址偏移量之和的映射关系。
  9. 一种数据混洗的方法，其特征在于，所述方法应用于内存的缓冲芯片， 所述内存还包括存储芯片，所述方法包括：
    获取待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量；
    根据所述每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每个数据的第二地址，所述第二地址用于指示混洗后的每个数据在所述存储芯片中的存储位置；
    根据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
  10. 根据权利要求9所述的方法，其特征在于，所述根据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合，包括：
    向所述存储芯片传输所述待混洗数据集合和所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址将所述待混洗数据写入所述每个数据的第二地址对应的存储位置，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
  11. 根据权利要求9所述的方法，其特征在于，所述根据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合，包括：
    向所述存储芯片传输所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址，从所述每个数据的第二地址对应的存储位置读出所述每个数据，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
  12. 根据权利要求9至11中任一项所述的方法，其特征在于，所述获取待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量包括：
    获取混洗开关控制字，所述混洗开关控制字用于指示开启或关闭数据混洗功能；
    当所述混洗开关控制字指示开启所述数据混洗功能时，获取所述每个数据的第一地址和所述每个数据的地址偏移量。
  13. 根据权利要求9至12在中任一项所述的方法，其特征在于，所述根据所述每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每 个数据的第二地址，包括：
    调用地址映射函数，计算得到所述每个数据的第二地址，所述地址映射函数为所述每个数据的第二地址与所述每个数据的第一地址与所述每个数据的地址偏移量之和的映射关系。
  14. 一种数据混洗的装置，其特征在于，所述装置应用于内存的缓冲芯片，所述内存还包括存储芯片，所述装置包括：
    获取模块，用于获取待混洗数据集合中每个数据的第一地址和每个数据的地址偏移量；
    计算模块，用于根据所述每个数据的第一地址和所述每个数据的地址偏移量，计算得到所述每个数据的第二地址，所述第二地址用于指示混洗后的每个数据在所述存储芯片中的存储位置；
    调整模块，用于根据所述第二地址与所述存储芯片进行数据交互，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
  15. 根据权利要求14所述的装置，其特征在于，所述调整模块包括：
    第一传输单元，用于向所述存储芯片传输所述待混洗数据集合和所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址将所述待混洗数据写入所述每个数据的第二地址对应的存储位置，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
  16. 根据权利要求14所述的装置，其特征在于，所述调整模块包括：
    第二传输单元，用于向所述存储芯片传输所述每个数据的第二地址，以使所述存储芯片按照所述每个数据的第二地址，从所述每个数据的第二地址对应的存储位置读出所述每个数据，实现对所述待混洗数据集合中数据顺序的调整，得到混洗后的数据集合。
  17. 根据权利要求14至16中任一项所述的装置，其特征在于，所述获取模块包括：
    第一获取单元，用于获取混洗开关控制字，所述混洗开关控制字用于指示开启或关闭数据混洗功能；
    第二获取单元，用于当所述混洗开关控制字指示开启所述数据混洗功能时，获取所述每个数据的第一地址和所述每个数据的地址偏移量。
  18. 根据权利要求14至17中任一项所述的装置，其特征在于，所述计算模块包括：
    计算单元，用于调用地址映射函数，计算得到所述每个数据的第二地址，所述地址映射函数为所述每个数据的第二地址与所述每个数据的第一地址与所述每个数据的地址偏移量之和的映射关系。
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