WO2016106911A1 - 一种mcu芯片的信息保护方法和装置 - Google Patents

一种mcu芯片的信息保护方法和装置 Download PDF

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Publication number
WO2016106911A1
WO2016106911A1 PCT/CN2015/071556 CN2015071556W WO2016106911A1 WO 2016106911 A1 WO2016106911 A1 WO 2016106911A1 CN 2015071556 W CN2015071556 W CN 2015071556W WO 2016106911 A1 WO2016106911 A1 WO 2016106911A1
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Prior art keywords
partition
flash
user area
state
access
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PCT/CN2015/071556
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English (en)
French (fr)
Inventor
李宝魁
王景华
王南飞
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北京兆易创新科技股份有限公司
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Priority to US15/505,926 priority Critical patent/US10102155B2/en
Priority to EP15874604.0A priority patent/EP3242214B1/en
Publication of WO2016106911A1 publication Critical patent/WO2016106911A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/82—Protecting input, output or interconnection devices
    • G06F21/85—Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2141—Access rights, e.g. capability lists, access control lists, access tables, access matrices

Definitions

  • the present application relates to the field of electronic circuit technologies, and in particular, to an information protection method for an MCU chip and an information protection device for an MCU chip.
  • MCU Micro Control Unit
  • the MCU chip usually includes a CPU (Central Processing Unit), a flash memory, a SRAM (Static Random Access Memory), and various peripheral devices.
  • CPU Central Processing Unit
  • SRAM Static Random Access Memory
  • Flash memory is usually divided into two separate areas: one is the flash user area, which is used to store the user's program; the other is the flash information area, which is used to store the configuration information of the MCU chip.
  • SRAM is generally used as an on-chip cache.
  • the program will eventually be written into the flash memory user area of the MCU chip. Since the core value of the solution provider lies in the developed program, it is required. Ensure that the program is absolutely secure and cannot be stolen by others.
  • the goal of the MCU chip's information protection scheme is to protect the contents of the flash user area from being stolen by others.
  • the products of the MCU chip on the market are only the overall protection of the contents of the flash memory user area in terms of information protection solutions, and cannot meet the requirements of the cooperation development programs of the two companies. Because it can only protect the contents of the flash user area from being stolen by customers, it cannot prevent companies that cooperate to develop programs from stealing each other's programs.
  • the technical problem to be solved by the embodiments of the present application is to provide an information protection method for an MCU chip, which is used to protect a program from being stolen by a client, and a company that protects the cooperative development program cannot steal each other's programs.
  • the embodiment of the present application further provides an information protection device for an MCU chip to ensure implementation and application of the foregoing method.
  • the present application discloses an information protection method for an MCU chip, where the MCU chip includes an instruction bus, a data bus, a flash controller, and a flash user area; the flash controller is used to divide the flash user area into the first a partition and a second partition; the method includes:
  • the instruction bus accesses the second partition, and enters a transition state; in the transition state, suspending the instruction bus to access the flash user area, allowing the data The bus accesses the first partition but prohibits the data bus from accessing the second partition;
  • the method further includes:
  • an initial state is entered; in the initial state, the instruction bus is allowed to access the flash user area, and the data bus is prohibited from accessing the first partition and the second partition.
  • the MCU chip includes a CPU, and the CPU is a Harvard structure;
  • the waiting time is set to be related to the characteristics of the CPU; if the CPU is ARM Cortex-M3, the preset waiting time is 20 CPU clock cycles.
  • the MCU chip includes a flash information area, and the flash information area includes an option byte; the method further includes:
  • the flash user area is allowed to be read, written, and erased
  • the first partition is allowed to be read, written, and erased, and the second partition is allowed to be read, written, and erased only when the flash user area is booted. except;
  • the option byte allows modification
  • the option byte In the primary read protection state, the option byte allows modification, and if the zero-level read protection state is modified from the primary read protection state based on the option byte, then all of the flash user area The information will be erased;
  • the option byte prohibits modification.
  • the MCU chip is designed with a private device, and the private device that works normally only when the first partition enable signal is output is the first device, and the private device that works normally only when the second partition enable signal is output.
  • the device is a second device; the method further includes:
  • the first partition enable signal is output; if the second partition is in the working state, or the second partition is in the transition state, the second partition is output Enable signal.
  • the device comprises a static random access memory SRAM.
  • the first partition is located in a first half of the address area of the flash user area
  • the second partition is located in a second half of the address area of the flash user area.
  • the embodiment of the present application further discloses an information protection device for an MCU chip, where the MCU chip includes an instruction bus, a data bus, a flash controller, and a flash user area; the flash controller is configured to divide the flash user area into the first partition. And a second partition; the device comprises:
  • the first determining module is configured to: when the instruction bus accesses the flash user area, determine whether the instruction bus accesses the first partition; if yes, invoke a first entering module;
  • a first entry module configured to enter a first partition working state; in the first partition working state, allowing the instruction bus to access the flash user area, allowing the data bus to access the first partition, but prohibiting The data bus accesses the second partition;
  • a second entry module configured to enter a transition state when the instruction bus accesses the second partition when in the first partition working state; in the transition state, suspend the instruction bus to access the flash memory a user area that allows the data bus to access the first partition but prohibits the data bus from accessing the second partition;
  • the second determining module is configured to determine whether the time in the transition state reaches a preset waiting time; if yes, the third entering module is invoked;
  • a third entry module configured to enter a second partition working state; in the second partition working state, allowing the instruction bus to access the flash user area, prohibiting the data bus from accessing the first partition, but allowing The data bus accesses the second partition.
  • the device further comprises:
  • a fourth entry module configured to enter an initial state after the MCU chip is reset; in the initial state, the instruction bus is allowed to access the flash user area, and the data bus is prohibited from accessing the first partition and Second partition.
  • the MCU chip includes a flash information area, and the flash information area includes an option byte; the device further includes:
  • Determining a module configured to determine a read protection status of the flash user area according to the option byte;
  • a first protection module configured to allow reading, writing, and erasing of the flash user area when in a zero-level read protection state
  • a second protection module configured to allow the first point when the level is read protection state
  • the area performs read, write, and erase, allowing read, write, and erase of the second partition only when the flash user area is booted;
  • the third protection module is configured to allow reading, writing, and erasing of the first partition and the second partition only when the flash user area is booted when in the secondary read protection state.
  • the option byte allows modification
  • the option byte In the primary read protection state, the option byte allows modification, and if the zero-level read protection state is modified from the primary read protection state based on the option byte, then all of the flash user area The information will be erased;
  • the option byte prohibits modification.
  • the MCU chip is designed with a private device, and the private device that works normally only when the output of the first partition enable signal is valid is the first device, and only works when the output of the second partition enable signal is valid.
  • the private device is a second device; the device further includes:
  • the first output module is configured to output a first partition enable signal when in the first partition working state or the first partition transition state;
  • the second output module is configured to output a second partition enable signal when in the second partition working state or the second partition transition state.
  • the embodiment of the present application also discloses a computer readable recording medium having recorded thereon a program for executing the method of claim 1.
  • the embodiments of the present application include the following advantages:
  • the flash controller in the MCU chip divides the flash user area into the first partition and the second partition.
  • the flash user area can normally accept the access of the instruction bus, but Data bus access partitions will be limited.
  • the instruction bus accesses the first partition
  • the data bus can only access the first partition and cannot access the second partition. If the instruction bus changes from accessing the first partition to accessing the second partition, the instruction bus is suspended to access the flash user area, and when the preset wait time is reached, the instruction bus can Accessing the flash user area, the data bus cannot access the first partition and can only access the second partition.
  • the instruction bus accesses the flash user area only the data bus is allowed to access the partition accessed by the instruction bus, and the program in the flash user area can be protected from being stolen by other companies that cooperate with the development program.
  • the MCU chip is also provided with a read protection level, and according to the option byte in the flash information area, the read protection level of the flash memory of the MCU chip is determined, and the operation of the flash user area is restricted.
  • the two companies cooperate to develop programs in the MCU chip, when a company develops, it can improve the read protection level of the flash user area to limit the program that other company readers burn to the flash user area, thus avoiding cooperation. Companies that develop programs steal each other's programs. In addition, if someone wants to steal access to programs that access the flash user area by reducing the level of read protection, all programs in the flash user area will be erased, further protecting the company's development.
  • the partition may be divided into different cooperative development companies, and the peripheral device may be designed as a private device of a certain partition, each partition has a corresponding partition enable signal, and the partition enable signal may be controlled. Its corresponding private device. For example, according to the partition enable signal, some or all of the functions of the corresponding private device can be turned on or off, and the intermediate result of the program developed by the cooperative development company is avoided, which is obtained by other cooperative companies.
  • FIG. 1 is a flow chart showing the steps of an embodiment of an information protection method for an MCU chip according to the present application
  • FIG. 2 is a schematic structural diagram of a system of a MCU chip based on a Harvard architecture CPU according to the present application;
  • FIG. 3 is a schematic diagram showing the workflow of an MCU chip flash controller of the present application.
  • FIG. 4 is a structural block diagram of an embodiment of an information protection device of an MCU chip of the present application.
  • the read protection level of the flash controller is controlled by a number of control bits of the flash information area.
  • the read protection level of the flash controller is divided into three levels, and the characteristics of each level are as follows:
  • Zero-level read protection The flash user area is completely open and can be read, written and erased arbitrarily.
  • the flash information area is also completely open.
  • First-level read protection The flash user area can be accessed normally from the flash user area; other boot modes (including booting from other locations and JTAG (Joint Test Action Group)) cannot access the flash user area. Reading, writing, and erasing are not possible. At this level, the flash information area can be accessed, but if the read control bit changes the read protection level of the flash controller to zero level, the contents of the flash user area are all erased.
  • JTAG Joint Test Action Group
  • the flash user area can be accessed normally from the flash user area; other boot modes (including booting from other locations and debugging methods such as JTAG) are not available. At this level, the flash information area is only readable, non-writable, and erasable.
  • the flash user area is protected as a whole. If the program of the MCU chip is completely developed by a company, this solution can meet the demand. However, as the application of MCU chips becomes more and more complex, the programs of MCU chips will become more and more complicated. There will be two companies and even a number of companies working together to develop the program's needs. The MCU chip information protection solution cannot be satisfied. Because it can only protect the contents of the flash user area from being stolen by customers, it cannot prevent the companies that cooperate to develop programs from stealing each other's programs. Based on such requirements, the embodiment of the present application further proposes an information protection scheme for an MCU chip.
  • Applying the MCU information protection scheme of the embodiment of the present application can meet the requirements of the two companies cooperating to develop the MCU chip program.
  • the flash memory user is divided into two partitions, and the two companies cooperatively developing the program can separately write the programs developed by themselves to the partitions belonging to them.
  • the embodiment of the present application can ensure that the programs of the two companies can normally realize mutual calling, and cannot mutually steal the programs in the other party's partition, and the protection program is not stolen by the client.
  • SRAM and other peripherals are shared by two companies that are cooperating, the program may be stolen by the partner through these shared resources.
  • the embodiment of the present application may further divide a specific SRAM or a peripheral device into a certain party as a private device, and the embodiment of the present application is broadened. The scope of application.
  • the MCU chip may include an instruction bus, a data bus, a flash controller, and a flash user area; Can be used to divide the flash user area into a first partition and a second partition;
  • the MCU chip usually includes a CPU, a bus, a flash memory, a flash controller, an SRAM, various master devices and slave devices (peripherals). and many more.
  • the bus may include an instruction bus, a data bus, and a system bus.
  • the CPU is connected to the bus interconnect matrix through an instruction bus, a data bus, and a system bus.
  • the instruction bus is responsible for reading the instructions; the data bus is responsible for data access; the system bus is responsible for accessing peripheral devices.
  • the flash controller of the MCU chip is a bridge connecting the bus and the flash memory.
  • the flash controller has the same three buses connected to the bus interconnect matrix, wherein the instruction bus is responsible for accepting the instruction access of the CPU; the data bus is responsible for accepting the data access of the CPU; and its configuration register is accessed through the system bus. SRAM and various peripheral devices are connected to the bus interconnect matrix.
  • the two partitions can be respectively divided into two companies of the cooperative development program, and the peripheral device can be designed as a private device of a certain partition, and each Each partition has a corresponding partition enable signal, and the private device is controlled by the partition enable signal output by the flash controller.
  • "access” contains all operations.
  • the bus of the MCU chip has read operations and write operations, and the bus access includes read operations and write operations.
  • Flash has read, write, and erase operations, and access to the flash includes read, write, and erase operations.
  • the method may specifically include the following steps:
  • Step 101 when the instruction bus accesses the flash user area, it is determined whether the instruction bus accesses the first partition; if yes, step 102 is performed;
  • Step 102 entering a first partition working state; in the first partition working state, allowing the instruction bus to access the flash user area, allowing the data bus to access the first Partitioning, but prohibiting the data bus from accessing the second partition;
  • Step 103 when in the first partition working state, the instruction bus accesses the second partition, enter a transition state; in the transition state, suspend the instruction bus to access the flash user area, allowing The data bus accesses the first partition but prohibits the data bus from accessing the second partition;
  • Step 104 it is determined whether the time in the transition state reaches a preset waiting time; if yes, step 105 is performed;
  • Step 105 entering a second partition working state; in the second partition working state, allowing the instruction bus to access the flash user area, prohibiting the data bus from accessing the first partition, but allowing the data bus Accessing the second partition.
  • Applying the embodiment of the present application has at least the following advantages: first, the content of the protected flash memory is not stolen by the terminal client; secondly, the two companies that ensure the cooperative development program cannot steal each other's programs.
  • the two companies that co-developed the program must have one to develop the main program and the other to develop the library function.
  • the company that develops the main program is called the first company
  • the company that develops the library function is called the second company.
  • the partitions corresponding to the two companies are the first partition and the second partition, respectively.
  • the first partition is located in the first half of the address space
  • the second partition is located in the second half of the address space. This facilitates the execution of the first company's program when the MCU chip is started.
  • the method for protecting the information of the MCU chip in the embodiment of the present application can be described in three parts: the first part is the partition protection working mode; the second part is the definition and usage method of the read protection level; the third part is the implementation method of the private device.
  • the first two parts are implemented in the flash controller; the third part is implemented in the private device based on the partition enable signal output by the flash controller.
  • the first part the way the partition protection works.
  • the flash user area When the flash user area is started, the flash user area can normally accept access to the CPU instruction bus and can be restricted to accept access to the CPU data bus, but does not accept access from other master devices.
  • the specific steps are as follows:
  • the MCU chip is reset and the flash controller is in the initial state. In the initial state, The instruction bus has access to all partitions and the data bus cannot access any partitions.
  • step 3 Determine whether the instruction bus is accessing the flash user area; if yes, execute step 3, if no, return to step 1.
  • step 3 Determine whether the instruction bus access is the first partition; if yes, execute step 4, if no, go to step 9.
  • the instruction bus can access all partitions, and the data bus can access the first partition but cannot access the second partition (if the second partition is accessed, an error response is returned).
  • step 5 Determine whether the instruction bus is accessing the flash user area; if not, return to step 4, that is, if the instruction bus does not access the flash user area, then keep in the current state (first partition working state); if yes, go to step 6.
  • step 8 Whether the waiting time has reached the preset waiting time in the transition state; if yes, execute step 9; if not, return to step 7.
  • step 10 Determine whether the instruction bus is accessing the flash user area; if not, return to step 9, that is, if the instruction bus does not access the flash user area, then keep in the current state (second partition working state); if yes, go to step 11.
  • step 11 Determine whether the instruction bus access is another partition (first partition); if the instruction bus accesses the currently working partition (second partition), keep the current state, that is, return to step 9, if the instruction bus accesses other partitions (First partition), go to step 12.
  • step 13 Whether the waiting time has reached the preset waiting time in the transition state; if yes, proceed to step 4; if not, return to step 12.
  • the length of the preset waiting time in the transition state is related to the characteristics of the CPU of the MCU chip.
  • the Harvard architecture CPU reads instructions through the instruction bus and completes data access through the data bus. The two work in parallel. The CPU obtains the instruction to be executed through the instruction bus, and after the instruction is parsed, it is determined whether data access is needed and which address data needs to be accessed, and then the corresponding data access is completed through the data bus.
  • the wait time should be long enough to ensure that the data access for the previous instruction for the current working partition is complete. Taking the ARM Cortex-M3 as an example, the wait time can be set to 20 CPU clock cycles.
  • the second part the definition of the read protection level and how to use it.
  • the MCU chip may include a flash information area, and the flash information area may include an option byte; the method may further include the following steps:
  • Step S11 determining, according to the option byte, a read protection status of the flash user area
  • Step S12 if the zero-level read protection state, read, write, and erase the flash user area
  • Step S13 if it is a level 1 read protection state, allowing read, write, and erase of the first partition, and allowing reading and writing of the second partition only when the flash user area is started. In and erase;
  • step S14 if it is the secondary read protection state, reading, writing and erasing of the first partition and the second partition are allowed only when the flash user area is started.
  • the option byte allows modification
  • the option byte In the primary read protection state, the option byte allows modification, and if the zero-level read protection state is modified from the primary read protection state based on the option byte, then all of the flash user area The information will be erased (to ensure that the contents of the flash user area are not stolen, zero-level read protection takes effect after the user area content is erased).
  • the option byte prohibits modification.
  • the read protection level can be controlled by a number of bytes in the flash information area, which are option bytes.
  • the method of control is arbitrary, as long as different read protection levels can be distinguished and the switching between the protection levels can be facilitated. For example, it is controlled by 1 byte.
  • the read protection state is zero level
  • the read protection level is level 2
  • the read protection level is one level.
  • the read protection level can be used as follows.
  • the factory MCU chip is first handed over to the second company.
  • the read protection level is zero-level protection state, and the flash user area is empty.
  • the second company burned the program they developed into the second partition of the flash user area.
  • the second company can debug the program in the zero-level read protection state.
  • the second company will modify the read protection level to the first level read protection before handing the chip to the first company.
  • the first company burned the programs they developed to the first partition of the flash user area.
  • the first partition of the flash user area stores the program of the first company
  • the second partition stores the program of the second company
  • the read protection level is the first level read protection.
  • the first company should complete the joint debugging of the two company programs in this state.
  • the first company would change the read protection level to secondary read protection before handing the chip to the customer.
  • the third part the implementation of private devices.
  • the MCU chip can design a private device according to a specific requirement, and the private device that works normally only when the first partition enable signal is output is the first device, and only the output has The private device that works normally when the second partition is enabled is The second device; the method may further include the following steps:
  • Step S21 if it is in the first partition working state, or the first partition transition state, outputting a first partition enable signal
  • Step S22 if in the second partition working state or the second partition transition state, output a second partition enable signal.
  • the private device is a device controlled by a partition enable signal output by the flash controller.
  • Each partition can correspond to a 1-bit partition enable signal.
  • the partition enable signal indicates that the corresponding partition is in working state.
  • the first partition enable signal is 1 in the first partition working state and the first partition transition state, and is 0 in other states; the second partition enable signal is 1 in the second partition working state and the second partition transition state, It is 0 in other states.
  • the method of control is to turn on or off some or all of the functions of the corresponding device according to the state of the specific partition enable signal.
  • the first partition enable signal As the enable signal for the SRAM read path; if you want a private device's operation result register to only allow the second company Program read, you can use the second partition enable signal to strobe the read path of the result register; if you want a private device to only allow the first company's program configuration, you can use the first partition enable signal as the device register configuration Enable signal.
  • the MCU chip may include an instruction bus, a data bus, a flash controller, and Flash user area.
  • the flash controller is configured to divide the flash user area into the first partition and the second partition; specifically, the following modules may be included:
  • the first judging module 201 is configured to: when the instruction bus accesses the flash user area, determine whether the instruction bus accesses the first partition; if yes, invoke the first entering module 202;
  • the first entering module 202 is configured to enter a first partition working state; in the first partition working state, allowing the instruction bus to access the flash user area, allowing the data bus to access the first partition, but Disabling the data bus from accessing the second partition;
  • the first partition is located in the first half of the address area of the flash user area
  • the second partition is located in the second half of the address area of the flash user area.
  • the second entering module 203 is configured to enter a transition state when the instruction bus accesses the second partition when in the first partition working state; in the transition state, suspend the instruction bus to access the a flash user area that allows the data bus to access the first partition but prohibits the data bus from accessing the second partition;
  • the second determining module 204 is configured to determine whether the time in the transition state reaches a preset waiting time; if yes, the third entering module 205 is invoked;
  • the third entering module 205 is configured to enter a second partition working state; in the second partition working state, the instruction bus is allowed to access the flash user area, and the data bus is prohibited from accessing the first partition, but The data bus is allowed to access the second partition.
  • the MCU chip includes a CPU, and the CPU is a Harvard structure; the preset waiting time is related to the characteristics of the CPU; if the CPU is an ARM Cortex-M3, The preset wait time is 20 CPU clock cycles.
  • the apparatus may further include the following modules:
  • a fourth entry module configured to enter an initial state after the MCU chip is reset; in the initial state, the instruction bus is allowed to access the flash user area, and the data bus is prohibited from accessing the first partition and Second partition.
  • the MCU chip includes a flash information area, and the flash information area includes an option byte; the device may further include the following modules:
  • Determining a module configured to determine a read protection status of the flash user area according to the option byte;
  • a first protection module configured to allow reading, writing, and erasing of the flash user area when in a zero-level read protection state
  • a second protection module configured to allow reading, writing, and erasing of the first partition when in a level 1 read protection state, allowing the second partition to be performed only when the flash user area is booted Read, write, and erase;
  • the third protection module is configured to allow reading, writing, and erasing of the first partition and the second partition only when the flash user area is booted when in the secondary read protection state.
  • the option byte allows modification
  • the option byte In the primary read protection state, the option byte allows modification, and if the zero-level read protection state is modified from the primary read protection state based on the option byte, then all of the flash user area The information will be erased;
  • the option byte prohibits modification.
  • the MCU chip can design a private device according to a specific requirement, and the private device that works normally only when the first partition enable signal is output is the first device, and only the output has The private device that works normally when the second partition is enabled is the second device; the device further includes:
  • the first output module is configured to output a first partition enable signal when in the first partition working state or the first partition transition state;
  • the second output module is configured to output a second partition enable signal when in the second partition working state or the second partition transition state.
  • the peripheral device may comprise a static random access memory (SRAM).
  • SRAM static random access memory
  • the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.
  • the embodiment of the present application also provides a computer readable recording medium on which the program for the above embodiment is recorded.
  • the computer readable recording medium includes any mechanism for storing or transmitting information in a form readable by a computer (eg, a computer).
  • a machine-readable medium includes read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash storage media, electrical, optical, acoustic, or other forms of propagation signals (eg, carrier waves) , infrared signals, digital signals, etc.).
  • embodiments of the embodiments of the present application can be provided as a method, apparatus, or computer program product. Therefore, the embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Moreover, embodiments of the present application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • Embodiments of the present application are described with reference to flowcharts and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the present application. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG.
  • These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing terminal device to produce a machine such that instructions are executed by a processor of a computer or other programmable data processing terminal device
  • Means are provided for implementing the functions specified in one or more of the flow or in one or more blocks of the flow chart.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • Command device Flowchart A process or a plurality of processes and/or block diagrams of functions specified in a block or blocks.

Abstract

一种MCU芯片的信息保护方法和装置，所述MCU芯片包括指令总线、数据总线、闪存控制器和闪存用户区；所述闪存控制器用于将闪存用户区划分为第一分区和第二分区；所述的方法包括：当所述指令总线访问所述闪存用户区时，判断所述指令总线是否访问所述第一分区（101）；若是，则进入第一分区工作状态（102）；当处于所述第一分区工作状态下，所述指令总线访问所述第二分区，则进入过渡状态（103）；判断处于所述过渡状态下的时间是否达到预设的等待时间（104）；若是，则进入第二分区工作状态（105）；所述方法和装置用以保护程序不被客户窃取，同时保护合作开发程序的公司不能相互窃取对方的程序。

Description

一种MCU芯片的信息保护方法和装置
本申请要求在2014年12月30日提交中国专利局、申请号为201410851200.8、发明名称为“一种MCU芯片的信息保护方法和装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子电路技术领域，特别是涉及一种MCU芯片的信息保护方法和一种MCU芯片的信息保护装置。
背景技术
随着集成电路技术的不断提高，MCU(Micro Control Unit，微控制单元)芯片的应用越来越广泛，小到儿童玩具，大到工程机械，都需要用到MCU芯片。MCU芯片通常包含CPU(Central Processing Unit，中央处理器)、闪存(Flash Memory)、SRAM(Static Random Access Memory，静态随机存储器)和各种外围设备。在MCU芯片掉电时，闪存的内容不会丢失，而SRAM的内容则会丢失。闪存通常会被分为两个独立的区域：一个是闪存用户区，用来存储用户的程序；另一个是闪存信息区，用来存放MCU芯片的配置信息。SRAM一般用作片上缓存。
对于MCU芯片的方案商而言，也就是基于MCU芯片开发程序和外围电路的厂商，程序最终会烧写到MCU芯片的闪存用户区中，由于方案商的核心价值在于所开发的程序，故需要保证程序绝对安全，不能被他人窃取。MCU芯片的信息保护方案的目标就是保护闪存用户区的内容不被他人窃取。目前市场上的MCU芯片的产品在信息保护方案方面，都只是对其闪存用户区的内容整体地保护，无法满足两家公司合作开发程序的需求。因为它只能保护闪存用户区的内容不被客户窃取，而不能阻止合作开发程序的公司相互窃取对方的程序。
因此，目前需要本领域技术人员迫切解决的一个技术问题就是：提出一种MCU芯片的信息保护方案，用以保护程序不被客户窃取，同时保护合作开发程序的公司不能相互窃取对方的程序。
发明内容
本申请实施例所要解决的技术问题是提供一种MCU芯片的信息保护方法，用以保护程序不被客户窃取，同时保护合作开发程序的公司不能相互窃取对方的程序。
相应的，本申请实施例还提供了一种MCU芯片的信息保护装置，用以保证上述方法的实现及应用。
为了解决上述问题，本申请公开了一种MCU芯片的信息保护方法，所述MCU芯片包括指令总线、数据总线、闪存控制器和闪存用户区；所述闪存控制器用于将闪存用户区划分为第一分区和第二分区；所述的方法包括：
当所述指令总线访问所述闪存用户区时，判断所述指令总线是否访问所述第一分区；
若是，则进入第一分区工作状态；在所述第一分区工作状态下，允许所述指令总线访问所述闪存用户区，允许所述数据总线访问所述第一分区，但禁止所述数据总线访问所述第二分区；
当处于所述第一分区工作状态下，所述指令总线访问所述第二分区，则进入过渡状态；在所述过渡状态下，暂停所述指令总线访问所述闪存用户区，允许所述数据总线访问所述第一分区，但禁止所述数据总线访问所述第二分区；
判断处于所述过渡状态下的时间是否达到预设的等待时间；
若是，则进入第二分区工作状态；在所述第二分区工作状态下，允许所述指令总线访问所述闪存用户区，禁止所述数据总线访问所述第一分区，但允许所述数据总线访问所述第二分区。
优选地，所述方法还包括：
在所述MCU芯片复位后，进入初始状态；在所述初始状态下，允许所述指令总线访问所述闪存用户区，禁止所述数据总线访问所述第一分区和第二分区。
优选地，所述MCU芯片包括CPU，所述CPU为哈佛结构；所述预 设的等待时间与CPU的特性相关；若所述CPU为ARM Cortex-M3，则所述预设的等待时间为20个CPU时钟周期。
优选地，所述MCU芯片包括闪存信息区，所述闪存信息区包括选项字节；所述的方法还包括：
依据所述选项字节确定所述闪存用户区的读保护状态；
若为零级读保护状态，则允许对所述闪存用户区进行读取、写入和擦除；
若为一级读保护状态，则允许对所述第一分区进行读取、写入和擦除，仅在所述闪存用户区启动时允许对所述第二分区进行读取、写入和擦除；
若为二级读保护状态，则仅在所述闪存用户区启动时允许对所述第一分区和第二分区进行读取、写入和擦除。
优选地，
在所述零级读保护状态下，所述选项字节允许修改；
在所述一级读保护状态下，所述选项字节允许修改，若基于所述选项字节从所述一级读保护状态修改为零级读保护状态，则所述闪存用户区中的全部信息将被擦除；
在所述二级读保护状态下，所述选项字节禁止修改。
优选地，所述MCU芯片设计有私有设备，仅在输出有第一分区使能信号时正常工作的私有设备为第一设备，以及，仅在输出有第二分区使能信号时正常工作的私有设备为第二设备；所述方法还包括：
若处于所述第一分区工作状态，或者，第一分区过渡状态，则输出第一分区使能信号；若处于所述第二分区工作状态，或者，第二分区过渡状态，则输出第二分区使能信号。
优选地，所述设备包括静态随机存储器SRAM。
优选地，所述第一分区位于闪存用户区的前半段地址空间，所述第二分区位于闪存用户区的后半段地址空间。
本申请实施例还公开了一种MCU芯片的信息保护装置，所述MCU芯片包括指令总线、数据总线、闪存控制器和闪存用户区；所述闪存控制器用于将闪存用户区划分为第一分区和第二分区；所述的装置包括：
第一判断模块，配置为当所述指令总线访问所述闪存用户区时，判断所述指令总线是否访问所述第一分区；若是，则调用第一进入模块；
第一进入模块，配置为进入第一分区工作状态；在所述第一分区工作状态下，允许所述指令总线访问所述闪存用户区，允许所述数据总线访问所述第一分区，但禁止所述数据总线访问所述第二分区；
第二进入模块，配置为当处于所述第一分区工作状态下，所述指令总线访问所述第二分区，则进入过渡状态；在所述过渡状态下，暂停所述指令总线访问所述闪存用户区，允许所述数据总线访问所述第一分区，但禁止所述数据总线访问所述第二分区；
第二判断模块，配置为判断处于所述过渡状态下的时间是否达到预设的等待时间；若是，则调用第三进入模块；
第三进入模块，配置为进入第二分区工作状态；在所述第二分区工作状态下，允许所述指令总线访问所述闪存用户区，禁止所述数据总线访问所述第一分区，但允许所述数据总线访问所述第二分区。
优选地，所述装置还包括：
第四进入模块，配置为在所述MCU芯片复位后，进入初始状态；在所述初始状态下，允许所述指令总线访问所述闪存用户区，禁止所述数据总线访问所述第一分区和第二分区。
优选地，所述MCU芯片包括闪存信息区，所述闪存信息区包括选项字节；所述的装置还包括：
确定模块，配置为依据所述选项字节确定所述闪存用户区的读保护状态；
第一保护模块，配置为在为零级读保护状态时，允许对所述闪存用户区进行读取、写入和擦除；
第二保护模块，配置为在为一级读保护状态时，允许对所述第一分 区进行读取、写入和擦除，仅在所述闪存用户区启动时允许对所述第二分区进行读取、写入和擦除；
第三保护模块，配置为在为二级读保护状态时，仅在所述闪存用户区启动时允许对所述第一分区和第二分区进行读取、写入和擦除。
优选地，
在所述零级读保护状态下，所述选项字节允许修改；
在所述一级读保护状态下，所述选项字节允许修改，若基于所述选项字节从所述一级读保护状态修改为零级读保护状态，则所述闪存用户区中的全部信息将被擦除；
在所述二级读保护状态下，所述选项字节禁止修改。
优选地，所述MCU芯片设计有私有设备，仅在输出有第一分区使能信号有效时正常工作的私有设备为第一设备，以及，仅在输出有第二分区使能信号有效时正常工作的私有设备为第二设备；所述装置还包括：
第一输出模块，配置为在处于所述第一分区工作状态，或者，第一分区过渡状态时，输出第一分区使能信号；
第二输出模块，配置为在处于所述第二分区工作状态，或者，第二分区过渡状态时，输出第二分区使能信号。
本申请实施例还公开了一种在其上记录有用于执行权利要求1所述方法的程序的计算机可读记录介质。
与现有技术相比，本申请实施例包括以下优点：
在本申请实施例中，在MCU芯片中的闪存控制器将闪存用户区划分为第一分区和第二分区，当指令总线访问闪存用户区时，闪存用户区可以正常接受指令总线的访问，但是数据总线访问分区将受到限制。例如，当指令总线访问第一分区时，数据总线只能访问第一分区，不能访问第二分区。如果指令总线从访问第一分区转为访问第二分区，则暂停指令总线访问闪存用户区，并且在达到预设的等待时间时，指令总线又可以 访问闪存用户区，此时数据总线不能访问第一分区，只能访问第二分区。本申请实施例在指令总线访问闪存用户区时，只允许数据总线访问指令总线所访问的分区，可以保护在闪存用户区中的程序不被合作开发程序的其他公司窃取。
在本申请实施例中，还对MCU芯片设置有读保护级别，根据闪存信息区中的选项字节，确定该MCU芯片对闪存的读保护级别，限制对于闪存用户区的操作。在两家公司合作开发MCU芯片中的程序时，当某个公司开发完毕后，可以提高闪存用户区的读保护级别，以限制其他公司读取器烧录到闪存用户区的程序，从而避免合作开发程序的公司相互窃取对方的程序。此外，如果有人想通过降低读保护级别的方式去窃取获得访问闪存用户区的程序的权限，闪存用户区中的全部程序都将被擦除，进一步保护了公司的开发成果。
在本申请实施例中，可以将分区划分给不同合作开发的公司，并且可以将外围设备设计为某一分区的私有设备，每个分区具有对应的分区使能信号，而分区使能信号可以控制其所对应的私有设备。例如，根据分区使能信号，可以开启或关闭对应私有设备的部分或全部功能，避免了合作开发的公司所开发的程序运行的中间结果，被其他合作公司得到。
附图说明
图1是本申请的一种MCU芯片的信息保护方法实施例的步骤流程图；
图2是本申请的一种基于哈佛结构CPU的MCU芯片的系统结构示意图；
图3是本申请的一种MCU芯片闪存控制器的工作流程示意图；
图4是本申请的一种MCU芯片的信息保护装置实施例的结构框图。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本申请作进一步详细的说明。
下面介绍了本申请实施例的一种MCU芯片的信息保护方案。
通过闪存信息区的若干控制位来控制闪存控制器的读保护级别。闪存控制器的读保护级别分三级，各级别的特征如下：
零级读保护：闪存用户区完全开放，可以任意读、写和擦除。闪存信息区也一样完全开放。
一级读保护：从闪存用户区启动可以正常访问闪存用户区；其他启动方式(包括从其他位置启动以及JTAG(Joint Test Action Group，联合测试工作组))等调试手段均不能访问闪存用户区，读、写和擦除等操作都不行。在此级别下，可以访问闪存信息区，但如果修改控制位将闪存控制器的读保护级别改为零级，闪存用户区的内容会全部被擦除。
二级读保护：从闪存用户区启动可以正常访问闪存用户区；其他启动方式(包括从其他位置启动以及JTAG等调试手段)均不可用。在此级别下，闪存信息区只可读，不可写，也不可擦除。
在上述的MCU芯片的信息保护方案中，将闪存用户区作为一个整体来保护的。如果MCU芯片的程序完全由一家公司来开发，采用此方案可以满足需求。但随着MCU芯片应用日趋复杂，MCU芯片的程序会越来越复杂。将会有两家公司甚至多家公司合作开发程序的需求。而该MCU芯片信息保护方案是满足不了的。因为它只能保护闪存用户区的内容不被客户窃取，不能阻止合作开发程序的公司之间相互窃取对方的程序。基于这样的需求，本申请实施例进一步提出了一种MCU芯片的信息保护方案。
应用本申请实施例的MCU信息保护方案，可以满足两家公司合作开发MCU芯片程序的需求。本申请实施例将闪存用户区分为两个分区，合作开发程序的两家公司可分别将自己开发的程序烧写到属于自己的分区中。本申请实施例可以保证两家公司的程序之间既可以正常实现相互调用，又不能相互窃取对方分区中的程序，同时保护程序不被客户窃取。另外，如果SRAM和其他外围设备都由是合作的两家公司共享，程序有可能通过这些共享资源被合作方窃取。对此，本申请实施例还可以将特定SRAM或外围设备划分给某一方作为私有设备，扩宽了本申请实施例 的应用范围。
参照图1，示出了本申请的一种MCU芯片的信息保护方法实施例的步骤流程图，所述MCU芯片可以包括指令总线、数据总线、闪存控制器和闪存用户区；所述闪存控制器可以用于将闪存用户区划分为第一分区和第二分区；
参照图2所示的本申请的一种基于哈佛结构CPU的MCU芯片的系统结构示意图，MCU芯片通常包含CPU、总线、闪存、闪存控制器、SRAM、各种主设备和从设备(外围设备)等等。其中，所述总线可以包括指令总线、数据总线和系统总线。在具体实现中，CPU通过指令总线、数据总线和系统总线与总线互联矩阵相连。指令总线负责读取指令；数据总线负责数据访问；系统总线负责访问外围设备。
MCU芯片的闪存控制器是连接总线和闪存的桥梁。闪存控制器有同样的三条总线与总线互联矩阵相连，其中指令总线负责接受CPU的取指令访问；数据总线负责接受CPU的数据访问；它的配置寄存器是通过系统总线被访问的。SRAM以及各种外围设备都是连接在总线互联矩阵上的。在本申请实施例中，在两家公司合作开发MCU芯片的程序时，可以将两个分区分别划分给合作开发程序的两家公司，并且可以将外围设备设计为某一分区的私有设备，每个分区具有对应的分区使能信号，私有设备会受闪存控制器输出的分区使能信号控制。
在具体实现中，“访问”包含所有的操作。MCU芯片的总线有读操作和写操作，那么总线访问包含读操作和写操作。闪存有读操作、写操作和擦除操作，那么对闪存的访问就包含读操作、写操作和擦除操作。
所述的方法具体可以包括如下步骤：
步骤101，当所述指令总线访问所述闪存用户区时，判断所述指令总线是否访问所述第一分区；若是，则执行步骤102；
步骤102，进入第一分区工作状态；在所述第一分区工作状态下，允许所述指令总线访问所述闪存用户区，允许所述数据总线访问所述第一 分区，但禁止所述数据总线访问所述第二分区；
步骤103，当处于所述第一分区工作状态下，所述指令总线访问所述第二分区，则进入过渡状态；在所述过渡状态下，暂停所述指令总线访问所述闪存用户区，允许所述数据总线访问所述第一分区，但禁止所述数据总线访问所述第二分区；
步骤104，判断处于所述过渡状态下的时间是否达到预设的等待时间；若是，则执行步骤105；
步骤105，进入第二分区工作状态；在所述第二分区工作状态下，允许所述指令总线访问所述闪存用户区，禁止所述数据总线访问所述第一分区，但允许所述数据总线访问所述第二分区。
应用本申请实施例，至少具有如下两个优点：第一，保护闪存的内容不被终端客户窃取；第二，确保合作开发程序的两家公司不能相互窃取对方的程序。
合作开发程序的两家公司一定有一家是开发主程序的，另一家是开发库函数的。此处将开发主程序的公司称为第一公司，开发库函数的公司称为第二公司。两家公司对应的分区分别是第一分区和第二分区。第一分区位于前半段地址空间，第二分区位于后半段地址空间。这样便于MCU芯片启动时率先执行第一公司的程序。本申请实施例的MCU芯片信息保护的方法可以分为三部分来描述：第一部分是分区保护工作方式；第二部分是读保护级别的定义及使用方法；第三部分是私有设备的实现方法。前两部分是在闪存控制器中实现的；第三部分是根据闪存控制器输出的分区使能信号在私有设备中实现的。
第一部分：分区保护工作方式。
在闪存用户区启动时，闪存用户区可以正常接受CPU指令总线的访问，并可以受限制的接受CPU数据总线的访问，但不接受其他主设备的访问。参照图3所示的本申请的一种MCU芯片闪存控制器的工作流程示意图，具体的步骤如下所示：
1、MCU芯片复位，闪存控制器处于初始状态。在所述初始状态下， 指令总线可以访问所有分区，数据总线不能访问任何分区。
2、判断指令总线是否在访问闪存用户区；若是，则执行步骤3，若否，则返回步骤1。
3、判断指令总线访问的是否为第一分区；若是，则执行步骤4，若否，则执行步骤9。
4、进入第一分区工作状态。在所述第一分区工作状态下，指令总线可以访问所有分区，数据总线可以访问第一分区但不能访问第二分区(若访问第二分区，返回错误响应)。
5、判断指令总线是否在访问闪存用户区；若否，则返回步骤4，即如果指令总线没有访问闪存用户区，则保持在当前状态(第一分区工作状态)；若是，执行步骤6。
6、判断指令总线访问的是否为其他分区(第二分区)；如果指令总线访问的是当前工作的分区(第一分区)，保持当前状态，即返回步骤4，如果指令总线访问的是其他分区(第二分区)，则执行步骤7。
7、进入第一分区过渡状态。在所述第一分区过渡状态下，暂停响应指令总线，数据总线可以访问第一分区但不能访问第二分区(若访问第二分区，返回错误响应)。
8、在过渡状态下等待时间是否已到达预设的等待时间；若是，则执行步骤9；若否，则返回步骤7。
9、进入第二分区工作状态。在所述第二分区工作状态下，指令总线可以访问所有分区，数据总线可以访问第二分区但不能访问第一分区(访问第一分区，返回错误响应)。
10、判断指令总线是否在访问闪存用户区；若否，则返回步骤9，即如果指令总线没有访问闪存用户区，则保持在当前状态(第二分区工作状态)；若是，执行步骤11。
11、判断指令总线访问的是否为其他分区(第一分区)；如果指令总线访问的是当前工作的分区(第二分区)，保持当前状态，即返回步骤9，如果指令总线访问的是其他分区(第一分区)，则执行步骤12。
12、进入第二分区过渡状态。在所述第二分区过渡状态下，暂停响应指令总线，数据总线可以访问第二分区但不能访问第一分区(若访问第一分区，返回错误响应)。
13、在过渡状态下等待时间是否已到达预设的等待时间；若是，则执行步骤4；若否，则返回步骤12。
在本申请的具体应用的一种示例中，在过渡状态中的预设等待时间的长短与MCU芯片的CPU的特性相关。哈佛结构CPU通过指令总线读取指令，通过数据总线完成数据访问，两者是并行工作的。CPU通过指令总线取得要执行的指令，经过指令解析得出是否需要数据访问以及需要访问哪个地址的数据，然后通过数据总线完成相应数据访问。
从指令总线读取指令到数据总线完成相应数据访问要经过若干周期。过渡状态的作用就是在阻止针对其他分区的指令总线访问完成的同时，让之前针对当前工作分区的指令所对应的数据访问都完成，然后再跳转到新的工作分区。等待时间需足够长，以确保之前针对当前工作分区的指令所对应的数据访问都完成。以ARM Cortex-M3为例，等待时间可设置为20个CPU时钟周期。
第二部分：读保护级别的定义及使用方法。
在本申请的一种优选实施例中，所述MCU芯片可以包括闪存信息区，所述闪存信息区可以包括选项字节；所述的方法还可以包括如下步骤：
步骤S11，依据所述选项字节确定所述闪存用户区的读保护状态；
步骤S12，若为零级读保护状态，则允许对所述闪存用户区进行读取、写入和擦除；
步骤S13，若为一级读保护状态，则允许对所述第一分区进行读取、写入和擦除，仅在所述闪存用户区启动时允许对所述第二分区进行读取、写入和擦除；
步骤S14，若为二级读保护状态，则仅在所述闪存用户区启动时允许对所述第一分区和第二分区进行读取、写入和擦除。
在本申请的一种优选实施例中，其特征在于，
在所述零级读保护状态下，所述选项字节允许修改；
在所述一级读保护状态下，所述选项字节允许修改，若基于所述选项字节从所述一级读保护状态修改为零级读保护状态，则所述闪存用户区中的全部信息将被擦除(为确保闪存用户区的内容不被窃取，用户区内容擦除完毕之后，零级读保护才生效)。
在所述二级读保护状态下，所述选项字节禁止修改。
在具体实现中，读保护级别可以由闪存信息区中的若干字节来控制，这些字节为选项字节。在本申请实施例中对于控制的方法随意，只要能区分不同的读保护级别并且方便读保护级别之间的切换即可。例如，用1个字节来控制，当该字节的值为A5时，读保护状态为零级；当该字节的值为CC时，读保护级别为二级；当该字节为除A5和CC之外的其他值时，读保护级别为一级。
在MCU芯片程序的开发过程中，读保护级别的使用方法可以为如下所示。刚出厂的MCU芯片先交到第二公司，此时读保护级别为零级保护状态，闪存用户区是空的。第二公司将他们开发的程序烧写到闪存用户区的第二分区中。第二公司可以在零级读保护状态下调试程序。正式生产时，第二公司要在把芯片交给第一公司之前将读保护级别修改为一级读保护。第一公司将他们开发的程序烧写到闪存用户区的第一分区。此时，闪存用户区的第一分区存有第一公司的程序，第二分区存有第二公司的程序，读保护级别为一级读保护。第一公司要在此状态下完成两家公司程序的联合调试。正式生产时，第一公司要在把芯片交给客户之前将读保护级别修改为二级读保护。
第三部分：私有设备的实现方法。
在本申请的一种优选实施例中，所述MCU芯片可以根据特定需求设计私有设备，仅在输出有第一分区使能信号时正常工作的私有设备为第一设备，以及，仅在输出有第二分区使能信号时正常工作的私有设备为 第二设备；所述方法还可以包括如下步骤：
步骤S21，若处于所述第一分区工作状态，或者，第一分区过渡状态，则输出第一分区使能信号；
步骤S22，若处于所述第二分区工作状态，或者，第二分区过渡状态，则输出第二分区使能信号。
在本申请实施例中，私有设备是通过闪存控制器输出的分区使能信号控制的设备。每个分区可以对应1比特分区使能信号。分区使能信号表示对应分区处于工作状态。第一分区使能信号在第一分区工作状态和第一分区过渡状态下为1，其他状态下为0；第二分区使能信号在第二分区工作状态和第二分区过渡状态下为1，其他状态下为0。控制的方法就是根据特定分区使能信号的状态，开启或关闭相应设备的部分或全部功能。
例如，若想让某私有SRAM只允许第一公司的程序读，可以用第一分区使能信号来作为SRAM读通路的使能信号；若想让某私有设备的运算结果寄存器只允许第二公司的程序读，可以用第二分区使能信号来选通结果寄存器的读通路；若想让某私有设备只允许第一公司的程序配置，可以用第一分区使能信号来作为设备寄存器的配置使能信号。
当然，在实际中也可以不设计私有设备。比如全部的设备可以为共享，本申请实施例对此不加以限制。
需要说明的是，对于方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请实施例并不受所描述的动作顺序的限制，因为依据本申请实施例，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作并不一定是本申请实施例所必须的。
参照图4，示出了本申请的一种MCU芯片的信息保护装置实施例的结构框图，所述MCU芯片可以包括指令总线、数据总线、闪存控制器和 闪存用户区。所述闪存控制器用于将闪存用户区划分为第一分区和第二分区；具体可以包括如下模块：
第一判断模块201，配置为当所述指令总线访问所述闪存用户区时，判断所述指令总线是否访问所述第一分区；若是，则调用第一进入模块202；
第一进入模块202，配置为进入第一分区工作状态；在所述第一分区工作状态下，允许所述指令总线访问所述闪存用户区，允许所述数据总线访问所述第一分区，但禁止所述数据总线访问所述第二分区；
在本申请的一种优选实施例中，所述第一分区位于闪存用户区的前半段地址空间，所述第二分区位于闪存用户区的后半段地址空间。
第二进入模块203，配置为当处于所述第一分区工作状态下，所述指令总线访问所述第二分区，则进入过渡状态；在所述过渡状态下，暂停所述指令总线访问所述闪存用户区，允许所述数据总线访问所述第一分区，但禁止所述数据总线访问所述第二分区；
第二判断模块204，配置为判断处于所述过渡状态下的时间是否达到预设的等待时间；若是，则调用第三进入模块205；
第三进入模块205，配置为进入第二分区工作状态；在所述第二分区工作状态下，允许所述指令总线访问所述闪存用户区，禁止所述数据总线访问所述第一分区，但允许所述数据总线访问所述第二分区。
在本申请的一种优选实施例中，所述MCU芯片包括CPU，所述CPU为哈佛结构；所述预设的等待时间与CPU的特性相关；若所述CPU为ARM Cortex-M3，则所述预设的等待时间为20个CPU时钟周期。
在本申请的一种优选实施例中，所述装置还可以包括如下模块：
第四进入模块，配置为在所述MCU芯片复位后，进入初始状态；在所述初始状态下，允许所述指令总线访问所述闪存用户区，禁止所述数据总线访问所述第一分区和第二分区。
在本申请的一种优选实施例中，所述MCU芯片包括闪存信息区，所述闪存信息区包括选项字节；所述的装置还可以包括如下模块：
确定模块，配置为依据所述选项字节确定所述闪存用户区的读保护状态；
第一保护模块，配置为在为零级读保护状态时，允许对所述闪存用户区进行读取、写入和擦除；
第二保护模块，配置为在为一级读保护状态时，允许对所述第一分区进行读取、写入和擦除，仅在所述闪存用户区启动时允许对所述第二分区进行读取、写入和擦除；
第三保护模块，配置为在为二级读保护状态时，仅在所述闪存用户区启动时允许对所述第一分区和第二分区进行读取、写入和擦除。
在本申请的一种优选实施例中，
在所述零级读保护状态下，所述选项字节允许修改；
在所述一级读保护状态下，所述选项字节允许修改，若基于所述选项字节从所述一级读保护状态修改为零级读保护状态，则所述闪存用户区中的全部信息将被擦除；
在所述二级读保护状态下，所述选项字节禁止修改。
在本申请的一种优选实施例中，所述MCU芯片可以根据特定需求设计私有设备，仅在输出有第一分区使能信号时正常工作的私有设备为第一设备，以及，仅在输出有第二分区使能信号时正常工作的私有设备为第二设备；所述装置还包括：
第一输出模块，配置为在处于所述第一分区工作状态，或者，第一分区过渡状态时，输出第一分区使能信号；
第二输出模块，配置为在处于所述第二分区工作状态，或者，第二分区过渡状态时，输出第二分区使能信号。
在本申请的一种优选实施例中，所述外围设备可以包括静态随机存储器SRAM。
对于装置实施例而言，由于其与方法实施例基本相似，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
本申请实施例还提供了一种在其上记录有用于上述实施例的程序的计算机可读记录介质。
所述计算机可读记录介质包括用于以计算机(例如计算机)可读的形式存储或传送信息的任何机制。例如，机器可读介质包括只读存储器(ROM)、随机存取存储器(RAM)、磁盘存储介质、光存储介质、闪速存储介质、电、光、声或其他形式的传播信号(例如，载波、红外信号、数字信号等)等。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
本领域内的技术人员应明白，本申请实施例的实施例可提供为方法、装置、或计算机程序产品。因此，本申请实施例可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请实施例可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请实施例是参照根据本申请实施例的方法、终端设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理终端设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理终端设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理终端设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在 流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理终端设备上，使得在计算机或其他可编程终端设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程终端设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本申请实施例的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请实施例范围的所有变更和修改。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者终端设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者终端设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者终端设备中还存在另外的相同要素。
以上对本申请所提供的一种MCU芯片的信息保护方法和一种MCU芯片的信息保护装置，进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (14)

  1. 一种MCU芯片的信息保护方法，其特征在于，所述MCU芯片包括指令总线、数据总线、闪存控制器和闪存用户区；所述闪存控制器用于将闪存用户区划分为第一分区和第二分区；所述的方法包括：
    当所述指令总线访问所述闪存用户区时，判断所述指令总线是否访问所述第一分区；
    若是，则进入第一分区工作状态；在所述第一分区工作状态下，允许所述指令总线访问所述闪存用户区，允许所述数据总线访问所述第一分区，但禁止所述数据总线访问所述第二分区；
    当处于所述第一分区工作状态下，所述指令总线访问所述第二分区，则进入过渡状态；在所述过渡状态下，暂停所述指令总线访问所述闪存用户区，允许所述数据总线访问所述第一分区，但禁止所述数据总线访问所述第二分区；
    判断处于所述过渡状态下的时间是否达到预设的等待时间；
    若是，则进入第二分区工作状态；在所述第二分区工作状态下，允许所述指令总线访问所述闪存用户区，禁止所述数据总线访问所述第一分区，但允许所述数据总线访问所述第二分区。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    在所述MCU芯片复位后，进入初始状态；在所述初始状态下，允许所述指令总线访问所述闪存用户区，禁止所述数据总线访问所述第一分区和第二分区。
  3. 根据权利要求1所述的方法，其特征在于，所述MCU芯片包括CPU，所述CPU为哈佛结构；所述预设的等待时间与CPU的特性相关；若所述CPU为ARM Cortex-M3，则所述预设的等待时间为20个CPU时钟周期。
  4. 根据权利要求1所述的方法，其特征在于，所述MCU芯片包括闪存信息区，所述闪存信息区包括选项字节；所述的方法还包括：
    依据所述选项字节确定所述闪存用户区的读保护状态；
    若为零级读保护状态，则允许对所述闪存用户区进行读取、写入和 擦除；
    若为一级读保护状态，则允许对所述第一分区进行读取、写入和擦除，仅在所述闪存用户区启动时允许对所述第二分区进行读取、写入和擦除；
    若为二级读保护状态，则仅在所述闪存用户区启动时允许对所述第一分区和第二分区进行读取、写入和擦除。
  5. 根据权利要求4所述的方法，其特征在于，
    在所述零级读保护状态下，所述选项字节允许修改；
    在所述一级读保护状态下，所述选项字节允许修改，若基于所述选项字节从所述一级读保护状态修改为零级读保护状态，则所述闪存用户区中的全部信息将被擦除；
    在所述二级读保护状态下，所述选项字节禁止修改。
  6. 根据权利要求1所述的方法，其特征在于，所述MCU芯片设计有私有设备，仅在输出有第一分区使能信号时正常工作的私有设备为第一设备，以及，仅在输出有第二分区使能信号时正常工作的私有设备为第二设备；所述方法还包括：
    若处于所述第一分区工作状态，或者，第一分区过渡状态，则输出第一分区使能信号；若处于所述第二分区工作状态，或者，第二分区过渡状态，则输出第二分区使能信号。
  7. 根据权利要求6所述的方法，其特征在于，所述设备包括静态随机存储器SRAM。
  8. 根据权利要求1所述的方法，其特征在于，所述第一分区位于闪存用户区的前半段地址空间，所述第二分区位于闪存用户区的后半段地址空间。
  9. 一种MCU芯片的信息保护装置，其特征在于，所述MCU芯片包括指令总线、数据总线、闪存控制器和闪存用户区；所述闪存控制器用于将闪存用户区划分为第一分区和第二分区；所述的装置包括：
    第一判断模块，配置为当所述指令总线访问所述闪存用户区时，判断所述指令总线是否访问所述第一分区；若是，则调用第一进入模块；
    第一进入模块，配置为进入第一分区工作状态；在所述第一分区工作状态下，允许所述指令总线访问所述闪存用户区，允许所述数据总线访问所述第一分区，但禁止所述数据总线访问所述第二分区；
    第二进入模块，配置为当处于所述第一分区工作状态下，所述指令总线访问所述第二分区，则进入过渡状态；在所述过渡状态下，暂停所述指令总线访问所述闪存用户区，允许所述数据总线访问所述第一分区，但禁止所述数据总线访问所述第二分区；
    第二判断模块，配置为判断处于所述过渡状态下的时间是否达到预设的等待时间；若是，则调用第三进入模块；
    第三进入模块，配置为进入第二分区工作状态；在所述第二分区工作状态下，允许所述指令总线访问所述闪存用户区，禁止所述数据总线访问所述第一分区，但允许所述数据总线访问所述第二分区。
  10. 根据权利要求9所述的装置，其特征在于，所述装置还包括：
    第四进入模块，配置为在所述MCU芯片复位后，进入初始状态；在所述初始状态下，允许所述指令总线访问所述闪存用户区，禁止所述数据总线访问所述第一分区和第二分区。
  11. 根据权利要求9所述的装置，其特征在于，所述MCU芯片包括闪存信息区，所述闪存信息区包括选项字节；所述的装置还包括：
    确定模块，配置为依据所述选项字节确定所述闪存用户区的读保护状态；
    第一保护模块，配置为在为零级读保护状态时，允许对所述闪存用户区进行读取、写入和擦除；
    第二保护模块，配置为在为一级读保护状态时，允许对所述第一分区进行读取、写入和擦除，仅在所述闪存用户区启动时允许对所述第二分区进行读取、写入和擦除；
    第三保护模块，配置为在为二级读保护状态时，仅在所述闪存用户 区启动时允许对所述第一分区和第二分区进行读取、写入和擦除。
  12. 根据权利要求11所述的装置，其特征在于，
    在所述零级读保护状态下，所述选项字节允许修改；
    在所述一级读保护状态下，所述选项字节允许修改，若基于所述选项字节从所述一级读保护状态修改为零级读保护状态，则所述闪存用户区中的全部信息将被擦除；
    在所述二级读保护状态下，所述选项字节禁止修改。
  13. 根据权利要求9所述的装置，其特征在于，所述MCU芯片设计有私有设备，仅在输出有第一分区使能信号有效时正常工作的私有设备为第一设备，以及，仅在输出有第二分区使能信号有效时正常工作的私有设备为第二设备；所述装置还包括：
    第一输出模块，配置为在处于所述第一分区工作状态，或者，第一分区过渡状态时，输出第一分区使能信号；
    第二输出模块，配置为在处于所述第二分区工作状态，或者，第二分区过渡状态时，输出第二分区使能信号。
  14. 一种在其上记录有用于执行权利要求1所述方法的程序的计算机可读记录介质。
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