WO2016101739A1 - 一种多路以太网到多路e1信道的适配方法和系统 - Google Patents

一种多路以太网到多路e1信道的适配方法和系统 Download PDF

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WO2016101739A1
WO2016101739A1 PCT/CN2015/095086 CN2015095086W WO2016101739A1 WO 2016101739 A1 WO2016101739 A1 WO 2016101739A1 CN 2015095086 W CN2015095086 W CN 2015095086W WO 2016101739 A1 WO2016101739 A1 WO 2016101739A1
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channel
configuration table
buffer
flow control
data
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PCT/CN2015/095086
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French (fr)
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刘兆先
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邦彦技术股份有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/30—Flow control; Congestion control in combination with information about buffer occupancy at either end or at transit nodes

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  • the present invention relates to the field of data communications, and in particular, to a multi-channel communication protocol conversion method, and to a multi-channel communication protocol conversion system.
  • the European 30-channel pulse code modulation PCM is referred to as E1, and the rate is 2.048 Mbit/s.
  • the time slot CH0 is used for frame synchronization
  • the time slot CH16 is used for transmitting signaling
  • the remaining 30 time slots of CH1 to CH15 and CH17 to CH31 are used for 30 voice channels.
  • Each time slot transmits 8 bits, so 256 bits are shared. It transmits 8000 frames per second, that is, the frame period is 125us. As shown in Figure 1.
  • Ethernet is the main LAN technology used in today's TCP/IP.
  • the Ethernet frame is encapsulated in the data link layer, and the network layer packet is added with a frame header and a frame tail to become a data frame (framing) that can be identified by the data link layer.
  • the number of bytes used for the header and the end of the frame is fixed, the length of the Ethernet frame varies depending on the size of the encapsulated packet. The range is 64 to 1518 bytes (not counting 8 words). The leading word of the section). As shown in the table below.
  • the Ethernet does not need to transmit through the E1 channel during the adaptation with the E1 channel.
  • E1 channel adaptation Ethernet is based on single-channel Ethernet and does not support dynamic configuration of multiple Ethernet
  • an object of the present invention is to provide an adaptation method of an Ethernet to E1 channel that supports multi-channel adaptation, has flow control, and can be flexibly configured.
  • an object of the present invention is to provide an adaptation system that supports multi-channel adaptation, traffic control, and flexible configuration of an Ethernet to E1 channel.
  • a method for adapting a multi-channel Ethernet to a multi-channel E1 channel comprising the steps of: S1, a flow control step, controlling each IP according to the fixed bandwidth of each E1 channel, the flow control configuration table, and the content of the E1 bundle configuration table
  • the data traffic of the interface; the S1, E1 bundling step, and the data traffic of each E1 channel is controlled according to the content of the E1 bundling configuration table
  • the content of the flow control configuration table includes the correspondence between the IP address, the port, and the guaranteed bandwidth
  • the content of the bundle configuration table includes the correspondence between the IP interface and the E1 channel.
  • the step S1 specifically includes the sub-steps: S11, extracting the data packet information; S12, comparing the extracted data packet information with the flow control configuration table one by one, if there is the same item, proceeding to step S13, if the same item does not exist Then proceeds to step S18; S13, it is determined whether the corresponding guaranteed bandwidth is used up, if yes, proceeds to step S14, if otherwise proceeds to step S17; S14, determines whether the remaining bandwidth is used up, if yes, proceeds to step S15, if otherwise proceeds to step S16; S15, discarding the data packet; S16, storing the data packet in the low priority buffer; S17, storing the data packet in the high priority buffer; S18, determining whether the remaining bandwidth is used up; if yes, proceeding to step S15, if Otherwise, it proceeds to step S16.
  • the step S2 specifically includes the sub-steps: S21, the data packet received from the IP interface is first stored in the IP receiving buffer; S22, the data packet is read out from the IP receiving buffer, and the configuration table is bound according to the E1.
  • the content distributes the data packet to the corresponding E1 channel; S23, the data packet is stored in the E1 transmission buffer for subsequent processing; and S24, the data packet received from the E1 channel is first stored in the E1 receiving buffer; S25, The data packet is read out in the E1 receiving buffer, and the data packet is aggregated to the corresponding IP interface according to the content of the E1 binding configuration table; in S26, the data packet is stored in the IP sending buffer for subsequent processing.
  • the step S3 further includes the sub-step: S27, monitoring the data traffic of each E1 channel, controlling the distribution of the data packets, so that the data traffic of each E1 channel is consistent; S28, when the IP address in the E1 binding configuration table is When the mapping between the interface and the E1 channel conflicts, the mapping with the lowest value of the IP interface number is valid.
  • An adaptation system for a multi-path Ethernet to multi-channel E1 channel which is used to implement a multi-path Ethernet to multi-channel E1 channel adaptation method, which includes: multiple IP interfaces;
  • the E1 channel is configured to control the data traffic of each IP interface according to the fixed bandwidth of the E1 channel, the flow control configuration table, and the content of the E1 binding configuration table.
  • the E1 bundling module is configured to bind the configuration table according to the E1.
  • the content controls data exchange between the E1 channel and the IP interface; the plurality of IP interfaces are sequentially connected to the plurality of E1 channels through the flow control unit and the E1 bundling unit.
  • the flow control module includes: an input buffer, configured to receive a data packet from the IP interface; and a data processing control sub-module, configured to control the data packet transmission to a high priority area and a low priority according to the flow control configuration table. Buffer or discard; high priority buffer; low priority buffer; output buffer for prioritizing the output of packets from the high priority buffer and then outputting packets from the low priority buffer.
  • the E1 bundling module includes: an IP transceiver buffer for connecting an IP interface; and a switch matrix for controlling data exchange between the E1 channel and the IP interface according to the content of the E1 bundling configuration table; Used to connect to the E1 channel.
  • the E1 bundling module further includes a traffic monitoring sub-module, configured to monitor data traffic of each E1 channel, and control data packet distribution, so that data traffic of each E1 channel is consistent.
  • a traffic monitoring sub-module configured to monitor data traffic of each E1 channel, and control data packet distribution, so that data traffic of each E1 channel is consistent.
  • the flow control module and the E1 bundle module are implemented by using an FPGA chip.
  • it further comprises a CPU for configuring the flow control configuration table and the E1 bundle configuration table, the FPGA chip having a CPU interface, the CPU interface being connected to the CPU.
  • the invention relates to a method for adapting multiple Ethernet to multiple E1 channels, and the Ethernet data Adapted to E1 channel transmission, realizes transparent transmission of IP datagrams on E1 channel, realizes dynamic configuration of bandwidth through bundle of E1 channels, realizes high-speed to low-speed flow control through IP flow control, and bandwidth guarantee of configurable important data, and solves The following questions:
  • the invention is based on FPGA implementation, has a short design cycle, a wide selection range and low cost.
  • the invention can be widely applied to various Ethernet to E1 channel adaptation systems.
  • the adapting system of the multi-channel Ethernet to the multi-channel E1 channel adapts the Ethernet data to the E1 channel transmission, realizes the transparent transmission of the IP datagram by the E1 channel, realizes the dynamic configuration of the bandwidth through the bundle of the E1 channel, and passes the IP.
  • Flow control enables high-speed to low-speed flow control and configurable bandwidth guarantees for important data, solving the following problems:
  • the invention is based on FPGA implementation, has a short design cycle, wide selection range, and cost low.
  • the invention can be widely applied to various Ethernet to E1 channel adaptation systems.
  • FIG. 1 is a schematic structural diagram of an E1 channel frame
  • FIG. 2 is a system structural diagram of an embodiment of the system of the present invention.
  • FIG. 3 is a schematic diagram showing the hardware structure connection of an embodiment of the system of the present invention.
  • FIG. 4 is a schematic structural diagram of an embodiment of a flow control module of the present invention.
  • FIG. 5 is a schematic structural diagram of an embodiment of an E1 binding module of the present invention.
  • an adaptation system of multiple Ethernet to multiple E1 channels includes: multiple IP interfaces; multiple E1 channels; and a flow control module for using a fixed bandwidth of each E1 channel,
  • the flow control configuration table and the content of the E1 bundle configuration table control the data traffic of each IP interface;
  • the E1 bundle module is configured to control data exchange between the E1 channel and the IP interface according to the content of the E1 bundle configuration table;
  • the multiple IPs The interface is connected to multiple E1 channels through the flow control unit and the E1 bundling unit in sequence.
  • multiple IP interfaces are sequentially connected to multiple E1 channels through IP transceiver buffering, filtering, flow control module, E1 bundling module, protocol conversion module, and E1 transceiving buffer.
  • the data packet For data packets received from the IP port, first stored in the IP transceiver buffer, the data packet is After the data packet is filtered, it is submitted to the flow control module.
  • the flow control module controls the flow of the data packet according to the content of the flow control configuration table, and then submits it to the E1 bundle module.
  • the E1 bundle module distributes the data packet to the corresponding protocol according to the content of the E1 bundle configuration table.
  • the conversion module, the protocol conversion module converts the IP data packet of the data packet into an E1 frame format, and submits it to the E1 transceiver buffer, and the E1 transceiver buffer sends the data according to the timing requirement of the E1.
  • the data received from the E1 interface is first stored in the E1 transceiver buffer and then submitted to the protocol conversion module.
  • the protocol conversion module assembles the E1 frame of the data into an IP data packet and submits it to the E1 bundle module.
  • the E1 bundle module is based on E1.
  • the bundle configuration table content merges the data packets of the corresponding E1 channel onto the Ethernet interface, and then submits the data packet to the IP transceiver buffer, and the IP transceiver buffer sends the data packet.
  • the flow control module and the E1 bundle module are implemented by using an FPGA chip.
  • the FPGA chip further includes a CPU interface, a flow control configuration table, an E1 bundle configuration table, a control register, a clock and a reset module, an IP transceiver buffer, a filter, a protocol conversion module, and an E1 transceiver buffer.
  • the CPU interface is externally connected with a CPU
  • the IP transceiver buffer is externally connected with an Ethernet interface chip having multiple IP interfaces.
  • the E1 transceiver buffer is externally connected with an E1 interface chip having multiple E1 channels.
  • the CPU interface is based on the CPU's BUS bus read and write timing, and realizes the interface of the CPU to operate the FPGA internal storage unit through the BUS bus. Assign a fixed address to map out the FPGA internal memory locations for read and write operations.
  • the CPU interface can be modified according to the interface requirements of different CPUs.
  • the traffic configuration table, the E1 bundle configuration table, and the control registers are all configured by an external CPU.
  • the control registers are used to implement control and status monitoring of each functional module.
  • the traffic configuration table and the E1 bundle configuration table are used to implement flow control and E1. Bundled.
  • the flow control configuration table can be configured as follows:
  • the E1 bundle configuration table can be configured as follows:
  • Offset address (address by byte) content Read and write Remarks 0x0 Bundled Ethernet interface number Rw E1 interface 1 0x02 Bundled Ethernet interface number Rw E1 interface 2 0x04 Bundled Ethernet interface number Rw E1 interface 3 0x06 Bundled Ethernet interface number Rw E1 interface 4 0x08 Bundled Ethernet interface number Rw E1 interface 5 0x0A Bundled Ethernet interface number Rw E1 interface 6 0x0C Bundled Ethernet interface number Rw E1 interface 7 0x0E Bundled Ethernet interface number Rw E1 interface 8
  • the clock and reset module is mainly to generate the clock required by the logic and generate the correct reset signal.
  • the clock logic section eliminates duty cycle distortion of the external input clock and reduces clock jitter.
  • the IP transceiver buffer is used to receive data packets from the IP interface and to send data packets received from E1 to the Ethernet interface. Since in most cases, the data bandwidth of the Ethernet interface is much larger than the data bandwidth of the E1 channel, another important role of the IP transceiver buffer is data buffering.
  • the packet filtering module is used to implement Ethernet packet filtering, because in most cases, the data bandwidth of the IP interface is much larger than the data bandwidth of the E1 channel; in an Ethernet network, there are usually a large number of data packets unrelated to the actual application. . Therefore, packet filtering is used to filter out the data packets unrelated to the application, thereby improving the effective communication bandwidth of the E1 channel.
  • the flow control module includes: an input buffer, configured to receive a data packet from the IP interface; and a data processing control sub-module, configured to control the data packet transmission to a high priority area and a low priority according to the flow control configuration table. Buffer or discard; high priority buffer; low priority buffer; output buffer for prioritizing the output of packets from the high priority buffer and then outputting packets from the low priority buffer.
  • the output buffer is also connected to the data processing control sub-module through flow control, and the data processing control sub-module can control the flow according to the information fed back from the output buffer.
  • the principle of the flow control module is shown in Figure 4. Since the data bandwidth of each E1 channel is fixed, the flow control module can calculate the guaranteed bandwidth according to the fixed bandwidth, IP flow control configuration table and E1 binding configuration table contents of each E1 channel. Information such as remaining bandwidth.
  • the flow control module caches the input data packet, then reads out and parses the data packet from the cache, and extracts information such as source IP and source port (frame header information extraction).
  • the flow control module compares the extracted data packet information with the flow control configuration table table entry one by one. If there is the same item, it determines whether the guaranteed bandwidth is used up. If the bandwidth is used up, it determines whether the remaining bandwidth is used up. If the remaining bandwidth is used up, if the remaining bandwidth is used up, The packet is discarded, and if there is remaining bandwidth, the packet is stored in the low priority buffer; if the traffic is not used up, the packet is stored in the high priority buffer; if there is no identical item, the remaining bandwidth is determined. Whether it is used up, the packet is discarded if the remaining bandwidth is used up, and the packet is stored in the low priority buffer if there is remaining bandwidth.
  • the output buffer preferentially transmits packets of the high priority buffer, and the packets of the low priority buffer are sent when the high priority buffer has no transmittable data.
  • the traffic statistics interval can be set to 1S, and all traffic statistics are cleared at the beginning of each second.
  • the E1 bundling module includes: an IP transceiver buffer for connecting an IP interface; and a switch matrix for controlling data exchange between the E1 channel and the IP interface according to the content of the E1 bundling configuration table; Used to connect to the E1 channel.
  • the E1 bundling module further includes a traffic monitoring sub-module, configured to monitor data traffic of each E1 channel, and control data packet distribution, so that data traffic of each E1 channel is consistent.
  • a traffic monitoring sub-module configured to monitor data traffic of each E1 channel, and control data packet distribution, so that data traffic of each E1 channel is consistent.
  • the principle of the E1 bundling module is shown in Figure 5.
  • the E1 bundling module calculates the number of E1 channels and total data traffic bundled on each IP interface based on the E1 bundling configuration table.
  • the E1 bundling module caches the data packets input by the IP interface, and then reads out the data packets from the receive buffer, and distributes the contents according to the E1 bundle configuration table to the E1 channel, and the data packets are distributed in units of IP packets.
  • Each E1 sending interface is configured with a traffic counter, and the switching module is always forwarded to the E1 channel with the lowest traffic value. When all flow counter values exceed the set threshold, all flow counter values are subtracted from the threshold to prevent the flow counter from overflowing.
  • the distribution of the data packets is controlled, so that the data traffic of each E1 channel is consistent, and the traffic equalization is achieved.
  • the final packet will be stored in the E1 send buffer for subsequent processing.
  • the data packet received from the E1 channel it is first stored in the E1 receiving buffer, and then the data packet is read out from the receiving buffer according to the content of the E1 binding configuration table, and is aggregated to the IP interface through the switching matrix, and the aggregation of the data packet is also in the IP packet. unit.
  • the final packet will be stored in the Ethernet send buffer for subsequent processing.
  • the IP interface number is the most The low bundle interface is valid.
  • the protocol conversion module includes an IPoE1 module and an E1oIP module.
  • the IPoE1 module is used to distribute IP packets in bytes to the E1 time slot and add the necessary header and trailer delimiters.
  • the E1oIP module is used to receive data from the E1 time slot in bytes, and then extract the complete IP data packet according to the header and the end of the packet.
  • the E1 transceiver buffer module is configured to receive data from the E1 channel according to the E1 time slot timing requirement and transmit the IP data to the E1 channel according to the E1 slot tempo.
  • the adapting system of the multi-channel Ethernet to the multi-channel E1 channel adapts the Ethernet data to the E1 channel transmission, realizes the transparent transmission of the IP datagram by the E1 channel, realizes the dynamic configuration of the bandwidth through the bundle of the E1 channel, and passes the IP.
  • Flow control enables high-speed to low-speed flow control and configurable bandwidth guarantees for important data, solving the following problems:
  • the invention is based on FPGA implementation, has a short design cycle, a wide selection range and low cost.
  • the invention can be widely applied to various Ethernet to E1 channel adaptation systems.
  • a method for adapting a multi-channel Ethernet to a multi-channel E1 channel comprising the steps of: S1, a flow control step, controlling each IP according to the fixed bandwidth of each E1 channel, the flow control configuration table, and the content of the E1 bundle configuration table
  • the data traffic of the interface; the S1, E1 bundling step, and the data traffic of each E1 channel is controlled according to the content of the E1 bundling configuration table
  • the content of the flow control configuration table includes the correspondence between the IP address, the port, and the guaranteed bandwidth
  • the content of the bundle configuration table includes the correspondence between the IP interface and the E1 channel.
  • the step S1 specifically includes the sub-steps: S11, extracting the data packet information; S12, comparing the extracted data packet information with the flow control configuration table one by one, if there is the same item, proceeding to step S13, if the same item does not exist Then proceeds to step S18; S13, it is determined whether the corresponding guaranteed bandwidth is used up, if yes, proceeds to step S14, if otherwise proceeds to step S17; S14, determines whether the remaining bandwidth is used up, if yes, proceeds to step S15, if otherwise proceeds to step S16; S15, discarding the data packet; S16, storing the data packet in the low priority buffer; S17, storing the data packet in the high priority buffer; S18, determining whether the remaining bandwidth is used up; if yes, proceeding to step S15, if Otherwise, it proceeds to step S16.
  • the step S2 specifically includes the sub-steps: S21, the data packet received from the IP interface is first stored in the IP receiving buffer; S22, the data packet is read out from the IP receiving buffer, and the configuration table is bound according to the E1.
  • the content distributes the data packet to the corresponding E1 channel; S23, the data packet is stored in the E1 transmission buffer for subsequent processing; and S24, the data packet received from the E1 channel is first stored in the E1 receiving buffer; S25, The data packet is read out in the E1 receiving buffer, and the data packet is aggregated to the corresponding IP interface according to the content of the E1 binding configuration table; in S26, the data packet is stored in the IP sending buffer for subsequent processing.
  • the step S3 further comprises the sub-step: S27, monitoring each E1 channel The data traffic is controlled to distribute the data packets so that the data traffic of each E1 channel is consistent.
  • S28 when the mapping between the IP interface and the E1 channel in the E1 binding configuration table conflicts, the mapping relationship with the lowest IP interface number is valid.
  • the working principle of the multi-path Ethernet to multi-channel E1 channel adaptation method of the present invention corresponds to a multi-channel Ethernet to multi-channel E1 channel adaptation system, which will not be described here.
  • a multi-channel Ethernet to multi-channel E1 channel adaptation system adapts Ethernet data to E1 channel transmission, implements E1 channel transparent transmission of IP datagrams, implements dynamic configuration of bandwidth through bundle of E1 channels, and controls IP traffic. Achieving high-speed to low-speed flow control and configurable bandwidth guarantees for important data solves the following problems:
  • the invention is based on FPGA implementation, has a short design cycle, a wide selection range and low cost.
  • the invention can be widely applied to various Ethernet to E1 channel adaptation systems.

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Abstract

本发明公开了一种多路以太网到多路E1信道的适配方法和系统。方法包括流量控制步骤和E1捆绑步骤；系统包括多个IP接口、多个E1信道、流量控制模块和E1捆绑模块。本发明将以太网数据适配到E1信道传输，实现E1信道透明传输IP数据报，通过E1通道的捆绑实现带宽的动态配置，通过IP流量控制实现高速到低速的流量控制以及可配置的重要数据的带宽保证。本发明可广泛应用于各种以太网到E1信道的适配系统。

Description

一种多路以太网到多路E1信道的适配方法和系统 技术领域
本发明涉及数据通信领域，尤其涉及一种多路通信协议转换方法，本发明还涉及一种多路通信协议转换系统。
背景技术
随着互联网的迅速发展，应用日益广泛，各种数字综合业务层出不穷，而IP也成为综合业务通信的主要协议。如何利用现有的网络资源组建IP网络(以太网)一直是近年来研究的热点。E1和IP的适配和融合就是其中重要的一方面。
欧洲的30路脉码调制PCM简称E1，速率是2.048Mbit/s。E1的一个时分复用帧(其长度T＝125us)共划分为32相等的时隙，时隙的编号为CH0～CH31。其中时隙CH0用作帧同步，时隙CH16用来传送信令，剩下CH1～CH15和CH17～CH31共30个时隙用作30个话路。每个时隙传送8bit，因此共用256bit。每秒传送8000个帧，即帧周期为125us。如图1所示。
以太网是当今TCP/IP采用的主要的局域网技术。以太网的帧是数据链路层的封装，网络层的数据包被加上帧头和帧尾成为可以被数据链路层识别的数据帧(成帧)。虽然帧头和帧尾所用的字节数是固定不变的，但依被封装的数据包大小的不同，以太网帧的长度也在变化，其范围是64～1518字节(不算8字节的前导字)。如下表所示。
前序(P) 目的地址 源地址 类型 数据 FCS
  (SD) (SA) (TYPE)    
8B 6B 6B 2B 46～1500B 4B
由于IEEE802.3规定的前序字节部分是固定值，所以以太网在和E1信道适配过程中不需要经过E1信道传输。
但是目前E1信道适配以太网存在以下问题：
(1)E1信道适配以太网都是基于单路以太网，不支持多路以太网的动态配置；
(2)没有流量控制或者控制方式简单，不能对重要数据预留带宽，保证重要数据的可靠传输；
(3)需要采用专业转换芯片，不能灵活的配置，不适合实现大规模多通道的E1承载IP设计。
发明内容
为了解决上述技术问题，本发明的目的是提供一种支持多路适配、具有流量控制、可灵活配置的以太网到E1信道的适配方法。
为了解决上述技术问题，本发明的目的是提供一种支持多路适配、具有流量控制、可灵活配置的以太网到E1信道的适配系统。
本发明所采用的技术方案是：
一种多路以太网到多路E1信道的适配方法，其包括步骤：S1，流量控制步骤，根据每路E1信道的固定带宽、流量控制配置表及E1捆绑配置表的内容控制每路IP接口的数据流量；S2，E1捆绑步骤，根据E1捆绑配置表的内容控制每路E1信道的数据流量；所述流量控制配置表的内容包括IP地址、端口和保证带宽的对应关系；所述E1 捆绑配置表的内容包括IP接口和E1信道的对应关系。
优选的，所述步骤S1具体包括子步骤：S11，提取数据包信息；S12，将提取的数据包信息与流量控制配置表逐一进行比较，如果存在相同项则进入步骤S13，如果不存在相同项则进入步骤S18；S13，判断对应保证带宽是否用完，如果是则进入步骤S14，如果否则进入步骤S17；S14，判断剩余带宽是否用完，如果是则进入步骤S15，如果否则进入步骤S16；S15，将数据包丢弃；S16，将数据包存入低优先级缓冲区；S17，将数据包存入高优先级缓冲区；S18，判断剩余带宽是否用完，如果是则进入步骤S15，如果否则进入步骤S16。
优选的，所述步骤S2具体包括子步骤：S21，将从IP接口接收的数据包，先存入IP接收缓冲区；S22，从IP接收缓冲区中读出数据包，根据E1捆绑配置表的内容将数据包分发到对应的E1信道；S23，将数据包存入E1发送缓冲区，供后续处理；S24，将从E1信道上接收的数据包，先存入E1接收缓冲区；S25，从E1接收缓冲区中读出数据包，根据E1捆绑配置表内容将数据包汇聚到对应的IP接口；S26，将数据包存入IP发送缓冲区，供后续处理。
优选的，所述步骤S3还包括子步骤：S27，监控每路E1信道的数据流量，对数据包的分发进行控制，使每路E1信道的数据流量一致；S28，当E1捆绑配置表中IP接口和E1信道对应关系冲突时，IP接口号数值最低的对应关系有效。
一种多路以太网到多路E1信道的适配系统,其用于实施一种多路以太网到多路E1信道的适配方法，其包括：多个IP接口；多个 E1信道；流量控制模块，用于根据每路E1信道的固定带宽、流量控制配置表及E1捆绑配置表的内容控制每路IP接口的数据流量；E1捆绑模块，用于根据E1捆绑配置表的内容控制E1信道和IP接口之间的数据交换；所述多个IP接口依次通过流量控制单元和E1捆绑单元连接到多个E1信道。
优选的，所述流量控制模块包括：输入缓冲区，用于接收来自IP接口的数据包；数据处理控制子模块，用于根据流量控制配置表控制数据包传输到高优先级区、低优先级缓冲区或丢弃；高优先级缓冲区；低优先级缓冲区；输出缓冲区，用于优先输出来自高优先级缓冲区的数据包，再输出来自低优先级缓冲区的数据包。
优选的，所述E1捆绑模块包括：IP收发缓冲区，用于连接IP接口；交换矩阵，用于根据E1捆绑配置表的内容控制E1信道和IP接口之间的数据交换；E1收发缓冲区，用于连接E1信道。
优选的，所述E1捆绑模块还包括流量监控子模块，用于监控每路E1信道的数据流量，对数据包的分发进行控制，使每路E1信道的数据流量一致。
优选的，所述流量控制模块和E1捆绑模块均采用FPGA芯片实现。
优选的，其还包括用于对流量控制配置表和E1捆绑配置表进行配置的CPU，所述FPGA芯片具有CPU接口，所述CPU接口与CPU连接。
本发明的有益效果是：
本发明一种多路以太网到多路E1信道的适配方法将以太网数据 适配到E1信道传输，实现E1信道透明传输IP数据报，通过E1通道的捆绑实现带宽的动态配置，通过IP流量控制实现高速到低速的流量控制以及可配置的重要数据的带宽保证，解决了以下多个问题：
1、解决了多网络环境下，多路以太网到多路E1信道不能动态配置的问题；
2、解决了在有限的带宽环境下，不能提供重要数据可靠传输服务的问题；
3、解决了在不同应用场景下，设计改动大，配置不灵活的问题。
另外，本发明基于FPGA实现，设计周期短，选型范围广，费用低。
本发明可广泛应用于各种以太网到E1信道的适配系统。
本发明的另一个有益效果是：
本发明一种多路以太网到多路E1信道的适配系统将以太网数据适配到E1信道传输，实现E1信道透明传输IP数据报，通过E1通道的捆绑实现带宽的动态配置，通过IP流量控制实现高速到低速的流量控制以及可配置的重要数据的带宽保证，解决了以下多个问题：
1、解决了多网络环境下，多路以太网到多路E1信道不能动态配置的问题；
2、解决了在有限的带宽环境下，不能提供重要数据可靠传输服务的问题；
3、解决了在不同应用场景下，设计改动大，配置不灵活的问题。
另外，本发明基于FPGA实现，设计周期短，选型范围广，费用 低。
本发明可广泛应用于各种以太网到E1信道的适配系统。
附图说明
下面结合附图对本发明的具体实施方式作进一步说明：
图1是E1信道帧结构示意图；
图2是本发明系统一种实施例的系统结构图；
图3是本发明系统一种实施例的硬件结构连接示意图；
图4是本发明流量控制模块一种实施例的结构原理示意图；
图5是本发明E1捆绑模块一种实施例的结构原理示意图。
具体实施方式
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
如图2所示，一种多路以太网到多路E1信道的适配系统,其包括：多个IP接口；多个E1信道；流量控制模块，用于根据每路E1信道的固定带宽、流量控制配置表及E1捆绑配置表的内容控制每路IP接口的数据流量；E1捆绑模块，用于根据E1捆绑配置表的内容控制E1信道和IP接口之间的数据交换；所述多个IP接口依次通过流量控制单元和E1捆绑单元连接到多个E1信道。
该实施例中，多个IP接口依次经过IP收发缓冲、过滤、流量控制模块、E1捆绑模块、协议转换模块和E1收发缓冲连接到多个E1信道。
对于从IP端口上接收的数据包，先存入IP收发缓冲，数据包经 过数据包过滤后提交给流量控制模块，流量控制模块根据流量控制配置表内容对数据包进行流量控制，然后提交给E1捆绑模块，E1捆绑模块根据E1捆绑配置表内容将数据包分发到相应协议转换模块，协议转换模块将数据包的IP数据报文转换为E1帧格式，并提交给E1收发缓冲，E1收发缓冲按照E1的时序要求将数据发送出去。
对于从E1接口上接收的数据，先存入E1收发缓冲，然后提交给协议转换模块，协议转换模块将数据的E1帧组装成IP数据报文，并提交给E1捆绑模块，E1捆绑模块根据E1捆绑配置表内容将相应E1信道的数据包合并到以太网接口上，然后将数据包提交给IP收发缓冲，IP收发缓冲将数据包发送出去。
如图2所示，所述流量控制模块和E1捆绑模块均采用FPGA芯片实现。
该实施例中，FPGA芯片还包括CPU接口、流量控制配置表、E1捆绑配置表、控制寄存器、时钟及复位模块、IP收发缓冲、过滤、协议转换模块、E1收发缓冲。CPU接口外接有CPU，IP收发缓冲外接有具有多个IP接口的以太网接口芯片，E1收发缓冲外接有具有多个E1信道的E1接口芯片。下面逐一说明各部分的功能和原理。
1.CPU接口
CPU接口是根据CPU的BUS总线读写时序，实现CPU通过BUS总线操作FPGA内部存储单元的接口。分配固定的地址，映射出可读写操作的FPGA内部存储单元。CPU接口可以根据不同的CPU的接口要求进行修改。
2.流量配置表、E1捆绑配置表及控制寄存器
流量配置表、E1捆绑配置表及控制寄存器均由外部CPU对其进行配置，控制寄存器用于实现对各功能模块的控制及状态监控，流量配置表、E1捆绑配置表用于实现流量控制和E1捆绑。
流量控制配置表可配置如下：
表1流量控制配置表
Figure PCTCN2015095086-appb-000001
注：保证流量以K字节/秒为单位
E1捆绑配置表可配置如下：
表2 E1捆绑配置表
偏移地址(按字节编址) 内容 读写 备注
0x0 捆绑以太网接口号 rw E1接口1
0x02 捆绑以太网接口号 rw E1接口2
0x04 捆绑以太网接口号 rw E1接口3
0x06 捆绑以太网接口号 rw E1接口4
0x08 捆绑以太网接口号 rw E1接口5
0x0A 捆绑以太网接口号 rw E1接口6
0x0C 捆绑以太网接口号 rw E1接口7
0x0E 捆绑以太网接口号 rw E1接口8
3.时钟及复位模块
时钟及复位模块主要是产生逻辑需要的时钟及生成正确的复位信号。时钟逻辑部分可消除外部输入时钟的占空比失真及减少时钟抖动。
4.IP收发缓冲
IP收发缓冲用于实现从IP接口接收数据包和将从E1接收到的数据包发送到以太网接口。由于在大多数情况，以太网接口的数据带宽远大于E1信道的数据带宽，IP收发缓冲的另一重要作用是数据缓冲。
5.过滤
数据包过滤模块用于实现以太网数据包的过滤，因为在大多数情况，IP接口的数据带宽远大于E1信道的数据带宽；在以太网网络中，通常存在大量的与实际应用无关的数据包。故使用数据包过滤，过滤掉与实现应用无关的数据包，以此来提高E1信道的有效通信带宽。
6.流量控制模块
优选的，所述流量控制模块包括：输入缓冲区，用于接收来自IP接口的数据包；数据处理控制子模块，用于根据流量控制配置表控制数据包传输到高优先级区、低优先级缓冲区或丢弃；高优先级缓冲区；低优先级缓冲区；输出缓冲区，用于优先输出来自高优先级缓冲区的数据包，再输出来自低优先级缓冲区的数据包。输出缓冲区还通过流量控制连接到数据处理控制子模块，数据处理控制子模块可根据输出缓冲区反馈的信息控制流量。
流量控制模块的原理如图4所示，由于每路E1信道的数据带宽固定，流量控制模块可根据每路E1信道的固定带宽、IP流量控制配置表及E1捆绑配置表内容计算出保证带宽、剩余带宽等信息。流量控制模块将输入的数据包缓存，然后从缓存中读出并解析数据包，提取源IP、源端口等信息(帧头信息提取)。
流量控制模块将提取的数据包信息与流量控制配置表表项逐一进行比较，如果存在相同项则判断保证带宽是否用完，如果保证带宽用完则判断剩余带宽是否用完，如果剩余带宽用完则将数据包丢弃，如果还有剩余带宽则将数据包存入低优先级缓冲区；如果保证流量未用完则将数据包存入高优先级缓冲区；如果不存在相同项则判断剩余带宽是否用完，如果剩余带宽用完则将数据包丢弃，如果还有剩余带宽则将数据包存入低优先级缓冲区。输出缓冲优先传输高优先级缓冲区的数据包，当高优先级缓冲区没有可发送数据时才发送低优先级缓冲区的数据包。流量统计时间间隔可设定为1S，所有流量统计内容在每秒开始时清零。
7.E1捆绑模块
优选的，所述E1捆绑模块包括：IP收发缓冲区，用于连接IP接口；交换矩阵，用于根据E1捆绑配置表的内容控制E1信道和IP接口之间的数据交换；E1收发缓冲区，用于连接E1信道。
优选的，所述E1捆绑模块还包括流量监控子模块，用于监控每路E1信道的数据流量，对数据包的分发进行控制，使每路E1信道的数据流量一致。
E1捆绑模块原理如图5所示，E1捆绑模块根据E1捆绑配置表内容计算出每路IP接口捆绑的E1信道数量、数据总流量等信息。
E1捆绑模块将IP接口输入的数据包缓存，然后从接收缓存中读出数据包，根据E1捆绑配置表内容分发到E1信道，数据包的分发以IP包为单位。每路E1发送接口配置有流量计数器，交换模块始终转发给流量值最低的E1信道。当所有流量计数器值都超过设定的阈值后，所有的流量计数器值均减去阈值，以防止流量计数器溢出。通过监控每路E1信道的数据流量，对数据包的分发进行控制，以使每路E1信道的数据流量一致，达到流量均衡的目的。最终数据包将存入E1发送缓冲区，供后续处理。
对于从E1信道上接收的数据包，先存入E1接收缓冲，然后根据E1捆绑配置表内容从接收缓存中读出数据包，通过交换矩阵汇聚到IP接口，数据包的汇聚同样以IP包为单位。最终数据包将存入以太网发送缓冲区，供后续处理。
当E1捆绑配置表中以太网捆绑接口号冲突时，IP接口号数值最 低的捆绑接口有效。
协议转换模块包括IPoE1模块和E1oIP模块。
(1)IPoE1模块
IPoE1模块用于实现将IP数据包以字节为单位分发到E1时隙上，并添加必要的包头、包尾界定符。
(2)E1oIP模块
E1oIP模块用于实现以字节为单位从E1时隙上接收数据，然后根据包头、包尾界定符提取出完整的IP数据包。
E1收发缓冲模块用于实现按照E1时隙时序要求从E1信道接收数据以及将IP数据按照E1时隙节拍发送到E1信道上。
本发明一种多路以太网到多路E1信道的适配系统将以太网数据适配到E1信道传输，实现E1信道透明传输IP数据报，通过E1通道的捆绑实现带宽的动态配置，通过IP流量控制实现高速到低速的流量控制以及可配置的重要数据的带宽保证，解决了以下多个问题：
1、解决了多网络环境下，多路以太网到多路E1信道不能动态配置的问题；
2、解决了在有限的带宽环境下，不能提供重要数据可靠传输服务的问题；
3、解决了在不同应用场景下，设计改动大，配置不灵活的问题。
另外，本发明基于FPGA实现，设计周期短，选型范围广，费用低。
本发明可广泛应用于各种以太网到E1信道的适配系统。
一种多路以太网到多路E1信道的适配方法，其包括步骤：S1，流量控制步骤，根据每路E1信道的固定带宽、流量控制配置表及E1捆绑配置表的内容控制每路IP接口的数据流量；S2，E1捆绑步骤，根据E1捆绑配置表的内容控制每路E1信道的数据流量；所述流量控制配置表的内容包括IP地址、端口和保证带宽的对应关系；所述E1捆绑配置表的内容包括IP接口和E1信道的对应关系。
优选的，所述步骤S1具体包括子步骤：S11，提取数据包信息；S12，将提取的数据包信息与流量控制配置表逐一进行比较，如果存在相同项则进入步骤S13，如果不存在相同项则进入步骤S18；S13，判断对应保证带宽是否用完，如果是则进入步骤S14，如果否则进入步骤S17；S14，判断剩余带宽是否用完，如果是则进入步骤S15，如果否则进入步骤S16；S15，将数据包丢弃；S16，将数据包存入低优先级缓冲区；S17，将数据包存入高优先级缓冲区；S18，判断剩余带宽是否用完，如果是则进入步骤S15，如果否则进入步骤S16。
优选的，所述步骤S2具体包括子步骤：S21，将从IP接口接收的数据包，先存入IP接收缓冲区；S22，从IP接收缓冲区中读出数据包，根据E1捆绑配置表的内容将数据包分发到对应的E1信道；S23，将数据包存入E1发送缓冲区，供后续处理；S24，将从E1信道上接收的数据包，先存入E1接收缓冲区；S25，从E1接收缓冲区中读出数据包，根据E1捆绑配置表内容将数据包汇聚到对应的IP接口；S26，将数据包存入IP发送缓冲区，供后续处理。
优选的，所述步骤S3还包括子步骤：S27，监控每路E1信道的 数据流量，对数据包的分发进行控制，使每路E1信道的数据流量一致；S28，当E1捆绑配置表中IP接口和E1信道对应关系冲突时，IP接口号数值最低的对应关系有效。
本发明一种多路以太网到多路E1信道的适配方法的工作原理对应于一种多路以太网到多路E1信道的适配系统，在此不做累述。
一种多路以太网到多路E1信道的适配系统将以太网数据适配到E1信道传输，实现E1信道透明传输IP数据报，通过E1通道的捆绑实现带宽的动态配置，通过IP流量控制实现高速到低速的流量控制以及可配置的重要数据的带宽保证，解决了以下多个问题：
1、解决了多网络环境下，多路以太网到多路E1信道不能动态配置的问题；
2、解决了在有限的带宽环境下，不能提供重要数据可靠传输服务的问题；
3、解决了在不同应用场景下，设计改动大，配置不灵活的问题。
另外，本发明基于FPGA实现，设计周期短，选型范围广，费用低。
本发明可广泛应用于各种以太网到E1信道的适配系统。
以上是对本发明的较佳实施进行了具体说明，但本发明创造并不限于所述实施例，熟悉本领域的技术人员在不违背本发明精神的前提下还可做作出种种的等同变形或替换，这些等同的变形或替换均包含在本申请权利要求所限定的范围内。

Claims (10)

  1. 一种多路以太网到多路E1信道的适配方法，其特征在于,其包括步骤：
    S1，流量控制步骤，根据每路E1信道的固定带宽、流量控制配置表及E1捆绑配置表的内容控制每路IP接口的数据流量；
    S2，E1捆绑步骤，根据E1捆绑配置表的内容控制每路E1信道的数据流量；
    所述流量控制配置表的内容包括IP地址、端口和保证带宽的对应关系；
    所述E1捆绑配置表的内容包括IP接口和E1信道的对应关系。
  2. 根据权利要求1所述的一种多路以太网到多路E1信道的适配方法，其特征在于，所述步骤S1具体包括子步骤：
    S11，提取数据包信息；
    S12，将提取的数据包信息与流量控制配置表逐一进行比较，如果存在相同项则进入步骤S13，如果不存在相同项则进入步骤S18；
    S13，判断对应保证带宽是否用完，如果是则进入步骤S14，如果否则进入步骤S17；
    S14，判断剩余带宽是否用完，如果是则进入步骤S15，如果否则进入步骤S16；
    S15，将数据包丢弃；
    S16，将数据包存入低优先级缓冲区；
    S17，将数据包存入高优先级缓冲区；
    S18，判断剩余带宽是否用完，如果是则进入步骤S15，如果否则进入步骤S16。
  3. 根据权利要求1所述的一种多路以太网到多路E1信道的适配方法，其特征在于，所述步骤S2具体包括子步骤：
    S21，将从IP接口接收的数据包，先存入IP接收缓冲区；
    S22，从IP接收缓冲区中读出数据包，根据E1捆绑配置表的内容将数据包分发到对应的E1信道；
    S23，将数据包存入E1发送缓冲区，供后续处理；
    S24，将从E1信道上接收的数据包，先存入E1接收缓冲区；
    S25，从E1接收缓冲区中读出数据包，根据E1捆绑配置表内容将数据包汇聚到对应的IP接口；
    S26，将数据包存入IP发送缓冲区，供后续处理。
  4. 根据权利要求3所述的一种多路以太网到多路E1信道的适配方法，其特征在于，所述步骤S3还包括子步骤：
    S27，监控每路E1信道的数据流量，对数据包的分发进行控制，使每路E1信道的数据流量一致；
    S28，当E1捆绑配置表中IP接口和E1信道对应关系冲突时，IP接口号数值最低的对应关系有效。
  5. 一种多路以太网到多路E1信道的适配系统,其特征在于，其用于实施如权利要求1至4任一项所述的一种多路以太网到多路E1信道的适配方法，其包括：
    多个IP接口；
    多个E1信道；
    流量控制模块，用于根据每路E1信道的固定带宽、流量控制配置表及E1捆绑配置表的内容控制每路IP接口的数据流量；
    E1捆绑模块，用于根据E1捆绑配置表的内容控制E1信道和IP接口之间的数据交换；
    所述多个IP接口依次通过流量控制单元和E1捆绑单元连接到多个E1信道。
  6. 根据权利要求5所述的一种多路以太网到多路E1信道的适配系统,其特征在于，所述流量控制模块包括：
    输入缓冲区，用于接收来自IP接口的数据包；
    数据处理控制子模块，用于根据流量控制配置表控制数据包传输到高优先级区、低优先级缓冲区或丢弃；
    高优先级缓冲区；
    低优先级缓冲区；
    输出缓冲区，用于优先输出来自高优先级缓冲区的数据包，再输出来自低优先级缓冲区的数据包。
  7. 根据权利要求5所述的一种多路以太网到多路E1信道的适配系统,其特征在于，所述E1捆绑模块包括：
    IP收发缓冲区，用于连接IP接口；
    交换矩阵，用于根据E1捆绑配置表的内容控制E1信道和IP接口之间的数据交换；
    E1收发缓冲区，用于连接E1信道。
  8. 根据权利要求7所述的一种多路以太网到多路E1信道的适配系统,其特征在于，所述E1捆绑模块还包括流量监控子模块，用于监控每路E1信道的数据流量，对数据包的分发进行控制，使每路E1信道的数据流量一致。
  9. 根据权利要求5至8任一项所述的一种多路以太网到多路E1信道的适配系统,其特征在于，所述流量控制模块和E1捆绑模块均采用FPGA芯片实现。
  10. 根据权利要求9所述的一种多路以太网到多路E1信道的适配系统,其特征在于，其还包括用于对流量控制配置表和E1捆绑配置表进行配置的CPU，所述FPGA芯片具有CPU接口，所述CPU接口与CPU连接。
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