WO2016095426A1 - 3G协议的turbo码并行译码方法及装置 - Google Patents

3G协议的turbo码并行译码方法及装置 Download PDF

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WO2016095426A1
WO2016095426A1 PCT/CN2015/079466 CN2015079466W WO2016095426A1 WO 2016095426 A1 WO2016095426 A1 WO 2016095426A1 CN 2015079466 W CN2015079466 W CN 2015079466W WO 2016095426 A1 WO2016095426 A1 WO 2016095426A1
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parallel
matrix
parallelism
interleaving
block length
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PCT/CN2015/079466
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English (en)
French (fr)
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杜凡平
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深圳市中兴微电子技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the present invention relates to decoding techniques in mobile communications, and more particularly to a method and apparatus for parallel decoding of turbo codes in a third generation mobile communication (3G, 3rd Generation) protocol.
  • 3G, 3rd Generation third generation mobile communication
  • 3G has improved over the second generation mobile communication (2G, 2nd Generation) in terms of multiple access technology, modulation technology, channel coding and interleaving, channel multiplexing technology, etc.
  • 2G, 2nd Generation the second generation mobile communication
  • the coding gain ratio is adopted in 3G.
  • the convolutional code is 1-2db higher than the turbo code.
  • the Turbo code has excellent performance when the interleaving length is large, but the Turbo code decoding has higher complexity and longer delay. Therefore, how to improve the Turbo code decoding speed has always been the bottleneck problem of the turbo code.
  • the fourth-generation mobile communication (4G, 4th Generation) long-term evolution (LTE, Long Term Evolution) system uses the Quadratic Permutation Polynomials (QPP) interleaver to make parallel interleaving possible, but 3G turbo Interleaver is not designed for parallel interleaving.
  • QPP Quadratic Permutation Polynomials
  • HSPA High-Speed Packet Access
  • For the terminal resources can be reduced, delay and power consumption can be reduced.
  • the base station can support multiple users to connect at the same time, improve the throughput of the base station, and reduce the processing delay of the single user.
  • the Turbo code interleaving process includes inputting and adding padding bits in a row to form an interleaving matrix, matrix in-row and inter-row permutation, and outputting and deleting padding bits in columns.
  • the input bits of the turbo code interleaver are denoted by x 1 , x 2 , x 3 , ..., x K , where K is the number of bits, and the value is 40 ⁇ K ⁇ 5114.
  • the first step is to form an interlace matrix by row input:
  • the rows of the interleaving matrix are sequentially numbered 0, 1, ..., R-1 in order from top to bottom.
  • the columns of the interlaced array are sequentially numbered 0, 1, ..., C-1 in order from left to right.
  • Table 1 is a prime number p and a corresponding original root v list
  • Step 2 Perform in-row and inter-row replacement:
  • ⁇ T(i)> i ⁇ 0,1,...,R-1 ⁇ is an inter - row permutation mode defined as one of the four modes shown in Table 2, and the mode selection depends on the number of input bits K;
  • the interline swap mode is shown in Table 2:
  • the third step is to output by column:
  • inter-row permutation and row after execution permutation matrix interleaved bits to y 'k represents:
  • the output of the Turbo intra-code interleaver is a bit sequence sequentially read out from the R ⁇ C interleaving matrix in the order of one column and one column.
  • the matrix has been replaced by intra-row and inter-row, and the bit sequence starts at y' 1 of the 0 row 0 column. Terminates y' CR in column C-1 of row R-1. Deletion of the deletion operation is a front row and inter-row permutation to all padding bits of the virtual input of the matrix, i.e., corresponding to y k, k> K bits y 'k are pruned away from the output.
  • the interleaving method in the above 3G is relatively complicated, it is generally considered in the prior art that the interleaver specified by the 3G protocol cannot implement parallel interleaving. Therefore, parallel decoding is implemented by other techniques, for example, by pre-reading data. Implementing in the buffer area, or processing 2, 3, and 4 bits simultaneously using bases 4, 8, and 16 improves efficiency. However, in the prior art, the parallel interleaving technique is not fundamentally used, but the efficiency is improved by some other techniques to achieve a certain degree of parallel effect.
  • the embodiments of the present invention are directed to a turbo code parallel decoding method and apparatus for a 3G protocol, which can implement parallel decoding of a turbo code of a 3G protocol by using a parallel interleaving technique.
  • An embodiment of the present invention provides a turbo code parallel decoding method for a 3G protocol, where the method includes:
  • the turbo code of the 3G protocol is decoded in parallel according to the result of parallel reading and writing.
  • the parallel interleaving technology is used for parallel reading and writing of the data storage space, including:
  • the dividing the storage space includes:
  • the data storage space is divided according to the interleaving matrix, and each row of the interlacing matrix is divided into independent storage spaces.
  • the setting parallelism includes:
  • the degree of parallelism is determined according to the number of rows of the interlacing matrix, the degree of parallelism being no greater than the number of rows of the interleaving matrix.
  • the determining the parallel block length comprises:
  • the initial length of the parallel block is corrected to obtain the parallel block length.
  • the modifying the initial length of the parallel block includes:
  • the parallel block length includes, but is not limited to, a minimum of all values that are not less than the initial length of the tile and that are relatively prime to the number of rows of the interleave matrix.
  • the parallel computing parallel interleaving addresses according to the degree of parallelism and the parallel block length includes:
  • the number of independent parallel interleave addresses generated in parallel each time is determined according to the degree of parallelism, the number of times the parallel interleave address is generated is determined according to the parallel block length, and the parallel interleave address is calculated in parallel according to the protocol.
  • the embodiment of the invention further provides a turbo code parallel decoding device of the 3G protocol, the device comprising: a parallel read/write module and a parallel decoding module, wherein
  • the parallel read/write module is configured to perform parallel read and write on the data storage space by using a parallel interleaving technology
  • the parallel decoding module is configured to perform parallel decoding on the turbo code of the 3G protocol according to the result of parallel reading and writing.
  • the parallel read/write module includes a data storage space division sub-module, a parallelism setting sub-module, a parallel block length determination sub-module, a parallel interleave address calculation sub-module, and a read-write sub-module, wherein
  • the data storage space dividing sub-module is configured to divide a data storage space
  • the parallelism setting submodule is configured to set a parallel degree
  • the parallel block length determining submodule configured to determine a parallel block length
  • the parallel interleave address calculation submodule is configured to calculate a parallel interleave address in parallel according to the parallelism and the parallel block length;
  • the read/write submodule is configured to perform parallel read and write on the data storage space according to the parallel interleaved address.
  • the data storage space division sub-module is configured to divide the data storage space according to an interlace matrix, and divide each row of the interlace matrix into independent storage spaces.
  • the parallel degree setting sub-module is configured to: determine the degree of parallelism according to the number of rows of the interlacing matrix, where the degree of parallelism is not greater than the number of rows of the interlacing matrix.
  • the parallel block length determining submodule is configured to: determine the initial length of the parallel block according to the number of rows, the number of columns, and the degree of parallelism of the interlaced matrix; and correct the initial length of the parallel block to obtain a parallel block length.
  • the parallel block length determining submodule is configured to: select a value that is not less than the initial length of the parallel block, and the value that is relatively prime with the number of interleaving matrix rows is regarded as the corrected parallel block length; in particular, The parallel block length includes, but is not limited to, a minimum of all values that are not less than the initial length of the parallel block and that are relatively prime to the number of rows of the interlaced matrix.
  • the parallel interleave address calculation submodule is configured to: determine the number of independent parallel interleave addresses generated in parallel each time according to the degree of parallelism, determine the number of times the parallel interleave address is generated according to the parallel block length, and calculate the parallel interleave address in parallel according to the protocol.
  • the turbo code parallel decoding method and device of the 3G protocol implement parallel decoding by using parallel interleaving technology.
  • parallel interleaving the data storage space can be read or written in parallel, so The data storage space is divided according to the interleaving matrix, so that each row of the interleaving matrix has independent storage space; then the parallelism is set; then the parallel block length is calculated according to the parallelism; then parallel computing is performed in parallel according to the parallelism and the parallel block length Interleaving the address, and finally, reading and writing the data storage space in parallel according to the parallel interleaved address.
  • the embodiment of the present invention reverses the previous theory that the turbo interleaver of the 3G protocol cannot be implemented in parallel, and realizes parallel decoding of the turbo code of the 3G protocol by implementing parallel interleaving of the turbo code of the 3G protocol.
  • FIG. 1 is a schematic flowchart of a method for implementing parallel interleaving in a parallel decoding method according to an embodiment of the present invention
  • FIG. 2 is a schematic flowchart of a method for determining a parallel block length according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a general principle of a turbo decoder
  • FIG. 4 is a schematic diagram of implementation of turbo parallel decoding according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of division and use of a storage space according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a turbo code parallel decoding apparatus according to a 3G protocol according to an embodiment of the present invention.
  • the key to the parallel decoding is to implement the parallel interleaving.
  • To implement the parallel interleaving as long as the conflict-free parallel interleaving address can be generated in parallel according to the protocol, the core of the embodiment of the present invention is The mind is how to generate parallel, collision-free parallel interleaved addresses.
  • the interleaving is divided into two steps: intra-row permutation and inter-row permutation.
  • the intra-row permutation does not change the position of the row where the bit is located.
  • inter-row permutation is performed, the inter-row permutation is The row data is replaced together, and the relative position of the row where the bit is located is not changed, that is, the bits in the same row are still in the same row after the inter-row replacement, and the bits of different rows are still different rows.
  • the interleaving is in the same row. The bits are still in the same line after interleaving, and the bits that are not in the same line before interleaving are still not in the same line.
  • the interleaved outputs are sequentially output according to the direction of the columns, that is, the interleaving always accesses each row of the interleaving matrix in a specific order, and the next row of each row is determined and different. Therefore, as long as the starting position of each parallel block read and written in parallel is not in the same row of the interleaving matrix, the position of reading and writing of each parallel block at the next moment is certainly not in the same row of the interleaving matrix, that is, parallel reading.
  • Write always reads and writes different lines of the interleaving matrix. In summary, as long as the data is stored in an interleaved matrix, and each row is stored in a separate memory, parallel read and write conflicts can be avoided.
  • the method for solving the parallel read and write conflicts in the embodiment of the present invention is that the starting line is staggered when the interleaving matrix is interleaved and read in parallel. Therefore, the method in the embodiment of the present invention may be referred to as a wrong line method.
  • the turbo code parallel decoding method of the 3G protocol includes the following steps: First, the data storage space is read and written in parallel by using the parallel interleaving technology; then, the parallel decoding of the turbo code of the 3G protocol is implemented by the parallel interleaving technique.
  • FIG. 1 is a schematic flowchart of a method for implementing parallel interleaving in a parallel decoding method according to an embodiment of the present invention, including the following steps:
  • Step 100 Divide the data storage space; divide the data storage space according to the manner of the interlace matrix, and divide each row of the interlace matrix into independent storage spaces;
  • Step 101 Set a parallelism degree para; the parallelism is not greater than the number of interlaced matrix rows;
  • the degree of parallelism is determined according to the number of rows of the interlacing matrix, because the number of rows r of the interlaced matrix is fixed, and the number of independent memories is equal to the number of rows of the interlaced matrix, therefore, the parallelism para set cannot be greater than the interleaving.
  • the number of rows r of the matrix if the degree of parallelism para is greater than the number of rows r of the interlaced matrix, parallel reads and writes will certainly access the same row of the interleaved matrix, causing an address conflict.
  • Step 102 Determine a parallel block length pk; the length pk of the parallel block is mutually prime with the number of interleave matrix rows r;
  • the initial length of the parallel block is determined according to the number of rows, the number of columns, and the degree of parallelism of the interleaving matrix; and the initial length of the parallel block is corrected to obtain the parallel block length.
  • FIG. 2 is a schematic flowchart of a method for determining a parallel block length according to an embodiment of the present invention, including the following steps:
  • Step 102A Determine a parallel block initial length pk 0 according to the number of rows r, the number of columns c, and the degree of parallelism para of the interlace matrix;
  • ceil is the upper rounding function, its function is to return the smallest integer greater than or equal to the specified expression.
  • Step 102B Correct the parallel block initial length pk 0 to obtain a parallel block length, and make the parallel block length pk and the interleave matrix row number r relatively prime.
  • the parallel block initial length pk 0 does not necessarily satisfy the interleave matrix row number r, it is necessary to find a value that is not less than the parallel block initial length pk 0 and is relatively prime with the interleave matrix row number as the corrected parallel block length.
  • the value closest to the initial block pk 0 of the parallel block is used as the corrected parallel block length in the embodiment of the present invention.
  • Step 103 Calculate parallel interleaved addresses in parallel according to the parallelism para and the parallel block length pk;
  • the number of parallel interleaving addresses generated each time is determined according to the degree of parallelism, the number of times of generating the parallel interleaving address is determined according to the parallel block length, and the parallel interleaving address is calculated in parallel according to the protocol.
  • the parallel degree para addresses are generated each time, and the parallel block length pk is generated.
  • parallel independent degree address calculation units are needed, and parallel parallel para-interleaved addresses are calculated.
  • row is the number of rows of the bit in the interleaving matrix before interleaving
  • col is the number of columns of the bit in the interleaving matrix before interleaving
  • xrow is the number of rows of the bit in the interleaving matrix after interleaving
  • xcol is the number of rows after interleaving The number of columns in the interleaving matrix.
  • r, c is the number of rows and columns of the interleaving matrix
  • p is the prime number determined in Table 1
  • q is the prime sequence specified by the protocol
  • T_row is the inter-row permutation mode as shown in Table 2
  • s(mod(col*q) (row), p-1)) is an inline replacement formula.
  • the read and write position of each parallel block is not in the same row of the interleaving matrix, so the read and write position of each parallel block during interleaving and reading is certainly not in the same row of the interleaving matrix.
  • Step 104 Parallel reading and writing of the data storage space according to the parallel interleaved address.
  • the parallel decoding method starts from the interleaver, and realizes parallel decoding of the turbo code of the 3G protocol by implementing parallel interleaving. And by the method given by the embodiment of the present invention, the previous argument that the turbo interleaver in 3G cannot be implemented in parallel is reversed.
  • the parallel implementation method of the 3G turbo interleaver is not more complicated than the 4G QPP interleaver designed specifically for parallel implementation. It can also be assumed that if the 4G QPP interleaver was invented before, it was found that the 3G turbo interleaver can pass this In the embodiment of the invention, the parallel decoding method is implemented in an easy parallel manner.
  • FIG. 3 is a schematic diagram of a general principle of a turbo decoder, and the principle will not be described herein.
  • data interleaving is realized by sequential write interleaving, and deinterleaving of data is realized by interleaving write sequential reading.
  • interleaving or de-interleaving is determined by the parity of the number of iterations, that is, odd-numbered iterations, system bit sequential reading, prior information sequential reading, external information sequential writing; even-numbered iterations, systematic bit interleaving reading, a priori information interleaving reading, Information interleaving writes, an odd iteration and an even iteration form a complete decoding iteration.
  • turbo parallel decoding includes a system bit storage module, a first parity bit storage module, a second parity bit storage module, an external information storage module, a decoding module, and a parallel interleaving address generation.
  • the external information storage module is a double-ended ram, the reading and writing can be performed independently, the read end reads the prior information, the write end writes the external information, and in addition, the hard decision bit can be used for the single bit storage space.
  • the information data storage space is spliced to reduce the amount of storage space, and the additional advantage of using the double-ended ram to store hard decision bits is that the hard decision bits written and read can be compared, and the turbo decoder is controlled according to the comparison result.
  • FIG. 5 is a schematic diagram of partitioning and usage of a storage space according to an embodiment of the present invention. In a storage space of 20 sets of depths of 256, only the space of the size of the interleaving matrix is used.
  • the present invention is merely an example of the above process, and does not limit the scope of protection of the present invention.
  • the parallel decoding method according to the embodiment of the present invention can be used for turbo parallel decoding of 3G and 4G dual modes.
  • FIG. 6 is a schematic structural diagram of a turbo code parallel decoding apparatus according to a 3G protocol according to an embodiment of the present invention. As shown in FIG. 6, the apparatus includes: a parallel read/write module 61 and a parallel decoding module 62, where
  • the parallel read/write module 61 is configured to perform parallel read and write on the data storage space by using a parallel interleaving technique
  • the parallel read/write module 61 includes a data storage space partitioning submodule 611, a parallelism setting submodule 612, a parallel block length determining submodule 613, a parallel interleaving address computing submodule 614, and a read/write submodule 615. ,among them,
  • the data storage space dividing sub-module 611 is configured to divide a data storage space
  • the data storage space dividing sub-module 611 divides the data storage space according to the manner of the interlace matrix, and divides each row of the interlacing matrix into independent storage spaces;
  • each row can be accessed separately, it is necessary to interleave the number of matrix rows r independent memories, and each memory size is the number of interleave matrix columns c; in practical applications, the maximum in the compatibility protocol
  • the length of the coding block, the size and number of memories should be the maximum, that is, 20 256-depth independent memories are required for various data.
  • the parallel degree setting sub-module 612 is configured to set a parallel degree; the parallel degree is not greater than the number of interleaving matrix rows;
  • the parallelism setting sub-module 612 determines the degree of parallelism according to the number of rows of the interlacing matrix, the parallelism is not greater than the number of rows of the interlacing matrix. Since the number of rows r of the interlaced matrix is fixed, and the number of independent memories is equal to the number of rows of the interlaced matrix, the parallelism para set cannot be greater than the number of rows r of the interleaving matrix; if the parallelism para is greater than the interleaving If the number of rows in the matrix is r, then parallel reads and writes will definitely access the same row of the interleaved matrix, causing an address conflict.
  • the parallel block length determining sub-module 613 is configured to determine a parallel block length; wherein a length pk of the parallel block is mutually prime with an interleave matrix row number r;
  • the parallel block length determining sub-module 613 first determines the number of rows, the number of columns, and the number of columns of the interleaving matrix. Parallelism, determining the initial length of the parallel block; then correcting the initial length of the parallel block to obtain the parallel block length.
  • the parallel block length determining sub-module 613 is configured to correct the initial length of the parallel block by selecting: a value that is not less than the initial length of the parallel block, and a value that is relatively prime with the number of rows of the interlaced matrix as the corrected parallel block length;
  • the parallel block length includes, but is not limited to, a minimum value of all values that are not less than the initial length of the parallel block and that are relatively prime to the number of rows of the interleaving matrix.
  • the parallel block length determining sub-module 613 first determines the parallel block initial length pk 0 according to the row number r, the column number c, and the parallelism degree of the interlacing matrix; and then corrects the parallel block initial length pk 0 to obtain the parallel block length pk.
  • the parallel block length pk is made to be mutually prime with the interleave matrix row number r.
  • the parallel block initial length pk 0 does not necessarily satisfy the interleave matrix row number r, it is necessary to find a value that is not less than the parallel block initial length pk 0 and is relatively prime with the interleave matrix row number as the corrected parallel block length.
  • the value closest to the initial block pk 0 of the parallel block is used as the corrected parallel block length in the embodiment of the present invention.
  • the parallel interleave address calculation sub-module 614 is configured to calculate a parallel interleave address in parallel according to the parallelism and the parallel block length;
  • the parallel interleave address calculation sub-module 614 determines the number of independent parallel interleave addresses generated in parallel each time according to the degree of parallelism, determines the number of times the parallel interleave address is generated according to the parallel block length, and calculates the parallel interleave address in parallel according to the protocol.
  • the parallel interleave address calculation sub-module 614 generates a parallel block length pk times each time according to the set parallelism degree para and the parallel block length pk and a method for generating a parallel interleave address specified by the protocol. In the implementation process, parallel independent degree address calculation units are needed, and parallel parallel para-interleaved addresses are calculated.
  • the read/write submodule 615 is configured to store data according to the parallel interleaved address Perform parallel read and write.
  • the parallel decoding module 62 is configured to perform parallel decoding on the turbo code of the 3G protocol according to the result of parallel reading and writing.
  • the embodiment of the present invention is only an example of the foregoing process.
  • the steps may be adjusted, replaced, deleted, etc. according to the actual application scenario.
  • a person skilled in the art can make various changes and modifications to the embodiments of the invention without departing from the spirit and scope of the invention.
  • the above steps can be appropriately adjusted, and part of the process is omitted or added to form a new method, and these adjustments are all within the scope of the present invention.
  • each processing module in the turbo code parallel decoding apparatus of the 3G protocol shown in FIG. 6 can be understood by referring to the related description of the turbo code parallel decoding method of the foregoing 3G protocol. It should be understood by those skilled in the art that the functions of the processing units in the turbo code parallel decoding apparatus of the 3G protocol shown in FIG. 6 can be implemented by a program running on a processor, or can be implemented by a specific logic circuit, such as : can be implemented by a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA); the storage unit can also be implemented by various memories or storage media. .
  • CPU central processing unit
  • MPU microprocessor
  • DSP digital signal processor
  • FPGA field programmable gate array
  • the disclosed method and apparatus may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the modules is only a logical function division.
  • there may be another division manner for example, multiple modules or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed.
  • the communication connections between the various components shown or discussed may be indirect coupling or communication connections through some interfaces, devices or modules, and may be electrical, mechanical or otherwise.
  • modules described above as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical units, that is, may be located in one place or distributed to multiple network units; You can choose some of them according to your actual needs. Or all modules to achieve the purpose of the solution of the embodiment.
  • each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may be separately used as one module, or two or more modules may be integrated into one module;
  • the module can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the foregoing program may be stored in a computer readable storage medium, and when executed, the program includes The foregoing steps of the method embodiment; and the foregoing storage medium includes: a removable storage device, a read-only memory (ROM), a magnetic disk or an optical disk, and the like, which can store program codes.
  • ROM read-only memory
  • the above-described integrated module of the embodiment of the present invention may be stored in a computer readable storage medium if it is implemented in the form of a software function module and sold or used as a stand-alone product.
  • the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • a computer device (which may be a personal computer, server, or network device, etc.) is caused to perform all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a mobile storage device, a ROM, a magnetic disk, or an optical disk.
  • the present invention is a method and a device for parallel decoding of a turbo code in the 3G protocol described in the example.
  • the above embodiment is exemplified, but it is not limited thereto, and those skilled in the art should understand that it can still be described in the foregoing embodiments.
  • the technical solutions are modified, or some or all of the technical features are equivalently replaced; and the modifications or substitutions do not deviate from the technical solutions of the embodiments of the present invention.

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Abstract

提供一种3G协议的turbo码并行译码方法和装置。该方法包括：将数据存储空间按照交织矩阵的方式划分，将交织矩阵的每一行划分到独立的存储空间；设置并行度，该并行度不大于交织矩阵行数；确定并行块长度，该并行块长度与该交织矩阵行数互质；根据该并行度和并行块长度，并行计算并行交织地址；以及根据该并行交织地址，对数据存储空间进行并行读写。

Description

3G协议的turbo码并行译码方法及装置 技术领域
本发明涉及移动通信中的译码技术，尤其涉及一种第三代移动通信(3G，3rd Generation)协议中turbo码并行译码方法及装置。
背景技术
3G在多址技术、调制技术、信道编码与交织、信道复用技术等方面都比第二代移动通信(2G，2nd Generation)有所改善，特别是信道编码方面，3G中采用了编码增益比卷积码高出1-2db的turbo码。Turbo码在交织长度较大时性能优异，但Turbo码译码的复杂性较高、延时较长，因此，如何提高Turbo码译码速度一直是turbo码的瓶颈问题。
第四代移动通信(4G，4th Generation)的长期演进(LTE，Long Term Evolution)系统中采用了二次置换多项式(QPP，Quadratic Permutation Polynomials)交织器，使并行交织成为可能，但是，3G的turbo交织器并不是为并行交织设计的，随着高速分组接入(HSPA，High-Speed Packet Access)的速率越来越高，如何提高3G的turbo译码成为了一个关键问题，因此实现译码的并行具有重要意义，对于终端来说，可以降低资源，减少延时和功耗；对于基站来说，可以使基站支持多个用户同时连接，提高基站的吞吐量，减少单用户的处理延时。
4G之所以能并行译码，是因为使用了并行交织器，因此，实现并行译码的关键是实现并行交织。
3G中的turbo码的交织器原理如下：
Turbo码交织过程包括按行输入并增加填充比特构成交织矩阵，矩阵行内和行间置换，以及按列输出并删减填充比特。Turbo码交织器的输入比特 记为x1,x2,x3,…,xK，其中，K是比特数目，取值为40≤K≤5114。
这里，首先定义以下参数：
K  Turbo码交织器输入比特数；
R  交织矩阵行数；
C  交织矩阵列数；
p  质数；
v  原根；
<s(j)>j∈{0,1,…,p-2}  行内置换基序列；
qi  最小质整数序列；
ri  置换后的质整数序列；
<T(i)>i∈{0,1,…,R-1}  行间置换模式；
<Ui(j)>j∈{0,1,…,C-1}  第i行的行内置换模式；
i  交织矩阵行编号指针；
j  交织矩阵列编号指针；
k  比特序列指针；
第一步，按行输入构成交织矩阵：
输入给Turbo码交织器的比特序列x1,x2,x3,…,xK以下列步骤写入交织矩阵中：
(1)确定交织矩阵的行数R，使得：
Figure PCTCN2015079466-appb-000001
交织矩阵各行按照由上至下的顺序依次编号为0，1，…，R-1。
(2)确定行内置换所需的质数，p，以及交织矩阵的列数，C，使得：
if(481≤K≤530)then
p＝53andC＝p
else
从表1中找到最小质数p，使得：
K≤R×(p+1)；
并确定C，使得：
Figure PCTCN2015079466-appb-000002
end if
交织阵各列按照由左至右的顺序依次编号为0，1，…，C-1。
其中，表1为质数p及相应原根v列表；
P v p v p v p v p v
7 3 47 5 101 2 157 5 223 3
11 2 53 2 103 5 163 2 227 2
13 2 59 2 107 2 167 5 229 6
17 3 61 2 109 6 173 2 233 3
19 2 67 2 113 3 179 2 239 7
23 5 71 7 127 3 181 2 241 7
29 2 73 5 131 2 191 19 251 6
31 3 79 3 137 3 193 5 257 3
37 2 83 2 139 2 197 2    
41 6 89 3 149 2 199 3    
43 3 97 5 151 6 211 2    
表1
(3)逐行将比特序列x1,x2,x3,…,xK写入R×C的交织矩阵中，首比特y1填入0行0列：
Figure PCTCN2015079466-appb-000003
其中，yk＝xk；for k＝1，2，…，K，并且如果R×C>K，则用虚拟比特yk＝0or1，k＝K+1，K+2，…，R×C填充。这些虚拟比特在执行完行内和行间置换之后，输出时需要从交织矩阵中删减掉。
第二步：进行行内及行间置换：
输入比特写入R×C的交织矩阵中后，按照如下的步骤(A1)–(A6)执行行内和行间置换：
(A1)从表1中选择一个原根，表中所有原根都列在质数p的右侧；
(A2)按如下方法构造用于行内置换的基序列<s(j)>j∈{0,1,…,p-2}：
s(j)＝(ν×s(j-1))mod p，j＝1，2，…(p-2)，且s(0)＝1；
(A3)指定q0＝1为序列<qi>i∈{0,1,…,R-1}中的第一个质数，序列<qi>i∈{0,1,…,R-1}其他质数确定方法为：对于每个i＝1，2，…，R–1，qi是满足g.c.d(qi，p-1)＝1，qi>6，且qi>q(i-1)的最小质整数。这里g.c.d.代表最大公约数；
(A4)置换序列<qi>i∈{0,1,…,R-1}，得到序列<ri>i∈{0,1,…,R-1}，使得：
rT(i)＝qi，i＝0，1，….，R–1；
其中<T(i)>i∈{0,1,…,R-1}是行间置换模式，定义为表2所示的四种模式中的一种，模式选择依赖于输入比特数K；
行间置换模式如表2所示：
Figure PCTCN2015079466-appb-000004
Figure PCTCN2015079466-appb-000005
表2
(A5)执行第i行的行内置换：
if(C＝p)then
    Ui(j)＝s((j×ri)mod(p-1))，j＝0，1，…，(p-2)，and Ui(p-1)＝0，
其中，Ui(j)是第i行的第j个需要置换的比特的原始位置。
End if
if(C＝p+1)then
    Ui(j)＝s((j×ri)mod(p-1))，j＝0，1，…，(p-2)；Ui(p-1)＝0，and Ui(p)＝p，
其中Ui(j)是第i行的第j个需要置换的比特的原始位置，且
if(K＝R×C)then
    交换UR-1(p)和UR-1(0).
end if
end if
if(C＝p-1)then
    Ui(j)＝s((j×ri)mod(p-1))-1，j＝0，1，…，(p-2)；
其中，Ui(j)是第i行的第j个需要置换的比特的原始位置。
end if
(A6)按照模式<T(i)>i∈{0,1,…,R-1}执行交织矩阵的行间置换，其中T(i)是 第i个置换行的原始行位置。
第三步，按列输出：
行内和行间置换执行后，置换后的交织矩阵比特以y'k表示：
Figure PCTCN2015079466-appb-000006
Turbo码内交织器的输出是从R×C交织矩阵中按照一列一列的顺序依次读出的比特序列，该矩阵已经过行内和行间置换，比特序列开始于0行0列的y'1，终止于R-1行C-1列的y'CR。删减操作是删减在行内和行间置换前填补到矩阵输入中的所有虚拟比特，即对应于yk，k>K的比特y'k需要从输出中删减掉。
由于上述3G中的交织方法较为复杂，因此，现有技术中一般都认为3G协议规定的交织器不能实现并行交织，因此实现并行译码都是通过其他一些技巧实现的，例如，通过预读数据到缓存区实现，或者使用基4、8、16等方法同时处理2、3、4个比特提高效率。但现有技术中并没有在根本上使用并行交织技术，而是通过一些其他技巧提高了效率，使其达到一定程度的并行效果而已。
发明内容
有鉴于此，本发明实施例期望提供一种3G协议的turbo码并行译码方法及装置，能够通过采用并行交织技术实现3G协议的turbo码并行译码。
为达到上述目的，本发明实施例的技术方案是这样实现的：
本发明实施例提供了一种3G协议的turbo码并行译码方法，所述方法包括：
采用并行交织技术对数据存储空间进行并行读写；
根据并行读写的结果对3G协议的turbo码进行并行译码。
上述方案中，所述采用并行交织技术对数据存储空间进行并行读写包括：
划分数据存储空间；
设置并行度；
确定并行块长度；
根据所述并行度和并行块长度，并行计算并行交织地址；
根据所述并行交织地址，对数据存储空间进行并行读写。
上述方案中，所述划分存储空间包括：
将数据存储空间按照交织矩阵的方式划分，将交织矩阵的每一行划分到独立的存储空间。
上述方案中，所述设置并行度包括：
根据交织矩阵的行数确定并行度，所述并行度不大于所述交织矩阵的行数。
上述方案中，所述确定并行块长度包括：
根据交织矩阵的行数、列数以及并行度，确定并行块初始长度；
对并行块初始长度进行修正，得到并行块长度。
上述方案中，所述对并行块初始长度进行修正包括：
选取不小于并行块初始长度，且与交织矩阵行数互质的值当作修正后的并行块长度；
特别的，并行块长度包括但不限于不小于并行块初始长度、且与交织矩阵行数互质的所有值中的最小值。
上述方案中，所述根据并行度和并行块长度，并行计算并行交织地址包括：
根据并行度确定每次并行产生的独立的并行交织地址数目，根据并行块长度确定产生并行交织地址的次数，按协议并行计算并行交织地址。
本发明实施例还提供了一种3G协议的turbo码并行译码装置，所述装置包括：并行读写模块、并行译码模块，其中，
所述并行读写模块，配置为采用并行交织技术对数据存储空间进行并行读写；
所述并行译码模块，配置为根据并行读写的结果对3G协议的turbo码进行并行译码。
上述方案中，所述并行读写模块包括数据存储空间划分子模块、并行度设置子模块、并行块长度确定子模块、并行交织地址计算子模块、读写子模块，其中，
所述数据存储空间划分子模块，配置为划分数据存储空间；
所述并行度设置子模块，配置为设置并行度；
所述并行块长度确定子模块，配置为确定并行块长度；
所述并行交织地址计算子模块，配置为根据所述并行度和并行块长度，并行计算并行交织地址；
所述读写子模块，配置为根据所述并行交织地址，对数据存储空间进行并行读写。
上述方案中，所述数据存储空间划分子模块配置为：将数据存储空间按照交织矩阵的方式划分，将交织矩阵的每一行划分到独立的存储空间。
上述方案中，所述并行度设置子模块配置为：根据交织矩阵的行数确定并行度，所述并行度不大于所述交织矩阵的行数。
上述方案中，所述并行块长度确定子模块配置为：根据交织矩阵的行数、列数以及并行度，确定并行块初始长度；对并行块初始长度进行修正，得到并行块长度。
上述方案中，所述并行块长度确定子模块配置为：选取不小于并行块初始长度，且与交织矩阵行数互质的值当作修正后的并行块长度；特别的， 并行块长度包括但不限于不小于并行块初始长度、且与交织矩阵行数互质的所有值中的最小值。
上述方案中，并行交织地址计算子模块配置为：根据并行度确定每次并行产生的独立的并行交织地址数目，根据并行块长度确定产生并行交织地址的次数，按协议并行计算并行交织地址。
本发明实施例所提供的3G协议的turbo码并行译码方法及装置，是通过采用并行交织技术实现并行译码的，要实现并行交织，就要求数据存储空间能并行读或写，因此首先将数据存储空间按照交织矩阵的方式划分，使交织矩阵的每一行都有独立的存储空间；然后设置并行度；再根据并行度计算并行块长度；然后根据所述并行度和并行块长度并行计算并行交织地址，最后，根据所述并行交织地址，对数据存储空间进行并行读写。本发明实施例推翻了之前关于3G协议的turbo交织器不能并行实现的这个断论，通过实现3G协议的turbo码的并行交织，进而实现3G协议的turbo码的并行译码。
附图说明
图1为本发明实施例并行译码方法中的并行交织实现方法流程示意图；
图2为本发明实施例确定并行块长度方法流程示意图；
图3为turbo译码器的一般原理示意图；
图4为本发明实施例turbo并行译码实现示意图；
图5为本发明实施例存储空间的划分及使用情况示意图；
图6为本发明实施例3G协议的turbo码并行译码装置结构示意图。
具体实施方式
要实现并行译码的关键是实现并行交织，要实现并行交织，只要能按照协议并行的产生无冲突的并行交织地址即可，因此，本发明实施例的核 心就是如何产生并行的无冲突的并行交织地址。
如协议所述，3G的交织有如下特点：
首先，如协议第二步所述，交织是分为行内置换和行间置换两步的，行内置换不改变比特所处的行的位置，虽然又进行了行间置换，但行间置换是整行数据一起置换的，并不改变比特所处的行的相对位置，即处于同一行的比特在行间置换后仍处于同一行，不同行的比特还是不同行，综上，交织前处于同一行的比特交织后仍处于同一行，交织前不处于同一行的比特交织后仍然不处于同一行。基于交织前不处于同一行的比特交织后仍然不处于同一行这一点可知，只要并行读写的每个并行块的比特在交织前不处于同一行，那么，并行交织读写时也不在同一行，可以通过这个特点简单地控制并行读写的每个并行块的起始位置不在交织矩阵的同一行。
其次，如协议第三步所述，交织输出是按照列的方向依次输出的，即交织总是按照特定的顺序访问交织矩阵的每一行，每一行的下一行都是确定的，不同的。因此，只要并行读写的每个并行块的起始位置不处于交织矩阵的同一行，那么，下一时刻每个并行块的读写的位置肯定也不处于交织矩阵的同一行，即并行读写总是读写交织矩阵的不同的行。综上，只要把数据按照交织矩阵的方式存储，每行都存储在独立的存储器中，就可以避免并行读写冲突。
因此，如何划分并行块的大小，使并行交织读写交织矩阵时的起始行不在同一行就是实现并行交织无冲突的关键，也是本发明实施例的关键。综上，本发明实施例解决并行读写冲突采用的方法是并行交织读写交织矩阵时，起始行是错开的，因此本发明实施例的方法可以称为错行法。
本发明实施例所述3G协议的turbo码并行译码方法包括以下步骤：首先，采用并行交织技术对数据存储空间进行并行读写；然后，通过并行交织技术实现3G协议的turbo码并行译码。
下面结合附图及实施例，对本发明实施例技术方案的实施作详细描述。图1为本发明实施例并行译码方法中的并行交织实现方法流程示意图，包括以下步骤：
步骤100：划分数据存储空间；将数据存储空间按照交织矩阵的方式划分，将交织矩阵的每一行划分到独立的存储空间；
本步骤中，由于要求存储空间按照交织矩阵的方式划分，且每行可以单独访问，因此需要交织矩阵行数r个独立的存储器，每个存储器大小为交织矩阵列数c；实际应用中，为了兼容协议中最大编码块长度，存储器的大小及数量要取最大值，即各种数据都需要20个256深度的独立存储器。
步骤101：设置并行度para；所述并行度不大于交织矩阵行数；
本步骤中，根据交织矩阵的行数确定并行度，因为交织矩阵的行数r是固定的，且独立的存储器的个数等于交织矩阵的行数，因此，所设置的并行度para不能大于交织矩阵的行数r；如果所述并行度para大于交织矩阵的行数r，则并行读写肯定会访问交织矩阵的同一行，发生地址冲突。
设置并行度的伪代码表示为：
para<＝r；
步骤102：确定并行块长度pk；所述并行块的长度pk与交织矩阵行数r互质；
本步骤中，根据交织矩阵的行数、列数以及并行度，确定并行块初始长度；对并行块初始长度进行修正，得到并行块长度。本发明实施例中，最终确定的并行块长度pk要使每一个并行块的起始位置都不在交织矩阵的同一行，这就要求并行块的长度pk与交织矩阵行数r互质，即gcd(pk,r)＝1，gcd为取最大公约数函数。
图2为本发明实施例确定并行块长度方法流程示意图，包括以下步骤：
步骤102A：根据交织矩阵的行数r、列数c以及并行度para，确定并 行块初始长度pk0；
本步骤中，所述确定并行块初始长度pk0的伪代码表示为：
pk0＝ceil(c*r/para)；
其中，ceil为上取整函数，其功能是返回大于或者等于指定表达式的最小整数。
步骤102B：对并行块初始长度pk0进行修正，得到并行块长度，并使并行块长度pk与交织矩阵行数r互质。
由于并行块初始长度pk0不一定满足与交织矩阵行数r互质，因此需要找不小于并行块初始长度pk0且与交织矩阵行数互质的值作为修正的后的并行块长度。
本步骤中，为了使并行块长度尽可能小，本发明实施例中采用最接近并行块初始长度pk 0的值作为修正的并行块长度。
利用伪代码编写如下：
Figure PCTCN2015079466-appb-000007
其中gcd是求最大公约数函数。
步骤103：根据所述并行度para和并行块长度pk，并行计算并行交织地址；
本步骤中，根据并行度确定每次产生的并行交织地址的数量，根据并行块长度确定产生并行交织地址的次数，按协议并行计算并行交织地址。
本步骤中，根据所述设置的并行度para和并行块长度pk以及协议规定的产生并行交织地址的方法，每次产生并行度para个地址，产生并行块长度pk次。实现过程中，需要并行度para个独立的地址计算单元，同时计算出并行度para个并行交织地址。
本发明实施例产生并行交织地址的伪代码如下：
Figure PCTCN2015079466-appb-000008
即交织后行地址；
Figure PCTCN2015079466-appb-000009
Figure PCTCN2015079466-appb-000010
其中row为交织前该比特在交织矩阵中的行数，col为交织前该比特在交织矩阵中的列数，xrow为交织后该比特在交织矩阵中的行数，xcol为交织后该比特在交织矩阵中列数。r，c是交织矩阵的行数和列数，p是表1所确定的质数，q是协议规定的质数序列，T_row是如表2所示的行间置换模式，s(mod(col*q(row),p-1))是行内置换公式。
根据以上的伪代码可以看出，交织前后的行地址置换关系为：xrow＝T_row(row)，即不在交织矩阵同一行的数据经过交织后仍然不在交织矩阵的同一行，因此只要保证了交织前的每一并行块的读写位置不在交织矩阵的同一行，那么交织读写时每一并行块的读写位置肯定也不在交织矩阵的同一行。
步骤104：根据所述并行交织地址，对数据存储空间进行并行读写。
综上所述，本发明实施例所述并行译码方法从交织器出发，通过实现并行交织进而实现了3G协议的turbo码的并行译码。并且通过本发明实施例给出的方法，推翻了之前关于3G中的turbo交织器不能并行实现的这个断论。使用本发明实施例所述方法，3G的turbo交织器的并行实现方法并不比专门为并行实现而设计的4G的QPP交织器复杂。也可以这样假设，如果4G的QPP交织器发明之前，就发现了3G的turbo交织器可以通过本 发明实施例所述并行译码方法轻松的并行实现，那么甚至没必要为4G单独提出与3G不兼容的QPP交织器，导致3G，4G需要两种不同交织器，不仅增加了设计的复杂度，还带来不兼容的问题。
图3为turbo译码器的一般原理示意图，原理这里就不再赘述。一般实现中，为了降低资源，只使用一套译码模块，通过顺序写交织读实现数据的交织，通过交织写顺序读实现数据的解交织。是交织还是解交织由迭代次数的奇偶性决定，即奇数次迭代，系统比特顺序读，先验信息顺序读，外信息顺序写；偶数次迭代，系统比特交织读，先验信息交织读，外信息交织写，一次奇迭代与一次偶迭代构成一次完整的译码迭代。
图4为本发明实施例turbo并行译码实现示意图，包括系统比特存储模块，第一校验比特存储模块，第二校验比特存储模块，外信息存储模块，译码模块，及并行交织地址生成模块。其中，外信息存储模块是一个双端ram，读写可以独立进行，读出端读出先验信息，写入端写入外信息，另外，可以把硬判决比特这种单比特存储空间与外信息数据存储空间拼接，降低存储空间数量，而且使用双端ram存储硬判决比特带来的额外好处是，可以将写入与读出的硬判决比特进行比较，根据比较结果控制turbo译码器的迭代次数，实现早停。由图4还可以看出，译码模块与并行交织地址生产模块的数量由最大并行度决定，最多可以有20套，实际工作中由于要满足本发明实施例提出的并行度不大于交织矩阵行数的条件，只能有para套在工作；每种数据存储模块都有20套，实际工作中，只使用交织矩阵行数r套。存储空间的划分及使用情况如图5所示，图5为本发明实施例存储空间的划分及使用情况示意图，20套深度为256的存储空间中，只使用了其中的交织矩阵大小的空间。
本发明仅仅是以上述过程为例，并不限定本发明的保护范围，例如，本发明实施例所述并行译码方法可以用于3G与4G双模的turbo并行译码。
本发明实施例还提供了一种3G协议的turbo码并行译码装置。图6为本发明实施例3G协议的turbo码并行译码装置结构示意图，如图6所示，所述装置包括：并行读写模块61、并行译码模块62，其中，
所述并行读写模块61，配置为采用并行交织技术对数据存储空间进行并行读写；
本发明实施例中，所述并行读写模块61包括数据存储空间划分子模块611、并行度设置子模块612、并行块长度确定子模块613、并行交织地址计算子模块614、读写子模块615，其中，
所述数据存储空间划分子模块611，配置为划分数据存储空间；
所述数据存储空间划分子模块611将数据存储空间按照交织矩阵的方式划分，将交织矩阵的每一行划分到独立的存储空间；
由于要求存储空间按照交织矩阵的方式划分，且每行可以单独访问，因此需要交织矩阵行数r个独立的存储器，每个存储器大小为交织矩阵列数c；实际应用中，为了兼容协议中最大编码块长度，存储器的大小及数量要取最大值，即各种数据都需要20个256深度的独立存储器。
所述并行度设置子模块612，配置为设置并行度；所述并行度不大于交织矩阵行数；
所述并行度设置子模块612根据交织矩阵的行数确定并行度，所述并行度不大于所述交织矩阵的行数。因为交织矩阵的行数r是固定的，且独立的存储器的个数等于交织矩阵的行数，因此，所设置的并行度para不能大于交织矩阵的行数r；如果所述并行度para大于交织矩阵的行数r，则并行读写肯定会访问交织矩阵的同一行，发生地址冲突。
所述并行块长度确定子模块613，配置为确定并行块长度；其中，所述并行块的长度pk与交织矩阵行数r互质；
所述并行块长度确定子模块613首先根据交织矩阵的行数、列数以及 并行度，确定并行块初始长度；然后对并行块初始长度进行修正，得到并行块长度。所述并行块长度确定子模块613对并行块初始长度进行修正的过程中配置为：选取不小于并行块初始长度，且与交织矩阵行数互质的值当作修正后的并行块长度；特别的，并行块长度包括但不限于不小于并行块初始长度、且与交织矩阵行数互质的所有值中的最小值。
由于最终确定的并行块长度pk要使每一个并行块的起始位置都不在交织矩阵的同一行，这就要求并行块的长度pk与交织矩阵行数r互质，即gcd(pk,r)＝1，gcd为取最大公约数函数。
所述并行块长度确定子模块613首先根据交织矩阵的行数r、列数c以及并行度para，确定并行块初始长度pk0；然后对并行块初始长度pk0进行修正，得到并行块长度pk并使并行块长度pk与交织矩阵行数r互质。
由于并行块初始长度pk0不一定满足与交织矩阵行数r互质，因此需要找不小于并行块初始长度pk0且与交织矩阵行数互质的值作为修正的后的并行块长度。为了使并行块长度尽可能小，本发明实施例中采用最接近并行块初始长度pk 0的值作为修正的并行块长度。
所述并行交织地址计算子模块614，配置为根据所述并行度和并行块长度，并行计算并行交织地址；
所述并行交织地址计算子模块614根据并行度确定每次并行产生的独立的并行交织地址数目，根据并行块长度确定产生并行交织地址的次数，按协议并行计算并行交织地址。
所述并行交织地址计算子模块614根据所述设置的并行度para和并行块长度pk以及协议规定的产生并行交织地址的方法，每次产生并行度para个地址，产生并行块长度pk次。实现过程中，需要并行度para个独立的地址计算单元，同时计算出并行度para个并行交织地址。
所述读写子模块615，配置为根据所述并行交织地址，对数据存储空间 进行并行读写。
所述并行译码模块62，配置为根据并行读写的结果对3G协议的turbo码进行并行译码。
本发明实施例仅是以上述过程为例，实现过程中，可根据实际应用场景对步骤进行调整、替换、删除等。本领域的技术人员对本发明实施例进行简单变动和变型仍然不脱离本发明的精神和范围。比如，在能够实现本发明实施例所述发明目的情况下，上述步骤可以适当调整，省略或增加部分过程，以形成新的方法，这些调整均属于本发明所述范围。
图6中所示的3G协议的turbo码并行译码装置中的各处理模块的实现功能，可参照前述3G协议的turbo码并行译码方法的相关描述而理解。本领域技术人员应当理解，图6所示的3G协议的turbo码并行译码装置中各处理单元的功能可通过运行于处理器上的程序而实现，也可通过具体的逻辑电路而实现，比如：可由中央处理器(CPU)、微处理器(MPU)、数字信号处理器(DSP)、或现场可编程门阵列(FPGA)实现；所述存储单元也可以由各种存储器、或存储介质实现。
在本发明所提供的几个实施例中，应该理解到，所揭露的方法、装置，可以通过其他的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个模块或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的通信连接可以是通过一些接口，设备或模块的间接耦合或通信连接，可以是电性的、机械的或其他形式的。
上述作为分离部件说明的模块可以是、或也可以不是物理上分开的，作为模块显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分 或全部模块来实现本实施例方案的目的。
另外，在本发明各实施例中的各功能模块可以全部集成在一个处理模块中，也可以是各模块分别单独作为一个模块，也可以两个或两个以上模块集成在一个模块中；上述集成的模块既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：移动存储设备、只读存储器(ROM，Read-Only Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
或者，本发明实施例上述集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：移动存储设备、ROM、磁碟或者光盘等各种可以存储程序代码的介质。
本发明是实例中记载的3G协议中turbo码并行译码方法、装置只以上述实施例为例，但不仅限于此，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。
以上所述仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。

Claims (14)

  1. 一种3G协议的turbo码并行译码方法，所述方法包括：
    采用并行交织技术对数据存储空间进行并行读写；
    根据并行读写的结果对3G协议的turbo码进行并行译码。
  2. 根据权利要求1所述方法，其中，所述采用并行交织技术对数据存储空间进行并行读写包括：
    划分数据存储空间；
    设置并行度；
    确定并行块长度；
    根据所述并行度和并行块长度，并行计算并行交织地址；
    根据所述并行交织地址，对数据存储空间进行并行读写。
  3. 根据权利要求2所述方法，其中，所述划分存储空间包括：
    将数据存储空间按照交织矩阵的方式划分，将交织矩阵的每一行划分到独立的存储空间。
  4. 根据权利要求2所述方法，其中，所述设置并行度包括：
    根据交织矩阵的行数确定并行度，所述并行度不大于所述交织矩阵的行数。
  5. 根据权利要求2所述方法，其中，所述确定并行块长度包括：
    根据交织矩阵的行数、列数以及并行度，确定并行块初始长度；
    对并行块初始长度进行修正，得到并行块长度。
  6. 根据权利要求5所述方法，其中，所述对并行块初始长度进行修正包括：
    选取不小于并行块初始长度，且与交织矩阵行数互质的值当作修正后的并行块长度；
    特别的，并行块长度包括但不限于不小于并行块初始长度、且与交织矩阵行数互质的所有值中的最小值。
  7. 根据权利要求2所述方法，其中，所述根据并行度和并行块长度，并行计算并行交织地址包括：
    根据并行度确定每次并行产生的独立的并行交织地址数目，根据并行块长度确定产生并行交织地址的次数，按协议并行计算并行交织地址。
  8. 一种3G协议的turbo码并行译码装置，所述装置包括：并行读写模块、并行译码模块，其中，
    所述并行读写模块，配置为采用并行交织技术对数据存储空间进行并行读写；
    所述并行译码模块，配置为根据并行读写的结果对3G协议的turbo码进行并行译码。
  9. 根据权利要求8所述装置，其中，所述并行读写模块包括数据存储空间划分子模块、并行度设置子模块、并行块长度确定子模块、并行交织地址计算子模块、读写子模块，其中，
    所述数据存储空间划分子模块，配置为划分数据存储空间；
    所述并行度设置子模块，配置为设置并行度；
    所述并行块长度确定子模块，配置为确定并行块长度；
    所述并行交织地址计算子模块，配置为根据所述并行度和并行块长度，并行计算并行交织地址；
    所述读写子模块，配置为根据所述并行交织地址，对数据存储空间进行并行读写。
  10. 根据权利要求8所述装置，其中，所述数据存储空间划分子模块配置为：将数据存储空间按照交织矩阵的方式划分，将交织矩阵的每一行划分到独立的存储空间。
  11. 根据权利要求8所述装置，其中，所述并行度设置子模块配置为：根据交织矩阵的行数确定并行度，所述并行度不大于所述交织矩阵的行数。
  12. 根据权利要求8所述装置，其中，所述并行块长度确定子模块配置为：根据交织矩阵的行数、列数以及并行度，确定并行块初始长度；对并行块初始长度进行修正，得到并行块长度。
  13. 根据权利要求12所述装置，其中，所述并行块长度确定子模块配置为：选取不小于并行块初始长度，且与交织矩阵行数互质的值当作修正后的并行块长度；特别的，并行块长度包括但不限于不小于并行块初始长度、且与交织矩阵行数互质的所有值中的最小值。
  14. 根据权利要求8所述装置，其中，并行交织地址计算子模块配置为：根据并行度确定每次并行产生的独立的并行交织地址数目，根据并行块长度确定产生并行交织地址的次数，按协议并行计算并行交织地址。
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