WO2016095412A1

WO2016095412A1 - Wire speed processing method and device

Info

Publication number: WO2016095412A1
Application number: PCT/CN2015/078693
Authority: WO
Inventors: 何波; 陈谡
Original assignee: 中兴通讯股份有限公司
Priority date: 2014-12-17
Filing date: 2015-05-11
Publication date: 2016-06-23
Also published as: CN105791158B; CN105791158A

Abstract

Disclosed in an embodiment of the present invention are a wire speed processing method and device. The method comprises: performing enqueue buffering on a high-level data link control (HDLC) frame packaged via a point-to-point protocol (PPP)/HDLC protocol performed by a packet over synchronous optical network (POS) mapper module; if sizes of all HDLC frames in a dequeue buffer are determined to be greater than or equal to a preset threshold, then performing wire speed processing on the HDLC frame in an enqueue buffer and saving the processed HDLC frame into the dequeue buffer.

Description

Method and device for realizing line speed processing

Technical field

This paper relates to the field of data communication, especially a method and device for implementing line rate processing.

Background technique

In Synchronous Optical Network (SONET)/Synchronous Digital Hierarchy (SDH), Packet over SONET (SD) technology enables high-performance routers to adopt SONET/SDH frames on the backbone network. Send Internet Protocol (IP) packets. An important indicator in the switching and forwarding of backbone network equipment is called line speed. The line speed refers to the maximum number of frames that the cable can pass in unit time. The POS technology uses the Point-to-Point Protocol (PPP) encapsulation format of the High-Level Data Link Control (HDLC) at the data link layer. The HDLC frame protocol specifies the start of the HDLC frame. The end and the end are identified by the hexadecimal identifier 0x7E. When the HDLC frame is transmitted at the line rate on the line, the interval between two adjacent HDLC frames requires at least one byte of 0x7E. FIG. 1 is a schematic structural diagram of a related art POS framer. As shown in FIG. 1, the POS framer includes a POS mapping (Mapper) module (PPP/HDLC protocol frame framing module) and a POS framing (Framer) module (POS frame framing module). In the downlink transmission, the POS Mapper module is configured to perform PPP/HDLC encapsulation on the data packet to obtain an HDLC frame, and then the POS Mapper module performs non-line rate processing on the HDLC frame according to the POS protocol (that is, to ensure continuity between HDLC frames). The POS Framer module is used to encapsulate the POS frame of the HDLC frame after the non-linear rate processing. The non-line rate processing of the HDLC frame introduces a multi-byte 0x7E overhead, and the cost of the POS interface fails to reach the line rate, thereby reducing the forwarding performance of the POS interface.

Summary of the invention

The embodiment of the invention provides a method and a device for implementing line rate processing, which can improve the forwarding performance of the POS interface.

The embodiment of the invention provides a method for implementing line rate processing, including:

The packet POS mapping module on the synchronous optical network performs a point-to-point protocol PPP/class advanced data link control HDLC frame encapsulation of the HDLC protocol for enqueue buffering;

It is determined that the size of all the HDLC frames in the outbound cache is greater than or equal to a preset threshold, and the HDLC frame in the enqueue buffer is subjected to line rate processing, and the HDLC frame processed by the line rate is dequeued.

Optionally, when it is determined that the size of all the HDLC frames in the dequeue buffer is less than a preset threshold, performing non-linear processing on the HDLC frame in the enqueue buffer, and saving the non-linear velocity processed HDLC frame. Go to the dequeue cache.

Optionally, the performing non-line rate processing on the HDLC frame in the enqueue buffer includes:

A frame interval is added between two adjacent HDLC frames, so that the rate of the POS interface reaches the line rate.

Optionally, performing line-speed processing on the HDLC frame in the enqueue buffer includes:

It is determined that the number of frame intervals between two adjacent HDLC frames is greater than one, and the frame interval between two adjacent HDLC frames is deleted, so that the number of frame intervals between two adjacent HDLC frames is equal to one.

An embodiment of the present invention further provides an apparatus for implementing line rate processing, including:

The enqueue cache module is configured to save the data packet POS mapping module on the synchronous optical network to perform a point-to-point protocol PPP/class advanced data link to control the HDLC frame encapsulated by the HDLC protocol;

The dequeue cache module is configured to determine whether the size of all HDLC frames in the dequeue cache module is greater than or equal to a preset threshold; and set to save the HDLC frame after the line rate processing;

The line rate processing module is configured to perform line rate processing on the HDLC frame in the enqueue buffer module when the dequeue cache module determines that the size of all HDLC frames in the dequeue cache module is greater than or equal to a preset threshold.

Optionally, the dequeue cache module is further configured to:

Determining whether the size of all HDLC frames in the outbound cache module is less than a preset threshold; and setting the non-linear velocity processed HDLC frame to the dequeue cache module;

The device further includes: a non-line rate processing module, configured to: when the dequeue cache module determines that the size of all HDLC frames in the dequeue cache module is less than a preset threshold, The HDLC frame in the memory module is subjected to non-line rate processing.

Optionally, the non-linear processing module is configured to:

When the dequeue cache module determines that the size of all the HDLC frames in the dequeue cache module is less than a preset threshold, a frame interval is added between two adjacent HDLC frames, so that the rate of the POS interface reaches the line rate.

Optionally, the line speed processing module is configured to:

When the dequeue cache module determines that the size of all the HDLC frames in the dequeue cache module is greater than or equal to a preset threshold, determine that the number of frame intervals between two adjacent HDLC frames is greater than one, and delete two adjacent frames. The frame interval between HDLC frames is such that the number of frame intervals between two adjacent HDLC frames is equal to one.

The embodiment of the invention further provides a computer readable storage medium storing program instructions, which can be implemented when the program instructions are executed.

Compared with the related art, the embodiment of the present invention includes: performing a point-to-point protocol PPP/class-type advanced data link control HDLC frame encapsulation of the HDLC frame on the synchronous optical fiber network to enter the queue buffer; The HDLC frame in the enqueue buffer is processed by the line rate of the HDLC frame in the enqueue buffer, and the HDLC frame processed by the line rate is dequeued. With the solution of the embodiment of the present invention, when the size of all the HDLC frames in the dequeue cache is greater than or equal to the preset threshold, the line rate of the HDLC frame in the enqueue buffer is processed, so that the rate of the POS interface reaches the line speed, and the POS interface speed is increased. Forwarding performance of the POS interface.

BRIEF abstract

1 is a schematic structural diagram of a POS framer in the related art;

2 is a flowchart of a method for implementing line speed processing according to an embodiment of the present invention;

3 is a schematic structural diagram of a device for implementing line speed processing according to an embodiment of the present invention;

4 is a flow chart of a method for implementing line speed processing according to an example of the present invention.

Embodiments of the invention

It should be noted that the various embodiments in the embodiments and the embodiments herein may be combined with each other without conflict.

Referring to FIG. 2, an embodiment of the present invention provides a method for implementing line rate processing, including:

Step 200: Enroll the HDLC frame encapsulated by the POS Mapper module into the PPP/HDLC protocol into the queue;

Step 201: Determine that the size of all the HDLC frames in the outbound cache is greater than or equal to a preset threshold, perform line rate processing on the HDLC frame in the enqueue buffer, and dequeue the HDLC frame processed by the line rate.

In this step, the preset threshold may be half the size of the dequeue cache.

In this step, the line rate processing of the HDLC frame in the enqueue buffer includes:

The frame interval between HDLC frames may be 0x7E, and the size of each frame interval is one byte.

The frame interval between HDLC frames can be deleted in multiple ways, so that the number of frame intervals between two adjacent HDLC frames is equal to one. For example, the number of frame intervals between two adjacent HDLC frames can be obtained, the difference between the obtained number of frame intervals and one is calculated, and the calculated difference frame interval between two adjacent HDLC frames is deleted. Or, the number of frame intervals between two adjacent HDLC frames is obtained. If it is determined that the number of obtained frame intervals is greater than one, the number of frame intervals between two adjacent HDLC frames is continuously performed; if it is determined that the obtained If the number of frame intervals is equal to one, the process of deleting the number of frame intervals between two adjacent HDLC frames is ended.

When it is determined that the size of all the HDLC frames in the queue buffer is less than the preset threshold, the HDLC frame in the enqueue buffer is subjected to non-line rate processing, and the non-line-speed processed HDLC frame is dequeued.

The non-line rate processing of the HDLC frame in the enqueue buffer includes:

A frame interval is added between two adjacent HDLC frames, so that the rate of the POS interface reaches the line rate. In the method of this embodiment, the POS Framer module performs POS encapsulation on the HDLC frame after the line rate processing in the dequeue cache or the HDLC frame after the non-line rate processing.

With the solution of the embodiment, when the size of all the HDLC frames in the dequeue buffer is greater than or equal to the preset threshold, the line rate of the HDLC frame in the enqueue buffer is processed, so that the rate of the POS interface reaches the line speed, and the POS is improved. Forwarding performance of the interface.

Referring to FIG. 3, an embodiment of the present invention further provides an apparatus for implementing line rate processing, including at least:

The enqueue cache module is configured to save the HDLC frame encapsulated by the POS Mapper module after PPP/HDLC protocol encapsulation;

The dequeue cache module is configured to determine whether the size of all HDLC frames in the dequeue cache module is greater than or equal to a preset threshold; and, is configured to save the HDLC frame after the line rate processing;

In the apparatus of this embodiment, the line speed processing module is set to:

When the dequeue cache module determines that the size of all HDLC frames in the outbound cache module is greater than or equal to a preset threshold, determining that the number of frame intervals between two adjacent HDLC frames is greater than one, and deleting between HDLC frames The frame interval is such that the number of frame intervals between two adjacent HDLC frames is equal to one.

In the apparatus of this embodiment, the dequeue cache module is further configured to:

Determining whether the size of all HDLC frames in the outbound cache module is less than a preset threshold; and setting the saved HDLC frame storage to the dequeue cache module;

The device further includes: a non-line rate processing module, configured to perform a non-line on the HDLC frame in the enqueue buffer module when the dequeue cache module determines that the size of all HDLC frames in the dequeue buffer module is less than a preset threshold Speed processing.

In the apparatus of this embodiment, the non-line rate processing module is set to:

When the dequeue cache module determines that the size of all the HDLC frames in the outbound cache module is less than the preset threshold, a frame interval is added between the two adjacent HDLC frames, so that the rate of the POS interface reaches the line rate.

An example is described below.

Referring to Figure 4, the method includes:

Step 400: In the downlink transmission, the POS Mapper module performs PPP/HDLC association on the data packet. Encapsulate the HDLC frame;

Step 401: The POS Mapper module saves the encapsulated HDLC frame to the enqueue cache module.

Step 402: The dequeue cache module determines whether the size of all HDLC frames in the queue buffer module is greater than or equal to a preset threshold, and if so, step 403 is performed, and if no, step 404 is performed;

Step 403: The line rate processing module performs line rate processing on the HDLC frame in the enqueue buffer module, and saves the line rate processed HDLC frame to the dequeue cache module.

Step 404: The non-line rate processing module performs non-line rate processing on the HDLC frame in the enqueue buffer module, and saves the non-line rate processed HDLC frame to the dequeue cache module.

One of ordinary skill in the art will appreciate that all or a portion of the above steps may be accomplished by a program that instructs the associated hardware, such as a read-only memory, a magnetic disk, or an optical disk. Alternatively, all or part of the steps of the above embodiments may also be implemented using one or more integrated circuits. Correspondingly, each module/unit in the foregoing embodiment may be implemented in the form of hardware or in the form of a software function module. Embodiments of the invention are not limited to any specific form of combination of hardware and software.

Industrial applicability

With the solution of the embodiment of the present invention, when the size of all the HDLC frames in the dequeue cache is greater than or equal to the preset threshold, the line rate of the HDLC frame in the enqueue buffer is processed, so that the rate of the POS interface reaches the line speed, and the POS interface speed is increased. Forwarding performance of the POS interface.

Claims

A method of implementing wire speed processing, comprising:

The packet POS mapping module on the synchronous optical network performs a point-to-point protocol PPP/class advanced data link control HDLC frame encapsulation of the HDLC protocol for enqueue buffering;

It is determined that the size of all the HDLC frames in the outbound cache is greater than or equal to a preset threshold, and the HDLC frame in the enqueue buffer is subjected to line rate processing, and the HDLC frame processed by the line rate is dequeued.
The method of claim 1 further comprising:

When it is determined that the size of all the HDLC frames in the dequeue buffer is less than a preset threshold, performing non-line rate processing on the HDLC frame in the enqueue buffer, and saving the non-line-speed processed HDLC frame to the out In the queue.
The method of claim 2 wherein said non-linear processing of HDLC frames in the enqueue buffer comprises:

A frame interval is added between two adjacent HDLC frames, so that the rate of the POS interface reaches the line rate.
The method according to claim 1 or 2, wherein said performing line rate processing on the HDLC frame in the enqueue buffer comprises:

It is determined that the number of frame intervals between two adjacent HDLC frames is greater than one, and the frame interval between two adjacent HDLC frames is deleted, so that the number of frame intervals between two adjacent HDLC frames is equal to one.
A device for implementing wire speed processing, comprising:

The enqueue cache module is configured to save the data packet POS mapping module on the synchronous optical network to perform a point-to-point protocol PPP/class advanced data link to control the HDLC frame encapsulated by the HDLC protocol;

The dequeue cache module is configured to determine whether the size of all HDLC frames in the dequeue cache module is greater than or equal to a preset threshold; and, is configured to save the HDLC frame after the line rate processing;

The line rate processing module is configured to perform line rate processing on the HDLC frame in the enqueue buffer module when the dequeue cache module determines that the size of all HDLC frames in the dequeue cache module is greater than or equal to a preset threshold.
The device according to claim 5,

The dequeue cache module is further configured to: determine the size of all HDLC frames in the queue cache module Whether it is less than a preset threshold; and is configured to save the non-line-speed processed HDLC frame to the dequeue cache module;

The device further includes: a non-line rate processing module, configured to: when the dequeue cache module determines that the size of all HDLC frames in the dequeue cache module is less than a preset threshold, in the enqueue cache module The HDLC frame is subjected to non-line rate processing.
The apparatus of claim 6 wherein said non-linear rate processing module is configured to:

When the dequeue cache module determines that the size of all the HDLC frames in the dequeue cache module is less than a preset threshold, a frame interval is added between two adjacent HDLC frames, so that the rate of the POS interface reaches the line rate.
The apparatus according to claim 5 or 6, wherein the line speed processing module is configured to:

When the dequeue cache module determines that the size of all the HDLC frames in the dequeue cache module is greater than or equal to a preset threshold, determine that the number of frame intervals between two adjacent HDLC frames is greater than one, and delete two adjacent frames. The frame interval between HDLC frames is such that the number of frame intervals between two adjacent HDLC frames is equal to one.
A computer readable storage medium storing program instructions that, when executed, can implement the method of any of claims 1-4.