WO2016095412A1 - Procédé et dispositif de traitement de vitesse de fil - Google Patents

Procédé et dispositif de traitement de vitesse de fil Download PDF

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Publication number
WO2016095412A1
WO2016095412A1 PCT/CN2015/078693 CN2015078693W WO2016095412A1 WO 2016095412 A1 WO2016095412 A1 WO 2016095412A1 CN 2015078693 W CN2015078693 W CN 2015078693W WO 2016095412 A1 WO2016095412 A1 WO 2016095412A1
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hdlc
frame
dequeue
frames
cache module
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PCT/CN2015/078693
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English (en)
Chinese (zh)
Inventor
何波
陈谡
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中兴通讯股份有限公司
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Publication of WO2016095412A1 publication Critical patent/WO2016095412A1/fr

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  • This paper relates to the field of data communication, especially a method and device for implementing line rate processing.
  • Packet over SONET (SD) technology enables high-performance routers to adopt SONET/SDH frames on the backbone network.
  • IP Internet Protocol
  • An important indicator in the switching and forwarding of backbone network equipment is called line speed.
  • the line speed refers to the maximum number of frames that the cable can pass in unit time.
  • the POS technology uses the Point-to-Point Protocol (PPP) encapsulation format of the High-Level Data Link Control (HDLC) at the data link layer.
  • PPP Point-to-Point Protocol
  • HDLC frame protocol specifies the start of the HDLC frame. The end and the end are identified by the hexadecimal identifier 0x7E.
  • FIG. 1 is a schematic structural diagram of a related art POS framer.
  • the POS framer includes a POS mapping (Mapper) module (PPP/HDLC protocol frame framing module) and a POS framing (Framer) module (POS frame framing module).
  • the POS Mapper module is configured to perform PPP/HDLC encapsulation on the data packet to obtain an HDLC frame, and then the POS Mapper module performs non-line rate processing on the HDLC frame according to the POS protocol (that is, to ensure continuity between HDLC frames).
  • the POS Framer module is used to encapsulate the POS frame of the HDLC frame after the non-linear rate processing.
  • the non-line rate processing of the HDLC frame introduces a multi-byte 0x7E overhead, and the cost of the POS interface fails to reach the line rate, thereby reducing the forwarding performance of the POS interface.
  • the embodiment of the invention provides a method and a device for implementing line rate processing, which can improve the forwarding performance of the POS interface.
  • the embodiment of the invention provides a method for implementing line rate processing, including:
  • the packet POS mapping module on the synchronous optical network performs a point-to-point protocol PPP/class advanced data link control HDLC frame encapsulation of the HDLC protocol for enqueue buffering;
  • the size of all the HDLC frames in the outbound cache is greater than or equal to a preset threshold, and the HDLC frame in the enqueue buffer is subjected to line rate processing, and the HDLC frame processed by the line rate is dequeued.
  • the dequeue buffer when it is determined that the size of all the HDLC frames in the dequeue buffer is less than a preset threshold, performing non-linear processing on the HDLC frame in the enqueue buffer, and saving the non-linear velocity processed HDLC frame. Go to the dequeue cache.
  • the performing non-line rate processing on the HDLC frame in the enqueue buffer includes:
  • a frame interval is added between two adjacent HDLC frames, so that the rate of the POS interface reaches the line rate.
  • performing line-speed processing on the HDLC frame in the enqueue buffer includes:
  • An embodiment of the present invention further provides an apparatus for implementing line rate processing, including:
  • the enqueue cache module is configured to save the data packet POS mapping module on the synchronous optical network to perform a point-to-point protocol PPP/class advanced data link to control the HDLC frame encapsulated by the HDLC protocol;
  • the dequeue cache module is configured to determine whether the size of all HDLC frames in the dequeue cache module is greater than or equal to a preset threshold; and set to save the HDLC frame after the line rate processing;
  • the line rate processing module is configured to perform line rate processing on the HDLC frame in the enqueue buffer module when the dequeue cache module determines that the size of all HDLC frames in the dequeue cache module is greater than or equal to a preset threshold.
  • the dequeue cache module is further configured to:
  • the device further includes: a non-line rate processing module, configured to: when the dequeue cache module determines that the size of all HDLC frames in the dequeue cache module is less than a preset threshold, The HDLC frame in the memory module is subjected to non-line rate processing.
  • a non-line rate processing module configured to: when the dequeue cache module determines that the size of all HDLC frames in the dequeue cache module is less than a preset threshold, The HDLC frame in the memory module is subjected to non-line rate processing.
  • the non-linear processing module is configured to:
  • the dequeue cache module determines that the size of all the HDLC frames in the dequeue cache module is less than a preset threshold, a frame interval is added between two adjacent HDLC frames, so that the rate of the POS interface reaches the line rate.
  • the line speed processing module is configured to:
  • the dequeue cache module determines that the size of all the HDLC frames in the dequeue cache module is greater than or equal to a preset threshold, determine that the number of frame intervals between two adjacent HDLC frames is greater than one, and delete two adjacent frames.
  • the frame interval between HDLC frames is such that the number of frame intervals between two adjacent HDLC frames is equal to one.
  • the embodiment of the invention further provides a computer readable storage medium storing program instructions, which can be implemented when the program instructions are executed.
  • the embodiment of the present invention includes: performing a point-to-point protocol PPP/class-type advanced data link control HDLC frame encapsulation of the HDLC frame on the synchronous optical fiber network to enter the queue buffer;
  • the HDLC frame in the enqueue buffer is processed by the line rate of the HDLC frame in the enqueue buffer, and the HDLC frame processed by the line rate is dequeued.
  • the line rate of the HDLC frame in the enqueue buffer is processed, so that the rate of the POS interface reaches the line speed, and the POS interface speed is increased. Forwarding performance of the POS interface.
  • FIG. 1 is a schematic structural diagram of a POS framer in the related art
  • FIG. 2 is a flowchart of a method for implementing line speed processing according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a device for implementing line speed processing according to an embodiment of the present invention.
  • FIG. 4 is a flow chart of a method for implementing line speed processing according to an example of the present invention.
  • an embodiment of the present invention provides a method for implementing line rate processing, including:
  • Step 200 Enroll the HDLC frame encapsulated by the POS Mapper module into the PPP/HDLC protocol into the queue;
  • Step 201 Determine that the size of all the HDLC frames in the outbound cache is greater than or equal to a preset threshold, perform line rate processing on the HDLC frame in the enqueue buffer, and dequeue the HDLC frame processed by the line rate.
  • the preset threshold may be half the size of the dequeue cache.
  • the line rate processing of the HDLC frame in the enqueue buffer includes:
  • the frame interval between HDLC frames may be 0x7E, and the size of each frame interval is one byte.
  • the frame interval between HDLC frames can be deleted in multiple ways, so that the number of frame intervals between two adjacent HDLC frames is equal to one.
  • the number of frame intervals between two adjacent HDLC frames can be obtained, the difference between the obtained number of frame intervals and one is calculated, and the calculated difference frame interval between two adjacent HDLC frames is deleted.
  • the number of frame intervals between two adjacent HDLC frames is obtained. If it is determined that the number of obtained frame intervals is greater than one, the number of frame intervals between two adjacent HDLC frames is continuously performed; if it is determined that the obtained If the number of frame intervals is equal to one, the process of deleting the number of frame intervals between two adjacent HDLC frames is ended.
  • the HDLC frame in the enqueue buffer is subjected to non-line rate processing, and the non-line-speed processed HDLC frame is dequeued.
  • the non-line rate processing of the HDLC frame in the enqueue buffer includes:
  • a frame interval is added between two adjacent HDLC frames, so that the rate of the POS interface reaches the line rate.
  • the POS Framer module performs POS encapsulation on the HDLC frame after the line rate processing in the dequeue cache or the HDLC frame after the non-line rate processing.
  • the line rate of the HDLC frame in the enqueue buffer is processed, so that the rate of the POS interface reaches the line speed, and the POS is improved. Forwarding performance of the interface.
  • an embodiment of the present invention further provides an apparatus for implementing line rate processing, including at least:
  • the enqueue cache module is configured to save the HDLC frame encapsulated by the POS Mapper module after PPP/HDLC protocol encapsulation;
  • the dequeue cache module is configured to determine whether the size of all HDLC frames in the dequeue cache module is greater than or equal to a preset threshold; and, is configured to save the HDLC frame after the line rate processing;
  • the line rate processing module is configured to perform line rate processing on the HDLC frame in the enqueue buffer module when the dequeue cache module determines that the size of all HDLC frames in the dequeue cache module is greater than or equal to a preset threshold.
  • the line speed processing module is set to:
  • the dequeue cache module determines that the size of all HDLC frames in the outbound cache module is greater than or equal to a preset threshold, determining that the number of frame intervals between two adjacent HDLC frames is greater than one, and deleting between HDLC frames
  • the frame interval is such that the number of frame intervals between two adjacent HDLC frames is equal to one.
  • the dequeue cache module is further configured to:
  • the device further includes: a non-line rate processing module, configured to perform a non-line on the HDLC frame in the enqueue buffer module when the dequeue cache module determines that the size of all HDLC frames in the dequeue buffer module is less than a preset threshold Speed processing.
  • a non-line rate processing module configured to perform a non-line on the HDLC frame in the enqueue buffer module when the dequeue cache module determines that the size of all HDLC frames in the dequeue buffer module is less than a preset threshold Speed processing.
  • the non-line rate processing module is set to:
  • the dequeue cache module determines that the size of all the HDLC frames in the outbound cache module is less than the preset threshold, a frame interval is added between the two adjacent HDLC frames, so that the rate of the POS interface reaches the line rate.
  • the method includes:
  • Step 400 In the downlink transmission, the POS Mapper module performs PPP/HDLC association on the data packet. Encapsulate the HDLC frame;
  • Step 401 The POS Mapper module saves the encapsulated HDLC frame to the enqueue cache module.
  • Step 402 The dequeue cache module determines whether the size of all HDLC frames in the queue buffer module is greater than or equal to a preset threshold, and if so, step 403 is performed, and if no, step 404 is performed;
  • Step 403 The line rate processing module performs line rate processing on the HDLC frame in the enqueue buffer module, and saves the line rate processed HDLC frame to the dequeue cache module.
  • Step 404 The non-line rate processing module performs non-line rate processing on the HDLC frame in the enqueue buffer module, and saves the non-line rate processed HDLC frame to the dequeue cache module.
  • the line rate of the HDLC frame in the enqueue buffer is processed, so that the rate of the POS interface reaches the line speed, and the POS interface speed is increased. Forwarding performance of the POS interface.

Abstract

La présente invention porte, dans un mode de réalisation, sur un procédé et sur un dispositif de traitement de vitesse de fil. Le procédé consiste à : effectuer une mise en mémoire tampon d'une mise en file d'attente sur une trame de commande de lien de données de haut niveau (HDLC pour High-level Data Link Control) conditionnée par l'intermédiaire d'un protocole point-à-point (PPP pour Point-to-Point Protocol)/protocole de commande HDLC effectué par un module de mappeur de paquet sur réseau optique synchrone (POS) ; si les tailles de toutes les trames de commande HDLC dans une mémoire tampon de retrait de file d'attente sont établies de sorte à être supérieures ou égales à un seuil prédéterminé, effectuer ensuite un traitement de vitesse de fil sur la trame de commande HDLC dans une mémoire tampon de mise en file d'attente et sauvegarder la trame de commande HDLC traitée dans la mémoire tampon de retrait de file d'attente.
PCT/CN2015/078693 2014-12-17 2015-05-11 Procédé et dispositif de traitement de vitesse de fil WO2016095412A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410789757.3A CN105791158B (zh) 2014-12-17 2014-12-17 一种实现线速处理的方法和装置
CN201410789757.3 2014-12-17

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WO2016095412A1 true WO2016095412A1 (fr) 2016-06-23

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090175278A1 (en) * 2003-03-24 2009-07-09 Corrigent Systems Ltd. Efficient transport of tdm services over packet networks
US20090207861A1 (en) * 2008-02-15 2009-08-20 Ibiquity Digital Corporation Method and Apparatus For Formatting Data Signals in a Digital Audio Broadcasting System
US20090290587A1 (en) * 2008-05-23 2009-11-26 Fujitsu Limited Method and apparatus for transmitting data from asynchronous network via synchronous network
CN101640615A (zh) * 2009-09-08 2010-02-03 杭州华三通信技术有限公司 一种pos端口扰码配置检测的方法和设备
CN102487330A (zh) * 2010-12-02 2012-06-06 中兴通讯股份有限公司 运行、管理和维护报文的发送方法及装置
CN102647243A (zh) * 2012-03-23 2012-08-22 华为技术有限公司 一种报文下插的方法、站点及系统

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090175278A1 (en) * 2003-03-24 2009-07-09 Corrigent Systems Ltd. Efficient transport of tdm services over packet networks
US20090207861A1 (en) * 2008-02-15 2009-08-20 Ibiquity Digital Corporation Method and Apparatus For Formatting Data Signals in a Digital Audio Broadcasting System
US20090290587A1 (en) * 2008-05-23 2009-11-26 Fujitsu Limited Method and apparatus for transmitting data from asynchronous network via synchronous network
CN101640615A (zh) * 2009-09-08 2010-02-03 杭州华三通信技术有限公司 一种pos端口扰码配置检测的方法和设备
CN102487330A (zh) * 2010-12-02 2012-06-06 中兴通讯股份有限公司 运行、管理和维护报文的发送方法及装置
CN102647243A (zh) * 2012-03-23 2012-08-22 华为技术有限公司 一种报文下插的方法、站点及系统

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CN105791158A (zh) 2016-07-20

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