CN105791158B - Method and device for realizing linear speed processing - Google Patents
Method and device for realizing linear speed processing Download PDFInfo
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- CN105791158B CN105791158B CN201410789757.3A CN201410789757A CN105791158B CN 105791158 B CN105791158 B CN 105791158B CN 201410789757 A CN201410789757 A CN 201410789757A CN 105791158 B CN105791158 B CN 105791158B
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Abstract
The invention discloses a method and a device for realizing linear speed processing, which comprises the following steps: performing enqueue caching on an HDLC frame packaged by a point-to-point protocol PPP/class high-level data link control HDLC protocol by a data packet POS mapping Mapper module on a synchronous optical fiber network; and judging that the sizes of all HDLC frames in the dequeue cache are larger than or equal to a preset threshold value, performing line speed processing on the HDLC frames in the enqueue cache, and storing the HDLC frames after line speed processing into the dequeue cache. According to the scheme of the invention, when the sizes of all HDLC frames in the dequeue cache are larger than or equal to the preset threshold, the HDLC frames in the enqueue cache are subjected to line speed processing, so that the speed of the POS interface reaches the line speed, and the forwarding performance of the POS interface is improved.
Description
Technical Field
The present invention relates to the field of data communications, and in particular, to a method and apparatus for implementing line speed processing.
Background
In Synchronous Optical Network (SONET)/Synchronous Digital Hierarchy (SDH), the Packet Over SONET (POS) technology enables a high-performance router to transmit an Internet Protocol (IP) message by adopting SONET/SDH frames on a backbone Network. An important index in the switching and forwarding of backbone network equipment is the line speed, which is the maximum number of frames that a cable passes in unit time theoretically. The POS technology uses a Point-to-Point Protocol (PPP) encapsulation format similar to High-Level DataLink Control (HDLC) at a data link layer, where the HDLC frame Protocol specifies that the beginning and the end of an HDLC frame are identified by a hexadecimal identifier 0x7E, and the interval between two adjacent HDLC frames requires 0x7E of at least one byte when the HDLC frames are transmitted at linear speed on a line. Fig. 1 is a schematic diagram of the structure of a conventional POS framer. As shown in fig. 1, the POS Framer includes a POS mapping (Mapper) module (PPP/HDLC protocol frame framing module) and a POS framing (Framer) module (POS frame framing module). In the downlink transmission, the POS Mapper module is configured to perform PPP/HDLC protocol encapsulation on the data packet to obtain an HDLC frame, then perform non-linear-speed processing on the HDLC frame according to the POS protocol (i.e., to ensure continuity between the HDLC frames, a frame interval of 0x7E is added between the HDLC frames), and the POS Framer module is configured to perform POS frame encapsulation on the HDLC frame after the non-linear-speed processing. Due to the fact that 0x7E overhead of a plurality of bytes is introduced after the HDLC frame is subjected to non-linear speed processing, the speed of the POS interface cannot reach the linear speed due to the overhead of the plurality of bytes, and therefore the forwarding performance of the POS interface is reduced.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method and an apparatus for implementing line speed processing, which can improve the forwarding performance of a POS interface.
In order to achieve the above object, the present invention provides a method for implementing line speed processing, including:
performing enqueue caching on an HDLC frame packaged by a point-to-point protocol PPP/class high-level data link control HDLC protocol by a data packet POS mapping Mapper module on a synchronous optical fiber network;
judging that the sizes of all HDLC frames in the dequeue cache are larger than or equal to a preset threshold value, performing line speed processing on the HDLC frames in the enqueue cache, and dequeuing and caching the HDLC frames after line speed processing.
Preferably, when it is determined that the sizes of all HDLC frames in the dequeue buffer are smaller than the preset threshold, the method further includes:
and performing non-linear speed processing on the HDLC frame in the enqueue cache module, and storing the HDLC frame after the non-linear speed processing into the dequeue cache.
Preferably, the non-line-speed processing of the HDLC frames in the enqueue buffer includes:
and adding a frame interval between two adjacent HDLC frames so that the rate of the POS interface reaches the linear speed.
Preferably, the line-speed processing of the HDLC frames in the enqueue buffer includes:
and judging that the number of the frame intervals between two adjacent HDLC frames is more than one, and deleting the frame intervals between two adjacent HDLC frames to enable the number of the frame intervals between two adjacent HDLC frames to be equal to one.
The invention also provides a device for realizing linear speed processing, which at least comprises:
the enqueue cache module is used for storing an HDLC frame after the point-to-point protocol PPP/class high-level data link control HDLC protocol encapsulation is carried out by a data packet POS mapping Mapper module on the synchronous optical fiber network;
the dequeue cache module is used for judging that the sizes of all HDLC frames in the dequeue cache module are larger than or equal to a preset threshold value; storing the HDLC frame after the linear speed processing;
and the line speed processing module is used for performing line speed processing on the HDLC frames in the enqueue cache module when the dequeue cache module judges that the sizes of all the HDLC frames in the dequeue cache module are greater than or equal to a preset threshold value.
Preferably, the dequeue cache module is further configured to:
judging that the sizes of all HDLC frames in the dequeuing cache module are smaller than a preset threshold value; storing the HDLC frame after the non-linear speed encapsulation into the dequeuing cache module;
further comprising:
and the non-linear speed processing module is used for performing non-linear speed processing on the HDLC frames in the enqueue cache module when the dequeue cache module judges that the sizes of all the HDLC frames in the dequeue cache module are smaller than a preset threshold value.
Preferably, the non-linear speed processing module is specifically configured to:
and when the dequeue cache module judges that the sizes of all the HDLC frames in the dequeue cache module are smaller than a preset threshold value, adding a frame interval between every two adjacent HDLC frames to enable the rate of the POS interface to reach the line speed.
Preferably, the line speed processing module is specifically configured to:
and when the dequeue cache module judges that the sizes of all the HDLC frames in the dequeue cache module are larger than or equal to a preset threshold value, judging that the number of the frame intervals between two adjacent HDLC frames is larger than one, and deleting the frame intervals between two adjacent HDLC frames to enable the number of the frame intervals between two adjacent HDLC frames to be equal to one.
Compared with the prior art, the invention comprises the following steps: performing enqueue caching on an HDLC frame packaged by a point-to-point protocol PPP/class high-level data link control HDLC protocol by a data packet POS mapping Mapper module on a synchronous optical fiber network; judging that the sizes of all HDLC frames in the dequeue cache are larger than or equal to a preset threshold value, performing line speed processing on the HDLC frames in the enqueue cache, and dequeuing and caching the HDLC frames after line speed processing. According to the scheme of the invention, when the sizes of all HDLC frames in the dequeue cache are larger than or equal to the preset threshold, the HDLC frames in the enqueue cache are subjected to line speed processing, so that the speed of the POS interface reaches the line speed, and the forwarding performance of the POS interface is improved.
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The accompanying drawings in the embodiments of the present invention are described below, and the drawings in the embodiments are provided for further understanding of the present invention, and together with the description serve to explain the present invention without limiting the scope of the present invention.
FIG. 1 is a block diagram of a conventional POS framer;
FIG. 2 is a flow chart of a method of implementing line speed processing in accordance with the present invention;
FIG. 3 is a schematic structural diagram of an apparatus for implementing line speed processing according to the present invention;
FIG. 4 is a flow chart of an embodiment of a method of implementing line speed processing of the present invention.
Detailed Description
The following further description of the present invention, in order to facilitate understanding of those skilled in the art, is provided in conjunction with the accompanying drawings and is not intended to limit the scope of the present invention. In the present application, the embodiments and various aspects of the embodiments may be combined with each other without conflict.
Referring to fig. 2, the present invention provides a method for implementing line speed processing, including:
and 200, enqueuing and caching the HDLC frame after the POS Mapper module performs PPP/HDLC protocol encapsulation.
In this step, the preset threshold may be half the size of the dequeue cache.
In this step, the line-speed processing of the HDLC frames in the enqueue cache includes:
and judging that the number of the frame intervals between two adjacent HDLC frames is more than one, and deleting the frame intervals between two adjacent HDLC frames to enable the number of the frame intervals between two adjacent HDLC frames to be equal to one.
The frame interval between HDLC frames may be 0x7E, where each frame interval is one byte in size.
The frame interval between the HDLC frames can be deleted by adopting various methods, so that the number of the frame intervals between two adjacent HDLC frames is equal to one. For example, the number of frame intervals between two adjacent HDLC frames may be obtained, the difference between the obtained number of frame intervals and one may be calculated, and the calculated difference between two adjacent HDLC frames may be deleted by one frame interval. Or acquiring the number of frame intervals between two adjacent HDLC frames, and if the acquired number of frame intervals is judged to be more than one, continuously acquiring the number of frame intervals between two adjacent HDLC frames; and if the obtained frame interval number is judged to be equal to one, ending the flow of deleting the frame interval number between two adjacent HDLC frames.
In this step, when it is determined that the sizes of all the HDLC frames in the dequeue cache are smaller than the preset threshold, the HDLC frames in the enqueue cache are subjected to non-linear-speed processing, and the HDLC frames after the non-linear-speed processing are dequeued and cached.
Wherein the non-line-speed packaging the HDLC frame in the enqueue buffer comprises the following steps:
and adding a frame interval between two adjacent HDLC frames so that the rate of the POS interface reaches the linear speed. The detailed implementation is a matter of routine skill for those skilled in the art, and is not intended to limit the scope of the present invention, which is not described herein.
In the method, the POS Framer module carries out POS encapsulation on the HDLC frame after the line speed encapsulation or the HDLC frame after the line speed encapsulation in the dequeue cache.
According to the scheme of the invention, when the sizes of all HDLC frames in the dequeue cache are larger than or equal to the preset threshold, the speed limit processing module performs linear speed processing on the HDLC frames in the enqueue cache, so that the speed of the POS interface reaches the linear speed, and the forwarding performance of the POS interface is improved.
Referring to fig. 3, the present invention further provides an apparatus for implementing line speed processing, which at least includes:
the enqueue cache module is used for storing the HDLC frame encapsulated by the PPP/HDLC protocol of the POS Mapper module;
the dequeue cache module is used for judging that the sizes of all HDLC frames in the dequeue cache module are larger than or equal to a preset threshold value; storing the HDLC frame after the linear speed processing;
and the line speed processing module is used for performing line speed processing on the HDLC frames in the enqueue cache module when the dequeue cache module judges that the sizes of all the HDLC frames in the dequeue cache module are greater than or equal to a preset threshold value.
In the apparatus of the present invention, the linear velocity processing module is specifically configured to:
and when the dequeue cache module judges that the sizes of all the HDLC frames in the dequeue cache module are larger than or equal to a preset threshold value, judging that the number of the frame intervals between two adjacent HDLC frames is larger than one, and deleting the frame intervals between the HDLC frames to enable the number of the frame intervals between two adjacent HDLC frames to be equal to one.
In the apparatus of the present invention, the dequeue cache module is further configured to:
judging that the sizes of all HDLC frames in the dequeuing cache module are smaller than a preset threshold value; storing the HDLC frame after the non-linear speed processing into a dequeue cache module;
further comprising:
and the non-linear speed processing module is used for performing non-linear speed processing on the HDLC frames in the enqueue cache module when the dequeue cache module judges that the sizes of all the HDLC frames in the dequeue cache module are smaller than a preset threshold value.
In the apparatus of the present invention, the non-linear velocity processing module is specifically configured to:
and when the dequeue cache module judges that the sizes of all the HDLC frames in the dequeue cache module are smaller than a preset threshold value, adding a frame interval between every two adjacent HDLC frames to enable the rate of the POS interface to reach the line speed.
The method of the present invention is described in detail below.
Referring to fig. 4, the method includes:
And step 404, the non-linear speed processing module performs non-linear speed processing on the HDLC frame in the enqueue cache module, and stores the HDLC frame after the non-linear speed processing in the dequeue cache module.
It should be noted that the above-mentioned embodiments are only for facilitating the understanding of those skilled in the art, and are not intended to limit the scope of the present invention, and any obvious substitutions, modifications, etc. made by those skilled in the art without departing from the inventive concept of the present invention are within the scope of the present invention.
Claims (6)
1. A method for implementing line speed processing, comprising:
performing enqueue caching on an HDLC frame packaged by a point-to-point protocol PPP/class high-level data link control HDLC protocol by a data packet POS mapping Mapper module on a synchronous optical fiber network;
judging that the sizes of all HDLC frames in the dequeue cache are larger than or equal to a preset threshold value, performing line speed processing on the HDLC frames in the enqueue cache, and dequeuing and caching the HDLC frames after line speed processing;
the line speed processing of the HDLC frame in the enqueue buffer comprises the following steps:
acquiring the frame interval quantity between two adjacent HDLC frames, calculating the difference between the acquired frame interval quantity and one, and deleting the difference frame interval between the two adjacent HDLC frames.
2. The method of claim 1, wherein when the size of all HDLC frames in the dequeue buffer is determined to be smaller than a predetermined threshold, the method further comprises:
and performing non-linear speed processing on the HDLC frame in the enqueue cache module, and storing the HDLC frame after the non-linear speed processing into the dequeue cache.
3. The method of claim 2, wherein non-line-speed processing the HDLC frames in the enqueue buffer comprises:
and adding a frame interval between two adjacent HDLC frames so that the rate of the POS interface reaches the linear speed.
4. An apparatus for implementing line speed processing, comprising at least:
the enqueue cache module is used for storing an HDLC frame after the point-to-point protocol PPP/class high-level data link control HDLC protocol encapsulation is carried out by a data packet POS mapping Mapper module on the synchronous optical fiber network;
the dequeue cache module is used for judging that the sizes of all HDLC frames in the dequeue cache module are larger than or equal to a preset threshold value; storing the HDLC frame after the linear speed processing;
the line speed processing module is used for performing line speed processing on the HDLC frames in the enqueue cache module when the dequeue cache module judges that the sizes of all the HDLC frames in the dequeue cache module are larger than or equal to a preset threshold value;
the line speed processing of the HDLC frame in the enqueue buffer comprises the following steps:
acquiring the frame interval quantity between two adjacent HDLC frames, calculating the difference between the acquired frame interval quantity and one, and deleting the difference frame interval between the two adjacent HDLC frames.
5. The apparatus of claim 4, wherein the dequeue cache module is further configured to:
judging that the sizes of all HDLC frames in the dequeuing cache module are smaller than a preset threshold value; storing the HDLC frame after the non-linear speed encapsulation into the dequeuing cache module;
further comprising:
and the non-linear speed processing module is used for performing non-linear speed processing on the HDLC frames in the enqueue cache module when the dequeue cache module judges that the sizes of all the HDLC frames in the dequeue cache module are smaller than a preset threshold value.
6. The apparatus of claim 5, wherein the non-wire-speed processing module is specifically configured to:
and when the dequeue cache module judges that the sizes of all the HDLC frames in the dequeue cache module are smaller than a preset threshold value, adding a frame interval between every two adjacent HDLC frames to enable the rate of the POS interface to reach the line speed.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410789757.3A CN105791158B (en) | 2014-12-17 | 2014-12-17 | Method and device for realizing linear speed processing |
| PCT/CN2015/078693 WO2016095412A1 (en) | 2014-12-17 | 2015-05-11 | Wire speed processing method and device |
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| CN201410789757.3A CN105791158B (en) | 2014-12-17 | 2014-12-17 | Method and device for realizing linear speed processing |
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| CN105791158B true CN105791158B (en) | 2020-06-26 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101640615A (en) * | 2009-09-08 | 2010-02-03 | 杭州华三通信技术有限公司 | Method and equipment for detecting POS port code disturbing configuration |
| CN102487330A (en) * | 2010-12-02 | 2012-06-06 | 中兴通讯股份有限公司 | Method and device for sending operation, administration and maintenance messages |
| CN102647243A (en) * | 2012-03-23 | 2012-08-22 | 华为技术有限公司 | Message interpolating method, site and system |
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| US7515605B2 (en) * | 2003-03-24 | 2009-04-07 | Corrigent Systems Ltd | Efficient transport of TDM services over packet networks |
| US8111716B2 (en) * | 2008-02-15 | 2012-02-07 | Ibiquity Digital Corporation | Method and apparatus for formatting data signals in a digital audio broadcasting system |
| JP5200660B2 (en) * | 2008-05-23 | 2013-06-05 | 富士通株式会社 | Transmission method and transmission apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101640615A (en) * | 2009-09-08 | 2010-02-03 | 杭州华三通信技术有限公司 | Method and equipment for detecting POS port code disturbing configuration |
| CN102487330A (en) * | 2010-12-02 | 2012-06-06 | 中兴通讯股份有限公司 | Method and device for sending operation, administration and maintenance messages |
| CN102647243A (en) * | 2012-03-23 | 2012-08-22 | 华为技术有限公司 | Message interpolating method, site and system |
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| CN105791158A (en) | 2016-07-20 |
| WO2016095412A1 (en) | 2016-06-23 |
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