WO2016095283A1 - 一种电感、电路板以及电感的实现方法 - Google Patents

一种电感、电路板以及电感的实现方法 Download PDF

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WO2016095283A1
WO2016095283A1 PCT/CN2014/095867 CN2014095867W WO2016095283A1 WO 2016095283 A1 WO2016095283 A1 WO 2016095283A1 CN 2014095867 W CN2014095867 W CN 2014095867W WO 2016095283 A1 WO2016095283 A1 WO 2016095283A1
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circuit board
inductor
pad
hole
metal trace
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PCT/CN2014/095867
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English (en)
French (fr)
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符俭泳
郭东胜
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深圳市华星光电技术有限公司
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Priority to US14/416,671 priority Critical patent/US9615459B2/en
Publication of WO2016095283A1 publication Critical patent/WO2016095283A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor

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  • the present invention relates to the field of power electronics, and in particular to an inductor, a circuit board, and an implementation method of an inductor.
  • the circuit symbol of the magnetic bead is the inductance, that is, the magnetic bead is the inductance.
  • the magnetic beads have a small inductance value and are easy to manufacture. They also have many features that are not found in ordinary inductors. For example, for a common inductor, due to the distributed capacitance, in the case of a high frequency (especially a high-order harmonic), the ordinary inductor may be equivalent to a capacitor, and thus cannot function as an inductor.
  • the magnetic beads do not have the above-mentioned defects of the ordinary inductance, and the magnetic beads have excellent high-frequency characteristics and have stable inductance characteristics in a high frequency environment. Therefore, as shown in Figure 1, the electronic engineer usually places one or even several magnetic beads (such as magnetic beads L1 and magnetic beads L2) at the power supply end and the like in order to better remove clutter. Suppresses noise and spikes on the power line.
  • the use of the magnetic beads removes the noise, but also causes the area of the circuit board to be too large, which greatly increases the production cost of the circuit board.
  • an embodiment of the present invention first provides an inductor, and the inductor includes:
  • the first hole has one end located in the first pad and the other end being located in the second pad, the first hole containing a conductive medium.
  • the first metal wiring layer and/or the second metal wiring layer is a surface metal wiring layer of the circuit board.
  • the inductor further comprises:
  • the second hole has one end located in the third pad and the other end being located in the fourth pad, the second hole containing a conductive medium.
  • the fourth metal wiring layer and the second metal wiring layer are the same metal wiring layer, and the fourth and second pads are connected by metal traces.
  • the third metal wiring layer and the first metal wiring layer are the same metal wiring layer, and the third pad and the first pad are connected by a metal trace.
  • the electrically conductive medium is copper, gold, silver or tin.
  • the present invention also provides a circuit board including the inductor as described above.
  • the present invention also provides a method of implementing an inductor that utilizes corresponding vias in a circuit board to form the desired inductance.
  • the inductance is formed by a plurality of vias connected in series or in parallel in the circuit board.
  • the required inductance value is obtained by adjusting the length of the via.
  • the existing circuit board uses the parasitic inductance of the via as a stray inductance.
  • the parasitic inductance of the via should be reduced as much as possible, thereby reducing the influence of the parasitic inductance of the via on the circuit.
  • the inductor provided by the present invention utilizes the parasitic inductance of the via hole, which not only can effectively solve the problem that the circuit design is difficult to be reduced due to the need to reduce the parasitic inductance of the via hole during circuit design, and can also Effectively reduce the footprint of the inductor in the board, thereby reducing the area and production cost of the entire board.
  • the thickness of the board is immutable (that is, the number of layers of the board and related parameters are determined, the thickness of the board is also fixed).
  • the minimum diameter of the hole provided on the circuit board is also relatively fixed (in order to meet the process requirements, the ratio of the diameter of the hole to the thickness of the circuit board cannot be less than a certain ratio) Therefore, the maximum inductance of the hole is relatively fixed.
  • the inductance required for the inductance in the circuit may exceed the maximum inductance that the hole can have. Therefore, to solve the problem, the present invention also provides an inductance obtained by connecting a plurality of via holes in series. This kind of inductance can have A larger inductance value, thereby getting rid of the limitation of the board thickness on the inductance value, which increases the application range of the inductor provided by the present invention.
  • the present invention also provides an inductor having a small inductance value obtained by using a plurality of via holes in parallel, thereby effectively reducing the processing difficulty and cost of the circuit board, and benefiting the cost and quality of the enterprise. control.
  • FIG. 1 is a circuit diagram of a conventional magnetic bead inductor connection circuit
  • FIG. 2 is a schematic structural view of an inductor according to an embodiment of the present invention.
  • FIG. 3 is a circuit diagram of an inductor connection circuit in accordance with one embodiment of the present invention.
  • FIG. 4 is a schematic structural view of an inductor according to another embodiment of the present invention.
  • FIG. 5 is a schematic structural view of an inductor according to still another embodiment of the present invention.
  • FIG. 6 is a schematic structural view of an inductor according to still another embodiment of the present invention.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • FIG. 2 is a schematic view showing the structure of the inductor provided in this embodiment.
  • the inductor provided in this embodiment includes a first pad 201, a second pad 202, and a first hole 203.
  • the first pad 201 is disposed on the first metal wiring layer 204a of the circuit board
  • the second pad 202 is disposed on the second metal wiring layer 204b of the circuit board.
  • One end of the first hole 203 is located in the first pad 201, and the other end is located in the second pad 202.
  • the first hole 203 also has a conductive medium.
  • the metallization process of the holes is used to cover the hole walls of the holes with a uniform layer of heat-resistant metal copper.
  • the metallization process specifically includes processes such as de-staining, chemical copper sinking, and thickening of copper.
  • the conductive medium contained in the first hole may also be other reasonable conductive. Materials such as gold, silver or tin, etc., the invention is not limited thereto.
  • the first metal trace layer 204a and the second metal trace layer 204b are the surface metal trace layers of the circuit board, so that the first hole 203 also penetrates the circuit board. Through hole.
  • the first metal wiring layer and/or the second metal wiring layer may also be located in other layers of the circuit board, so that the first hole becomes a buried hole or a blind hole in the circuit board. The invention is not limited thereto.
  • the inductance value L thereof can be calculated by the following expression:
  • h represents the length of the first hole (that is, the thickness of the circuit board in this embodiment), and d represents the diameter of the first hole.
  • the board thickness is 0.04 inches, and the first hole in the board has a diameter of 0.01 inch.
  • the inductance of the first hole can be calculated by the expression (1) to be 0.77 nH.
  • the inductance L of the hole is related to the length h of the hole and the diameter d, but the change in the diameter d has a small influence on the inductance L. Therefore, in various embodiments of the present invention, the required inductance value can be obtained by appropriately adjusting the length of the hole (for example, adjusting the metal wiring layer where the two ports of the hole are located, etc.). Of course, in other embodiments of the present invention, the holes may have the required inductance value by other reasonable means, and the present invention is not limited thereto.
  • FIG. 3 is a schematic circuit diagram of the inductor connection circuit provided by the embodiment. As can be seen by comparing FIG. 1 with FIG. 3, the inductance provided in this embodiment is realized by a via hole in the circuit board, so that similarity does not occur. Magnetic beads need to occupy a large amount of area in the board.
  • Vias are one of the important components of a circuit board, and vias have parasitic inductance.
  • the parasitic inductance of vias often causes more damage than parasitic capacitance.
  • the parasitic inductance of the via weakens the effect of the bypass capacitor, thereby attenuating the filtering effect of the entire filter circuit.
  • the existing circuit board uses the parasitic inductance of the via as a stray inductance.
  • the inductor provided in this embodiment utilizes the parasitic inductance of the via hole, which not only can effectively solve the problem that the circuit design is difficult to be reduced due to the need to reduce the parasitic inductance of the via hole during circuit design, and
  • the use of vias in the board can be effectively utilized to reduce the footprint of the inductor in the board, thereby reducing the area and cost of the entire board.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the thickness of the board is immutable (that is, after determining the number of layers used and related parameters of the board, the thickness of the board is also fixed).
  • the minimum diameter of the hole provided on the circuit board is also relatively fixed (in order to meet the process requirements, the ratio of the diameter of the hole to the thickness of the circuit board cannot be less than a certain value. The ratio), so from the expression (1), the maximum inductance of the hole is relatively fixed.
  • FIG. 4 is a schematic view showing the structure of the inductor provided in this embodiment.
  • the inductor provided in this embodiment includes a first pad 401a, a second pad 401b, a first hole 401c, a third pad 402a, a fourth pad 402b, and a second hole 402c.
  • the first pad 401a and the third pad 402a are respectively located on the first metal trace layer and the third metal trace layer of the circuit board, and the second pad 401b and the fourth pad 402b are respectively located on the second board.
  • a metal trace layer and a fourth metal trace layer are respectively located on the first metal trace layer and the third metal trace layer of the circuit board, and the second pad 401b and the fourth pad 402b are respectively located on the second board.
  • a metal trace layer and a fourth metal trace layer are respectively located on the first metal trace layer and the third metal trace layer.
  • the third metal trace layer and the fourth metal trace layer are also the same metal trace layer.
  • One end of the first hole 401c is located in the first pad and the other end is located in the second pad.
  • One end of the second hole 402c is located in the third pad, and the other end is located in the fourth pad.
  • a conductive medium for example, copper, gold, silver or tin
  • the second pad 401b and the fourth pad 402b are connected by a metal trace.
  • the inductance value of the resulting inductor will be the inductance of the first hole and the inductance of the second hole. The sum of the values thus overcomes the limitation of the thickness of the board to the inductance of the hole, so that the range of application of the inductor provided by the embodiment is wider.
  • the metal trace layer in which the four pads are located may be the surface metal trace layer of the circuit board or the intermediate metal trace layer of the circuit board, that is, the first hole.
  • the second hole may be a through hole, a blind hole or a buried hole, and the invention is not limited thereto.
  • the structure of the inductor shown in FIG. 5 is compared with the inductor shown in FIG. 4, the third pad 502a of the inductor shown in FIG. 5 is located in the middle metal trace layer, and the fourth pad is still located on the surface metal trace.
  • the inductance shown in FIG. 5 can be regarded as an inductance composed of a through hole and a blind hole in series.
  • three or more holes may be connected in series based on the same principle to obtain an inductance having a large inductance value, and the present invention is not limited thereto.
  • the inductor provided in this embodiment also replaces the inductance (such as a magnetic bead, etc.) in the existing circuit by using a via hole in the circuit board.
  • the inductor provided in this embodiment obtains a larger inductance value by connecting a plurality of via holes in series, thereby getting rid of the limitation of the circuit board thickness on the inductance value of the via hole, which increases the number provided by the embodiment. The range of applications of the inductor.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the maximum inductance value of the hole in the circuit board is relatively fixed (that is, the inductance value of the through hole). Therefore, for some circuits that require a small inductance value, it is necessary to obtain the required inductance value by reducing the length of the hole (that is, using a buried hole or a blind hole).
  • the production difficulty and cost of the buried hole or the blind hole are much higher than the production difficulty and cost of the through hole. Therefore, in order to solve the above problem, the embodiment provides an inductance as shown in FIG. 6.
  • the inductor provided in this embodiment is similar to the inductor shown in FIG. 4, and the inductor also includes two pairs of pads and two holes.
  • the first pad 601a and the third pad 602a are connected by a metal trace, and the second pad 601b and the fourth pad 602b are also connected by a metal trace.
  • the first hole 601c and the second hole 602c can be regarded as parallel, and the two inductors connected in parallel have a smaller inductance value. Therefore, the inductor provided in this embodiment obtains a smaller inductance value by using the through hole, so that not only the limitation of the thickness of the circuit board on the inductance value but also the difficulty and cost of the circuit board design and the production are reduced.
  • three or more holes may be connected in parallel based on the same principle to make the obtained inductance have a small inductance value, and the present invention is not limited thereto.
  • the present embodiment provides an inductor having a small inductance value obtained by using a plurality of vias in parallel, and the structure of the inductor can effectively reduce the processing difficulty and cost of the circuit board. Thereby facilitating Enterprise cost and quality control.
  • the present invention also provides a circuit board in which all or part of the inductance is implemented by the inductance provided by any of the above embodiments. This eliminates the need for the board to provide independent placement of the corresponding inductors, thereby reducing board area and design difficulty, and reducing board design and production costs.

Abstract

一种电感、电路板以及电感的实现方法，其中电感包括：第一焊盘（201，401a，601a），其设置在电路板的第一金属走线层（204a）；第二焊盘（202，401b，601b），其设置在电路板的第二金属走线层（204b）；以及，第一孔洞（203，401c，601c），其一端位于第一焊盘（201，401a，601a）中，另一端位于第二焊盘（202，401b，601b）中，第一孔洞（203，401c，601c）中含有导电介质。该电感能够有效减小电感在电路板中的占用面积。

Description

一种电感、电路板以及电感的实现方法
相关技术的交叉引用
本申请要求享有2014年12月18日提交的名称为：“一种电感、电路板以及电感的实现方法”的中国专利申请CN201410797963.9的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及电力电子技术领域，具体地说，涉及一种电感、电路板以及电感的实现方法。
背景技术
在电路设计中，磁珠的电路符号就是电感，即磁珠就是电感。磁珠的电感值较小，制作方便，它还具有诸多普通电感所没有的特点。例如对于普通电感，由于存在分布电容，所以在频率很高(特别是高次谐波)的情况下，普通电感有可能会被等效成一个电容，从而无法起到电感的作用。
但是磁珠就没有普通电感的上述缺陷，磁珠具有极好的高频特性，在频率很高的环境下仍具有稳定的电感特性。因此，如图1所示，电子工程师在进行电路设计时通常在电源端等位置处会放置一颗甚至几颗磁珠(例如磁珠L1和磁珠L2)，以便更好地去除杂波，抑制电源线上的噪声和尖峰干扰。然而，磁珠的使用虽然去除了杂讯，但也造成了电路板的面积过大，大大提高了电路板的生产成本。
发明内容
本发明所要解决的技术问题是为了克服现有技术中因使用磁珠等电感而造成的电路板的面积过大、成本过高等问题。为解决上述问题，本发明的实施例首先提供了一种电感，所述电感包括：
第一焊盘，其设置在电路板的第一金属走线层；
第二焊盘，其设置在所述电路板的第二金属走线层；以及，
第一孔洞，其一端位于所述第一焊盘中，另一端位于所述第二焊盘中，所述第一孔洞中含有导电介质。
根据本发明的一个实施例，所述第一金属走线层和/或第二金属走线层为所述电路板的表层金属走线层。
根据本发明的一个实施例，所述电感还包括：
第三焊盘，其设置在所述电路板的第三金属走线层；
第四焊盘，其设置在所述电路板的第四金属走线层；
第二孔洞，其一端位于所述第三焊盘中，另一端位于所述第四焊盘中，所述第二孔洞中含有导电介质。
根据本发明的一个实施例，所述第四金属走线层与第二金属走线层为同层金属走线层，所述第四焊盘与第二焊盘通过金属走线连接。
根据本发明的一个实施例，所述第三金属走线层与第一金属走线层为同层金属走线层，所述第三焊盘与第一焊盘通过金属走线连接。
根据本发明的一个实施例，所述导电介质为铜、金、银或锡。
本发明还提供了一种电路板，所述电路板包括如上所述的电感。
本发明还提供了一种电感的实现方法，该方法利用电路板中的相应过孔形成所需要的电感。
根据本发明的一个实施例，利用电路板中多个串联或并联的过孔形成所述电感。
根据本发明的一个实施例，通过调整所述过孔的长度得到所需要的电感感值。
现有的电路板将过孔的寄生电感作为一种杂散电感，在设计过孔时需要将过孔的寄生电感尽可能的减小，从而减小过孔的寄生电感对电路造成的影响。而本发明所提供的电感正是将过孔所具有的寄生电感加以利用，这样不仅能够有效解决电路设计时因需要减小过孔的寄生电感而使得电路设计的难度增大的问题，还能够有效减小电感在电路板中的占用面积，从而减小整个电路板的面积与生产成本。
在电路设计的过程中，电路板的厚度是不可变的(即电路板的层数及相关参数确定后，电路板的厚度也就固定了)。对于某一电路板，由于厚度是固定的，因此设置在该电路板上的孔洞的最小直径的也是相对固定的(为了满足工艺要求，孔洞的直径与电路板的厚度比值不能小于某一比值)，所以孔洞的最大电感值是也就是相对固定的。然而对于不同的电路，电路中的电感所需要的电感值可能超过了孔洞所能够具有的最大电感值。所以解决该问题，本发明还提供了一种通过将多个过孔串联而得到的电感。这种电感能够具有 更大的电感值，从而摆脱了电路板厚度对电感值的限制，这也就增加了本发明所提供的电感的应用范围。
电路板中孔洞的最大电感值是是相对固定的(即通孔所具有的电感值)。所以对于某些需要较小电感值的电路，就需要通过减小孔洞的长度(即采用埋孔或盲孔)来得到所需要的电感值。然而在电路板的生产过程中，埋孔或盲孔的生产难度及成本要远高于通孔的生产难度及成本。所以为了解决该问题，本发明还提供了一种利用多个过孔并联而得到的具有较小感值的电感，从而有效地降低了电路板的加工难度以及成本，有利于企业的成本以及质量控制。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要的附图做简单的介绍：
图1是现有的磁珠电感连接电路的电路示意图；
图2是根据本发明一个实施例的电感的结构示意图；
图3是根据本发明一个实施例的电感连接电路的电路示意图；
图4是根据本发明另一个实施例的电感的结构示意图；
图5是根据本发明又一个实施例的电感的结构示意图；
图6是根据本发明再一个实施例的电感的结构示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
同时，在以下说明中，出于解释的目的而阐述了许多具体细节，以提供对本发明实施例的彻底理解。然而，对本领域的技术人员来说显而易见的是，本发明可以不用这里的 具体细节或者所描述的特定方式来实施。
实施例一：
图2示出了本实施例所提供的电感的结构示意图。
如图2所示，本实施例所提供的电感包括第一焊盘201、第二焊盘202和第一孔洞203。其中，第一焊盘201设置在电路板的第一金属走线层204a上，第二焊盘202设置在电路板的第二金属走线层204b上。第一孔洞203的一端位于第一焊盘201中，另一端位于第二焊盘202中。同时，为了使得第一孔洞能够实现导电功能，第一孔洞203中还具有导电介质。
具体地，本实施例中，利用孔的金属化工艺来使得孔洞的孔壁上覆盖上一层均匀的、耐热冲击的金属铜。该金属化工艺具体包括去钻污、化学沉铜和加厚铜等流程。
需要说明的是，在本发明的其他实施例中，也可以采用其他合理的方式来使得第一孔洞具有良好的导电能力，同时，第一孔洞中所包含的导电介质也可以为其他合理的导电材料，例如金、银或锡等，本发明不限于此。
如图2所示，本实施例中，第一金属走线层204a和第二金属走线层204b均为电路板的表层金属走线层，这样第一孔洞203也就成了贯穿电路板的通孔。当然，在本发明的其他实施例中，第一金属走线层和/或第二金属走线层也可以位于电路板的其他层，从而使得第一孔洞成为电路板中的埋孔或盲孔，本发明不限于此。
对于第一孔洞203，其所具有的电感值L可以采用如下表达式计算得到：
Figure PCTCN2014095867-appb-000001
其中，h表示第一孔洞的长度(本实施例中也就是电路板的厚度)，d表示第一孔洞的直径。
对于电路板X，其板厚为0.04英寸，电路板中第一孔洞的直径为0.01英寸，由表达式(1)可以计算得到第一孔洞的电感值为0.77nH。
从表达式(1)可以看出，孔洞的电感值L与该孔洞的长度h以及直径d有关，然而直径d的变化对于电感值L的影响较小。所以，在本发明的不同实施例中，可以通过适当调整孔洞的长度(例如调整孔洞两个端口所在的金属走线层等)来获得所需要的电感值。当然，在本发明的其他实施例中，也可以通过其他合理方式来使得孔洞具有所需要的电感值，本发明不限于此。
图3示出了本实施例所提供的电感连接电路的电路示意图。对比图1与图3可以看出，本实施例所提供的电感由于是通过电路板中的过孔来实现，因此也就不会出现类似于 磁珠那样需要占用电路板中大量面积的情况。
过孔是电路板的重要组成部分之一，而过孔具有寄生电感，在高速数字电路的设计中，过孔的寄生电感所带来的危害往往大于寄生电容的影响。在一些滤波电路中，过孔的寄生电感会削弱旁路电容的作用，从而减弱整个滤波电路的滤波效果。
由此可以看出，现有的电路板将过孔的寄生电感作为一种杂散电感，在设计过孔时需要将过孔的寄生电感尽可能地减小，从而减小过孔的寄生电感对电路造成的影响。而本实施例所提供的电感正是将过孔所具有的寄生电感加以利用，这样不仅能够有效解决电路设计时因需要减小过孔的寄生电感而使得电路设计的难度增大的问题，还能够有效利用电路板中的过孔来减小电感在电路板中的占用面积，从而减小整个电路板的面积与成本。
实施例二：
在电路设计的过程中，电路板的厚度是不可变的(即确定电路板的使用层数及相关参数后，电路板的厚度也就固定了)。对于某一电路板，由于电路板的厚度是固定的，因此设置在该电路板上的孔洞的最小直径也是相对固定的(为了满足工艺要求，孔洞的直径与电路板的厚度比值不能小于某一比值)，所以从表达式(1)可以得出，孔洞的最大电感值是也就是相对固定的。
然而对于不同的电路，电路中的电感所需要的电感值可能超过了电路板中孔洞所能够具有的最大电感值。针对该问题，本实施例提供了一种新的电感。图4示出了本实施例所提供的电感的结构示意图。
如图4所示，本实施例所提供的电感包括：第一焊盘401a、第二焊盘401b、第一孔洞401c、第三焊盘402a、第四焊盘402b和第二孔洞402c。其中，第一焊盘401a和第三焊盘402a分别位于电路板的第一金属走线层和第三金属走线层，第二焊盘401b和第四焊盘402b分别位于电路板的第二金属走线层和第四金属走线层。本实施例中，第一金属走线层与第三金属走线层为同层金属走线层，第三金属走线层与第四金属走线层也为同层金属走线层。
第一孔洞401c的一端位于第一焊盘中，另一端位于第二焊盘中。第二孔洞402c的一端位于第三焊盘中，另一端位于第四焊盘中。为了保证孔洞的导电性，第一孔洞和第二孔洞中均具有导电介质(例如铜、金、银或锡等)。
为了使得电感具有更大的电感值，本实施例中，第二焊盘401b与第四焊盘402b通过金属走线连接。这样最终得到的电感的电感值将是第一孔洞的电感值与第二孔洞的电感 值之和，由此便克服了电路板厚度对孔洞的电感值的限制，从而使得本实施例所提供的电感的应用范围范围更加广泛。
当然，在本发明的其他实施例中，上述四个焊盘所在的金属走线层既可以为电路板的表层金属走线层，也可以为电路板的中间金属走线层，即第一孔洞和/或第二孔洞可以为通孔、盲孔或埋孔，本发明不限于此。例如图5所示的电感的结构示意图，相较于图4所示的电感，图5所示的电感的第三焊盘502a位于中间金属走线层，第四焊盘仍位于表层金属走线层。这样，图5所示的电感便可以视为由一个通孔与一个盲孔串联构成的电感。
此外，在本发明的其他实施例中，为了得到所需要的电感值，也可以基于相同原理将三个以上的孔洞串联而得到具有较大电感值的电感，本发明不限于此。
从上述描述中可以看出，与实施例一所提供的电感类似，本实施例所提供的电感也是利用电路板中的过孔来替代现有电路中的电感(例如磁珠等)。但是，本实施例所提供的电感通过将多个过孔串联而得到了更大的电感值，从而摆脱了电路板厚度对过孔的电感值的限制，这也就增加了本实施例所提供的电感的应用范围。
实施例三：
从实施例二可以知道，电路板中孔洞的最大电感值是是相对固定的(即通孔所具有的电感值)。所以对于某些需要较小电感值的电路，就需要通过减小孔洞的长度(即采用埋孔或盲孔)来得到所需要的电感值。然而在电路板的生产过程中，埋孔或盲孔的生产难度及成本要远高于通孔的生产难度及成本。所以为了解决上述问题，本实施例提供了一种如图6所示的电感。
如图6所示，本实施例所提供的电感与图4所示的电感类似，该电感也包括两对焊盘以及两个孔洞。其中，第一焊盘601a与第三焊盘602a通过金属走线连接，第二焊盘601b与第四焊盘602b也通过金属走线连接。这样第一孔洞601c与第二孔洞602c也就可以视为并联，而并联的两个电感也就具有更小的电感值。由此，本实施例所提供的电感利用通孔得到了更小的电感值，这样不仅摆脱了电路板厚度对电感值的限制，还降低了电路板设计以及生产的难度和成本。
当然，在本发明的其他实施例中，为了得到所需要的电感值，也可以基于相同原理将三个以上的孔洞并联来使得所得到的电感具有较小的电感值，本发明不限于此。
从上述描述中可以看出，本实施例所提供了一种利用多个过孔并联所得到的具有较小感值的电感，电感的这种结构能够有效地降低电路板的加工难度以及成本，从而有利于 企业的成本以及质量控制。
此外，本发明还提供了一种电路板，该电路板中的全部或部分电感采用上述任一实施例所提供的电感来实现。这样使得电路板不再需要为相应电感提供独立的放置空间，从而减小了电路板的面积与设计难度，降低了电路板的设计及生产成本。
应该理解的是，本发明所公开的实施例不限于这里所公开的特定结构、处理步骤或材料，而应当延伸到相关领域的普通技术人员所理解的这些特征的等同替代。还应当理解的是，在此使用的术语仅用于描述特定实施例的目的，而并不意味着限制。
说明书中提到的“一个实施例”或“实施例”意指结合实施例描述的特定特征、结构或特性包括在本发明的至少一个实施例中。因此，说明书通篇各个地方出现的短语“一个实施例”或“实施例”并不一定均指同一个实施例。
为了方便，在此使用的多个项目、结构单元、组成单元和/或材料可出现在共同列表中。然而，这些列表应解释为该列表中的每个元素分别识别为单独唯一的成员。因此，在没有反面说明的情况下，该列表中没有一个成员可仅基于它们出现在共同列表中便被解释为相同列表的任何其它成员的实际等同物。另外，在此还可以连同针对各元件的替代一起来参照本发明的各种实施例和示例。应当理解的是，这些实施例、示例和替代并不解释为彼此的等同物，而被认为是本发明的单独自主的代表。
此外，所描述的特征或特性可以任何其他合适的方式结合到一个或多个实施例中。在上面的描述中，提供一些具体的细节，例如长度、感值等，以提供对本发明的实施例的全面理解。然而，相关领域的技术人员将明白，本发明无需上述一个或多个具体的细节便可实现，或者也可采用其它方法、组件、材料等实现。
虽然上述示例用于说明本发明在一个或多个应用中的原理，但对于本领域的技术人员来说，在不背离本发明的原理和思想的情况下，明显可以在形式上、用法及实施的细节上作各种修改而不用付出创造性劳动。因此，本发明由所附的权利要求书来限定。

Claims (17)

  1. 一种电感，包括：
    第一焊盘，其设置在电路板的第一金属走线层；
    第二焊盘，其设置在所述电路板的第二金属走线层；以及，
    第一孔洞，其一端位于所述第一焊盘中，另一端位于所述第二焊盘中，所述第一孔洞中含有导电介质。
  2. 如权利要求1所述的电感，其中，所述第一金属走线层和/或第二金属走线层为所述电路板的表层金属走线层。
  3. 如权利要求1所述的电感，其中，所述电感还包括：
    第三焊盘，其设置在所述电路板的第三金属走线层；
    第四焊盘，其设置在所述电路板的第四金属走线层；
    第二孔洞，其一端位于所述第三焊盘中，另一端位于所述第四焊盘中，所述第二孔洞中含有导电介质。
  4. 如权利要求3所述的电感，其中，所述第四金属走线层与第二金属走线层为同层金属走线层，所述第四焊盘与第二焊盘通过金属走线连接。
  5. 如权利要求3所述的电感，其中，所述第三金属走线层与第一金属走线层为同层金属走线层，所述第三焊盘与第一焊盘通过金属走线连接。
  6. 如权利要求4所述的电感，其中，所述第三金属走线层与第一金属走线层为同层金属走线层，所述第三焊盘与第一焊盘通过金属走线连接。
  7. 如权利要求1所述的电感，其中，所述导电介质为铜、金、银或锡。
  8. 一种电路板，所述电路板包括电感，其中，所述电感包括：
    第一焊盘，其设置在电路板的第一金属走线层；
    第二焊盘，其设置在所述电路板的第二金属走线层；以及，
    第一孔洞，其一端位于所述第一焊盘中，另一端位于所述第二焊盘中，所述第一孔洞中含有导电介质。
  9. 如权利要求8所述的电路板，其中，所述第一金属走线层和/或第二金属走线层为所述电路板的表层金属走线层。
  10. 如权利要求8所述的电路板，其中，所述电感还包括：
    第三焊盘，其设置在所述电路板的第三金属走线层；
    第四焊盘，其设置在所述电路板的第四金属走线层；
    第二孔洞，其一端位于所述第三焊盘中，另一端位于所述第四焊盘中，所述第二孔洞中含有导电介质。
  11. 如权利要求10所述的电路板，其中，所述第四金属走线层与第二金属走线层为同层金属走线层，所述第四焊盘与第二焊盘通过金属走线连接。
  12. 如权利要求10所述的电路板，其中，所述第三金属走线层与第一金属走线层为同层金属走线层，所述第三焊盘与第一焊盘通过金属走线连接。
  13. 如权利要求8所述的电路板，其中，所述导电介质为铜、金、银或锡。
  14. 一种电感的实现方法，所述方法利用电路板中的相应过孔形成所需要的电感。
  15. 如权利要求14所述的方法，其中，利用电路板中多个串联或并联的过孔形成所述电感。
  16. 如权利要求14所述的方法，其中，通过调整所述过孔的长度得到所需要的电感感值。
  17. 如权利要求15所述的方法，其中，通过调整所述过孔的长度得到所需要的电感感值。
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