WO2016087206A1

WO2016087206A1 - Inverter circuit with adaptive dead time

Info

Publication number: WO2016087206A1
Application number: PCT/EP2015/076973
Authority: WO
Inventors: Christian Nesensohn; Oliver Wynnyczenko
Original assignee: Tridonic Gmbh & Co Kg
Priority date: 2014-12-03
Filing date: 2015-11-18
Publication date: 2016-06-09
Also published as: AT16743U1; DE102014224752A1

Abstract

An inverter circuit (6) is disclosed, comprising an inverter, in particular an half-bridge inverter circuit (21), which has at least two switches (HS, LS) connected in series and provided with direct voltage, at the central point (mp) of which an alternating voltage can be provided in the case of alternating clocking of the switches, and a control unit (9), which is configured to clock the switches (HS, LS) and evaluate a measuring signal (Vmp), in particular a central point voltage, tapped at the central point, and, according to the measuring signal, to adjust the clocking of each of the switches separately such that a dead time (Tdead) is established in a variable manner between a deactivating of one of the switches and an activating of another switch.

Description

Inverter circuit with adaptive dead time

The invention relates to an inverter circuit and in particular an inverter half-bridge circuit and a driver circuit for lighting with such an inverter circuit. In addition, the invention relates to a method for controlling an inverter circuit or switching elements such as switches and / or transistors of an inverter. The lighting means may in particular be one or more LEDs.

Driver circuits for lighting devices are known from the prior art and are usually supplied on the basis of an electrical supply, in particular an AC voltage or a mains voltage. This alternating voltage can be supplied to a rectifier and, in particular, on the basis thereof to a power factor correction circuit (PFC circuit) connected downstream of it, which supply a direct voltage (DC voltage), which possibly also has a residual ripple. This generated DC voltage is then fed to a particular high-frequency clocked inverter, which generates a high-frequency AC voltage from the DC voltage. The generated alternating voltage is then supplied to the lighting means, wherein the lighting means upstream of other circuit components such as a rectifier and / or a filter, in particular a ripple filter, may be connected upstream.

The inverter and in particular the inverter half-bridge usually have two series-connected switches, which can be configured as power transistors (FET, M0SFET) and are clocked by a control unit. Preferably, starting from the inverter, a resonant circuit can be fed. As well For example, a transformer can be provided which can be used, for example, for transmission via an electrically insulating barrier. This transformer may also be coupled to the resonant circuit.

During the switching operations of the switches of the inverter, care must be taken to avoid so-called "hard switching." A "hard switching" means that during a freewheeling phase of a current through the half-bridge through the freewheeling diode (parallel to the switch and possibly integrated into it) the other switch is turned on. This can otherwise damage the switch. The switches of the inverter are switched by the control unit in each case for a EinschaltZeitdauer conductive (t ₀ n ^_ time), the turn-on time of the two switches are normally the same length. The control is carried out, for example, such that between the switching off of the one switch and the switching on of the other switch in the case of an inverter half-bridge a so-called dead time fixed t _de ad _f ix is provided, while none of the two switches is activated, ie turned on.

Fig. La shows an example of a section of a driver circuit, with an inverter designed as an inverter half-bridge inverter. The inverter is supplied at its potential higher side with a supply voltage V _DC , or a bus voltage. The supply voltage V _DC can be 400V, for example. The half-bridge has two switches Ls, HS, which are controlled by a control unit SE. The higher-potential switch HS is controlled by the control unit SE by a drive signal hs, while a potential-lower switch LS is controlled by the control unit SE by a drive signal ls. At a midpoint mp of the inverter half-bridge, a mid-point voltage V _mp can then be detected. Fig. Lb shows an ideal case of driving the switches LS, HS of the inverter half-bridge and a corresponding, for example, detected by the control unit SE voltage signal V _mp at the midpoint mp of the inverter half-bridge. The capture of

Midpoint voltage V _mp occurs in particular in a time phase of the timing of the switch LS, HS, in which the potential-lower switch LS is open. In particular, only the potential higher switch HS is closed during the voltage detection at the midpoint mp of the inverter. In Fig. Lb, an interlinked clocking of the switches LS, HS and the mid-point voltage V _{mp is} shown schematically, wherein a rectangular drive pulse of the drive signal Is for the switch LS is shown by a solid line, while a rectangular drive pulse of the drive signal hs for the potential higher switch HS is shown in dashed lines. Also shown is the dead time t ^ ead _f ix _{/ is provided} as an example between the end of the switch-on time of the potential-lower switch LS and the beginning of the switch-on time of the higher-potential switch HS.

In Fig. Lb is also shown that the voltage V _mp after turning off the potential lower switch LS increases and decreases after switching off the higher-potential switch HS. In particular, it is shown that the center point voltage V _mp drops to zero after activation of the higher-potential switch HS, before the potential-lower switch LS is activated. The potential at the mid point then corresponds to the zero potential until activation of the lower-potential switch LS of the higher-potential switch HS is activated. This is done by taking advantage of the time between the blocking of the lower-potential switch LS and the conducting of the higher-potential switch HS, the potential at the center point mp to draw on the supply voltage V _DC . Meanwhile, the dead time _f ix between inhibiting the higher potential switch HS and conducting the lower potential switch LS is used to pull the center point voltage V _mp to zero. This ensures that when switching on the respective switch, the potential difference across the switch is zero possible. Thus, switching losses can be avoided and the burden in particular for the switch is kept low.

The course of the voltage curve V _mp , however, depends on the load operated by the driver circuit or the connected light source. Thus, it may happen that, when the potential-lowing switch LS is switched on, the zero potential has not yet been reached when it is to be turned on. This means that the intended delay time t ^ ead _f ix i ⁿ insufficient this case, to draw the middle point voltage V _mp up to switch on the lower-potential switch LS to the reference potential or ground. This is shown in Fig. 2a. Thus, when the potential-lower switch LS is switched on, a voltage not equal to zero is present. The potential difference during switching therefore leads to increased switching losses.

Conversely, it may be that when switching on the higher-potential switch HS, the potential at the midpoint mp, ie the midpoint voltage V _mp , has not yet reached the level of the supply voltage V _DC and thus a potential at the midpoint mp is present, which is not equal to the supply voltage V _DC , This is illustrated in Fig. 2b. Now, if the higher potential switch HS is turned on, also here higher switching losses caused by the rapid increase of the voltage at the midpoint mp.

The above and in Figs. 2a and 2b illustrated behavior is especially at low Observe loads that cause a lower slope of the voltage signal V _mp and thus slower rising and falling edges. In order here to achieve a voltage-free switching, ie switching to the time at which the voltage across the switches when switching is zero, therefore, an extension of the dead time t ^ ead _f ix would be necessary.

At high loads, however, a different behavior is observed. Here it can come to a steeper slope of the midpoint voltage V _mp . This can have the consequence that the center point voltage V _{mp has} already dropped to zero after deactivation of the higher-potential switch HS, and thus an increase of the mid-point voltage V _{mp has} already occurred again when the potential-low switch LS is switched on, as shown in FIG. 2c is shown. Consequently, even at the midpoint mp applied potential is not the zero potential which also circuit losses.

On the other hand, upon deactivation of the lower-potential switch LS and before activation of the higher-potential switch HS, the phenomenon can be observed that the mid-point voltage V _mp has already risen to the operating voltage V _DC and already drops again when the higher-potential switch HS is activated, that is turned on. This is illustrated in Fig. 2d. As a result, the potential at the midpoint of the inverter mp differs from the potential of the operating voltage V _{DC of} the inverter, which in turn leads to switching losses.

Accordingly, at high loads, the dead time t _de ad _f ix would have to be shortened in order to be able to ensure the potential difference when switching on the respective switch from zero. Since switching losses in ballasts are to be avoided as much as possible, for example, to reduce thermal stress, or to protect the electronic components of the driver circuit (in particular switching of power transistors at a potential difference not equal to zero they can be damaged), the invention provides a solution , which allows a potential difference-free switching of the inverter.

The invention therefore provides an inverter circuit, a driver circuit having such an inverter circuit, and a method of operating the inverter circuit according to the independent claims. Further developments of the invention are the subject of the dependent claims.

In a first aspect, an inverter circuit is provided, comprising an inverter, in particular an inverter half-bridge circuit, having at least two switches connected in series and supplied with DC voltage, at the midpoint of which the switch is an AC voltage can be provided in mutual clocking, and a

Control unit, which is adapted to clock the switches and a tapped off at the midpoint measurement signal, in particular a midpoint voltage, and depending on the measurement signal to adjust the timing of each of the switches separately such that a dead time between a deactivating one of the switches and a Activating another switch is set variably. The control unit can tapped the at the middle point

Evaluate measuring signal in different temporal phases of the timing of the switch. For each of the switches, a threshold may be provided. The control unit can evaluate the tapped measurement signal with respect to the threshold values, and, depending on the result of the respective evaluation, activate / deactivate the switch for which the threshold value is defined.

The control unit may store the threshold for each switch and / or each evaluate and / or store a signal supplied to it as a threshold for at least one of the switches.

The control unit can detect an edge profile of the measurement signal and activate / deactivate each of the switches as a function of the edge profile.

The control unit can activate / deactivate a switch on a rising edge of the measurement signal and a switch on a falling edge of the measurement signal.

After reaching a threshold value, the control unit can activate / deactivate the associated switch only after a predetermined period of time. The control unit may set the duration of activating / deactivating the switches depending on a target frequency. The control unit may recalculate the dead time after each / every mutual activation of the switches.

The control unit can evaluate the measurement signal as a voltage value of the midpoint in a phase in which at least the more potential lower switch is open.

The dead time may be variable depending on the detected midpoint voltage.

The control unit can each have a comparator for comparing the measurement signal with the respective threshold value. The control unit can evaluate a signal output by each of the comparators and, depending on this, in particular after the dead time expires, activate the switches by means of activation signals. The control unit may be an IC, ASIC and / or microcontroller.

The inverter may feed a resonant circuit, in particular an LLC resonant circuit.

In another aspect, a driver circuit with an inverter circuit as described above is provided. In yet another aspect, a method of operating an inverter, in particular an inverter half-bridge circuit, having at least two switches connected in series and supplied with DC voltage at its midpoint in mutual Clocking the switch an AC voltage is provided, and a control unit that clocks the switches and a tapped at the midpoint measurement signal, in particular a midpoint voltage, evaluates and depending on the measurement signal, the timing of each of the switches separately such that a dead time between deactivating a the switch and an activation of another switch is set variably.

The invention will now be described with reference to the figures. Show it:

Fig. La schematically an inverter AnSteuerung;

Fig. Lb schematically control signals for

Inverter switch and one

Midpoint voltage history;

Figs. 2a-2d midpoint voltage waveforms at

different loads;

Fig. 3 shows schematically a driver circuit with a

Inverter circuit according to the

Invention;

Figs. 4a and 4b schematically components of a

Control unit according to the invention;

Fig. 5 shows schematically an inventive

Switch control; and Fig. 6 schematically shows an inverter circuit according to an embodiment of the invention.

Fig. 3 shows a driver circuit 1 with an inverter circuit 6 according to the invention. Fig. 3 shows schematically the structure of the driver circuit 1 for operating a lamp 2, in particular an LED track with at least one LED. The LEDs of the LED track can be arranged in series, in parallel or in a series / parallel connection.

The driver circuit 1 is preferably fed by an input voltage Vi _n, for example in the form of an alternating voltage or starting from the mains voltage. The input voltage Vi _n at the input side of the driver circuit 1 is preferably supplied to a rectifier 3 and / or a filter (for example an electromagnetic interference filter 4) which filters out electromagnetic interference.

The rectified and optionally filtered input voltage of the driver circuit 1 is then preferably fed to a power factor correction circuit (PFC) 5, which on the output side generates a supply voltage V _DC , in particular a bus voltage. The supply voltage V _DC is preferably a DC voltage or an approximately constant bus voltage, which may have a residual ripple. For example. For example, the supply voltage V _{DC may} be a DC voltage of 400V.

Alternatively, the supply voltage V _{DC may} also be a DC voltage or a constant voltage such as a battery voltage. In this case, the rectifier 3, the optional filter 4 and / or the power factor correction circuit 5 can be dispensed with. The supply voltage V _DC supplies an inverter circuit 6. The inverter circuit 6 is preferably a DC / AC converter which switches the supply voltage V _DC by means of an inverter and in particular by means of a half-bridge inverter. The inverter circuit 6 preferably also comprises a resonant circuit (LLC).

Resonant circuit) fed by the inverter. An inductance of the resonant circuit can serve as a primary winding for a transformer. The transformer is provided to transmit power via a galvanic barrier 7 from a primary side of the transformer to a secondary side of the transformer. The inverter circuit 6 is thus a clocked converter, in which the resonant circuit is fed from the inverter with the at least two switches LS, HS.

On the secondary side of the galvanically isolating barrier 7, an AC / DC converter 8 is shown, which may also comprise other components, such as a rectifier or a filter. The switches LS, HS are driven by a control unit 9, which accordingly alternately inputs the switches, i. in their conductive state, or from, i. in its non-conductive state, switches. The secondary side of the transformer supplies a load and / or the light source 2.

The galvanic barrier 7 can be a SELV barrier (safety extra-low voltage barrier) and can be overcome by the transformer, wherein the transformer can be designed in particular as a transformer. The transmission of electrical energy from the primary side to the secondary side of the transformer via the galvanic barrier 7 is also controlled or regulated by the control unit 9 by driving the switches LS, HS. The control unit 9 is preferably arranged on the primary side of the galvanic barrier 7, but may also be arranged on the secondary side. In order to set a desired current through the luminous means 2, the control unit 9 then measures an electrical quantity on the primary side (double arrow) and / or on the secondary side (double arrow dotted). On the basis of these returned values, the control unit 9 then controls the inverter or the switches of the inverter of the inverter circuit 6 in such a way that the desired current flows through the lighting means. The control unit ensures that the load is supplied with the desired current in the form of a light source, in particular in the form of an LED track. The core of the invention is to increase the load ranges for which the driver circuit can be used, and in particular to avoid the problem that for small loads the fixed dead time tdead fix too short and for large loads, the dead time tdead fix is too long. The invention therefore provides for a threshold value to be provided for each switch of the inverter of the inverter circuit 6, and in particular for each of the two switches LS, HS of the half-bridge. Whenever the midpoint voltage V _mp under or over the associated threshold, the switching of the associated switch is triggered. The threshold values are thus ideally matched to the voltage conditions at the respective switch. Therefore, a variable or an adaptive dead time tdead adpt results depending on the edge characteristics of the voltage change at the center point mp of the inverter. In this case, this adaptive adaptation of the dead time t _de ad adpt i ^m normal operation of the inverter circuit is present and not in an error state, the example for Prevent damage to the circuit targeted the

Dead time tdead adpt is changed, by the way, i. E. in normal operation, but constant.

FIG. 4a shows, by way of example, an embodiment according to the invention of the control unit 9 for controlling the inverter of the inverter circuit 6 and, in particular, of the higher-potential switch HS or of the lower-potential switch LS. In particular, the control unit 9 is designed so that it can detect the mid-point voltage V _mp at a voltage divider and, depending on this, the respective switches LS, HS of the inverter can be triggered by the drive signals hs and ls.

For this purpose, a threshold value can be stored in the control unit 9 for each of the switches, or this threshold value can be supplied externally to the control unit 9 or evaluated by it. In particular, the control unit 9 can receive or evaluate information about the connected light source or the operated load, in particular via a bus, such as a building services bus (for example by DALI protocol). It may also be possible that the threshold for each switch may be supplied to the control unit, for example via the bus, and thus e.g. is adjustable depending on the connected lamp.

In Fig. 4b is shown in more detail how the control unit 9 can be configured. The center point voltage V _mp or a parameter representing this is detected at an input 40 of the control unit 9 and fed to a comparator K1, K2 for each switch. In the example shown is for the potential higher switch HS a first comparator Kl and the potential-lower switch LS, a second comparator K2 provided. Each of the comparators K1, K2 is then supplied with a threshold provided for the respective switch. A threshold value SW _HS is for example supplied to the comparator K1 for the higher-potential switch HS, while a further threshold value SW _{LS is} supplied to the comparator K2 for the more-potential switch HS. The outputs of the comparators Kl, K2, which is based on a comparison of the midpoint voltage V _mp with the respective threshold value SW _HS , SW _LS , are fed to a detection circuit 41, which may also be aware of a standard dead time tdead de _f auit. The detection circuit 41 may be formed as part of the control unit 9. The control unit 9 then outputs the drive signals hs and ls to the switches HS and LS via a respective output 42, 43 in order to control them, in particular to turn them on, in particular depending on the respective comparison of the threshold value for each switch with the midpoint voltage V _mp for their respective switch-on time (t ₀ n ^_ time).

It should be noted that it is also possible to evaluate how the edge profile of the mid-point voltage V _mp at the time of comparison is. This is shown in FIG. 5. Here, the mid-point voltage curve V _{mp is} shown above and also the threshold values SW _LS , SW _H s are plotted for the switches LS, HS of the inverter. In this case, the threshold value SW _HS represents the threshold value for the higher-potential switch HS, while the threshold value SW _{HS represents} the threshold value for the lower-potential switch LS. As can be seen from the second curve from above, when the threshold value SW _H s is exceeded, a signal is generated by the comparator Kl when the rising edge of the midpoint voltage V _mp indicates that the associated higher-potential switch HS can now be turned on. Likewise, when the threshold value SW _LS is undershot, it is signaled by the comparator K2 that the potential-lowing switch LS can now be activated when the edge of the midpoint voltage V _mp drops. The signals of the comparators K1, K2 are only illustrated by way of example and can show other courses. If it is signaled that a threshold value SW _LS / SW _{HS has been reached} , a delay period t adder adpt _/ which is stored in the control unit 9, can be fed to it, or was calculated by it, begins from the time of the signaling. The delay time period Tdead ADPT may in particular equal to the period of time t be ead_defauit _d. In particular, the delay period t _de i _a y defauit programmable, that is changeable during operation of the control unit 9. Accordingly, the turn-on timings of the switches are the result of the target frequency set by the inverter in frequency control. In this respect, the respective dead time tdead adpt is adaptively calculated by the control unit for each switching cycle, ie for each alternate switching of the switches HS, LS. As shown in FIG. 6, the inverter according to the invention feeds in particular an LLC converter, which will be described in more detail below. FIG. 6 shows an exemplary embodiment of the inverter circuit 6 for supplying the luminous means 2, shown here as an LED. In this case, FIG. 6 shows an exemplary embodiment of the AC / DC converter 8 from FIG. 3 and a filter 20 connected downstream of the latter. As shown in FIG. 3, the supply voltage V _DC supplies the inverter circuit 6 to the driver circuit 1. The input side is in the inverter circuit 6 is a clocked

Inverter is provided. In Fig. 6, for example, an inverter in the form of a half-bridge circuit 21 is shown. The half-bridge circuit 21 is supplied by the supply voltage V _DC and preferably has the potential-lower switch LS and the higher-potential switch HS. It should be understood that the clocked circuit has at least one switch. As an inverter with a switch, for example, a flyback converter can be used.

The switches LS, HS of the half-bridge circuit 21 may be implemented as transistors, e.g. FET or MOSFET be configured. The switches LS, HS can be controlled by control signals ls, hs, which are output by the control unit 9. The potential-lower switch LS is connected to a primary-side ground. At the higher potential switch HS of the half-bridge circuit 21, however, the input voltage VDC is applied.

At the midpoint mp of the half-bridge circuit 21, ie between the two switches LS, HS, the resonant circuit 22 is connected in the form of a series resonant circuit, consisting of a resonant capacitor Cr and a resonant inductor Lr. In addition, a winding LI is provided in the resonant circuit. Alternatively, according to the invention, a parallel resonant circuit at the midpoint mp of the half-bridge circuit 21 may also be connected. The resonant circuit 22 is between the primary side ground and the midpoint mp of the half-bridge circuit. The resonant circuit 22 is referred to in this case as the LLC resonant circuit. The resonance capacitor Cr and the resonance inductor Lr preferably form an LC resonance circuit.

The winding / coil LI is preferably used for the primary winding of a transformer 23 in the form of e.g. a transformer, provided. The transformer 23 shown in FIG. 6 comprises the primary winding LI, that is to say the winding LI of the LLC resonant circuit, and an electromagnetically coupled to this primary winding LI

Secondary winding L2. Due to the transformer coupling between the winding LI and the secondary winding L2, an energy transfer takes place across the galvanic barrier 7, if the transformer is controlled accordingly, in particular by controlling the timing of the switch HS, LS by the control unit 9. The transformer 23 can additionally have a leakage inductance and a main inductance (not shown). The leakage inductance may be provided in series with the winding LI. The main inductance can serve to guide the magnetizing current and preferably be arranged parallel to the winding LI.

During operation, an alternating current (AC current) preferably flows through the secondary winding L2 of the transformer 23. The voltage of the secondary winding L2 is then preferably fed to a rectifier 24, which is formed in the illustrated example by the diodes Dl and D2. The secondary winding L2 of the transformer 23 additionally has a tapping, which may be provided in particular as a center point tapping. This midpoint tap creates a potential of Rectifier 24 and a potential of the voltage applied to the LED track voltage V _LED .

One side of the secondary winding L2 is connected to an anode of the first diode Dl, while the other side of the secondary winding L2 is connected to the anode of the second diode D2. The respective cathodes of the diodes D1, D2 are brought together and form an output potential of the rectifier 24. The rectifier 24 can be coupled on the output side with a storage or filter capacitor C2. When

Storage capacitor can in particular a

Electrolytic capacitor (ELKO) can be used. In order to filter a voltage output by the rectifier 24 and in particular to provide a ripple filter, the capacitor C2 is followed by an inductance Lf, which in turn is connected to a further capacitor C3. The capacitors C2 and C3 are connected at their potential higher side with the inductance Lf, while they are connected with their potential side lower side with the secondary side ground. The secondary-side ground potential may differ from the primary-side.

On the primary side of the inverter circuit 6 shown in FIG. 6, means 25 for measuring a primary-side current or the current through the resonant circuit 22 may be provided. Preferably, the means 25 for measuring the current I _LLC by the resonant circuit 22 as a shunt (shunt) is configured, which is not shown in Fig. 6. The measuring resistor can be connected in a known manner in series with the winding LI of the transformer 23. If on the measuring resistor an applied voltage is detected by the control unit 9, the control unit 9 is able to detect the current through the resonant circuit 22. Accordingly, the control unit 9 can thus perform a control of the switches LS, HS of the half bridge 21.

Further, on the primary side of the inverter circuit means 26 may be provided for measuring a voltage V _L i across the primary-side winding LI. According to one embodiment, the voltage measurement can be effected by connecting both sides of the primary winding LI to the control unit 9 such that it can detect the voltage at the inductance LI. Overall, the control unit 9 can thus be a direct information about the voltage applied to the winding LI voltage V _L i accessible. Alternatively, a voltage divider (not shown) may be provided between the terminals of the winding LI and the control unit 9 may be supplied in accordance with a partial voltage of the voltage divider, which then can reproduce a current applied to the winding LI voltage VL I as an actual signal for the voltage ,

Of course, it can also be provided that the control unit 9 on the secondary side of the circuit shown in Fig. 6 detects a parameter that reflects the current and / or the voltage on the secondary side detected. The parameter may, for example, be fed back via the resistor or capacitor circuit via the galvanic barrier 7. Thus, the control unit 9 in particular detect a voltage transmitted to the secondary side or a current. Here, too, a control of the switches LS, HS of the half-bridge 21 can be effected by the control unit 9 (see intimation by the dashed arrow in FIG. 6).

Claims

claims

Inverter circuit (6), comprising

a. an inverter, in particular a

Inverter half-bridge circuit (21), with at least two series-connected and with DC voltage (V _DC ) supplied switches (LS, HS), at their midpoint (mp) at

alternating clocking of the switches (LS, HS) an AC voltage can be provided, and b. a control unit (9) which is set up to clock the switches (LS, HS) and to evaluate a measuring signal tapped at the middle point, in particular a midpoint voltage (V _mp ), and depending on the measuring signal, the timing of each of the switches (LS , HS) separately so as to variably set a dead time (tdead) between disabling one of the switches and activating another switch.

Inverter circuit (6) according to claim 1, wherein the control unit (9) is adapted to evaluate the measured at the midpoint (mp) measurement signal in different temporal phases of the timing of the switches (LS, HS).

An inverter circuit (6) according to claim 1 or 2, wherein for each of the switches (LS, HS)

Threshold (SW _LS , SW _HS ) is provided, and wherein the control unit (9) is adapted to evaluate the tapped measurement signal with respect to the threshold values (SW _LS , SW _HS ), and depending on the Result of the respective evaluation the switch

(LS / HS) for which the threshold value (SW _LS / SW _H s)

is defined, enable / disable.

Inverter circuit (6) according to one of

preceding claims, wherein the control unit (9) is _adapted to store the threshold value (SW _LS , SW _HS ) for each switch (LS, HS) and / or in each case a signal supplied to it as a threshold value (SW _LSi SW _HS ) for at least one of the switches (LS, HS) to save.

Inverter circuit (6) according to one of

preceding claims, wherein the control unit (9) is adapted to a trailing edge of the

To detect measuring signal and each switch (LS, HS) depending on the slope

enable / disable.

An inverter circuit (6) according to claim 5, wherein the control unit (9) is adapted to operate on a rising edge of the measurement signal

Switch and on a falling edge of the

Signal to another switch

enable / disable. Inverter circuit (6) according to one of

preceding claims, wherein the control unit is adapted after reaching a

Threshold value (SW _LSi SW _HS ) only after one

predetermined period of time (t ^ ead) the associated

Switch (LS, HS) to activate / deactivate. Inverter circuit (6) according to one of

preceding claims, wherein the control unit (9) is adapted to set the duration of the activation / deactivation of the switches (LS, HS) depending on a target frequency.

Inverter circuit (6) according to one of

preceding claims, wherein the control unit (9) is adapted to recalculate the dead time (t _de ad) after one / each mutual activation of the switches (LS, HS).

Inverter circuit (6) according to one of the preceding claims, wherein the control unit (9) is adapted to the measurement signal as

To evaluate voltage value of the midpoint (mp) in a phase in which at least the

potential lower switch (LS) is open.

11. Inverter circuit (6) according to one of

preceding claims, wherein the dead time (tdead)

is variable according to the detected midpoint voltage (Vj.) 12. Inverter circuit (6) according to one of

preceding claims, wherein the control unit (9) each have a comparator (K1 / K2) for comparing the measurement signal with the respective threshold value

(SW _L S / SWHS).

13. Inverter circuit (6) according to claim 12, wherein the control unit (9) is adapted to evaluate a signal output by each of the comparators (Kl, K2) and depending thereon, in particular after expiration of the dead time (tdead) to activate the switches (LS, HS) by means of control signals (ls, hs).

14. Inverter circuit (6) according to one of

preceding claims, wherein the control unit is an IC,

ASIC and / or microcontroller is.

15. Inverter circuit (6) according to one of

preceding claims, wherein the inverter comprises a resonant circuit (22), in particular an LLC

Resonant circuit, feeds.

16. driver circuit (1) with an inverter circuit (6) according to any one of claims 1-15.

17. A method for operating an inverter circuit (6) with an inverter, in particular an inverter half-bridge circuit, with

a. at least two switches connected in series and supplied with DC voltage (VDC) (LS,

HS), at its midpoint (mp)

alternating clocking of the switches (LS, HS) an AC voltage is provided, and b. a control unit (9) which clocks the switches (LS, HS) and one at the midpoint

tapped measurement signal, in particular a mid-point voltage (Vmp), evaluates, and depending on the measurement signal, the timing of each of the switches (LS, HS) separately such

to set a dead time (tdead) between disabling one of the switches and activating another switch variably.