WO2016078210A1 - 一种阵列基板和液晶显示面板及其驱动方法 - Google Patents

一种阵列基板和液晶显示面板及其驱动方法 Download PDF

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WO2016078210A1
WO2016078210A1 PCT/CN2015/071061 CN2015071061W WO2016078210A1 WO 2016078210 A1 WO2016078210 A1 WO 2016078210A1 CN 2015071061 W CN2015071061 W CN 2015071061W WO 2016078210 A1 WO2016078210 A1 WO 2016078210A1
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switch
control
signal
control switch
scan
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PCT/CN2015/071061
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English (en)
French (fr)
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姚晓慧
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深圳市华星光电技术有限公司
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Priority to DE112015004744.1T priority Critical patent/DE112015004744B4/de
Priority to GB1708693.5A priority patent/GB2548045B/en
Priority to KR1020177016465A priority patent/KR101963062B1/ko
Priority to JP2017525595A priority patent/JP6369926B2/ja
Priority to RU2017120528A priority patent/RU2659579C1/ru
Priority to US14/417,707 priority patent/US9829760B2/en
Publication of WO2016078210A1 publication Critical patent/WO2016078210A1/zh

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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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Definitions

  • the present invention relates to liquid crystal display technology, and more particularly to an array substrate and a liquid crystal display panel capable of improving the difference in brightness between left and right eyes and a driving method thereof.
  • three-dimensional stereo imaging technology can provide more vivid stereoscopic images, and thus has become the mainstream direction of current display technology development. Due to its slimness, low power consumption and no radiation pollution, the liquid crystal display device has become the mainstream configuration of various industries and even home entertainment displays. Therefore, the three-dimensional stereoscopic imaging liquid crystal display device developed on the basis of the original two-dimensional planar display technology has also become a new development hot spot.
  • the more common three-dimensional imaging technology is shutter glasses technology.
  • the technology adopts the time division effect, so that the left lens and the right lens of the 3D glasses are sequentially switched in turn: when the right lens is opened, the liquid crystal display device simultaneously outputs the image provided to the right eye; when the left lens is opened, the liquid crystal The display device simultaneously outputs an image supplied to the left eye. Then, by the difference in angle between the left and right eye angles, the image viewer superimposes the images of the left and right eyes into a three-dimensional image with depth of field and layering in the brain.
  • the liquid crystal display device generally drives the liquid crystal molecules to rotate by alternating current, and realizes different gray scale image display by changing the rotation angle of the liquid crystal molecules. This is because if the liquid crystal molecules are driven to rotate by the direct current mode, the moving ions in the liquid crystal molecules will move in the same direction, thereby generating another electric field and affecting the steering of the liquid crystal molecules, that is, the DC residual phenomenon occurs. In order to prevent such a DC residual phenomenon from affecting the display quality of the screen, the liquid crystal display device usually changes the positive and negative polarities of the image information data signal, and periodically changes the voltage applied to the pixel electrode of the pixel unit.
  • a light-transmissive bright picture (a white picture of 255 steps) is recorded as L255, and a dark picture (a black picture of 0th order) which is opaque is recorded as L0.
  • the positive and negative driving voltages of the white screen are 7V and 5V, respectively, and the positive and negative driving voltages of the black screen are 1V and 11V, respectively, and the common electrode voltage is 6V.
  • the voltage on the panel and the difference between the voltage and the common electrode voltage are as shown in Table 1 below.
  • the voltage difference across the pixel electrode relative to the common electrode will vary between 1V and 5V. That is, the voltage applied to the liquid crystal during the positive polarity driving period was 1 V; and the voltage applied to the liquid crystal during the negative polarity driving period was 5V. Since the voltages acting on the liquid crystal during the positive and negative driving periods are too large and always positive, they cannot cancel each other out. Therefore, after a long time of operation, the point will have a residual charge similar to DC residual, thereby causing three-dimensional image sticking. .
  • the dual-frame image polarity inversion driving method is often used in the prior art to change the positive and negative polarities of the image information data signal. Since the polarity of the data signal is inverted every two frames, the voltage on the pixel electrode and the difference between the voltage and the common electrode voltage are shown in Table 2 below.
  • the voltage difference with respect to the common electrode on the pixel electrode is repeatedly cycled between 1V ⁇ -5V ⁇ -1V ⁇ 5V. That is, the voltage applied to the liquid crystal during the positive polarity driving period was 1 V and -5 V; and the voltage applied to the liquid crystal during the negative polarity driving period was -1 V and 5 V.
  • the voltage difference on the pixel electrode with respect to the common electrode during the positive and negative polarity driving is mutually compensated, so that the image sticking phenomenon does not occur.
  • the problem of uneven brightness of the left and right eyes is derived. This phenomenon is particularly prominent for liquid crystal display panels that use charge sharing technology (LCS) to improve color shift.
  • LCD charge sharing technology
  • the pixel electrode of the pixel unit in the liquid crystal display panel is usually divided into two parts of a main area (Main) and a sub-area (Sub), and a sharing capacitor is set to be in the control signal.
  • Main main area
  • Sub sub-area
  • the charge on the primary and secondary regions is redistributed, and the voltage on the primary and secondary regions is changed.
  • the shared capacitor has a function of storing the charge, when the shared capacitor obtains the same polarity during the new frame image as the charge stored during the previous frame image, the new frame image will be relatively more due to the charge accumulation effect.
  • the new frame image will be relatively dark because the charges cancel each other out. Therefore, when the same data signal is input (for example, the input signal L255 in Table 3 below), the brightness of the left-eye image output by the liquid crystal display panel operating in the dual-frame image polarity inversion driving mode is always lower than that of the right-eye image. .
  • the inventors of the present invention have repeatedly explored and experimented, and proposed a new array substrate and liquid crystal display panel capable of improving the difference in brightness between left and right eyes and a driving method thereof.
  • an object of the present invention is to provide a new array substrate and liquid crystal display panel and a driving method thereof.
  • the array substrate and the liquid crystal display panel can overcome the large-view role deviation in the two-dimensional scanning mode.
  • the phenomenon can also improve the difference in left and right eye brightness in the three-dimensional scanning mode.
  • the array substrate provided by the invention comprises:
  • a plurality of pixel units disposed in an array of the plurality of scan lines and the plurality of data lines, each of the pixel units corresponding to the scan line and the data line, and comprising:
  • a main area electrode connected to the corresponding data line through a main area control switch, wherein the control end of the main area control switch is connected to the corresponding scan line to receive the data signal on the data line when there is a scan signal on the scan line Has a main zone voltage;
  • sub-area electrode connected to the corresponding data line through the sub-area control switch, wherein the control end of the sub-area control switch is connected to the corresponding scan line to receive the data signal on the data line when there is a scan signal on the scan line Has a sub-region voltage;
  • Sharing a capacitor, which is connected to the sub-area electrode through a sharing control switch, and the control end of the sharing control switch passes through a first control switch and a scan line corresponding to the Nth pixel unit arranged in the scanning direction from the pixel unit Connecting, on the other hand, connecting to the scan line corresponding to the pixel unit through the second control switch;
  • the first control switch in the two-dimensional scanning mode, is configured to be turned on at least when there is a scan signal on the scan line to which it is connected, and the second control switch is configured to be at least on the scan line to which it is connected and The scan signal connected to the first control switch of the same level is turned off when there is a scan signal; in the three-dimensional scan mode, the first control switch is configured to be turned off at least when there is a scan signal on the scan line connected thereto, the second The control switch is configured to conduct at least when there is a scan signal on the scan line to which it is connected.
  • the control end of the first control switch corresponding to the pixel unit corresponding to the odd scan line is connected to a first switch control line, and receives the first switch control signal, and the pixel corresponding to the even scan line
  • the control end of the first control switch corresponding to the unit is connected to a second switch control line, and receives the second switch control signal
  • the control end of the second control switch corresponding to the pixel unit corresponding to the odd scan line is connected in parallel a third switch control line receives a third switch control signal
  • a control end of the second control switch corresponding to the pixel unit corresponding to the even scan line is connected to a fourth switch control line to receive the fourth switch control signal ;
  • the first switch control signal and the second switch control signal are synchronous but opposite polarity timing pulse signals
  • the third switch control signal and the fourth switch control signal are synchronous but opposite polarity timing pulse signals
  • the second switch control signal has the same polarity as the third switch control signal
  • the pulse width of the pulse signal is equal to the duration of the scan signal
  • the first switch control signal is an odd pulse sequence signal
  • the first switch control signal is an even pulse sequence signal
  • the first switch control signal is an even pulse sequence signal
  • the first switch control signal is an odd pulse sequence signal
  • an auxiliary line corresponding to the scan line is further disposed on the array substrate, and a control end of the sharing control switch in each of the pixel units is connected to the corresponding first through the auxiliary line A control switch and a second control switch.
  • the first control switch and the second control switch may be disposed in a fan-out area.
  • the main zone control switch, the secondary zone control switch, the share control switch, the first control switch and the second control switch are all thin film switching transistors.
  • the present invention also provides a liquid crystal display panel, including:
  • the array substrate, the color filter substrate, and a liquid crystal layer between the array substrate and the color filter substrate are provided.
  • the present invention also provides a driving method of the liquid crystal display panel described above, including a two-dimensional scanning driving step and a three-dimensional scanning driving step;
  • the two-dimensional scan driving step includes:
  • Scanning signals are sequentially input to the respective scanning lines along the scanning direction;
  • the second control switch connected to the scan line When there is a scan signal on a scan line, the second control switch connected to the scan line is turned off, so that the main area control switch and the sub-area control switch in the pixel unit corresponding to the scan line are turned on, thereby making the main area electrode And the sub-area electrode has the same voltage under the action of the data signal on the data line; at the same time controlling the first control switch connected to the scan line to be turned on, and the second control switch of the same level as the first control switch is turned off, thereby Pixel unit corresponding to the first control switch connected to the scan line realizes a charge sharing function through an internal shared capacitor;
  • the three-dimensional scan driving step includes:
  • Scanning signals are sequentially input to the respective scanning lines along the scanning direction;
  • the second control switch connected to the scan line When there is a scan signal on a scan line, the second control switch connected to the scan line is turned on, so that the main area control switch and the sub-area control switch and the share control switch in the pixel unit corresponding to the scan line are turned on. Thereby causing the main area electrode and the sub-area electrode and the shared capacitance to be under the action of the data signal on the data line Having the same voltage; simultaneously controlling the first control switch connected to the scan line to be turned off.
  • the control end of the first control switch corresponding to the pixel unit corresponding to the odd scan line is applied with the first switch control signal
  • the control of the first control switch corresponding to the pixel unit corresponding to the even scan line Applying a second switch control signal
  • the control end of the second control switch corresponding to the pixel unit corresponding to the odd scan line applies a third switch control signal
  • the second control switch corresponding to the pixel unit corresponding to the even scan line The control terminal applies a fourth switch control signal;
  • the first switch control signal and the second switch control signal are synchronous but opposite polarity timing pulse signals, and the third switch control signal and the fourth switch control signal are synchronous but opposite polarity timing pulse signals, and the second switch control signal
  • the polarity is the same as the third switch control signal; the pulse width of the timing pulse signal is equal to the duration of the scan signal;
  • the first switch control signal is an odd pulse sequence signal
  • the first switch control signal is an even pulse sequence signal
  • the first switch control signal is an even pulse sequence signal
  • the first switch control signal is an odd pulse sequence signal
  • 1 is a partial equivalent circuit diagram of an array substrate of the present invention
  • 2A is a timing control signal diagram in a two-dimensional scanning mode when an embodiment N of the present invention is an odd number;
  • 2B is a timing control signal diagram in a two-dimensional scanning mode when the embodiment N of the present invention is an even number
  • 3A is a timing control signal diagram in a three-dimensional scan mode when an embodiment N of the present invention is an odd number;
  • Fig. 3B is a timing control signal diagram in the three-dimensional scanning mode when the embodiment N of the present invention is an even number.
  • the present invention proposes a new array substrate and liquid crystal display panel and a driving method thereof.
  • the array substrate comprises:
  • each The pixel unit corresponds to a scan line and a data line, and includes:
  • the main area electrode is connected to the corresponding data line through the main area control switch, and the control end of the main area control switch is connected to the corresponding scan line to receive the data signal on the data line when there is a scan signal on the scan line and has the main Zone voltage
  • the sub-area electrode is connected to the corresponding data line through the sub-area control switch, and the control end of the sub-area control switch is connected to the corresponding scan line to receive the data signal on the data line when there is a scan signal on the scan line.
  • Sharing a capacitor which is connected to the sub-area electrode through a sharing control switch, and the control end of the sharing control switch is connected on the one hand to the scan line corresponding to the Nth pixel unit arranged in the scanning direction from the pixel unit through the first control switch, and On one hand, the second control switch is connected to the scan line corresponding to the pixel unit;
  • the first control switch in the two-dimensional scanning mode, is configured to be turned on at least when there is a scan signal on the scan line to which it is connected, and the second control switch is configured to be at least on the scan line to which it is connected and when The first control switch is configured to be turned off when there is a scan signal on the scan line connected to the first control switch; in the three-dimensional scan mode, the first control switch is configured to be turned off at least when there is a scan signal on the scan line to which it is connected, and the second control switch is configured to be at least The connected scan line is turned on when there is a scan signal.
  • the array substrate includes an image display area AA and a fan-out area Fanout (neither shown in the figure).
  • the image display area AA includes a plurality of common electrodes, a plurality of scan lines and a plurality of data lines, and a plurality of pixel units disposed in the pixel array in which the plurality of scan lines and the plurality of data lines are interlaced.
  • Each pixel unit has the same structure, corresponds to one scan line and one data line, and includes a main area electrode (Main) and a sub-area electrode (Sub), and a sharing capacitor Cshare for charge sharing.
  • the pixel unit structure of the array substrate of the present invention will be described in detail by taking the pixel unit P 1M corresponding to the first scanning line Gate_1 and the Mth data line Data_M as an example.
  • the main area electrode (Main) is configured with a main area control switch TFT_A.
  • the first end of the main area control switch TFT_A is connected to the corresponding data line Data_M, the second end is connected to the main area electrode, and the control end is connected to the corresponding scan line Gate_1.
  • the control end of the main area control switch TFT_A receives the scan signal from the scan driving circuit through the scan line Gate_1, the first end and the second end of the main area control switch TFT_A are turned on, thereby putting the data line Data_M from the data driving circuit.
  • the data signal is passed to the main area electrode.
  • the main area liquid crystal capacitor Clc_A which is coupled between the main area electrode and the common electrode CF_com of the color filter substrate, and the main area electrode and The main area storage capacitor Cst_A coupled between the common electrodes A_com of the array substrate starts to be charged by the data signal, so that the main area electrode has and maintains a certain main area voltage.
  • the sub-area electrode (Sub) is provided with a sub-area control switch TFT_B.
  • the first end of the sub-region control switch TFT_B is connected to the corresponding data line Data_M, the second end is connected to the sub-area electrode, and the control end is connected to the corresponding scan line Gate_1.
  • the control end of the sub-region control switch TFT_B receives the scan signal from the scan driving circuit through the scan line Gate_1, the first end and the second end of the sub-region control switch TFT_B are turned on, thereby bringing the data line Data_M from the data driving circuit.
  • the data signal is passed to the secondary electrode.
  • Sharing capacitor Cshare configuration has a shared control switch TFT_C.
  • the first end of the sharing control switch TFT_C is connected to the secondary electrode, the second end is connected to one electrode of the sharing capacitor Cshare, and the other electrode of the sharing capacitor Cshare is connected to the common electrode A_com of the array substrate.
  • the control terminal of the sharing control switch TFT_C is connected on the one hand by the first control switch TFT_1-1 to the scan line Gate_N corresponding to the Nth pixel unit arranged in the scanning direction from the pixel unit, and on the other hand through the second
  • the control switch TFT_2-1 is connected to the scan line Gate_1 corresponding to the pixel unit.
  • the number of the first control switches and the number of the first control switches disposed on the array substrate are equal to the number of scan lines, that is, one first control switch and one second control switch are responsible for Manage the pixel unit corresponding to one scan line, that is, one row of pixel units.
  • All of the first control switch and the second control switch in this embodiment are preferably arranged at the fan-out area of the array substrate, and are sequentially arranged in the scanning direction.
  • the array substrate is also preferably arranged with an auxiliary line corresponding to the scan line, and the control end of the sharing control switch in each pixel unit is connected to the corresponding first control switch and the corresponding line through the corresponding auxiliary line. Two control switches.
  • the scan lines Gate_1, Gate_2, and Gate_3 are arranged on the array substrate. . . . . One-to-one corresponding auxiliary lines Gate_Share_1, Gate_Share_2, Gate_Share_3. . . . . .
  • the control end of the sharing control switch in the pixel unit of the first row is connected to its corresponding first control switch TFT_1-1 on the one hand and the corresponding second control switch TFT_2-1 on the other hand through the first auxiliary line Gate_Share_1;
  • the other end of the control switch TFT_1-1 is connected to the Nth scanning line Gate_N by wiring, and the other end of the second control switch TFT_2-1 is connected to the first scanning line Gate_1 by wiring.
  • the control end of the sharing control switch in the second row of pixel units is connected on the one hand via the second auxiliary line Gate_Share_2
  • the corresponding first control switch TFT_1-2 is connected to its corresponding second control switch TFT_2-2 on the other hand; the other end of the first control switch TFT_1-2 is connected to the N+1th scan line Gate_N+ through wiring. 1; the other end of the second control switch TFT_2-2 is connected to the second scan line Gate_2 by wiring. . . . . . And so on.
  • the main area control switch, the sub-area control switch, the share control switch, the first control switch and the second control switch may all be thin film switching transistors.
  • the present invention proposes:
  • the first control switch is configured to be turned on at least when there is a scan signal on the scan line to which it is connected, and the second control switch is configured to be at least on the scan line to which it is connected and when the first The scan line connected to the control switch is turned off when there is a scan signal;
  • the first control switch is configured to be turned off at least when there is a scan signal on the scan line to which it is connected
  • the second control switch is configured to be turned on at least when there is a scan signal on the scan line to which it is connected.
  • the inventors of the present invention have proposed an embodiment. That is, the first/second control switch is divided into two groups: the first/second control switches corresponding to the pixel units corresponding to the odd scan lines are grouped together, referred to as the odd array first/second control switch; The first/second control switches corresponding to the pixel units of the even scan lines are classified into another group, which is referred to as an even array first/second control switch. among them:
  • the odd array first controls the switches TFT_1-1, TFT_1-3, and TFT_1-5. . . . .
  • the control terminal is connected to the first switch control line Line_1 to receive the first control signal SW1, and is turned on or off under its action;
  • the first array of even arrays controls TFT_1-2, TFT_1-4, and TFT_1-6. . . . .
  • the control terminal is connected to the second switch control line Line_2 to receive the second control signal SW2, and is turned on or off under its action;
  • the odd array controls the switches TFT_2-1, TFT_2-3, TFT_2-5. . . . .
  • the control terminal is connected in parallel to the third switch control line Line_3 to receive the third control signal SW3, and is turned on or off under its action;
  • the second array of even arrays controls TFT_2-2, TFT_2-4, TFT_2-6. . . . .
  • the control terminal is connected in parallel to the fourth switch control line Line_4 to receive the fourth control signal SW4 and is turned on or off under its action.
  • the first switch control signal SW1 and the second switch control signal SW2 are synchronized but opposite polarity timing pulse signals
  • the third switch control signal SW3 and the fourth switch control signal SW4 are synchronous but opposite polarity timing pulse signals.
  • the second switch control signal SW2 and the third switch control signal SW3 have the same polarity.
  • the pulse width of the timing pulse signal is equal to the duration T of the scan signal.
  • first switch control signal SW1, the second switch control signal SW2, and the third switch control The specific pulse timing of signal SW3 and fourth switch control signal SW4 is also related to the parity nature of N.
  • the 2A is a timing control signal diagram in a two-dimensional scanning mode when N is an odd number.
  • the first control switch is turned on at least when there is a scan signal on the scan line to which it is connected in the two-dimensional scan mode
  • the second control switch is at least on the scan line to which it is connected and when the first control switch is on the same stage
  • the connected scan line has an operating condition when the scan signal is off.
  • the first switch control signal SW1 is an odd pulse sequence signal
  • the second switch control signal SW2 is an even pulse sequence signal
  • the third switch control signal SW3 is an even pulse.
  • the sequence signal, the fourth switch control signal SW2 is correspondingly an odd pulse sequence signal.
  • N 3 as an example for explanation.
  • the first switch control signal SW1 is at a high level, and the third switch control signal SW3 is at a low level, so the first control switch TFT_1 connected to the third scan line Gate_3 is -1 is turned on, the second control switch TFT_2-3 connected to the third scan line Gate_3 is turned off, and the second control switch TFT_2-1 of the same level as the first control switch TFT_1-1 is turned off. Therefore, the main area control switch and the sub-area control switch in the pixel unit corresponding to the third scanning line Gate_3 are turned on, so that the main area electrode and the sub-area electrode have the same voltage under the action of the data signals on the data line.
  • the sharing control switch in the pixel unit corresponding to the first scanning line Gate_1 is turned on, thereby turning on the charge sharing function, and re-adjusting the voltage of the secondary region electrode through the internal sharing capacitor to improve the color shift phenomenon.
  • the second switch control signal SW2 When the scan signal is input to the fourth scan line Gate_4, the second switch control signal SW2 is at a high level, and the fourth switch control signal SW4 is at a low level, so the first control switch TFT_1 connected to the fourth scan line Gate_4 is -2 is turned on, the second control switch TFT_2-4 connected to the fourth scan line Gate_4 is turned off, and the second control switch TFT_2-2 of the same level as the first control switch TFT_1-2 is turned off. Therefore, the main area control switch and the sub-area control switch in the pixel unit corresponding to the fourth scanning line Gate_4 are turned on, so that the main area electrode and the sub-area electrode have the same voltage under the action of the data signals on the data line. At the same time, the sharing control switch in the pixel unit corresponding to the second scanning line Gate_2 is turned on, thereby turning on the charge sharing function, and re-adjusting the voltage of the secondary region electrode through the internal sharing capacitor to improve the color shift phenomenon.
  • the first control switch connected to the scan line when there is a scan signal on a scan line, the first control switch connected to the scan line is turned on, and the second control switch connected to the scan line is turned off.
  • the second control switch of the same level as the first control switch is turned off, so that the foregoing "first control switch is turned on at least when there is a scan signal on the scan line to which it is connected, and the second control switch is connected at least when it is connected.
  • the operating condition on the scan line and when there is a scan signal on the scan line connected to the first control switch of the same level.
  • the 2B is a timing control signal diagram in the two-dimensional scanning mode when N is an even number.
  • the first control switch is turned on at least when there is a scan signal on the scan line to which it is connected in the two-dimensional scan mode
  • the second control switch is at least on the scan line to which it is connected and when the first control switch is on the same stage
  • the connected scan line has an operating condition when the scan signal is off.
  • the first switch control signal SW1 is an even pulse sequence signal
  • the second switch control signal SW2 is an odd pulse sequence signal
  • the third switch control signal SW3 is an odd pulse.
  • the sequence signal, the fourth switch control signal SW2 is correspondingly an even pulse sequence signal.
  • the whole working process is similar to the two-dimensional scanning mode when N is an odd number, and will not be described here.
  • FIG. 3A is a timing control signal diagram in a three-dimensional scan mode when N is an odd number.
  • the first control switch is turned off when there is a scan signal on the scan line connected thereto in the three-dimensional scan mode, and the second control switch is turned on at least when there is a scan signal on the scan line to which it is connected
  • a switch control signal SW1 is an even pulse sequence signal
  • a second switch control signal SW2 is an odd pulse sequence signal
  • a third switch control signal SW3 is an odd pulse sequence signal
  • a fourth switch control signal SW2 is an even pulse sequence signal.
  • N 3 as an example for explanation.
  • the first switch control signal SW1 is at a low level
  • the third switch control signal SW3 is at a high level
  • the first control switch TFT_1 connected to the third scan line Gate_3 is The -1 cutoff
  • the second control switch TFT_2-3 connected to the third scan line Gate_3 is turned on
  • the second control switch TFT_2-1 of the same level as the first control switch TFT_1-1 is turned on. Therefore, the main area control switch and the sub-area control switch and the sharing control switch in the pixel unit corresponding to the third scanning line Gate_3 are turned on, so that the main area electrode and the sub-area electrode and the data signal of the shared capacitor on the data line are It has the same voltage under its action.
  • the sharing control switch in the first row of pixel units connected to the first control switch TFT_1-1 through the auxiliary line Gate_Share_1 cannot be turned on, and the charge sharing function cannot be realized. In this way, the phenomenon of uneven brightness of the left and right eyes can be avoided.
  • the second switch control signal SW2 When the scan signal is input to the fourth scan line Gate_4, the second switch control signal SW2 is at a low level, and the fourth switch control signal SW4 is at a high level, so the first control switch TFT_1 connected to the fourth scan line Gate_4 is The -2 cutoff, the second control switch TFT_2-4 connected to the fourth scan line Gate_4 is turned on, and the second control switch TFT_2-2 of the same level as the first control switch TFT_1-2 is turned on. Therefore, the main area control switch and the sub-area control switch and the sharing control switch in the pixel unit corresponding to the fourth scan line Gate_4 are turned on, so that the main area electrode and the sub-area electrode and the data signal of the shared capacitor on the data line are It has the same voltage under its action.
  • the sharing control switch in the first row of pixel units connected to the first control switch TFT_1-1 through the auxiliary line Gate_Share_1 cannot be turned on, and the charge sharing function cannot be realized. In this way, the phenomenon of uneven brightness of the left and right eyes can be avoided.
  • the first control switch connected to the scan line when there is a scan signal on a scan line, the first control switch connected to the scan line is turned off, and the second control switch connected to the scan line is turned on.
  • the second control switch of the same level as the first control switch is turned on, so that the foregoing "first control switch is turned off at least when there is a scan signal on the scan line to which it is connected, and the second control switch is at least connected to the scan.
  • the working condition of "on" when there is a scan signal on the line when there is a scan signal on the line.
  • FIG. 3B is a timing control signal diagram in the three-dimensional scanning mode when N is an even number.
  • a switch control signal SW1 is an odd pulse sequence signal
  • a second switch control signal SW2 is an even pulse sequence signal
  • a third switch control signal SW3 is an even pulse sequence signal
  • a fourth switch control signal SW2 is an odd pulse sequence signal.
  • the present invention also provides a liquid crystal display panel.
  • the liquid crystal display panel includes the above array substrate, a color filter substrate, and a liquid crystal layer between the array substrate and the color filter substrate.

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Abstract

一种阵列基板和液晶显示面板及其驱动方法。阵列基板上的每一像素单元包括主区电极和次区电极以及分享电容（Cshare），连接分享电容（Cshare）与次区电极的分享控制开关（TFT_C）的控制端通过第一控制开关（TFT_1-1）与从本像素单元起沿扫描方向排列的第N个像素单元对应的扫描线连接，以及通过第二控制开关（TFT_2-1）与本像素单元对应的扫描线连接。在二维扫描模式下，第一控制开关（TFT_1-1）配置成至少当其连接的扫描线有扫描信号时导通，第二控制开关（TFT_2-1）配置成至少当其连接的扫描线上以及当与同级的第一控制开关（TFT_1-1）连接的扫描线上有扫描信号时截止；在三维扫描模式下，第一控制开关（TFT_1-1）配置成至少当其连接的扫描线上有扫描信号时截止，第二控制开关（TFT_2-1）配置成至少当其连接的扫描线上有扫描信号时导通。

Description

一种阵列基板和液晶显示面板及其驱动方法
本申请要求享有2014年11月17日提交的名称为“一种阵列基板和液晶显示面板及其驱动方法”的中国专利申请为CN201410654293.5的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示技术，尤其涉及一种能够改善左右眼亮度差异的阵列基板和液晶显示面板及其驱动方法。
背景技术
相较于传统的二维平面显示技术，三维立体成像技术能够提供更加生动的立体影像，因此成为当前显示技术发展的主流方向。液晶显示装置因其外型轻薄、低耗电量和无辐射污染等优点已成为当前各行各业乃至家庭娱乐显示的主流配置。因此在原二维平面显示技术基础上拓展开来的三维立体成像液晶显示装置也成为了新的发展热点。
目前较为常见的三维立体成像技术是快门眼镜(shutter glasses)技术。该技术采用时间分割效应，让三维眼镜的左眼镜片和右眼镜片轮流依序开关：当右眼镜片打开时，液晶显示装置同时输出提供给右眼的影像；当左眼镜片打开时，液晶显示装置同时输出提供给左眼的影像。然后藉由左右眼视角的角度差异，影像观看者在脑中将左右眼的影像迭合成具有景深及层次感的三维立体影像。
液晶显示装置通常采用交流方式驱动液晶分子旋转，通过改变液晶分子的旋转角度来实现不同灰阶的影像显示。这是因为，如果采用直流方式驱动液晶分子旋转，液晶分子内的移动离子会朝着同一方向移动，进而产生另一电场而影响液晶分子的转向，也即出现直流残留现象。为了避免这种直流残留现象影响画面的显示质量，液晶显示装置通常改变影像信息数据信号的正负极性，使作用于像素单元像素电极上的电压周期性地变化。但是对于与快门眼镜联合工作的三维液晶显示面板而言，如果采用单帧极性反转驱动方法改变影像信息数据信号的正负极性，还是会出现类似直流残留的电荷残留，进而引发三维残影现象(IS)。
假设一个256灰阶显示的液晶显示装置，呈现透光的亮画面(255阶的白画面)记为L255，呈现不透光的暗画面(0阶的黑画面)记为L0。白画面的正负极性驱动电压分别为7V和5V，黑画面的正负极性驱动电压分别为1V和11V，共同电极电压为6V。那么对于面板中的某一个像素电极，其上的电压以及该电压与共同电极电压的差值的变化情况如下表表一所示。
Figure PCTCN2015071061-appb-000001
表一
从表一可知，在这种情况下，像素电极上相对于共同电极的电压差会在1V和5V之间变化。也即，在正极性驱动期间内作用于液晶上的电压为1V；在负极性驱动期间内作用于液晶上的电压为5V。由于正、负极性驱动期间内作用于液晶上的电压相差太大，且始终为正极性，不能相互抵消，因此长时间工作后该点会有类似直流残留的电荷残留，从而引发三维残影现象。
为避免出现三维残影现象，现有技术中多采用双帧影像极性反转驱动方法改变影像信息数据信号的正负极性。由于数据信号的极性每两帧才会翻转一次，因此像素电极上的电压以及该电压与共同电极电压的差值的变化情况如下表表二所示。
Figure PCTCN2015071061-appb-000002
表二
从表二可知，在这种情况下，像素电极上相对于共同电极的电压差会在1V→-5V→-1V→5V之间反复循环。也即，在正极性驱动期间内作用于液晶上的电压为1V和-5V；在负极性驱动期间内作用于液晶上的电压为-1V和5V。正、负极性驱动期间内像素电极上相对于共同电极的电压差互相补偿，因此不会出现残影现象。但是在这种情况下又会衍生出左右眼亮度不均的问题。特别是对于采用电荷分享技术(LCS)改善色偏现象的液晶显示面板而言，这种现象尤为突出。这是因为，为了改善大视角色偏现象，液晶显示面板中的像素单元的像素电极通常会分成主区(Main)和次区(Sub)两个部分，并且设置分享电容，以在控制信号的作用下重新分配主区和次区上的电荷，改变主区和次区上的电压。由于分享电容对电荷有存储功能，因此当分享电容在新一帧影像期间所获得的电荷与前一帧影像期间所存储的电荷极性相同时，由于电荷累积效果，新一帧影像会相对较亮；反之，当分享电容在新一帧影像期间所获得的电荷与前一帧影像期间所存储的电荷极性相反时，由于电荷相互抵消，新一帧影像会相对较暗。故而当输入同样的数据信号(例如下表表三中的输入讯号L255)，以双帧影像极性反转驱动方式工作的液晶显示面板输出的左眼影像的亮度始终比右眼影像的亮度低。
Figure PCTCN2015071061-appb-000003
表三
针对上述问题，本发明的发明人经过反复的探索和实验，提出了一种新的能够改善左右眼亮度差异的阵列基板和液晶显示面板及其驱动方法。
发明内容
基于上述原因，本发明的目的是提供一种新的阵列基板和液晶显示面板及其驱动方法。该阵列基板和液晶显示面板既能够在二维扫描模式下克服大视角色偏 现象，又能够在三维扫描模式下改善左右眼亮度差问题。
本发明提供的阵列基板，其包括：
多条扫描线和多条数据线；
配置在由所述多条扫描线和多条数据线交错而成的阵列中的多个像素单元，每一所述像素单元对应一所述扫描线和一所述数据线，并包括：
主区电极，其通过主区控制开关连接对应的数据线，所述主区控制开关的控制端连接对应的扫描线，以当该扫描线上有扫描信号时接收该数据线上的数据信号而具有主区电压；
次区电极，其通过次区控制开关连接对应的数据线，所述次区控制开关的控制端连接对应的扫描线，以当该扫描线上有扫描信号时接收该数据线上的数据信号而具有次区电压；
分享电容，其通过分享控制开关连接所述次区电极，所述分享控制开关的控制端一方面通过第一控制开关与从本像素单元起沿扫描方向排列的第N个像素单元对应的扫描线连接，另一方面通过第二控制开关与本像素单元对应的扫描线连接；
其中，在二维扫描模式下，所述第一控制开关配置成至少当其连接的扫描线上有扫描信号时导通，所述第二控制开关配置成至少当其连接的扫描线上以及与同级的第一控制开关连接的扫描线上有扫描信号时截止；在三维扫描模式下，所述第一控制开关配置成至少当其连接的扫描线上有扫描信号时截止，所述第二控制开关配置成至少当其连接的扫描线上有扫描信号时导通。
根据本发明的实施例，与奇数扫描线对应的像素单元所对应的第一控制开关的控制端并接在一第一开关控制线上，接收第一开关控制信号，与偶数扫描线对应的像素单元所对应的第一控制开关的控制端并接在一第二开关控制线上，接收第二开关控制信号；与奇数扫描线对应的像素单元所对应的第二控制开关的控制端并接在一第三开关控制线上，接收第三开关控制信号，与偶数扫描线对应的像素单元所对应的第二控制开关的控制端并接在一第四开关控制线上，接收第四开关控制信号；
其中，所述第一开关控制信号与第二开关控制信号为同步但极性相反的时序脉冲信号，所述第三开关控制信号与第四开关控制信号为同步但极性相反的时序脉冲信号，同时所述第二开关控制信号与第三开关控制信号极性相同；所述时序 脉冲信号的脉冲宽度等于所述扫描信号的时长；
在二维扫描模式下，若N为奇数，所述第一开关控制信号为奇脉冲序列信号，若N为偶数，所述第一开关控制信号为偶脉冲序列信号；
在三维扫描模式下，若N为奇数，所述第一开关控制信号为偶脉冲序列信号，若N为偶数，所述第一开关控制信号为奇脉冲序列信号。
根据本发明的实施例，所述阵列基板上还设置有与所述扫描线一一对应的辅助线，各所述像素单元中的分享控制开关的控制端通过所述辅助线连接其对应的第一控制开关和第二控制开关。
根据本发明的实施例，所述第一控制开关和第二控制开关可以设置在扇出区。
根据本发明的实施例，所述主区控制开关、次区控制开关、分享控制开关、第一控制开关和第二控制开关均为薄膜开关晶体管。
此外，本发明还提供一种液晶显示面板，其包括：
上述阵列基板、彩色滤光基板以及位于所述阵列基板和彩色滤光基板之间的液晶层。
此外，本发明还提供上述的液晶显示面板的驱动方法，包括二维扫描驱动步骤和三维扫描驱动步骤；其中，
所述二维扫描驱动步骤包括：
沿扫描方向依次向各扫描线输入扫描信号；
当一扫描线上有扫描信号时，控制与该扫描线连接的第二控制开关截止，使该扫描线对应的像素单元中的主区控制开关和次区控制开关导通，从而使主区电极和次区电极在数据线上的数据信号的作用下具有相同的电压；同时控制与该扫描线连接的第一控制开关导通，与该第一控制开关同级的第二控制开关截止，从而使与该扫描线连接的第一控制开关对应的像素单元通过内部的分享电容实现电荷分享功能；
所述三维扫描驱动步骤包括：
沿扫描方向依次向各扫描线输入扫描信号；
当一扫描线上有扫描信号时，控制与该扫描线连接的第二控制开关导通，使该扫描线对应的像素单元中的主区控制开关和次区控制开关以及分享控制开关导通，从而使主区电极和次区电极以及分享电容在数据线上的数据信号的作用下 具有相同的电压；同时控制与该扫描线连接的第一控制开关截止。
根据本发明的实施例，与奇数扫描线对应的像素单元所对应的第一控制开关的控制端施以第一开关控制信号，与偶数扫描线对应的像素单元所对应的第一控制开关的控制端施以第二开关控制信号，与奇数扫描线对应的像素单元所对应的第二控制开关的控制端施以第三开关控制信号，与偶数扫描线对应的像素单元所对应的第二控制开关的控制端施以第四开关控制信号；其中，
第一开关控制信号与第二开关控制信号为同步但极性相反的时序脉冲信号，第三开关控制信号与第四开关控制信号为同步但极性相反的时序脉冲信号，同时第二开关控制信号与第三开关控制信号极性相同；时序脉冲信号的脉冲宽度等于扫描信号的时长；
在二维扫描模式下，若N为奇数，第一开关控制信号为奇脉冲序列信号，若N为偶数，第一开关控制信号为偶脉冲序列信号；
在三维扫描模式下，若N为奇数，第一开关控制信号为偶脉冲序列信号，若N为偶数，第一开关控制信号为奇脉冲序列信号。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
图1是本发明的阵列基板的局部等效电路图；
图2A是本发明的实施例N为奇数时二维扫描模式下的时序控制信号图；
图2B是本发明的实施例N为偶数时二维扫描模式下的时序控制信号图；
图3A是本发明的实施例N为奇数时三维扫描模式下的时序控制信号图；
图3B是本发明的实施例N为偶数时三维扫描模式下的时序控制信号图。
具体实施方式
为实现上述目的，本发明提出了一种新的阵列基板和液晶显示面板及其驱动方法。其中，阵列基板包括：
多条扫描线和多条数据线；
配置在由多条扫描线和多条数据线交错而成的阵列中的多个像素单元，每一 像素单元对应一扫描线和一数据线，并包括：
主区电极，其通过主区控制开关连接对应的数据线，主区控制开关的控制端连接对应的扫描线，以当该扫描线上有扫描信号时接收该数据线上的数据信号而具有主区电压；
次区电极，其通过次区控制开关连接对应的数据线，次区控制开关的控制端连接对应的扫描线，以当该扫描线上有扫描信号时接收该数据线上的数据信号而具有次区电压；
分享电容，其通过分享控制开关连接次区电极，分享控制开关的控制端一方面通过第一控制开关与从本像素单元起沿扫描方向排列的第N个像素单元所对应的扫描线连接，另一方面通过第二控制开关与本像素单元所对应的扫描线连接；
其中，在二维扫描模式下，第一控制开关配置成至少当其连接的扫描线上有扫描信号时导通，第二控制开关配置成至少当其连接的扫描线上以及当与同级的第一控制开关连接的扫描线上有扫描信号时截止；在三维扫描模式下，第一控制开关配置成至少当其连接的扫描线上有扫描信号时截止，第二控制开关配置成至少当其连接的扫描线上有扫描信号时导通。
为使本发明的发明目的和技术方案，以及所能达到的技术效果更加清楚，下面结合具体实施例和附图对本发明作进一步地详细说明。
图1是本发明提供的阵列基板的局部等效电路图。该阵列基板包括影像显示区AA和扇出区Fanout(图中均未示出)。其中，影像显示区AA包括由多条公共电极，多条扫描线和多条数据线，以及配置在由多条扫描线和多条数据线交错而成的像素阵列中的多个像素单元。每一像素单元的结构相同，对应于一条扫描线和一条数据线，并且包括主区电极(Main)和次区电极(Sub)，以及用于电荷分享的分享电容Cshare。下面以与第一条扫描线Gate_1和第M条数据线Data_M对应的像素单元P1M为例，详细说明本发明阵列基板的像素单元结构。
主区电极(Main)配置有主区控制开关TFT_A。该主区控制开关TFT_A的第一端连接对应的数据线Data_M，第二端连接主区电极，控制端连接对应的扫描线Gate_1。当主区控制开关TFT_A的控制端通过扫描线Gate_1收到来自扫描驱动电路的扫描信号时，主区控制开关TFT_A的第一端与第二端导通，从而将数据线Data_M上来自数据驱动电路的数据信号传至主区电极。同时，主区电极与彩色滤光基板的公共电极CF_com之间耦合而成的主区液晶电容Clc_A，以及主区电极与 阵列基板的公共电极A_com之间耦合而成的主区存储电容Cst_A，在数据信号的作用下开始充电，进而使主区电极具有并保持一定的主区电压。
次区电极(Sub)配置有次区控制开关TFT_B。该次区控制开关TFT_B的第一端连接对应的数据线Data_M，第二端连接次区电极，控制端连接对应的扫描线Gate_1。当次区控制开关TFT_B的控制端通过扫描线Gate_1收到来自扫描驱动电路的扫描信号时，次区控制开关TFT_B的第一端与第二端导通，从而将数据线Data_M上来自数据驱动电路的数据信号传至次区电极。同时，次区电极与彩色滤光基板的公共电极CF_com之间耦合而成的次区液晶电容Clc_B，以及次区电极与阵列基板的公共电极A_com之间耦合而成的次区存储电容Cst_B，在数据信号的作用下开始充电，进而使次区电极具有并保持一定的次区电压。
分享电容Cshare配置有分享控制开关TFT_C。该分享控制开关TFT_C的第一端连接次区电极，第二端连接分享电容Cshare的一个电极，分享电容Cshare的另一个电极连接阵列基板的公共电极A_com。同时，分享控制开关TFT_C的控制端一方面通过第一控制开关TFT_1-1与从本像素单元起沿扫描方向排列的第N个像素单元所对应的扫描线Gate_N连接，另一方面还通过第二控制开关TFT_2-1与本像素单元所对应的扫描线Gate_1连接。
需要说明的是，在本实施例中，阵列基板上设置的第一控制开关的数目和第一控制开关的数目均等于扫描线的数目，也即一个第一控制开关和一个第二控制开关负责管理一条扫描线所对应的像素单元，也即一行像素单元。本实施例中所有第一控制开关和第二控制开关优选地布置在阵列基板的扇出区处，并且沿扫描方向顺次排布。此外，为了方便连接，阵列基板上还优选地排布有与扫描线一一对应的辅助线，各像素单元中的分享控制开关的控制端通过相应的辅助线连接对应的第一控制开关和第二控制开关。
如图1所示，阵列基板上排布有与扫描线Gate_1、Gate_2、Gate_3。。。。。。一一对应的辅助线Gate_Share_1、Gate_Share_2、Gate_Share_3。。。。。。第一行像素单元中的分享控制开关的控制端通过第一条辅助线Gate_Share_1一方面连接其对应的第一控制开关TFT_1-1，另一方面连接其对应的第二控制开关TFT_2-1；第一控制开关TFT_1-1的另一端则通过配线连接第N条扫描线Gate_N，第二控制开关TFT_2-1的另一端则通过配线连接第一条扫描线Gate_1。第二行像素单元中的分享控制开关的控制端通过第二条辅助线Gate_Share_2一方面连接 其对应的第一控制开关TFT_1-2，另一方面连接其对应的第二控制开关TFT_2-2；第一控制开关TFT_1-2的另一端则通过配线连接第N+1条扫描线Gate_N+1；第二控制开关TFT_2-2的另一端则通过配线连接第二条扫描线Gate_2。。。。。。如此类推。当然在实际应用时，排布方式可以有很多种，不限于此。
上述主区控制开关、次区控制开关、分享控制开关、第一控制开关和第二控制开关可以均为薄膜开关晶体管。
为了能够实现在二维扫描模式下保留电荷分享功能以克服大视角色偏，以及在三维扫描模式下关闭电荷分享功能以改善左右眼亮度差的目的，本发明提出：
在二维扫描模式下，第一控制开关配置成至少当其连接的扫描线上有扫描信号时导通，第二控制开关配置成至少当其连接的扫描线上以及当与同级的第一控制开关连接的扫描线上有扫描信号时截止；
在三维扫描模式下，第一控制开关配置成至少当其连接的扫描线上有扫描信号时截止，第二控制开关配置成至少当其连接的扫描线上有扫描信号时导通。
为此，本发明的发明人提出了一种实施方式。即，将第一/第二控制开关分为两组：对应于奇数扫描线的像素单元所对应的第一/第二控制开关归为一组，简称奇数组第一/第二控制开关；对应于偶数扫描线的像素单元所对应的第一/第二控制开关归为另一组，简称偶数组第一/第二控制开关。其中：
奇数组第一控制开关TFT_1-1、TFT_1-3、TFT_1-5。。。。。。的控制端并接在第一开关控制线Line_1上以接收第一控制信号SW1，并在其作用下导通或者截止；
偶数组的第一控制开关TFT_1-2、TFT_1-4、TFT_1-6。。。。。。的控制端并接在第二开关控制线Line_2上以接收第二控制信号SW2，并在其作用下导通或者截止；
奇数组第二控制开关TFT_2-1、TFT_2-3、TFT_2-5。。。。。。的控制端并接在第三开关控制线Line_3上以接收第三控制信号SW3，并在其作用下导通或者截止；
偶数组的第二控制开关TFT_2-2、TFT_2-4、TFT_2-6。。。。。。的控制端并接在第四开关控制线Line_4上以接收第四控制信号SW4，并在其作用下导通或者截止。
上述第一开关控制信号SW1与第二开关控制信号SW2为同步但极性相反的时序脉冲信号，第三开关控制信号SW3与第四开关控制信号SW4为同步但极性相反的时序脉冲信号。同时，第二开关控制信号SW2与第三开关控制信号SW3极性相同。所述时序脉冲信号的脉冲宽度等于扫描信号的时长T。
此外，所述第一开关控制信号SW1、第二开关控制信号SW2、第三开关控制 信号SW3和第四开关控制信号SW4的具体脉冲时序还与N的奇偶性质有关。
图2A是N为奇数时二维扫描模式下的时序控制信号图。为了满足“在二维扫描模式下第一控制开关至少当其连接的扫描线上有扫描信号时导通，第二控制开关至少当其连接的扫描线上以及当与同级的第一控制开关连接的扫描线上有扫描信号时截止”的工作条件，第一开关控制信号SW1为奇脉冲序列信号，第二开关控制信号SW2相应地为偶脉冲序列信号，第三开关控制信号SW3为偶脉冲序列信号，第四开关控制信号SW2相应地为奇脉冲序列信号。
下面以N＝3为例进行说明。
当第三条扫描线Gate_3输入有扫描信号时，第一开关控制信号SW1为高电平，第三开关控制信号SW3为低电平，因此与第三条扫描线Gate_3连接的第一控制开关TFT_1-1导通，与第三条扫描线Gate_3连接的第二控制开关TFT_2-3截止，而与第一控制开关TFT_1-1同级的第二控制开关TFT_2-1截止。故，第三条扫描线Gate_3对应的像素单元中的主区控制开关和次区控制开关导通，从而使主区电极和次区电极在数据线上的数据信号的作用下具有相同的电压。同时，第一条扫描线Gate_1对应的像素单元中的分享控制开关导通，进而开启电荷分享功能，通过内部的分享电容重新调整次区电极的电压，改善色偏现象。
当第四条扫描线Gate_4输入有扫描信号时，第二开关控制信号SW2为高电平，第四开关控制信号SW4为低电平，因此与第四条扫描线Gate_4连接的第一控制开关TFT_1-2导通，与第四条扫描线Gate_4连接的第二控制开关TFT_2-4截止，而与第一控制开关TFT_1-2同级的第二控制开关TFT_2-2截止。故，第四条扫描线Gate_4对应的像素单元中的主区控制开关和次区控制开关导通，从而使主区电极和次区电极在数据线上的数据信号的作用下具有相同的电压。同时，第二条扫描线Gate_2对应的像素单元中的分享控制开关导通，进而开启电荷分享功能，通过内部的分享电容重新调整次区电极的电压，改善色偏现象。
以此类推，基于这种二维扫描时序控制方式，当一扫描线上有扫描信号时，与所述扫描线连接的第一控制开关导通，与所述扫描线连接的第二控制开关截止，同时与该第一控制开关同级的第二控制开关截止，就能够满足前述“第一控制开关至少当其连接的扫描线上有扫描信号时导通，第二控制开关至少当其连接的扫描线上以及当与同级的第一控制开关连接的扫描线上有扫描信号时截止”的工作条件。
图2B是N为偶数时二维扫描模式下的时序控制信号图。为了满足“在二维扫描模式下第一控制开关至少当其连接的扫描线上有扫描信号时导通，第二控制开关至少当其连接的扫描线上以及当与同级的第一控制开关连接的扫描线上有扫描信号时截止”的工作条件，第一开关控制信号SW1为偶脉冲序列信号，第二开关控制信号SW2相应地为奇脉冲序列信号，第三开关控制信号SW3为奇脉冲序列信号，第四开关控制信号SW2相应地为偶脉冲序列信号。整个工作过程与N为奇数时的二维扫描模式类似，此处不再赘述。
图3A是N为奇数时三维扫描模式下的时序控制信号图。为了满足“在三维扫描模式下第一控制开关至少当其连接的扫描线上有扫描信号时截止，第二控制开关至少当其连接的扫描线上有扫描信号时导通”的工作条件，第一开关控制信号SW1为偶脉冲序列信号，第二开关控制信号SW2相应地为奇脉冲序列信号，第三开关控制信号SW3为奇脉冲序列信号，第四开关控制信号SW2相应地为偶脉冲序列信号。
下面以N＝3为例进行说明。
当第三条扫描线Gate_3输入有扫描信号时，第一开关控制信号SW1为低电平，第三开关控制信号SW3为高电平，因此与第三条扫描线Gate_3连接的第一控制开关TFT_1-1截止，与第三条扫描线Gate_3连接的第二控制开关TFT_2-3导通，而与第一控制开关TFT_1-1同级的第二控制开关TFT_2-1导通。故，第三条扫描线Gate_3对应的像素单元中的主区控制开关和次区控制开关以及分享控制开关导通，从而使主区电极和次区电极以及分享电容在数据线上的数据信号的作用下具有相同的电压。同时，由于第一控制开关TFT_1-1截止，因此通过辅助线Gate_Share_1与第一控制开关TFT_1-1连接的第一行像素单元中的分享控制开关不能导通，也就不能实现电荷分享功能。如此一来就能避免出现左右眼亮度不均的现象。
当第四条扫描线Gate_4输入有扫描信号时，第二开关控制信号SW2为低电平，第四开关控制信号SW4为高电平，因此与第四条扫描线Gate_4连接的第一控制开关TFT_1-2截止，与第四条扫描线Gate_4连接的第二控制开关TFT_2-4导通，而与第一控制开关TFT_1-2同级的第二控制开关TFT_2-2导通。故，第四条扫描线Gate_4对应的像素单元中的主区控制开关和次区控制开关以及分享控制开关导通，从而使主区电极和次区电极以及分享电容在数据线上的数据信号的 作用下具有相同的电压。同时，由于第一控制开关TFT_1-2截止，因此通过辅助线Gate_Share_1与第一控制开关TFT_1-1连接的第一行像素单元中的分享控制开关不能导通，也就不能实现电荷分享功能。如此一来就能避免出现左右眼亮度不均的现象。
以此类推，基于这种三维扫描时序控制方式，当一扫描线上有扫描信号时，与所述扫描线连接的第一控制开关截止，与所述扫描线连接的第二控制开关导通，同时与该第一控制开关同级的第二控制开关导通，就能够满足前述“第一控制开关至少当其连接的扫描线上有扫描信号时截止，第二控制开关至少当其连接的扫描线上有扫描信号时导通”的工作条件。
图3B是N为偶数时三维扫描模式下的时序控制信号图。为了满足“在三维扫描模式下第一控制开关至少当其连接的扫描线上有扫描信号时截止，第二控制开关至少当其连接的扫描线上有扫描信号时导通”的工作条件，第一开关控制信号SW1为奇脉冲序列信号，第二开关控制信号SW2相应地为偶脉冲序列信号，第三开关控制信号SW3为偶脉冲序列信号，第四开关控制信号SW2相应地为奇脉冲序列信号。整个工作过程与N为奇数的三维扫描模式类似，此处不再赘述。
此外，本发明还提供一种液晶显示面板。该液晶显示面板包括上述阵列基板、彩色滤光基板以及位于阵列基板和彩色滤光基板之间的液晶层。
虽然本发明所揭露的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (18)

  1. 一种阵列基板，其中包括：
    多条扫描线和多条数据线；
    配置在由所述多条扫描线和多条数据线交错而成的阵列中的多个像素单元，每一所述像素单元对应一所述扫描线和一所述数据线，并包括：
    主区电极，其通过主区控制开关连接对应的数据线，所述主区控制开关的控制端连接对应的扫描线，以当该扫描线上有扫描信号时接收该数据线上的数据信号而具有主区电压；
    次区电极，其通过次区控制开关连接对应的数据线，所述次区控制开关的控制端连接对应的扫描线，以当该扫描线上有扫描信号时接收该数据线上的数据信号而具有次区电压；
    分享电容，其通过分享控制开关连接所述次区电极，所述分享控制开关的控制端一方面通过第一控制开关与从本像素单元起沿扫描方向排列的第N个像素单元对应的扫描线连接，另一方面通过第二控制开关与本像素单元对应的扫描线连接；
    其中，在二维扫描模式下，所述第一控制开关配置成至少当其连接的扫描线上有扫描信号时导通，所述第二控制开关配置成至少当其连接的扫描线上以及与同级的第一控制开关连接的扫描线上有扫描信号时截止；在三维扫描模式下，所述第一控制开关配置成至少当其连接的扫描线上有扫描信号时截止，所述第二控制开关配置成至少当其连接的扫描线上有扫描信号时导通。
  2. 如权利要求1所述的阵列基板，其中：
    与奇数扫描线对应的像素单元所对应的第一控制开关的控制端并接在一第一开关控制线上，接收第一开关控制信号，与偶数扫描线对应的像素单元所对应的第一控制开关的控制端并接在一第二开关控制线上，接收第二开关控制信号；
    与奇数扫描线对应的像素单元所对应的第二控制开关的控制端并接在一第三开关控制线上，接收第三开关控制信号，与偶数扫描线对应的像素单元所对应的第二控制开关的控制端并接在一第四开关控制线上，接收第四开关控制信号；
    其中，所述第一开关控制信号与第二开关控制信号为同步但极性相反的时序脉冲信号，所述第三开关控制信号与第四开关控制信号为同步但极性相反的时序脉冲信号，同时所述第二开关控制信号与第三开关控制信号极性相同；所述时序 脉冲信号的脉冲宽度等于所述扫描信号的时长；
    在二维扫描模式下，若N为奇数/偶数，所述第一开关控制信号为奇/偶脉冲序列信号；
    在三维扫描模式下，若N为奇数/偶数，所述第一开关控制信号为偶/奇脉冲序列信号。
  3. 如权利要求1所述的阵列基板，其中：
    所述阵列基板上还设置有与所述扫描线一一对应的辅助线，各所述像素单元中的分享控制开关的控制端通过所述辅助线连接其对应的第一控制开关和第二控制开关。
  4. 如权利要求2所述的阵列基板，其中：
    所述阵列基板上还设置有与所述扫描线一一对应的辅助线，各所述像素单元中的分享控制开关的控制端通过所述辅助线连接其对应的第一控制开关和第二控制开关。
  5. 如权利要求3所述的阵列基板，其中：
    所述第一控制开关和第二控制开关设置于扇出区。
  6. 如权利要求4所述的阵列基板，其中：
    所述第一控制开关和第二控制开关设置于扇出区。
  7. 如权利要求1所述的阵列基板，其中：
    所述主区控制开关、次区控制开关、分享控制开关、第一控制开关和第二控制开关均为薄膜开关晶体管。
  8. 如权利要求2所述的阵列基板，其中：
    所述主区控制开关、次区控制开关、分享控制开关、第一控制开关和第二控制开关均为薄膜开关晶体管。
  9. 如权利要求5所述的阵列基板，其中：
    所述主区控制开关、次区控制开关、分享控制开关、第一控制开关和第二控制开关均为薄膜开关晶体管。
  10. 一种液晶显示面板，包括阵列基板，其中：
    多条扫描线和多条数据线；
    配置在由所述多条扫描线和多条数据线交错而成的阵列中的多个像素单元，每一所述像素单元对应一所述扫描线和一所述数据线，并包括：
    主区电极，其通过主区控制开关连接对应的数据线，所述主区控制开关的控制端连接对应的扫描线，以当该扫描线上有扫描信号时接收该数据线上的数据信号而具有主区电压；
    次区电极，其通过次区控制开关连接对应的数据线，所述次区控制开关的控制端连接对应的扫描线，以当该扫描线上有扫描信号时接收该数据线上的数据信号而具有次区电压；
    分享电容，其通过分享控制开关连接所述次区电极，所述分享控制开关的控制端一方面通过第一控制开关与从本像素单元起沿扫描方向排列的第N个像素单元对应的扫描线连接，另一方面通过第二控制开关与本像素单元对应的扫描线连接；
    其中，在二维扫描模式下，所述第一控制开关配置成至少当其连接的扫描线上有扫描信号时导通，所述第二控制开关配置成至少当其连接的扫描线上以及与同级的第一控制开关连接的扫描线上有扫描信号时截止；在三维扫描模式下，所述第一控制开关配置成至少当其连接的扫描线上有扫描信号时截止，所述第二控制开关配置成至少当其连接的扫描线上有扫描信号时导通。
  11. 如权利要求10所述的液晶显示面板，其中：
    与奇数扫描线对应的像素单元所对应的第一控制开关的控制端并接在一第一开关控制线上，接收第一开关控制信号，与偶数扫描线对应的像素单元所对应的第一控制开关的控制端并接在一第二开关控制线上，接收第二开关控制信号；
    与奇数扫描线对应的像素单元所对应的第二控制开关的控制端并接在一第三开关控制线上，接收第三开关控制信号，与偶数扫描线对应的像素单元所对应的第二控制开关的控制端并接在一第四开关控制线上，接收第四开关控制信号；
    其中，所述第一开关控制信号与第二开关控制信号为同步但极性相反的时序脉冲信号，所述第三开关控制信号与第四开关控制信号为同步但极性相反的时序脉冲信号，同时所述第二开关控制信号与第三开关控制信号极性相同；所述时序脉冲信号的脉冲宽度等于所述扫描信号的时长；
    在二维扫描模式下，若N为奇数/偶数，所述第一开关控制信号为奇/偶脉冲序列信号；
    在三维扫描模式下，若N为奇数/偶数，所述第一开关控制信号为偶/奇脉冲序列信号。
  12. 如权利要求10所述的液晶显示面板，其中：
    所述阵列基板上还设置有与所述扫描线一一对应的辅助线，各所述像素单元中的分享控制开关的控制端通过所述辅助线连接其对应的第一控制开关和第二控制开关。
  13. 如权利要求11所述的液晶显示面板，其中：
    所述阵列基板上还设置有与所述扫描线一一对应的辅助线，各所述像素单元中的分享控制开关的控制端通过所述辅助线连接其对应的第一控制开关和第二控制开关。
  14. 如权利要求10所述的液晶显示面板，其中：
    所述第一控制开关和第二控制开关设置于扇出区。
  15. 如权利要求11所述的液晶显示面板，其中：
    所述第一控制开关和第二控制开关设置于扇出区。
  16. 如权利要求12所述的液晶显示面板，其中：
    所述第一控制开关和第二控制开关设置于扇出区。
  17. 一种液晶显示面板的驱动方法，包括二维扫描驱动步骤和三维扫描驱动步骤；其中，
    所述二维扫描驱动步骤包括：
    沿扫描方向依次向各扫描线输入扫描信号；
    当一扫描线上有扫描信号时，控制与该扫描线连接的第二控制开关截止，使该扫描线对应的像素单元中的主区控制开关和次区控制开关导通，从而使主区电极和次区电极在数据线上的数据信号的作用下具有相同的电压；同时控制与该扫描线连接的第一控制开关导通，与该第一控制开关同级的第二控制开关截止，从而使与该扫描线连接的第一控制开关对应的像素单元通过内部的分享电容实现电荷分享功能；
    所述三维扫描驱动步骤包括：
    沿扫描方向依次向各扫描线输入扫描信号；
    当一扫描线上有扫描信号时，控制与该扫描线连接的第二控制开关导通，使该扫描线对应的像素单元中的主区控制开关和次区控制开关以及分享控制开关导通，从而使主区电极和次区电极以及分享电容在数据线上的数据信号的作用下具有相同的电压；同时控制与该扫描线连接的第一控制开关截止。
  18. 如权利要求17所述的驱动方法，其中：
    与奇数扫描线对应的像素单元所对应的第一控制开关的控制端施以第一开关控制信号，与偶数扫描线对应的像素单元所对应的第一控制开关的控制端施以第二开关控制信号，与奇数扫描线对应的像素单元所对应的第二控制开关的控制端施以第三开关控制信号，与偶数扫描线对应的像素单元所对应的第二控制开关的控制端施以第四开关控制信号；其中，
    第一开关控制信号与第二开关控制信号为同步但极性相反的时序脉冲信号，第三开关控制信号与第四开关控制信号为同步但极性相反的时序脉冲信号，同时第二开关控制信号与第三开关控制信号极性相同；所述时序脉冲信号的脉冲宽度等于所述扫描信号的时长；
    在二维扫描模式下，若N为奇数/偶数，第一开关控制信号为奇/偶脉冲序列信号；
    在三维扫描模式下，若N为奇数/偶数，第一开关控制信号为偶/奇脉冲序列信号。
PCT/CN2015/071061 2014-11-17 2015-01-20 一种阵列基板和液晶显示面板及其驱动方法 WO2016078210A1 (zh)

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US9829760B2 (en) 2017-11-28
GB2548045A (en) 2017-09-06
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KR20170103770A (ko) 2017-09-13
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DE112015004744B4 (de) 2022-03-31
CN104345513A (zh) 2015-02-11
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