WO2016076138A1 - Solid-state imaging element, manufacturing method, and electronic device - Google Patents
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- 238000003384 imaging method Methods 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 104
- 239000004065 semiconductor Substances 0.000 claims abstract description 102
- 150000001875 compounds Chemical class 0.000 claims abstract description 88
- 238000006243 chemical reaction Methods 0.000 claims abstract description 70
- 238000012545 processing Methods 0.000 claims abstract description 12
- 239000012212 insulator Substances 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 10
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 9
- 238000000926 separation method Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 4
- 229910052714 tellurium Inorganic materials 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 229910052711 selenium Inorganic materials 0.000 claims description 3
- 229910052717 sulfur Inorganic materials 0.000 claims description 3
- 238000001311 chemical methods and process Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 238000012546 transfer Methods 0.000 description 6
- 239000003574 free electron Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003796 beauty Effects 0.000 description 1
- 210000004204 blood vessel Anatomy 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000012993 chemical processing Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000036541 health Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 210000004761 scalp Anatomy 0.000 description 1
- 150000003346 selenoethers Chemical class 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 150000004772 tellurides Chemical class 0.000 description 1
- 150000003568 thioethers Chemical class 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The present disclosure relates to a solid-state imaging element, a manufacturing method, and an electronic device which enable an increase in shot noise to be suppressed.
A solid-state imaging element of one aspect of the present disclosure is a stacked solid-state imaging element configured by bonding a compound semiconductor substrate including a photoelectric conversion part and a Si substrate including a circuit part for processing photoelectrons produced by the photoelectric conversion part. The compound semiconductor substrate is provided with a first highly doped layer stacked on the photoelectric conversion part, the Si substrate is provided with a Si plug, and the photoelectrons produced by the photoelectric conversion part are transferred to the circuit part via the first highly doped layer and the Si plug. The present disclosure is applicable to a stacked CMOS image sensor.
Description
本開示は、固体撮像素子、製造方法、および電子装置に関し、特に、光電変換部にて生成された光電子が回路部に転送されるまでの経路におけるショットノイズを低減できるようにした固体撮像素子、製造方法、および電子装置に関する。
The present disclosure relates to a solid-state imaging device, a manufacturing method, and an electronic device, and in particular, a solid-state imaging device capable of reducing shot noise in a path until photoelectrons generated in a photoelectric conversion unit are transferred to a circuit unit, The present invention relates to a manufacturing method and an electronic device.
従来、特に赤外光を検出する用途に用いるCMOSイメージセンサなどの固体撮像素子において、その光電変換部をＩｎＧａＡｓなどの化合物半導体基板上に設けることによって高感度化を実現する方法が知られている（例えば、特許文献１参照）。
Conventionally, in a solid-state imaging device such as a CMOS image sensor particularly used for detecting infrared light, a method for realizing high sensitivity by providing a photoelectric conversion portion on a compound semiconductor substrate such as InGaAs has been known. (For example, refer to Patent Document 1).
一方、固体撮像素子において、光電変換部にて生成された光電子を保持したり、後段に出力したりする回路部は、特性やコストなどの観点からＳｉ基板上に設けることが多い。
On the other hand, in a solid-state imaging device, a circuit unit that holds photoelectrons generated by a photoelectric conversion unit or outputs it to a subsequent stage is often provided on a Si substrate from the viewpoint of characteristics and cost.
したがって、光電変換部を含む化合物半導体基板と、回路部を含むＳｉ基板とにより固体撮像素子を構成する場合、両者を何らかの手段によって電気的に接続する必要がある。
Therefore, when a solid-state imaging device is constituted by a compound semiconductor substrate including a photoelectric conversion unit and a Si substrate including a circuit unit, it is necessary to electrically connect both by some means.
図１は、光電変換部を含む化合物半導体基板と、回路部を含むＳｉ基板から成る固体撮像素子の従来の構成の一例を示している。
FIG. 1 shows an example of a conventional configuration of a solid-state imaging device including a compound semiconductor substrate including a photoelectric conversion unit and a Si substrate including a circuit unit.
図１に示される固体撮像素子１０は、Ｓｉ基板１１と、化合物半導体基板１５が張り合わされて構成される。Ｓｉ基板１１には、MEM,FD，Vdd，TRX，TG，RSTなどの回路部１２が形成されており、化合物半導体基板１５と張り合わされる面には絶縁体層１３が設けられている。また、Ｓｉ基板１１にはｎＳｉプラグ２０が縦方向に設けられている。
The solid-state imaging device 10 shown in FIG. 1 is configured by bonding a Si substrate 11 and a compound semiconductor substrate 15 together. A circuit portion 12 such as MEM, FD, Vdd, TRX, TG, and RST is formed on the Si substrate 11, and an insulator layer 13 is provided on the surface to be bonded to the compound semiconductor substrate 15. In addition, nSi plugs 20 are provided in the vertical direction on the Si substrate 11.
一方、化合物半導体基板１５には、光電変換部１６（ｐ－化合物半導体１６Ａおよびｎ－化合物半導体１６Ｂからなるｐ－ｎ接合構造のフォトダイオード）が形成されており、光電変換部１６の上層側（受光面側）には上部透明電極１８が、下層側には金属層１９が設けられている。また、化合物半導体基板１５には金属層１９に繋がる金属プラグ２２が縦方向に設けられている。
On the other hand, on the compound semiconductor substrate 15, a photoelectric conversion unit 16 (a photodiode having a pn junction structure made of a p-compound semiconductor 16A and an n-compound semiconductor 16B) is formed. An upper transparent electrode 18 is provided on the light receiving surface side, and a metal layer 19 is provided on the lower layer side. The compound semiconductor substrate 15 is provided with a metal plug 22 connected to the metal layer 19 in the vertical direction.
Ｓｉ基板１１と化合物半導体基板１５との接続は、Ｓｉ基板１１に設けられたｎＳｉプラグ２０と、化合物半導体基板１５に設けた金属プラグ２２とをｎ＋Ｓｉ層２１を介して接続することにより実現される。すなわち、化合物半導体基板１５の光電変換部１６で生成された光電子は、金属層１９、金属プラグ２２、ｎ＋Ｓｉ層２１、およびｎＳｉプラグ２０を介して、Ｓｉ基板１１の回路部１２に転送されることになる。
The connection between the Si substrate 11 and the compound semiconductor substrate 15 is realized by connecting the nSi plug 20 provided on the Si substrate 11 and the metal plug 22 provided on the compound semiconductor substrate 15 via the n + Si layer 21. . That is, photoelectrons generated in the photoelectric conversion unit 16 of the compound semiconductor substrate 15 are transferred to the circuit unit 12 of the Si substrate 11 through the metal layer 19, the metal plug 22, the n + Si layer 21, and the nSi plug 20. become.
図１に示された従来の構成例の場合、光電変換部１６で生成された光電子が回路部１２に転送されるまでの経路に自由電子濃度の高い金属が存在し、多くの自由電子が存在するので、該自由電子の数に依存するショットノイズが増大してしまう要因となっていた。
In the case of the conventional configuration example shown in FIG. 1, there is a metal having a high free electron concentration in the path until the photoelectrons generated by the photoelectric conversion unit 16 are transferred to the circuit unit 12, and there are many free electrons. As a result, the shot noise depending on the number of free electrons increases.
本開示はこのような状況に鑑みてなされたものであり、固体撮像素子におけるショットノイズの増大を抑止できるようにするものである。
The present disclosure has been made in view of such a situation, and is intended to suppress an increase in shot noise in a solid-state imaging device.
本開示の第１の側面である固体撮像素子は、光電変換部を含む化合物半導体基板と、前記光電変換部により生成された光電子を処理するための回路部を含むＳｉ基板とが張り合わされて構成される積層型の固体撮像素子において、前記化合物半導体基板は、前記光電変換部と積層された第１の高濃度ドープ層を備え、前記Ｓｉ基板には、Ｓｉプラグを備え、前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層および前記Ｓｉプラグを介して前記回路部に転送される。
A solid-state imaging device according to the first aspect of the present disclosure includes a compound semiconductor substrate including a photoelectric conversion unit and a Si substrate including a circuit unit for processing photoelectrons generated by the photoelectric conversion unit. In the stacked solid-state imaging device, the compound semiconductor substrate includes a first highly doped layer stacked with the photoelectric conversion unit, the Si substrate includes a Si plug, and the photoelectric conversion unit The generated photoelectrons are transferred to the circuit section through the first highly doped layer and the Si plug.
前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層、前記第１の高濃度ドープ層の側面に接する第２の高濃度ドープ層、および前記Ｓｉプラグを介して前記回路部に転送されるようにすることができる。
The photoelectrons generated by the photoelectric conversion unit are connected to the circuit unit via the first heavily doped layer, the second heavily doped layer in contact with a side surface of the first heavily doped layer, and the Si plug. Can be transferred to.
前記第２の高濃度ドープ層は、Ｓｉ層が前記第１の高濃度ドープ層と同じ半導体型で高濃度にドープされたものとすることができる。
The second high-concentration doped layer may be one in which the Si layer is highly doped with the same semiconductor type as the first high-concentration doped layer.
前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層、前記第１の高濃度ドープ層の側面に接する第２の高濃度ドープ層、前記Ｓｉプラグをエピタキシャル成長させたＳｉプラグエピタキシャル層、および前記Ｓｉプラグを介して前記回路部に転送されるようにすることができる。
The photoelectrons generated by the photoelectric conversion unit are the first heavily doped layer, the second heavily doped layer in contact with the side surface of the first heavily doped layer, and the Si plug epitaxial obtained by epitaxially growing the Si plug. It can be transferred to the circuit section through the layer and the Si plug.
前記光電変換部は、化合物半導体がｐ－ｎ接合またはｐ－ｉ－ｎ接合されたフォトダイオードからなるようにすることができる。
The photoelectric conversion unit may be formed of a photodiode in which a compound semiconductor is a pn junction or a pin junction.
前記フォトダイオードをなすｐ－化合物半導体には、Ｚｎ，Ｍｇ，Ｂｅ，Ｃのうち一種がドーピングされているＩｎＧａＡｓ、ＩＩＩ－Ｖ系化合物、またはＩＩ－ＶＩ系化合物が採用され、ｎ－化合物半導体には、Ｓｉ，Ｓ，Ｓｅ，Ｔｅのうち一種がドーピングされているＩｎＧａＡｓ、ＩＩＩ－Ｖ系化合物、またはＩＩ－ＶＩ系化合物が採用されているようにすることができる。
As the p-compound semiconductor forming the photodiode, InGaAs, III-V compound, or II-VI compound doped with one of Zn, Mg, Be, and C is adopted. May be made of InGaAs, III-V compound, or II-VI compound doped with one of Si, S, Se, and Te.
前記化合物半導体基板は、前記光電変換部を１画素毎に分離するための画素分離部をさらに備えることができる。
The compound semiconductor substrate may further include a pixel separation unit for separating the photoelectric conversion unit for each pixel.
前記第２の高濃度ドープ層は、１画素毎に分離された前記光電変換部の外側の側面に接するように形成されているようにすることができる。
The second high-concentration doped layer can be formed so as to be in contact with the outer side surface of the photoelectric conversion unit separated for each pixel.
前記第２の高濃度ドープ層は、１画素毎に分離された前記光電変換部の内側中央付近の側面に接するように形成されているようにすることができる。
The second high-concentration doped layer may be formed so as to be in contact with the side surface near the inner center of the photoelectric conversion unit separated for each pixel.
前記第１の高濃度ドープ層は、不純物濃度が１０１６／ｃｍ３以上５×１０１７／ｃｍ３以下とすることができる。
The first heavily doped layer may have an impurity concentration of 10 16 / cm 3 or more and 5 × 10 17 / cm 3 or less.
前記第１の高濃度ドープ層の厚さは、２０ｎｍ以下とすることができる。
The thickness of the first heavily doped layer can be 20 nm or less.
前記第２の高濃度ドープ層の厚さは、前記第１の高濃度ドープ層の厚さと同程度とすることができる。
The thickness of the second heavily doped layer can be approximately the same as the thickness of the first heavily doped layer.
前記化合物半導体基板と前記Ｓｉ基板は、プラズマ接合処理、高温処理、または薬液処理によって張り合わされているようにすることができる。
The compound semiconductor substrate and the Si substrate can be bonded to each other by plasma bonding processing, high temperature processing, or chemical processing.
前記化合物半導体基板と前記Ｓｉ基板との貼り合わせ面には、絶縁体層が形成されているようにすることができる。
An insulator layer may be formed on the bonding surface between the compound semiconductor substrate and the Si substrate.
前記絶縁体層は、Ｓｉ，Ａｌ，Ｔａ、またはＴｉの酸化膜または窒化膜からなるようにすることができる。
The insulator layer can be made of an oxide film or nitride film of Si, Al, Ta, or Ti.
本開示の第２の側面である製造方法は、固体撮像素子の製造方法において、光電変換部、第１の高濃度ドープ層、および絶縁体層が順に積層された化合物半導体基板と、前記光電変換部により生成された光電子を処理するための回路部を含み、縦方向にＳｉプラグが形成され、表面に絶縁体層が形成されたＳｉ基板との前記絶縁体層どうしを張り合わせ、前記第第１の高濃度ドープ層と前記Ｓｉプラグとを第２の高濃度ドープ層を介して電気的に接続するステップを含む。
The manufacturing method according to the second aspect of the present disclosure includes a compound semiconductor substrate in which a photoelectric conversion unit, a first highly doped layer, and an insulator layer are sequentially stacked in the method for manufacturing a solid-state imaging device, and the photoelectric conversion. Including a circuit unit for processing the photoelectrons generated by the unit, the Si plug formed in the vertical direction, and the insulator layer and the Si substrate having the insulator layer formed on the surface are bonded together, and the first Electrically connecting the heavily doped layer and the Si plug through a second heavily doped layer.
本開示の第３の側面である電子装置は、固体撮像素子が搭載された電子装置において、前記固体撮像素子は、光電変換部を含む化合物半導体基板と、前記光電変換部により生成された光電子を処理するための回路部を含むＳｉ基板とが張り合わされて構成され、前記化合物半導体基板は、前記光電変換部と積層された第１の高濃度ドープ層を備え、前記Ｓｉ基板には、Ｓｉプラグを備え、前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層および前記Ｓｉプラグを介して前記回路部に転送される。
An electronic device according to a third aspect of the present disclosure is an electronic device in which a solid-state imaging element is mounted, wherein the solid-state imaging element includes a compound semiconductor substrate including a photoelectric conversion unit and photoelectrons generated by the photoelectric conversion unit. The compound semiconductor substrate includes a first heavily doped layer laminated with the photoelectric conversion unit, and the Si substrate includes a Si plug. The Si substrate including a circuit unit for processing is bonded to the Si substrate. The photoelectrons generated by the photoelectric conversion unit are transferred to the circuit unit via the first highly doped layer and the Si plug.
本開示の第１乃至第３の側面においては、固体撮像素子において化合物半導体基板に含まれる光電変換部により生成された光電子は、第１の高濃度ドープ層およびＳｉプラグを介してＳｉ基板に含まれる回路部に転送される。
In the first to third aspects of the present disclosure, the photoelectrons generated by the photoelectric conversion unit included in the compound semiconductor substrate in the solid-state imaging device are included in the Si substrate via the first highly doped layer and the Si plug. Is transferred to the circuit unit.
本開示の第１乃至３の側面によれば、固体撮像素子におけるショットノイズの増大を抑止することができる。
According to the first to third aspects of the present disclosure, an increase in shot noise in the solid-state imaging device can be suppressed.
以下、本開示を実施するための最良の形態（以下、実施の形態と称する）について、図面を参照しながら詳細に説明する。
Hereinafter, the best mode for carrying out the present disclosure (hereinafter referred to as an embodiment) will be described in detail with reference to the drawings.
＜本開示の実施の形態である固体撮像素子の第１の構成例＞
図２は、本開示の実施の形態である固体撮像素子の第１の構成例を示す断面図である。図３は、図２に示される固体撮像素子の受光面側の上面図である。 <First Configuration Example of Solid-State Imaging Device according to Embodiment of Present Disclosure>
FIG. 2 is a cross-sectional view illustrating a first configuration example of the solid-state imaging element according to the embodiment of the present disclosure. FIG. 3 is a top view of the light receiving surface side of the solid-state imaging device shown in FIG.
図２は、本開示の実施の形態である固体撮像素子の第１の構成例を示す断面図である。図３は、図２に示される固体撮像素子の受光面側の上面図である。 <First Configuration Example of Solid-State Imaging Device according to Embodiment of Present Disclosure>
FIG. 2 is a cross-sectional view illustrating a first configuration example of the solid-state imaging element according to the embodiment of the present disclosure. FIG. 3 is a top view of the light receiving surface side of the solid-state imaging device shown in FIG.
本開示の実施の形態である固体撮像素子３０の第１の構成例は、図１に示された従来の固体撮像素子１０と同様、回路部３２を含むＳｉ基板３１と、光電変換部３５を含む化合物半導体基板３４が張り合わされて構成される、いわゆる、積層型の固体撮像素子である。
The first configuration example of the solid-state imaging device 30 according to the embodiment of the present disclosure includes the Si substrate 31 including the circuit unit 32 and the photoelectric conversion unit 35 as in the conventional solid-state imaging device 10 illustrated in FIG. This is a so-called stacked type solid-state image pickup device in which the compound semiconductor substrate 34 including the substrate is laminated.
Ｓｉ基板３１には、MEM,FD，Vdd，TRX，TG，RSTなどの回路部３２が形成されており、化合物半導体基板３４と張り合わされる表面には絶縁体層３３が設けられている。また、Ｓｉ基板１１には、画素毎にＳｉプラグ４０が縦方向に設けられている。
The Si substrate 31 is formed with circuit portions 32 such as MEM, FD, Vdd, TRX, TG, and RST, and an insulator layer 33 is provided on the surface to be bonded to the compound semiconductor substrate 34. The Si substrate 11 is provided with Si plugs 40 in the vertical direction for each pixel.
一方、化合物半導体基板３４には、光電変換部３５（ｐ－化合物半導体３５Ａおよびｎ－化合物半導体３５Ｂからなるｐ－ｎ接合構造のフォトダイオード）が形成されており、光電変換部３５は、絶縁体層４２から成る画素分離部５１により画素毎に分離されている。光電変換部３５の下層側には、不純物濃度が１０１６／ｃｍ３以上５×１０１７／ｃｍ３以下にドープ(dope)された厚さ２０ｎｍ以下のｎ＋化合物半導体３６を介して絶縁体層３７が、上層側（受光面側）には上部透明電極３８が設けられている。
On the other hand, the compound semiconductor substrate 34 is formed with a photoelectric conversion part 35 (a photodiode having a pn junction structure made of a p-compound semiconductor 35A and an n-compound semiconductor 35B). Each pixel is separated by a pixel separation unit 51 formed of the layer 42. On the lower layer side of the photoelectric conversion unit 35, an insulator layer 37 is interposed via an n + compound semiconductor 36 having a thickness of 20 nm or less doped with an impurity concentration of 10 16 / cm 3 or more and 5 × 10 17 / cm 3 or less. However, the upper transparent electrode 38 is provided on the upper layer side (light receiving surface side).
Ｓｉ基板３１と化合物半導体基板３４とは、Ｓｉ基板３１の絶縁体層３３と化合物半導体基板３４の絶縁体層３７が対向するように張り合わされている。
The Si substrate 31 and the compound semiconductor substrate 34 are bonded together so that the insulator layer 33 of the Si substrate 31 and the insulator layer 37 of the compound semiconductor substrate 34 face each other.
Ｓｉ基板３１と化合物半導体基板３４とは、Ｓｉ基板３１の画素毎に縦方向に設けられるＳｉプラグ４０が絶縁体層３３および３７を貫いて形成されるエピタキシャル成長部分（Ｓｉプラグエピタキシャル層４１）と、化合物半導体基板３４のｎ＋化合物半導体３６の横方向に連なって形成された、ｎ＋化合物半導体３６とほぼ同じ厚さの薄いｎ＋Ｓｉ層４３とが接続されることにより電気的な接続が実現される。
The Si substrate 31 and the compound semiconductor substrate 34 include an epitaxially grown portion (Si plug epitaxial layer 41) in which an Si plug 40 provided in the vertical direction for each pixel of the Si substrate 31 is formed through the insulator layers 33 and 37; An electrical connection is realized by connecting a thin n + Si layer 43 having a thickness substantially the same as that of the n + compound semiconductor 36 formed continuously in the lateral direction of the n + compound semiconductor 36 of the compound semiconductor substrate 34.
固体撮像素子３０を構成する各部の具体例について説明する。Ｓｉ基板３１の上部表面に形成する絶縁体層３３には、Ｓｉ，Ａｌ，Ｔａ，Ｔｉなどの酸化膜、窒化膜などを採用できる。また、異なる材料の組み合わせを採用することもできる。さらに、界面準位の生成とその影響を抑制するために、Ｓｉ基板３１と絶縁体層３３の間に高濃度にドープされたＳｉ層を挿入することも可能である。
Specific examples of each part constituting the solid-state imaging device 30 will be described. For the insulator layer 33 formed on the upper surface of the Si substrate 31, an oxide film such as Si, Al, Ta, or Ti, a nitride film, or the like can be employed. Also, a combination of different materials can be employed. Further, a highly doped Si layer can be inserted between the Si substrate 31 and the insulator layer 33 in order to suppress the generation of interface states and its influence.
化合物半導体３４の下部表面に形成する絶縁体層３７には、Ｓｉ，Ａｌ，Ｔａ，Ｔｉなどの酸化膜、窒化膜などを採用できる。ｎ＋化合物半導体３６と絶縁体層３７の間に、界面準位の生成とその影響を抑制する化合物材料、Ｇａ，Ｉｎなどの酸化膜や窒化膜を挿入することも可能である。
For the insulator layer 37 formed on the lower surface of the compound semiconductor 34, an oxide film such as Si, Al, Ta, Ti, a nitride film, or the like can be employed. Between the n + compound semiconductor 36 and the insulator layer 37, it is also possible to insert a compound material that suppresses the generation of the interface state and its influence, an oxide film such as Ga, In, or a nitride film.
Ｓｉ基板３１に設けるＳｉプラグ４０の半導体極性は、本実施の形態ではｎ型としている。ただし、Ｓｉプラグ４０の半導体極性はその周囲の構成の半導体極性に応じて決まるので、Ｓｉプラグ４０の半導体極性をｐ型とする場合もあり得る。
The semiconductor polarity of the Si plug 40 provided on the Si substrate 31 is n-type in this embodiment. However, since the semiconductor polarity of the Si plug 40 is determined according to the semiconductor polarity of the surrounding configuration, the semiconductor polarity of the Si plug 40 may be p-type.
ｐ－化合物半導体３５ＡにはＺｎがドーピングされているＩｎＧａＡｓを採用することができ、ｎ－化合物半導体３５ＢにはＳｉがドーピングされているＩｎＧａＡｓを採用することができる。これらの他、化合物半導体には、Ａｌ，Ｇａ，Ｉｎのリン化物、ヒ化物、窒化物、アンチモン化物などのＩＩＩ－Ｖ系化合物、Ｚｎ，Ｃｄ，Ｔｅなどの硫化物、セレン化物、テルル化物などのＩＩ－ＶＩ系化合物などを採用することができる。
InGaAs doped with Zn can be used for the p-compound semiconductor 35A, and InGaAs doped with Si can be used for the n-compound semiconductor 35B. In addition to these, compound semiconductors include phosphides, arsenides, nitrides, antimonides, and other III-V compounds, sulfides such as Zn, Cd, Te, selenides, tellurides, etc. II-VI compounds and the like can be employed.
また、光電変換部３５には、ｐ－ｎ接合構造のフォトダイオードの代わりに、イントリンジック半導体層を挟んだｐ－ｉ－ｎ接合構造のフォトダイオードを採用してもよい。
Further, the photoelectric conversion unit 35 may employ a photodiode having a pin junction structure with an intrinsic semiconductor layer interposed therebetween, instead of the photodiode having a pn junction structure.
固体撮像素子３０においては、化合物半導体基板３４の光電変換部３５にて生成された光電子が、ｎ＋化合物半導体３６、ｎ＋Ｓｉ層４３、ｎＳｉプラグエピタキシャル層４１、およびｎＳｉプラグ４０を転送路として、Ｓｉ基板３１の回路部３２に転送され、電荷信号として後段に出力される。
In the solid-state imaging device 30, photoelectrons generated in the photoelectric conversion unit 35 of the compound semiconductor substrate 34 are transferred to the Si substrate using the n + compound semiconductor 36, the n + Si layer 43, the nSi plug epitaxial layer 41, and the nSi plug 40 as transfer paths. 31 is transferred to the circuit unit 32 and output to the subsequent stage as a charge signal.
固体撮像素子３０の場合、光電子の転送路に薄い高濃度半導体（ｎ＋化合物半導体３６）が存在するので、その部分での自由電子によるショットノイズが発生する。ただし、導体（図１の金属層１９および金属プラグ２２）と半導体（図２のｎ＋化合物半導体３６）とのキャリア濃度は１０５程度以上異なり、ショットノイズはその平方根に比例して低減する。よって、固体撮像素子３０は、光電子の転送路で発生するショットノイズを固体撮像素子１０に比較して削減することができる。
In the case of the solid-state imaging device 30, since a thin high-concentration semiconductor (n + compound semiconductor 36) is present in the photoelectron transfer path, shot noise due to free electrons occurs in that portion. However, the conductor carrier concentration (Figure 1 of the metal layer 19 and metal plug 22) and the semiconductor (n + compound semiconductor 36 in FIG. 2) is different than the order of 10 5, shot noise is reduced in proportion to the square root. Therefore, the solid-state imaging device 30 can reduce shot noise generated in the photoelectron transfer path compared to the solid-state imaging device 10.
また、自由電子数は、高濃度半導体（ｎ＋化合物半導体３６）および高濃度Ｓｉ層（ｎ＋Ｓｉ層４３）の体積に比例するため、これらの厚さは両者間で光電子を転送できる範囲で可能な限り薄いことが望ましい。
Moreover, since the number of free electrons is proportional to the volume of the high concentration semiconductor (n + compound semiconductor 36) and the high concentration Si layer (n + Si layer 43), these thicknesses are within the range where photoelectrons can be transferred between them. Thin is desirable.
＜本開示の実施の形態である固体撮像素子の第２の構成例＞
次に、図４は、本開示の実施の形態である固体撮像素子の第２の構成例を示す断面図である。図５は、図４に示される固体撮像素子の受光面側の上面図である。なお、図２および図３に示された第１の構成例と共通する構成要素に対しては同一の符号を付しているので、その説明は適宜省略する。 <Second Configuration Example of Solid-State Imaging Device according to Embodiment of Present Disclosure>
Next, FIG. 4 is a cross-sectional view illustrating a second configuration example of the solid-state imaging element according to the embodiment of the present disclosure. FIG. 5 is a top view of the light receiving surface side of the solid-state imaging device shown in FIG. Note that the same reference numerals are given to the components common to the first configuration example shown in FIGS. 2 and 3, and the description thereof will be omitted as appropriate.
次に、図４は、本開示の実施の形態である固体撮像素子の第２の構成例を示す断面図である。図５は、図４に示される固体撮像素子の受光面側の上面図である。なお、図２および図３に示された第１の構成例と共通する構成要素に対しては同一の符号を付しているので、その説明は適宜省略する。 <Second Configuration Example of Solid-State Imaging Device according to Embodiment of Present Disclosure>
Next, FIG. 4 is a cross-sectional view illustrating a second configuration example of the solid-state imaging element according to the embodiment of the present disclosure. FIG. 5 is a top view of the light receiving surface side of the solid-state imaging device shown in FIG. Note that the same reference numerals are given to the components common to the first configuration example shown in FIGS. 2 and 3, and the description thereof will be omitted as appropriate.
本開示の実施の形態である固体撮像素子３０の第２の構成例は、光電子を転送するためのＳｉプラグ４０を各画素の中央付近に配置したものである。この場合、Ｓｉプラグ４０を各画素の端に配置していた第１の構成例に比較し、光電子の転送路の横方向の距離が短くなるため、転送中に再結合してしまい電荷信号に変換されない光電子の数を減少させることができる。よって、光電子の転送効率を向上させることができる。
In the second configuration example of the solid-state imaging device 30 according to the embodiment of the present disclosure, the Si plug 40 for transferring photoelectrons is arranged near the center of each pixel. In this case, compared to the first configuration example in which the Si plug 40 is arranged at the end of each pixel, the lateral distance of the photoelectron transfer path is shortened, so that recombination occurs during transfer and the charge signal is generated. The number of unconverted photoelectrons can be reduced. Therefore, photoelectron transfer efficiency can be improved.
＜本開示の実施の形態である固体撮像素子の製造方法＞
次に、図６乃至図８は、本開示の実施の形態である固体撮像素子３０の第１の構成例の製造工程を示している。 <Method for Producing Solid-State Imaging Device According to Embodiment of Present Disclosure>
Next, FIGS. 6 to 8 illustrate a manufacturing process of the first configuration example of the solid-state imaging element 30 according to the embodiment of the present disclosure.
次に、図６乃至図８は、本開示の実施の形態である固体撮像素子３０の第１の構成例の製造工程を示している。 <Method for Producing Solid-State Imaging Device According to Embodiment of Present Disclosure>
Next, FIGS. 6 to 8 illustrate a manufacturing process of the first configuration example of the solid-
始めに、従来のCMOSイメージセンサの製造方法と同様の方法により、図６のＡに示す回路部３２およびＳｉプラグ４０を含むＳｉ基板３１を形成し、その表面に絶縁体層３３を形成する。Ｓｉプラグ４０は、例えばイオン注入等によって形成することができる。
First, the Si substrate 31 including the circuit portion 32 and the Si plug 40 shown in FIG. 6A is formed by the same method as the conventional CMOS image sensor manufacturing method, and the insulator layer 33 is formed on the surface thereof. The Si plug 40 can be formed, for example, by ion implantation.
次に、図６のＢに示すように、化合物半導体基板３４上に光電変換部３５、ｎ＋化合物半導体３６、および絶縁体層３７を形成する。化合物半導体基板３４には、例えばＩｎＰ基板の他、ＧａＡｓ基板、ＧａＰ基板、ＩｎＳｂ基板、ＩｎＡｓ基板などを用いることができる。光電変換部３５を成すｐ－化合物半導体３５Ａおよびｎ－化合物半導体３５Ｂの成膜にはMOCVD装置の他、MBE装置、LPE装置などを用いることができる。
Next, as shown in FIG. 6B, a photoelectric conversion portion 35, an n + compound semiconductor 36, and an insulator layer 37 are formed on the compound semiconductor substrate 34. As the compound semiconductor substrate 34, for example, a GaAs substrate, a GaP substrate, an InSb substrate, an InAs substrate, or the like can be used in addition to the InP substrate. In addition to the MOCVD apparatus, an MBE apparatus, an LPE apparatus, or the like can be used for forming the p-compound semiconductor 35A and the n-compound semiconductor 35B forming the photoelectric conversion unit 35.
絶縁体層３３および絶縁体層３７の成膜には、ALD装置の他、スパッタ装置、蒸着装置などを用いることができる。
In addition to the ALD apparatus, a sputtering apparatus, a vapor deposition apparatus, or the like can be used for forming the insulator layer 33 and the insulator layer 37.
このようにして形成されたＳｉ基板３１と化合物半導体基板３４は、図６のＣに示されるように、それぞれの絶縁体層３３と絶縁体層３７が貼り合わせ面となって接合される。この接合には、プラズマ接合の他、高温処理や薬液処理等を用いた直接接合などを用いることができる。
The Si substrate 31 and the compound semiconductor substrate 34 formed in this way are bonded to each other with the insulator layers 33 and the insulator layers 37 bonded together as shown in FIG. 6C. For this bonding, in addition to plasma bonding, direct bonding using high-temperature treatment, chemical solution treatment, or the like can be used.
次に、図７のＡに示されるように、化合物半導体基板３４の受光面側の化合物半導体３４Ａを機械研磨と薬液によるエッチングで除去した後、化合物半導体３４Ａ上にハードマスク６１を成膜する。さらに、フォトリソグラフィにより、１画素分の光電変換部３５に対応する領域以外のハードマスク６１を除去した後に、化合物半導体３４Ａ、ｐ－化合物半導体３５Ａ、ｎ－化合物半導体３５Ｂ、およびｎ＋化合物半導体３６のエッチングを行う。これにより、図７のＢに示されるように、ハードマスク６１の下層側にのみ化合物半導体３４Ａ、ｐ－化合物半導体３５Ａ、ｎ－化合物半導体３５Ｂ、およびｎ＋化合物半導体３６が残り、その周囲には画素分離部５１となる空間が形成される。
Next, as shown in FIG. 7A, the compound semiconductor 34A on the light receiving surface side of the compound semiconductor substrate 34 is removed by mechanical polishing and chemical etching, and then a hard mask 61 is formed on the compound semiconductor 34A. Further, after removing the hard mask 61 other than the region corresponding to the photoelectric conversion unit 35 for one pixel by photolithography, the compound semiconductor 34A, the p-compound semiconductor 35A, the n-compound semiconductor 35B, and the n + compound semiconductor 36 Etching is performed. As a result, as shown in FIG. 7B, the compound semiconductor 34A, the p-compound semiconductor 35A, the n-compound semiconductor 35B, and the n + compound semiconductor 36 remain only on the lower layer side of the hard mask 61, and a pixel is formed around the compound semiconductor 34A. A space to be the separation part 51 is formed.
そして、図７のＣに示されるように、画素分離部５１となる空間から、エッチングにより、絶縁体層３７および絶縁体層３３を貫いてＳｉプラグ４０に達する接続孔６２が形成される。続いて、図８のＡに示されるように、Ｓｉプラグエピタキシャル層４１とｎ＋Ｓｉ層４３を接続孔６２の位置に選択的にエピタキシャル成長させる。このとき、ｎ＋Ｓｉ層４３とｎ＋化合物半導体層４の断面位置が一致し、電気的に接続されるようにＳｉプラグエピタキシャル層４１の厚さを調整する。
Then, as shown in FIG. 7C, a connection hole 62 that reaches the Si plug 40 through the insulator layer 37 and the insulator layer 33 is formed by etching from the space that becomes the pixel separation portion 51. Subsequently, as shown in FIG. 8A, the Si plug epitaxial layer 41 and the n + Si layer 43 are selectively epitaxially grown at the position of the connection hole 62. At this time, the thickness of the Si plug epitaxial layer 41 is adjusted so that the cross-sectional positions of the n + Si layer 43 and the n + compound semiconductor layer 4 coincide and are electrically connected.
最後に、ハードマスク６１を除去した後、画素分離部５１の空間を埋めるように絶縁体層１３を成膜し、ｐ－化合物半導体３５Ａの表面が出るまで平面研磨を行い、その上に上部透明電極３８を成膜する。上部透明電極３８は、フォトリソグラフィとエッチングによって所望のパターンに加工する。以上のようにして固体撮像素子３０の第１の構成例は製造される。なお、固体撮像素子３０の第２の構成例についても同様の工程によって製造できる。
Finally, after removing the hard mask 61, the insulator layer 13 is formed so as to fill the space of the pixel separation portion 51, and planar polishing is performed until the surface of the p-compound semiconductor 35A comes out. An electrode 38 is formed. The upper transparent electrode 38 is processed into a desired pattern by photolithography and etching. As described above, the first configuration example of the solid-state imaging device 30 is manufactured. Note that the second configuration example of the solid-state imaging element 30 can be manufactured by the same process.
＜固体撮像素子３０の使用例＞
次に、図９は固体撮像素子３０の使用例を示している。 <Use Example of Solid-State Image Sensor 30>
Next, FIG. 9 shows an example of use of the solid-state imaging device 30.
次に、図９は固体撮像素子３０の使用例を示している。 <Use Example of Solid-
Next, FIG. 9 shows an example of use of the solid-
上述したイメージセンサは、例えば、以下のように、可視光や、赤外光、紫外光、Ｘ線等の光をセンシングする様々なケースに使用することができる。
The image sensor described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as follows.
・ディジタルカメラや、カメラ機能付きの携帯機器等の、鑑賞の用に供される画像を撮影する装置
・自動停止等の安全運転や、運転者の状態の認識等のために、自動車の前方や後方、周囲、車内等を撮影する車載用センサ、走行車両や道路を監視する監視カメラ、車両間等の測距を行う測距センサ等の、交通の用に供される装置
・ユーザのジェスチャを撮影して、そのジェスチャに従った機器操作を行うために、TVや、冷蔵庫、エアーコンディショナ等の家電に供される装置
・内視鏡や、赤外光の受光による血管撮影を行う装置等の、医療やヘルスケアの用に供される装置
・防犯用途の監視カメラや、人物認証用途のカメラ等の、セキュリティの用に供される装置
・肌を撮影する肌測定器や、頭皮を撮影するマイクロスコープ等の、美容の用に供される装置
・スポーツ用途等向けのアクションカメラやウェアラブルカメラ等の、スポーツの用に供される装置
・畑や作物の状態を監視するためのカメラ等の、農業の用に供される装置 ・ Devices for taking images for viewing, such as digital cameras and mobile devices with camera functions ・ For safe driving such as automatic stop and recognition of the driver's condition, Devices used for traffic, such as in-vehicle sensors that capture the back, surroundings, and interiors of vehicles, surveillance cameras that monitor traveling vehicles and roads, and ranging sensors that measure distances between vehicles, etc. Equipment used for home appliances such as TVs, refrigerators, air conditioners, etc. to take pictures and operate the equipment according to the gestures ・ Endoscopes, equipment that performs blood vessel photography by receiving infrared light, etc. Equipment used for medical and health care ・ Security equipment such as security surveillance cameras and personal authentication cameras ・ Skin measuring instrument for photographing skin and scalp photography Such as a microscope to do beauty Equipment used for sports-Equipment used for sports such as action cameras and wearable cameras for sports applications-Used for agriculture such as cameras for monitoring the condition of fields and crops apparatus
・自動停止等の安全運転や、運転者の状態の認識等のために、自動車の前方や後方、周囲、車内等を撮影する車載用センサ、走行車両や道路を監視する監視カメラ、車両間等の測距を行う測距センサ等の、交通の用に供される装置
・ユーザのジェスチャを撮影して、そのジェスチャに従った機器操作を行うために、TVや、冷蔵庫、エアーコンディショナ等の家電に供される装置
・内視鏡や、赤外光の受光による血管撮影を行う装置等の、医療やヘルスケアの用に供される装置
・防犯用途の監視カメラや、人物認証用途のカメラ等の、セキュリティの用に供される装置
・肌を撮影する肌測定器や、頭皮を撮影するマイクロスコープ等の、美容の用に供される装置
・スポーツ用途等向けのアクションカメラやウェアラブルカメラ等の、スポーツの用に供される装置
・畑や作物の状態を監視するためのカメラ等の、農業の用に供される装置 ・ Devices for taking images for viewing, such as digital cameras and mobile devices with camera functions ・ For safe driving such as automatic stop and recognition of the driver's condition, Devices used for traffic, such as in-vehicle sensors that capture the back, surroundings, and interiors of vehicles, surveillance cameras that monitor traveling vehicles and roads, and ranging sensors that measure distances between vehicles, etc. Equipment used for home appliances such as TVs, refrigerators, air conditioners, etc. to take pictures and operate the equipment according to the gestures ・ Endoscopes, equipment that performs blood vessel photography by receiving infrared light, etc. Equipment used for medical and health care ・ Security equipment such as security surveillance cameras and personal authentication cameras ・ Skin measuring instrument for photographing skin and scalp photography Such as a microscope to do beauty Equipment used for sports-Equipment used for sports such as action cameras and wearable cameras for sports applications-Used for agriculture such as cameras for monitoring the condition of fields and crops apparatus
なお、本開示の実施の形態は、上述した実施の形態に限定されるものではなく、本開示の要旨を逸脱しない範囲において種々の変更が可能である。
Note that the embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present disclosure.
本開示は以下のような構成も取ることができる。
（１）
光電変換部を含む化合物半導体基板と、前記光電変換部により生成された光電子を処理するための回路部を含むＳｉ基板とが張り合わされて構成される積層型の固体撮像素子において、
前記化合物半導体基板は、前記光電変換部と積層された第１の高濃度ドープ層を備え、
前記Ｓｉ基板には、Ｓｉプラグを備え、
前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層および前記Ｓｉプラグを介して前記回路部に転送される
固体撮像素子。
（２）
前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層、前記第１の高濃度ドープ層の側面に接する第２の高濃度ドープ層、および前記Ｓｉプラグを介して前記回路部に転送される
前記（１）に記載の固体撮像素子。
（３）
前記第２の高濃度ドープ層は、Ｓｉ層が前記第１の高濃度ドープ層と同じ半導体型で高濃度にドープされたものである
前記（２）に記載の固体撮像素子。
（４）
前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層、前記第１の高濃度ドープ層の側面に接する第２の高濃度ドープ層、前記Ｓｉプラグをエピタキシャル成長させたＳｉプラグエピタキシャル層、および前記Ｓｉプラグを介して前記回路部に転送される
前記（１）から（３）のいずれかに記載の固体撮像素子。
（５）
前記光電変換部は、化合物半導体がｐ－ｎ接合またはｐ－ｉ－ｎ接合されたフォトダイオードからなる
前記（１）から（４）のいずれかに記載の固体撮像素子。
（６）
前記フォトダイオードをなすｐ－化合物半導体には、Ｚｎ，Ｍｇ，Ｂｅ，Ｃのうち一種がドーピングされているＩｎＧａＡｓ、ＩＩＩ－Ｖ系化合物、またはＩＩ－ＶＩ系化合物が採用され、ｎ－化合物半導体には、Ｓｉ，Ｓ，Ｓｅ，Ｔｅのうち一種がドーピングされているＩｎＧａＡｓ、ＩＩＩ－Ｖ系化合物、またはＩＩ－ＶＩ系化合物が採用されている
前記（５）に記載の固体撮像素子。
（７）
前記化合物半導体基板は、前記光電変換部を１画素毎に分離するための画素分離部を
さらに備える前記（１）から（６）のいずれかに記載の固体撮像素子。
（８）
前記第２の高濃度ドープ層は、１画素毎に分離された前記光電変換部の外側の側面に接するように形成されている
前記（７）に記載の固体撮像素子。
（９）
前記第２の高濃度ドープ層は、１画素毎に分離された前記光電変換部の内側中央付近の側面に接するように形成されている
前記（７）に記載の固体撮像素子。
（１０）
前記第１の高濃度ドープ層は、不純物濃度が１０１６／ｃｍ３以上５×１０１７／ｃｍ３以下である
前記（１）から（９）のいずれかに記載の固体撮像素子。
（１１）
前記第１の高濃度ドープ層の厚さは、２０ｎｍ以下である
前記（１）から（１０）のいずれかに記載の固体撮像素子。
（１２）
前記第２の高濃度ドープ層の厚さは、前記第１の高濃度ドープ層の厚さと同程度である
前記（１１）に記載の固体撮像素子。
（１３）
前記化合物半導体基板と前記Ｓｉ基板は、プラズマ接合処理、高温処理、または薬液処理によって張り合わされている
前記（１）から（１２）のいずれかに記載の固体撮像素子。
（１４）
前記化合物半導体基板と前記Ｓｉ基板との貼り合わせ面には、絶縁体層が形成されている
前記（１）から（１３）のいずれかに記載の固体撮像素子。
（１５）
前記絶縁体層は、Ｓｉ，Ａｌ，Ｔａ、またはＴｉの酸化膜または窒化膜からなる
前記（１４）に記載の固体撮像素子。
（１６）
固体撮像素子の製造方法において、
光電変換部、第１の高濃度ドープ層、および絶縁体層が順に積層された化合物半導体基板と、前記光電変換部により生成された光電子を処理するための回路部を含み、縦方向にＳｉプラグが形成され、表面に絶縁体層が形成されたＳｉ基板との前記絶縁体層どうしを張り合わせ、
前記第第１の高濃度ドープ層と前記Ｓｉプラグとを第２の高濃度ドープ層を介して電気的に接続する
ステップを含む製造方法。
（１７）
固体撮像素子が搭載された電子装置において、
前記固体撮像素子は、
光電変換部を含む化合物半導体基板と、前記光電変換部により生成された光電子を処理するための回路部を含むＳｉ基板とが張り合わされて構成され、
前記化合物半導体基板は、前記光電変換部と積層された第１の高濃度ドープ層を備え、
前記Ｓｉ基板には、Ｓｉプラグを備え、
前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層および前記Ｓｉプラグを介して前記回路部に転送される
電子装置。 This indication can also take the following composition.
(1)
In a stacked solid-state imaging device configured by bonding a compound semiconductor substrate including a photoelectric conversion unit and an Si substrate including a circuit unit for processing photoelectrons generated by the photoelectric conversion unit,
The compound semiconductor substrate includes a first highly doped layer stacked with the photoelectric conversion unit,
The Si substrate includes a Si plug,
Photoelectrons generated by the photoelectric conversion unit are transferred to the circuit unit via the first highly doped layer and the Si plug.
(2)
The photoelectrons generated by the photoelectric conversion unit are connected to the circuit unit via the first heavily doped layer, the second heavily doped layer in contact with a side surface of the first heavily doped layer, and the Si plug. The solid-state imaging device according to (1).
(3)
The solid-state imaging device according to (2), wherein the second highly doped layer is a Si layer having the same semiconductor type as that of the first heavily doped layer and highly doped.
(4)
The photoelectrons generated by the photoelectric conversion unit are the first heavily doped layer, the second heavily doped layer in contact with the side surface of the first heavily doped layer, and the Si plug epitaxial obtained by epitaxially growing the Si plug. The solid-state imaging device according to any one of (1) to (3), wherein the solid-state imaging device is transferred to the circuit unit via a layer and the Si plug.
(5)
The solid-state imaging device according to any one of (1) to (4), wherein the photoelectric conversion unit includes a photodiode in which a compound semiconductor is a pn junction or a pin junction.
(6)
As the p-compound semiconductor forming the photodiode, InGaAs, III-V compound, or II-VI compound doped with one of Zn, Mg, Be, and C is adopted. The solid-state imaging device according to (5), wherein InGaAs, III-V compound, or II-VI compound doped with one of Si, S, Se, and Te is employed.
(7)
The solid-state imaging device according to any one of (1) to (6), wherein the compound semiconductor substrate further includes a pixel separation unit for separating the photoelectric conversion unit for each pixel.
(8)
The solid-state imaging device according to (7), wherein the second high-concentration doped layer is formed in contact with an outer side surface of the photoelectric conversion unit separated for each pixel.
(9)
The solid-state imaging device according to (7), wherein the second high-concentration doped layer is formed so as to be in contact with a side surface near an inner center of the photoelectric conversion unit separated for each pixel.
(10)
The solid-state imaging device according to any one of (1) to (9), wherein the first heavily doped layer has an impurity concentration of 10 16 / cm 3 or more and 5 × 10 17 / cm 3 or less.
(11)
The thickness of the first heavily doped layer is 20 nm or less. The solid-state imaging device according to any one of (1) to (10).
(12)
The thickness of the second highly doped layer is approximately the same as the thickness of the first heavily doped layer. The solid-state imaging device according to (11).
(13)
The solid-state imaging device according to any one of (1) to (12), wherein the compound semiconductor substrate and the Si substrate are bonded together by a plasma bonding process, a high temperature process, or a chemical process.
(14)
The solid-state imaging device according to any one of (1) to (13), wherein an insulating layer is formed on a bonding surface between the compound semiconductor substrate and the Si substrate.
(15)
The solid-state imaging device according to (14), wherein the insulator layer is made of an oxide film or a nitride film of Si, Al, Ta, or Ti.
(16)
In the method for manufacturing a solid-state imaging device,
A compound semiconductor substrate in which a photoelectric conversion unit, a first high-concentration doped layer, and an insulator layer are sequentially stacked, and a circuit unit for processing photoelectrons generated by the photoelectric conversion unit, including a Si plug in a vertical direction And the insulator layers with the Si substrate having the insulator layer formed on the surface are bonded together,
A manufacturing method including the step of electrically connecting the first heavily doped layer and the Si plug via a second heavily doped layer.
(17)
In an electronic device equipped with a solid-state image sensor,
The solid-state imaging device is
A compound semiconductor substrate including a photoelectric conversion unit and a Si substrate including a circuit unit for processing photoelectrons generated by the photoelectric conversion unit are bonded to each other.
The compound semiconductor substrate includes a first highly doped layer stacked with the photoelectric conversion unit,
The Si substrate includes a Si plug,
The photoelectron generated by the photoelectric conversion unit is transferred to the circuit unit via the first highly doped layer and the Si plug.
（１）
光電変換部を含む化合物半導体基板と、前記光電変換部により生成された光電子を処理するための回路部を含むＳｉ基板とが張り合わされて構成される積層型の固体撮像素子において、
前記化合物半導体基板は、前記光電変換部と積層された第１の高濃度ドープ層を備え、
前記Ｓｉ基板には、Ｓｉプラグを備え、
前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層および前記Ｓｉプラグを介して前記回路部に転送される
固体撮像素子。
（２）
前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層、前記第１の高濃度ドープ層の側面に接する第２の高濃度ドープ層、および前記Ｓｉプラグを介して前記回路部に転送される
前記（１）に記載の固体撮像素子。
（３）
前記第２の高濃度ドープ層は、Ｓｉ層が前記第１の高濃度ドープ層と同じ半導体型で高濃度にドープされたものである
前記（２）に記載の固体撮像素子。
（４）
前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層、前記第１の高濃度ドープ層の側面に接する第２の高濃度ドープ層、前記Ｓｉプラグをエピタキシャル成長させたＳｉプラグエピタキシャル層、および前記Ｓｉプラグを介して前記回路部に転送される
前記（１）から（３）のいずれかに記載の固体撮像素子。
（５）
前記光電変換部は、化合物半導体がｐ－ｎ接合またはｐ－ｉ－ｎ接合されたフォトダイオードからなる
前記（１）から（４）のいずれかに記載の固体撮像素子。
（６）
前記フォトダイオードをなすｐ－化合物半導体には、Ｚｎ，Ｍｇ，Ｂｅ，Ｃのうち一種がドーピングされているＩｎＧａＡｓ、ＩＩＩ－Ｖ系化合物、またはＩＩ－ＶＩ系化合物が採用され、ｎ－化合物半導体には、Ｓｉ，Ｓ，Ｓｅ，Ｔｅのうち一種がドーピングされているＩｎＧａＡｓ、ＩＩＩ－Ｖ系化合物、またはＩＩ－ＶＩ系化合物が採用されている
前記（５）に記載の固体撮像素子。
（７）
前記化合物半導体基板は、前記光電変換部を１画素毎に分離するための画素分離部を
さらに備える前記（１）から（６）のいずれかに記載の固体撮像素子。
（８）
前記第２の高濃度ドープ層は、１画素毎に分離された前記光電変換部の外側の側面に接するように形成されている
前記（７）に記載の固体撮像素子。
（９）
前記第２の高濃度ドープ層は、１画素毎に分離された前記光電変換部の内側中央付近の側面に接するように形成されている
前記（７）に記載の固体撮像素子。
（１０）
前記第１の高濃度ドープ層は、不純物濃度が１０１６／ｃｍ３以上５×１０１７／ｃｍ３以下である
前記（１）から（９）のいずれかに記載の固体撮像素子。
（１１）
前記第１の高濃度ドープ層の厚さは、２０ｎｍ以下である
前記（１）から（１０）のいずれかに記載の固体撮像素子。
（１２）
前記第２の高濃度ドープ層の厚さは、前記第１の高濃度ドープ層の厚さと同程度である
前記（１１）に記載の固体撮像素子。
（１３）
前記化合物半導体基板と前記Ｓｉ基板は、プラズマ接合処理、高温処理、または薬液処理によって張り合わされている
前記（１）から（１２）のいずれかに記載の固体撮像素子。
（１４）
前記化合物半導体基板と前記Ｓｉ基板との貼り合わせ面には、絶縁体層が形成されている
前記（１）から（１３）のいずれかに記載の固体撮像素子。
（１５）
前記絶縁体層は、Ｓｉ，Ａｌ，Ｔａ、またはＴｉの酸化膜または窒化膜からなる
前記（１４）に記載の固体撮像素子。
（１６）
固体撮像素子の製造方法において、
光電変換部、第１の高濃度ドープ層、および絶縁体層が順に積層された化合物半導体基板と、前記光電変換部により生成された光電子を処理するための回路部を含み、縦方向にＳｉプラグが形成され、表面に絶縁体層が形成されたＳｉ基板との前記絶縁体層どうしを張り合わせ、
前記第第１の高濃度ドープ層と前記Ｓｉプラグとを第２の高濃度ドープ層を介して電気的に接続する
ステップを含む製造方法。
（１７）
固体撮像素子が搭載された電子装置において、
前記固体撮像素子は、
光電変換部を含む化合物半導体基板と、前記光電変換部により生成された光電子を処理するための回路部を含むＳｉ基板とが張り合わされて構成され、
前記化合物半導体基板は、前記光電変換部と積層された第１の高濃度ドープ層を備え、
前記Ｓｉ基板には、Ｓｉプラグを備え、
前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層および前記Ｓｉプラグを介して前記回路部に転送される
電子装置。 This indication can also take the following composition.
(1)
In a stacked solid-state imaging device configured by bonding a compound semiconductor substrate including a photoelectric conversion unit and an Si substrate including a circuit unit for processing photoelectrons generated by the photoelectric conversion unit,
The compound semiconductor substrate includes a first highly doped layer stacked with the photoelectric conversion unit,
The Si substrate includes a Si plug,
Photoelectrons generated by the photoelectric conversion unit are transferred to the circuit unit via the first highly doped layer and the Si plug.
(2)
The photoelectrons generated by the photoelectric conversion unit are connected to the circuit unit via the first heavily doped layer, the second heavily doped layer in contact with a side surface of the first heavily doped layer, and the Si plug. The solid-state imaging device according to (1).
(3)
The solid-state imaging device according to (2), wherein the second highly doped layer is a Si layer having the same semiconductor type as that of the first heavily doped layer and highly doped.
(4)
The photoelectrons generated by the photoelectric conversion unit are the first heavily doped layer, the second heavily doped layer in contact with the side surface of the first heavily doped layer, and the Si plug epitaxial obtained by epitaxially growing the Si plug. The solid-state imaging device according to any one of (1) to (3), wherein the solid-state imaging device is transferred to the circuit unit via a layer and the Si plug.
(5)
The solid-state imaging device according to any one of (1) to (4), wherein the photoelectric conversion unit includes a photodiode in which a compound semiconductor is a pn junction or a pin junction.
(6)
As the p-compound semiconductor forming the photodiode, InGaAs, III-V compound, or II-VI compound doped with one of Zn, Mg, Be, and C is adopted. The solid-state imaging device according to (5), wherein InGaAs, III-V compound, or II-VI compound doped with one of Si, S, Se, and Te is employed.
(7)
The solid-state imaging device according to any one of (1) to (6), wherein the compound semiconductor substrate further includes a pixel separation unit for separating the photoelectric conversion unit for each pixel.
(8)
The solid-state imaging device according to (7), wherein the second high-concentration doped layer is formed in contact with an outer side surface of the photoelectric conversion unit separated for each pixel.
(9)
The solid-state imaging device according to (7), wherein the second high-concentration doped layer is formed so as to be in contact with a side surface near an inner center of the photoelectric conversion unit separated for each pixel.
(10)
The solid-state imaging device according to any one of (1) to (9), wherein the first heavily doped layer has an impurity concentration of 10 16 / cm 3 or more and 5 × 10 17 / cm 3 or less.
(11)
The thickness of the first heavily doped layer is 20 nm or less. The solid-state imaging device according to any one of (1) to (10).
(12)
The thickness of the second highly doped layer is approximately the same as the thickness of the first heavily doped layer. The solid-state imaging device according to (11).
(13)
The solid-state imaging device according to any one of (1) to (12), wherein the compound semiconductor substrate and the Si substrate are bonded together by a plasma bonding process, a high temperature process, or a chemical process.
(14)
The solid-state imaging device according to any one of (1) to (13), wherein an insulating layer is formed on a bonding surface between the compound semiconductor substrate and the Si substrate.
(15)
The solid-state imaging device according to (14), wherein the insulator layer is made of an oxide film or a nitride film of Si, Al, Ta, or Ti.
(16)
In the method for manufacturing a solid-state imaging device,
A compound semiconductor substrate in which a photoelectric conversion unit, a first high-concentration doped layer, and an insulator layer are sequentially stacked, and a circuit unit for processing photoelectrons generated by the photoelectric conversion unit, including a Si plug in a vertical direction And the insulator layers with the Si substrate having the insulator layer formed on the surface are bonded together,
A manufacturing method including the step of electrically connecting the first heavily doped layer and the Si plug via a second heavily doped layer.
(17)
In an electronic device equipped with a solid-state image sensor,
The solid-state imaging device is
A compound semiconductor substrate including a photoelectric conversion unit and a Si substrate including a circuit unit for processing photoelectrons generated by the photoelectric conversion unit are bonded to each other.
The compound semiconductor substrate includes a first highly doped layer stacked with the photoelectric conversion unit,
The Si substrate includes a Si plug,
The photoelectron generated by the photoelectric conversion unit is transferred to the circuit unit via the first highly doped layer and the Si plug.
３０ 固体撮像素子， ３１ Ｓｉ基板， ３２ 回路部， ３３ 絶縁体層， ３４ 化合物半導体基板， ３５ 光電変換部， ３５Ａ ｐ－化合物半導体， ３５Ｂ ｎ－化合物半導体， ３６ ｎ＋化合物半導体， ３７ 絶縁体層， ３８ 上部透明電極， ４０ Ｓｉプラグ， ４１ Ｓｉプラグエピタキシャル層， ４２ 絶縁体層， ４３ ｎ＋Ｓｉ層， ５１ 画素分離部， ５２ 画素境界
30 solid-state imaging device, 31 Si substrate, 32 circuit part, 33 insulator layer, 34 compound semiconductor substrate, 35 photoelectric conversion part, 35A p-compound semiconductor, 35B n-compound semiconductor, 36 n + compound semiconductor, 37 insulator layer, 38 upper transparent electrode, 40 Si plug, 41 Si plug epitaxial layer, 42 insulator layer, 43 n + Si layer, 51 pixel separation part, 52 pixel boundary
Claims (17)
- 光電変換部を含む化合物半導体基板と、前記光電変換部により生成された光電子を処理するための回路部を含むＳｉ基板とが張り合わされて構成される積層型の固体撮像素子において、
前記化合物半導体基板は、前記光電変換部と積層された第１の高濃度ドープ層を備え、
前記Ｓｉ基板には、Ｓｉプラグを備え、
前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層および前記Ｓｉプラグを介して前記回路部に転送される
固体撮像素子。 In a stacked solid-state imaging device configured by bonding a compound semiconductor substrate including a photoelectric conversion unit and an Si substrate including a circuit unit for processing photoelectrons generated by the photoelectric conversion unit,
The compound semiconductor substrate includes a first highly doped layer stacked with the photoelectric conversion unit,
The Si substrate includes a Si plug,
Photoelectrons generated by the photoelectric conversion unit are transferred to the circuit unit via the first highly doped layer and the Si plug. - 前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層、前記第１の高濃度ドープ層の側面に接する第２の高濃度ドープ層、および前記Ｓｉプラグを介して前記回路部に転送される
請求項１に記載の固体撮像素子。 The photoelectrons generated by the photoelectric conversion unit are connected to the circuit unit via the first heavily doped layer, the second heavily doped layer in contact with a side surface of the first heavily doped layer, and the Si plug. The solid-state imaging device according to claim 1. - 前記第２の高濃度ドープ層は、Ｓｉ層が前記第１の高濃度ドープ層と同じ半導体型で高濃度にドープされたものである
請求項２に記載の固体撮像素子。 3. The solid-state imaging device according to claim 2, wherein the second highly doped layer is formed by doping a Si layer with the same semiconductor type as the first heavily doped layer to a high concentration. - 前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層、前記第１の高濃度ドープ層の側面に接する第２の高濃度ドープ層、前記Ｓｉプラグをエピタキシャル成長させたＳｉプラグエピタキシャル層、および前記Ｓｉプラグを介して前記回路部に転送される
請求項２に記載の固体撮像素子。 The photoelectrons generated by the photoelectric conversion unit are the first heavily doped layer, the second heavily doped layer in contact with the side surface of the first heavily doped layer, and the Si plug epitaxial obtained by epitaxially growing the Si plug. The solid-state imaging device according to claim 2, wherein the layer is transferred to the circuit unit via the Si plug. - 前記光電変換部は、化合物半導体がｐ－ｎ接合またはｐ－ｉ－ｎ接合されたフォトダイオードからなる
請求項２に記載の固体撮像素子。 The solid-state imaging device according to claim 2, wherein the photoelectric conversion unit includes a photodiode in which a compound semiconductor is a pn junction or a pin junction. - 前記フォトダイオードをなすｐ－化合物半導体には、Ｚｎ，Ｍｇ，Ｂｅ，Ｃのうち一種がドーピングされているＩｎＧａＡｓ、ＩＩＩ－Ｖ系化合物、またはＩＩ－ＶＩ系化合物が採用され、ｎ－化合物半導体には、Ｓｉ，Ｓ，Ｓｅ，Ｔｅのうち一種がドーピングされているＩｎＧａＡｓ、ＩＩＩ－Ｖ系化合物、またはＩＩ－ＶＩ系化合物が採用されている
請求項２に記載の固体撮像素子。 As the p-compound semiconductor forming the photodiode, InGaAs, III-V compound, or II-VI compound doped with one of Zn, Mg, Be, and C is adopted. The solid-state imaging device according to claim 2, wherein InGaAs, III-V compound, or II-VI compound doped with one of Si, S, Se, and Te is employed. - 前記化合物半導体基板は、前記光電変換部を１画素毎に分離するための画素分離部を
さらに備える請求項２に記載の固体撮像素子。 The solid-state imaging device according to claim 2, wherein the compound semiconductor substrate further includes a pixel separation unit for separating the photoelectric conversion unit for each pixel. - 前記第２の高濃度ドープ層は、１画素毎に分離された前記光電変換部の外側の側面に接するように形成されている
請求項２に記載の固体撮像素子。 The solid-state imaging element according to claim 2, wherein the second high-concentration doped layer is formed so as to contact an outer side surface of the photoelectric conversion unit separated for each pixel. - 前記第２の高濃度ドープ層は、１画素毎に分離された前記光電変換部の内側中央付近の側面に接するように形成されている
請求項２に記載の固体撮像素子。 The solid-state imaging device according to claim 2, wherein the second high-concentration doped layer is formed so as to be in contact with a side surface near an inner center of the photoelectric conversion unit separated for each pixel. - 前記第１の高濃度ドープ層は、不純物濃度が１０１６／ｃｍ３以上５×１０１７／ｃｍ３以下である
請求項２に記載の固体撮像素子。 The solid-state imaging device according to claim 2, wherein the first highly doped layer has an impurity concentration of 10 16 / cm 3 or more and 5 × 10 17 / cm 3 or less. - 前記第１の高濃度ドープ層の厚さは、２０ｎｍ以下である
請求項２に記載の固体撮像素子。 The solid-state imaging device according to claim 2, wherein a thickness of the first highly doped layer is 20 nm or less. - 前記第２の高濃度ドープ層の厚さは、前記第１の高濃度ドープ層の厚さと同程度である
請求項１１に記載の固体撮像素子。 The solid-state imaging device according to claim 11, wherein a thickness of the second heavily doped layer is approximately the same as a thickness of the first heavily doped layer. - 前記化合物半導体基板と前記Ｓｉ基板は、プラズマ接合処理、高温処理、または薬液処理によって張り合わされている
請求項２に記載の固体撮像素子。 The solid-state imaging device according to claim 2, wherein the compound semiconductor substrate and the Si substrate are bonded together by a plasma bonding process, a high temperature process, or a chemical process. - 前記化合物半導体基板と前記Ｓｉ基板との貼り合わせ面には、絶縁体層が形成されている
請求項２に記載の固体撮像素子。 The solid-state imaging device according to claim 2, wherein an insulator layer is formed on a bonding surface between the compound semiconductor substrate and the Si substrate. - 前記絶縁体層は、Ｓｉ，Ａｌ，Ｔａ、またはＴｉの酸化膜または窒化膜からなる
請求項１４に記載の固体撮像素子。 The solid-state imaging device according to claim 14, wherein the insulator layer is made of an oxide film or a nitride film of Si, Al, Ta, or Ti. - 固体撮像素子の製造方法において、
光電変換部、第１の高濃度ドープ層、および絶縁体層が順に積層された化合物半導体基板と、前記光電変換部により生成された光電子を処理するための回路部を含み、縦方向にＳｉプラグが形成され、表面に絶縁体層が形成されたＳｉ基板との前記絶縁体層どうしを張り合わせ、
前記第第１の高濃度ドープ層と前記Ｓｉプラグとを第２の高濃度ドープ層を介して電気的に接続する
ステップを含む製造方法。 In the method for manufacturing a solid-state imaging device,
A compound semiconductor substrate in which a photoelectric conversion unit, a first high-concentration doped layer, and an insulator layer are sequentially stacked, and a circuit unit for processing photoelectrons generated by the photoelectric conversion unit, including a Si plug in a vertical direction And the insulator layers with the Si substrate having the insulator layer formed on the surface are bonded together,
A manufacturing method including the step of electrically connecting the first heavily doped layer and the Si plug via a second heavily doped layer. - 固体撮像素子が搭載された電子装置において、
前記固体撮像素子は、
光電変換部を含む化合物半導体基板と、前記光電変換部により生成された光電子を処理するための回路部を含むＳｉ基板とが張り合わされて構成され、
前記化合物半導体基板は、前記光電変換部と積層された第１の高濃度ドープ層を備え、
前記Ｓｉ基板には、Ｓｉプラグを備え、
前記光電変換部により生成された光電子は、前記第１の高濃度ドープ層および前記Ｓｉプラグを介して前記回路部に転送される
電子装置。 In an electronic device equipped with a solid-state image sensor,
The solid-state imaging device is
A compound semiconductor substrate including a photoelectric conversion unit and a Si substrate including a circuit unit for processing photoelectrons generated by the photoelectric conversion unit are bonded to each other.
The compound semiconductor substrate includes a first highly doped layer stacked with the photoelectric conversion unit,
The Si substrate includes a Si plug,
The photoelectron generated by the photoelectric conversion unit is transferred to the circuit unit via the first highly doped layer and the Si plug.
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