WO2016072005A1 - Solar cell - Google Patents

Solar cell Download PDF

Info

Publication number
WO2016072005A1
WO2016072005A1 PCT/JP2014/079521 JP2014079521W WO2016072005A1 WO 2016072005 A1 WO2016072005 A1 WO 2016072005A1 JP 2014079521 W JP2014079521 W JP 2014079521W WO 2016072005 A1 WO2016072005 A1 WO 2016072005A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
crystalline
polarity
heavily doped
polar
Prior art date
Application number
PCT/JP2014/079521
Other languages
French (fr)
Japanese (ja)
Inventor
敬司 渡邉
峰 利之
克矢 小田
真 三浦
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to PCT/JP2014/079521 priority Critical patent/WO2016072005A1/en
Publication of WO2016072005A1 publication Critical patent/WO2016072005A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Definitions

  • the present invention relates to a solar battery cell.
  • Sunlight is composed of light in a wide wavelength range, and light that can be absorbed by the solar battery cell is light having energy equal to or higher than the band gap of the semiconductor material of the power generation layer. Electron-hole pairs are generated by the energy of the absorbed light, and electrons and holes are collected in separate electrodes, creating a potential difference between the electrodes and generating power. This is the operation principle of the battery cell.
  • surplus energy exceeding the band gap hereinafter referred to as Eg is dissipated as heat in a general solar battery cell.
  • multi-exciton generation is a phenomenon in which electron-hole pairs are further generated by surplus energy when the surplus energy is twice or more Eg (hereinafter referred to as 2Eg).
  • Patent Document 1 discloses a method of using multi-exciton generation in a crystalline silicon (hereinafter referred to as crystalline Si) solar battery cell.
  • crystalline Si crystalline silicon
  • the internal quantum efficiency is More than 1 phenomenon was observed.
  • the internal quantum efficiency represents the number of electrons and holes generated from one photon absorbed inside the solar battery cell and collected by the electrode. Therefore, an internal quantum efficiency exceeding 1 indicates that multi-exciton generation occurs inside the solar battery cell.
  • multi-exciton generation is a phenomenon that occurs due to high-energy light.
  • high-energy light is absorbed near the surface of a solar battery cell.
  • a high-quality surface passivation film is necessary for use.
  • a low-quality surface passivation film that is, when there are many recombination levels at the interface between the surface passivation film and the power generation layer, electrons and holes generated by multi-exciton generation are collected at the electrode. There is a high probability of disappearing by recombination before being done.
  • a SiO 2 film formed by a thermal oxidation method is used as a high-quality passivation film.
  • Non-Patent Document 1 describes a mixed crystal of Si and Ge (hereinafter referred to as crystalline Si 1-x Ge x .
  • x is a composition ratio of Ge and takes a value of 0 ⁇ x ⁇ 1.
  • the calculation results of ⁇ and Eg are described in FIG. According to this, both ⁇ ⁇ and Eg monotonously decrease with respect to x, and furthermore, the value of ⁇ ⁇ -2Eg monotonously decreases with respect to x.
  • x ⁇ 0.68 in ⁇ ⁇ -2Eg> is 0, x> in 0.68 ⁇ ⁇ -2Eg ⁇ 0.
  • Non-Patent Document 2 describes a method using a composition gradient buffer layer as a method of forming a crystalline Si 1-x Ge x film on a crystalline Si substrate.
  • Non-Patent Document 2 by using the composition graded buffer layer, on a crystalline Si substrate, directly, as compared with the case of forming a crystalline Si 1-x Ge x film, the crystalline Si 1-x Ge x film It is possible to reduce the crystal defect density.
  • Patent Document 2 describes a method using a Ge buffer layer as a method of forming a crystalline Ge film on a crystalline Si substrate. According to this, a Ge buffer layer is first formed on a crystalline Si substrate, and the Ge buffer layer is lattice-relaxed by applying heat treatment. Thereafter, a crystalline Ge layer is formed on the Ge buffer layer. According to Patent Document 2, it is possible to form a crystalline Ge layer having a low crystal defect density on a crystalline Si substrate by using a Ge buffer layer.
  • Patent Document 3 describes the diffusion coefficient of phosphorus in crystalline Si 1-x Ge x . According to this, the higher the Ge composition x of the crystalline Si 1-x Ge x , the larger the diffusion coefficient of phosphorus, and in particular, the diffusion coefficient of phosphorus in crystalline Ge is the diffusion coefficient of phosphorus in crystalline Si. 10 5 times or more.
  • the first problem relates to a method for forming a crystalline Si 1-x Ge x film.
  • the composition gradient buffer is increased as the Ge composition x of the crystalline Si 1-x Ge x film is increased. It is necessary to form a thick layer. Since the composition gradient buffer layer is a film having a high defect density, there is a high probability that carriers passing through the composition gradient buffer layer will recombine during solar cell operation.
  • the composition gradient buffer layer is formed thick, the crystal defect density of the crystalline Si 1-x Ge x film formed thereon increases with the Ge composition x. For this reason, carrier recombination inside the crystalline Si 1-x Ge x film during solar cell operation is more likely to occur as the Ge composition x is higher. Therefore, when a solar cell using a crystalline Si 1-x Ge x film having a high Ge composition x as a power generation layer using a composition gradient buffer layer, there is a problem that the carrier recombination probability is high.
  • the second problem relates to a method of forming a selective emitter for a stacked film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge.
  • the selective emitter refers to an emitter formed locally only on the lower part of the surface electrode among the emitters formed on the light receiving surface (hereinafter referred to as surface) side of the solar battery cell.
  • surface the light receiving surface
  • the higher the doping concentration of the emitter the higher the carrier recombination probability inside the emitter, while the higher the doping concentration of the emitter, the lower the contact resistance between the emitter and the emitter and the electrode. To do.
  • the higher the doping concentration of the emitter the lower the potential energy of the selected emitter region for the electrons, thereby improving the carrier collection efficiency.
  • an emitter having a relatively low doping concentration is formed on the entire surface, and the doping concentration is relatively low only in the lower part of the surface electrode that is shielded by the surface electrode and does not receive light.
  • a technique of reducing the contact resistance between the emitter and the electrode is often used by forming a high selective emitter so as to cover the contact hole.
  • FIG. 10 shows the results of experiments conducted by the present inventors prior to the present invention.
  • the vertical axis represents the internal quantum efficiency at a wavelength of 290 nm of the crystalline Si solar cell, and the horizontal axis represents the surface phosphorous concentration of the selected emitter. It is a graph.
  • the internal quantum efficiency is the number of electron-hole pairs collected by the electrode per photon absorbed inside the solar battery cell. That is, the internal quantum efficiency exceeds 1 when multi-exciton generation occurs and the resulting electron-hole pairs are collected at the electrode.
  • the surface phosphorus concentration of the emitter formed on the entire surface other than the selected emitter is 3.5 ⁇ 10 18 cm ⁇ 3 .
  • the data with the lowest surface phosphorous concentration of the selected emitter represents the characteristics of the solar cell in which the emitter of the same concentration is formed on the entire surface without the selected emitter.
  • the internal quantum efficiency does not exceed 1, and the internal quantum efficiency exceeds 1 by forming a selective emitter having a higher phosphorus concentration.
  • the cause is considered to be that the carrier collection efficiency is improved by forming the selective emitter.
  • the data in FIG. 10 means that it is necessary to form a selective emitter in order to utilize multi-exciton production in a solar cell.
  • the internal quantum efficiency exceeds 1 when the surface phosphor concentration of the selective emitter is 8 ⁇ 10 18 cm ⁇ 3 or more and 7 ⁇ 10 19 cm ⁇ 3 or less.
  • the width of the selective emitter of the crystalline Ge layer is larger than the width of the selective emitter of crystalline Si and therefore larger than the width of the contact hole.
  • the width of the selective emitter of the crystalline Ge layer becomes larger than the width of the surface electrode, and a part of the selective emitter may be formed in a region that is not shielded by the surface electrode.
  • the composition of Ge using the composition gradient buffer layer is as follows.
  • a solar cell using a crystalline Si 1-x Ge x film having a high x as a power generation layer is produced, there is a problem that the carrier recombination probability is high.
  • a selective emitter is formed for a stacked film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge, a part of the selective emitter is shielded by the surface electrode due to the difference in phosphorus diffusion coefficient. There is a problem that a loss due to carrier recombination occurs in a region that is not formed.
  • a typical object of the present invention is to realize a highly efficient solar cell by making use of multi-exciton generation and reducing carrier recombination loss at the same time.
  • a solar cell a first polar crystalline Si substrate, a Ge buffer layer formed on the surface of the first polar crystalline Si substrate, and a crystalline Ge layer formed on the surface of the Ge buffer layer
  • a second polarity crystalline Si 1-x Ge x layer formed on the surface of the crystalline Ge layer, and a second polarity crystalline Si layer formed on the surface of the second polarity crystalline Si 1-x Ge x layer
  • a passivation layer formed of an insulating material on the surface of the second polar crystalline Si layer, a second polar highly doped crystalline Si layer formed in the same plane as the second polar crystalline Si layer, A surface electrode formed on the surface of the second polarity highly doped crystal Si layer, and the second polarity highly doped crystal Si at the interface between the second polarity highly doped crystal Si layer and the surface electrode
  • the width of the layer is such that the heavily doped crystalline Si layer of the second polarity is connected to the second polarity.
  • Si 1-x Ge x is larger than
  • a solar cell a first polar crystalline Si substrate, a Ge buffer layer formed on the surface of the first polar crystalline Si substrate, and a crystalline Ge layer formed on the surface of the Ge buffer layer
  • a solar cell a first polar crystalline Si substrate, an insulating film formed on the surface of the first polar crystalline Si substrate, a crystalline Ge layer formed on the surface of the insulating film, A second polarity crystalline Si 1-x Ge x layer formed on the surface of the crystalline Ge layer, a second polarity crystalline Si layer formed on the surface of the second polarity crystalline Si 1-x Ge x layer, A passivation layer formed of an insulating material on the surface of the second polar crystalline Si layer, and a surface electrode formed on the surface of the second polar crystalline Si layer, wherein the second polar crystalline Si layer is The first polar crystalline Si substrate and the crystalline Ge layer are in contact with each other.
  • a high-efficiency solar cell can be obtained by simultaneously using multi-exciton generation and reducing carrier recombination loss. Can be realized.
  • FIG.2 It is sectional drawing which shows the manufacturing method of a photovoltaic cell following FIG.2 (d). It is a top view which shows the manufacturing method of a photovoltaic cell following FIG.2 (e). It is sectional drawing which shows the manufacturing method of the photovoltaic cell following FIG.2 (f). It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.2 (g). It is sectional drawing which shows the manufacturing method of a photovoltaic cell following FIG.2 (h). It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.2 (i). It is sectional drawing which shows the manufacturing method of the photovoltaic cell following FIG.2 (j).
  • FIG.4 It is sectional drawing which shows the manufacturing method of a photovoltaic cell following FIG.4 (d). It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.4 (e). It is sectional drawing which shows the manufacturing method of a photovoltaic cell following FIG.4 (f). It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.4 (g). It is sectional drawing which shows the manufacturing method of the photovoltaic cell following FIG.4 (h). It is a top view which shows the photovoltaic cell which concerns on Example 3 of this invention. It is sectional drawing which shows the photovoltaic cell which concerns on Example 3 of this invention.
  • FIG. 6 is a top view showing a solar cell in the case where a selective emitter is formed by a conventional technique with respect to a laminated film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge.
  • FIG. 6 is a top view showing a solar cell in the case where a selective emitter is formed by a conventional technique with respect to a laminated film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge.
  • FIG. 6 is a cross-sectional view showing a solar cell in the case where a selective emitter is formed by a conventional technique with respect to a laminated film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge. It is a graph which shows the relationship between the internal quantum efficiency in wavelength 290nm, and the surface phosphorus density
  • a solar battery cell according to Example 1 of the present invention will be described with reference to FIGS.
  • FIG. 1A and FIG. 1B are a top view and a cross-sectional view, respectively, showing the solar battery cell according to the first embodiment.
  • the top view of FIG. 1A is hatched in the same manner as the cross-sectional view for easy understanding of the correspondence with the cross-sectional view of FIG. .
  • the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, the crystalline Si layer 15, and the passivation layer 16 were formed on the crystalline Si substrate 11. It is a solar battery cell, and has a front electrode 21 and a back electrode 22 as electrodes.
  • the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31 each have a concentration of a dopant such as phosphorus or boron in the crystalline Ge layer. 13, higher than the dopant concentration inside the crystalline Si 1-x Ge x layer 14 and the crystalline Si layer 15.
  • the heavily doped crystal Ge layer 33 is characterized in that the width in the planar direction is smaller than the width of the surface electrode 21.
  • the width of the heavily doped crystal Si layer 31 at the interface between the heavily doped crystal Si layer 31 and the surface electrode 21 is larger than the width of the opening of the passivation layer 16.
  • the width of the heavily doped crystal Si layer 31 at the interface between the heavily doped crystal Si layer 31 and the heavily doped crystal Si 1-x Ge x layer 32 is as follows. It is characterized in that it is smaller than the width of the heavily doped crystalline Si layer 31 at the interface. The effects brought about by these features are described below.
  • FIG. 1A and FIG. 1B the structure in the case where the surface electrode 21 is formed in a straight line when viewed from above is shown, as in a general solar battery cell.
  • the surface electrode 21 may have a different top surface shape.
  • the passivation layer 16 is patterned, and in the structure of the first embodiment, the surface electrode 21 and the heavily doped crystalline Si layer 31 are formed in the opening where the passivation layer 16 does not exist. And are connected.
  • the shape of the upper surface of the opening where the passivation layer 16 does not exist is arbitrary, and may be linear when viewed from the upper surface, or there may be a plurality of circular openings when viewed from the upper surface.
  • the top surface shape of the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31 is arbitrary, and may be linear when viewed from above. Alternatively, there may be a plurality of circular openings as viewed from the top.
  • crystalline Si substrate 11 and the back electrode 22 are connected, but a back surface field (BSF) layer is provided at the interface between the crystalline Si substrate 11 and the back electrode 22 as in a general solar battery cell.
  • BSF back surface field
  • a back contact passivation film may be further added to form a point contact structure.
  • the conductivity type of the semiconductor constituting the solar battery cell of Example 1 will be described. The following p-type and n-type may be reversed.
  • the crystalline Si substrate 11 is p-type, and the four layers of the crystalline Si layer 15, the highly doped crystalline Ge layer 33, the highly doped crystalline Si 1-x Ge x layer 32, and the highly doped crystalline Si layer 31 are n-type. It is.
  • the two layers of the crystalline Ge layer 13 and the crystalline Si 1-x Ge x layer 14 may be both n-type or i-type, or the two layers may be n-type on the surface side and i-type on the substrate side, and 2 There may be an n-type and i-type interface on either side of the layer.
  • the crystalline Si layer 31 can have a single crystal structure, a polycrystal structure, a microcrystal structure, or the like.
  • the material of the passivation layer 16 is an insulator such as SiO 2 , SiN (silicon nitride), amorphous Si, SiC (silicon carbide), CdS, or a laminated structure of these insulators.
  • the material of the front electrode 21 and the back electrode 22 is a metal such as Ag, Al, Ti, Pd, Ni, or Cu, or a laminated structure of these metals.
  • the passivation layer 16 it is particularly desirable to use SiO 2 as the passivation layer 16.
  • SiO 2 the interface between the crystalline Si and SiO 2, compared with the interface between the crystalline Si 1-x Ge x and SiO 2, because the interface recombination is suppressed.
  • the effect of the first embodiment will be described by taking the case of using the above materials as an example.
  • a highly efficient solar battery cell can be realized by using both the use of multi-exciton generation and the reduction of carrier recombination loss.
  • the locations where multi-exciton generation can occur are the crystalline Si substrate 11, the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15. .
  • it is effective to reduce the value of ⁇ ⁇ -2Eg in the band structure, and in the crystalline Si 1-x Ge x , ⁇ ⁇ -2Eg The value of decreases monotonically with respect to x.
  • the crystal Si 1-x Ge x layer 14 is used as a main generation layer for multi-exciton generation, thereby improving the use efficiency of multi-exciton generation compared to the crystal Si solar cell. can do.
  • the crystal Si 1-x Ge x layer 14, to the main generating layer Maruchiekishiton generated light having a higher energy 2Eg crystal Si 1-x Ge x, as many crystal Si 1-x Ge It is necessary to absorb the inside of the x layer 14, as will be described later. This is because the film thicknesses of the crystalline Si 1-x Ge x layer 14 and the crystalline Si layer 15 and the crystalline Si 1-x Ge x layer 14 This is possible by appropriately selecting the Ge composition x.
  • the first carrier recombination loss is a loss due to recombination at the interface between the crystalline Si layer 15 and the passivation layer 16.
  • the crystalline Si 1-x Ge x / SiO 2 interface state density is higher than the crystalline Si / SiO 2 interface state density, and as a result, the crystalline Si 1-x Ge x solar cell has There is a problem that it is difficult to form a high-quality surface passivation film.
  • the crystalline Si layer 15 exists between the passivation layer 16 and the crystalline Si 1-x Ge x layer 14. For this reason, surface passivation is performed at the crystalline Si / SiO 2 interface, and a high-quality surface passivation film can be formed.
  • Recombination loss second carrier the interior of the crystal Si 1-x Ge crystal Si during the formation of the x layer 14 1-x Ge x layer 14, and the crystal Si 1-x Ge x layer 14 and the crystal Si substrate 11 It is a recombination loss due to a crystal defect generated in a region between.
  • a method for forming the crystalline Si 1-x Ge x layer 14 applying the method of using the composition graded buffer layer, when the crystal Si 1-x Ge x layer 14 of the Ge composition x is high, the recombination The loss is great. Therefore, in the solar battery cell of Example 1, the Ge buffer layer 12 is used to form the crystalline Ge layer 13 on the crystalline Si substrate 11, and then the crystalline Si 1-x on the crystalline Ge layer 13.
  • a Ge x layer 14 is formed. According to this method, the crystalline Ge layer 13 having a low crystal defect density can be formed. Therefore, when the Ge composition x of the crystalline Si 1-x Ge x layer 14 is high, the crystal defect density of the crystalline Si 1-x Ge x layer 14 formed on the crystalline Ge layer 13 can also be reduced. Moreover, since the film thickness of the Ge buffer layer 12 is smaller than the film thickness of the composition gradient buffer layer as compared with the method using the composition gradient buffer layer described above, carrier recombination inside the Ge buffer layer 12 is This is suppressed more than the carrier recombination inside the composition gradient buffer layer.
  • the third carrier recombination is a recombination loss inside the selective emitter.
  • three layers of the highly doped crystal Ge layer 33, the highly doped crystal Si 1-x Ge x layer 32, and the highly doped crystal Si layer 31 form a selective emitter.
  • a selective emitter is formed for a stacked film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge, a part of the selective emitter becomes a surface electrode due to a difference in diffusion coefficient of phosphorus. It is formed in a region that is not shielded, and loss due to carrier recombination occurs.
  • the selective emitter is formed in a region shielded by the surface electrode 21 by performing multi-step dopant implantation using a plurality of masks having different opening widths when forming the selective emitter. Details of the manufacturing method will be described later, but the outline is as follows. First, as a first step, a selective emitter having a depth extending over three layers of a heavily doped crystal Ge layer 33, a heavily doped crystal Si 1-x Ge x layer 32, and a heavily doped crystal Si layer 31 is formed with a narrow opening width. It is formed using a mask. At this time, the opening width of the mask is set so that the width of the heavily doped crystal Ge layer 33 among the three layers is smaller than the width of the surface electrode 21.
  • a selective emitter is formed only in the surface region of the heavily doped crystal Si layer 31 using a mask having a wide opening width.
  • the opening width of the mask is set so that the width of the heavily doped crystal Si layer 31 is larger than the width of the opening of the passivation layer 16.
  • the heavily doped crystal Si layer 31 at the interface between the heavily doped crystal Si layer 31 and the heavily doped crystal Si 1-x Ge x layer 32 is obtained. Is smaller than the width of the heavily doped crystalline Si layer 31 at the interface between the heavily doped crystalline Si layer 31 and the surface electrode 21. Since the selective emitter formed by the above method is formed in a region shielded by the surface electrode 21, unlike the structure shown in FIG. 9, there is no increase in carrier recombination loss inside the selective emitter.
  • the recombination loss at the interface between the crystalline Si layer 15 and the passivation layer 16 the recombination loss due to crystal defects generated when the crystalline Si 1-x Ge x layer 14 is formed, and It is possible to reduce three of the recombination losses inside the selective emitter.
  • the first parameter is the Ge composition x of the crystalline Si 1-x Ge x layer 14. In determining the value of x, it is necessary to consider two points: improvement in utilization efficiency of multi-exciton generation and formation conditions of the crystalline Si 1-x Ge x layer 14.
  • the value of ⁇ ⁇ -2Eg is 0 or more and as small as possible.
  • the value of x is preferably in the range of 0 ⁇ x ⁇ 0.68, and in particular, the value of x is preferably as large as possible within the above range.
  • Example 1 conditions for forming the crystalline Si 1-x Ge x layer 14 will be described.
  • the lattice constant between the crystalline Ge layer 13 and the crystalline Si 1-x Ge x layer 14 is changed. It is desirable that the difference is small. For this reason, epitaxial growth can be easily performed when the value of x is large. From the above, it is desirable that the range is 0 ⁇ x ⁇ 0.68, and it is particularly desirable that the value of x is as large as possible within the above range.
  • the second parameter is the film thickness of the crystalline Si 1-x Ge x layer 14.
  • the thickness of the determination of the crystal Si 1-x Ge x layer 14 consideration of the two points of the light absorption in the crystal Si 1-x Ge x layer 14, the formation conditions of the crystal Si 1-x Ge x layer 14 There is a need to.
  • the crystalline Si 1-x Ge x layer 14 is a main generation layer for multi-exciton generation. For this reason, it is desirable that the high energy light used for generating multi-exciton is absorbed by the emitter layer 12 as much as possible. For example, light having energy higher than 2 eV, the thickness of the crystal Si 1-x Ge x layer 14 only required to absorb crystal Si 1-x Ge x layer 14, the light absorption coefficient, estimated to 2 ⁇ m It is.
  • the film thickness of the crystalline Si 1-x Ge x layer 14 is desirably 2 ⁇ m or less in terms of solar cell characteristics, and particularly within the above range, the film thickness of the crystalline Si 1-x Ge x layer 14 Is desirably as large as possible, but ultimately it is necessary to determine the film thickness of the crystalline Si 1-x Ge x layer 14 in consideration of the formation conditions.
  • the third parameter is the film thickness of the crystalline Si layer 15.
  • the thickness of the crystal Si layer 15 the light absorption in the crystal Si 1-x Ge x layer 14, is necessary to consider two points and diffusion of Ge from the crystal Si 1-x Ge x layer 14 is there.
  • the thickness of the crystalline Si layer 15 is smaller than the thickness of the crystalline Si 1-x Ge x layer 14 for the purpose of light absorption. This can be said to be an outstanding feature with respect to the structure disclosed in the above-described prior art document, which the structure of the first embodiment has.
  • the film thickness of the crystalline Si layer 15 is desirably 7 nm or more.
  • the film thickness of the crystalline Si layer 15 is desirably as small as possible within the above range.
  • FIG. 2A to FIG. 2L are a top view and a cross-sectional view showing a method for manufacturing a solar battery cell according to the first embodiment.
  • each process of the manufacturing method of the photovoltaic cell of this Example 1 is demonstrated based on Fig.2 (a)-FIG.2 (l).
  • a Ge buffer layer 12, a crystalline Ge layer 13, a crystalline Si 1-x Ge x layer 14, and a crystalline Si layer 15 are formed in this order on the surface of the crystalline Si substrate 11.
  • the formation method of the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 is preferably performed by an epitaxial growth method to reduce crystal defects.
  • the layer may be formed by other film forming methods such as a CVD method.
  • the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 is an emitter doped over the entire surface.
  • the doping may be performed during the film formation, or may be performed by a method such as ion implantation, gas phase diffusion, or solid phase diffusion after the film formation.
  • a mask 34 is formed on the surface of the crystalline Si layer 15.
  • the opening of the mask 34 is performed by lithography and etching or laser processing. Alternatively, a method in which the mask 34 is not initially formed in the opening portion of the mask 34 by a screen printing method or the like may be used.
  • FIG. 2A A top view of the structure after forming the mask 34 is shown in FIG. 2A, and a cross-sectional view is shown in FIG. 2B.
  • a heavily doped crystal Ge layer 33, a heavily doped crystal Si 1-x Ge x layer 32, and a heavily doped crystal Si layer 31 are formed.
  • a top view of the structure after formation is shown in FIG. 2C, and a cross-sectional view is shown in FIG.
  • Formation of the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31 can be performed by a diffusion method such as ion implantation or vapor phase diffusion. .
  • a diffusion method such as ion implantation or vapor phase diffusion.
  • activation after dopant implantation is performed by heat treatment or laser treatment.
  • FIG. 2C and FIG. 2D show the state after activation of the dopant.
  • the diffusion coefficient of the dopant varies depending on the Ge composition x of the crystalline Si 1-x Ge x , and in particular, the higher the Ge composition x, the larger the diffusion coefficient of phosphorus. Therefore, as shown in FIG. Further, among the three layers of the highly doped crystal Ge layer 33, the highly doped crystal Si 1-x Ge x layer 32, and the highly doped crystal Si layer 31, the width of the heavily doped crystal Ge layer 33 is the largest, The width of the heavily doped crystal Si layer 31 is the smallest.
  • FIG. 2 (e) A top view of the structure after formation is shown in FIG. 2 (e), and a cross-sectional view is shown in FIG. 2 (f).
  • the mask 35 can be removed by a process such as ashing if the mask 35 is a resist, or by a process such as etching if the mask 35 is an insulating film.
  • the mask 35 to be re-formed can use the same material and formation method as the mask 34 used for the first time.
  • the heavily doped crystalline Si layer 31 is formed on the surface portion of the crystalline Si layer 15 using the mask 35.
  • a top view of the structure after formation is shown in FIG. 2G, and a cross-sectional view is shown in FIG.
  • the heavily doped crystalline Si layer 31 and the heavily doped crystalline Si 1-x Ge x are formed.
  • the width of the heavily doped crystal Si layer 31 at the interface with the layer 32 is smaller than the width of the heavily doped crystal Si layer 31 at the interface between the heavily doped crystal Si layer 31 and the surface electrode 21.
  • the highly doped crystal Si layer 31 is formed when the above-described three layers of the highly doped crystal Ge layer 33, the highly doped crystal Si 1-x Ge x layer 32, and the highly doped crystal Si layer 31 are formed. Similarly to the above, it can be carried out by an ion implantation method or a diffusion method such as vapor phase diffusion. However, in forming the heavily doped crystalline Si layer 31 this time, for example, the heat treatment for activating the dopant is shortened so that the dopant does not diffuse into the crystalline Si 1-x Ge x layer 14 and the crystalline Ge layer 13. It is necessary to use means such as.
  • the passivation layer 16 is formed by a thermal oxidation method, a plasma oxidation method, a CVD method, or the like. As described above, in order to form a high-quality surface passivation film, it is desirable to form the passivation layer 16 by a thermal oxidation method. However, if the thermal oxidation method is used, the passivation layer 16 is also formed on the back surface side of the crystalline Si substrate 11. 16 is formed. On the other hand, for example, when the plasma CVD method is used, the passivation layer 16 is not formed on the back side of the crystalline Si substrate 11.
  • a back electrode 22 is formed on the back side of the crystalline Si substrate 11.
  • a top view of the structure after formation is shown in FIG. 2 (i), and a cross-sectional view is shown in FIG. 2 (j).
  • the back electrode 22 is formed by a film forming method such as a printing method, a vapor deposition method, a plating method, a sputtering method, or a CVD method.
  • a film forming method such as a printing method, a vapor deposition method, a plating method, a sputtering method, or a CVD method.
  • the passivation layer 16 when the passivation layer 16 is formed also on the back surface side of the crystalline Si substrate 11, the crystalline Si substrate 11 in the passivation layer 16 is formed before the back surface electrode 22 is formed. It is necessary to remove the area on the back side of the.
  • the opening of the passivation layer 16 may be formed by a patterning method using lithography and etching, or a patterning method using an etching paste.
  • the width of the opening of the passivation layer 16 needs to be smaller than the width at the outermost surface of the heavily doped crystal Si layer 31. If the width of the opening of the passivation layer 16 is larger than the width at the outermost surface of the heavily doped crystalline Si layer 31, and as a result, the opening of the passivation layer 16 also exists above the crystalline Si layer 15, The crystalline Si layer 15, which is a layer having a relatively low doping concentration, and the surface electrode 21 are in direct contact, and carrier recombination loss occurs at the contact interface.
  • the surface electrode 21 is formed.
  • a top view of the structure after formation is shown in FIG. 2 (k), and a cross-sectional view is shown in FIG. 2 (l).
  • the surface electrode 21 is formed by a film forming method such as a printing method, a vapor deposition method, a plating method, a sputtering method, or a CVD method.
  • an opening is formed in the passivation layer 16 and then the surface electrode 21 is formed.
  • the opening is not formed in the passivation layer 16, and baking is performed after the surface electrode 21 is formed.
  • the surface electrode 21 and the heavily doped crystal Si layer 31 may be electrically connected to each other by a method using a so-called fire-through.
  • the shape seen from the upper surface of the opening of the passivation layer 16 is the same as the shape seen from the upper surface of the surface electrode 21.
  • the method of forming the opening in the passivation layer 16 it is possible to reduce the contact area between the surface electrode 21 and the heavily doped crystal Si layer 31.
  • the above is the method for manufacturing the solar battery cell of Example 1.
  • heat treatment, plasma treatment, etc. may be added as appropriate to improve the crystallinity and film quality of each film or to improve the quality of the interface with the adjacent film.
  • Example 2 of the present invention will be described with reference to FIGS. In the second embodiment, differences from the first embodiment will be mainly described.
  • FIG. 3A and FIG. 3B are a top view and a cross-sectional view showing the solar battery cell according to the second embodiment.
  • 3A is a top view
  • FIG. 3B is a cross-sectional view.
  • a Ge buffer layer 12 a crystalline Ge layer 13, a crystalline Si 1-x Ge x layer 14, a crystalline Si layer 15, and a passivation layer 16 are formed on a crystalline Si substrate 11, Furthermore, it is a solar cell in which a highly doped crystalline Si layer 31 in contact with a plurality of layers among the above layers is formed, and has a front electrode 21 and a back electrode 22 as electrodes.
  • FIG. 3B shows a structure in which the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 are all patterned. Only the surface side of the Si layer 15 and the crystalline Si 1-x Ge x layer 14 is patterned, and other regions may not be patterned. Further, as shown in FIG.
  • FIG. 3B shows a case where the shape of the opening is a quadrangle, but an opening having another shape such as a round shape or a triangle may be formed.
  • the first point is that the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 are not patterned in the first embodiment, whereas the first embodiment 2 indicates that any of the four layers is patterned.
  • the second point is that, in the first embodiment, the selective emitter is composed of three layers of the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31. In contrast, in the second embodiment, the selective emitter is composed of only the heavily doped crystal Si layer 31.
  • the number of times of patterning associated with the formation of the selective emitter can be reduced as compared with the case of the first embodiment.
  • the selective emitter can be formed in a deeper region with respect to the surface of the solar battery cell.
  • the first effect the reduction in the number of times of patterning associated with the formation of the selective emitter, will be described.
  • patterning is performed twice using a mask 34 having different opening widths in order to form a selective emitter. Further, after forming the selective emitter, patterning for forming an opening of the passivation layer 16 is also necessary.
  • a Ge buffer layer 12, a crystalline Ge layer 13, a crystalline Si 1-x Ge x layer are used to form a selective emitter by using a manufacturing method described later.
  • the second embodiment the number of times of patterning necessary for manufacturing the solar battery cell can be reduced as compared with the case of the first embodiment, so that the manufacturing at a lower cost is possible.
  • the formation depth of the selective emitter is determined by the reach distance of the dopant by the ion implantation method or the diffusion method. Specifically, the higher the ion implantation energy, the higher the diffusion and activation temperatures, and the longer the time, the more selective emitters are formed in deeper regions. However, if these parameters are changed, the width of the formed selective emitter is also changed, so that it is difficult to control only the depth of the selected emitter.
  • an opening is formed by patterning in at least one layer in order from the layer closest to the surface.
  • the depth of the opening can be controlled over a relatively wide range by using dry etching or wet etching having a different etching rate depending on the crystal orientation. Since the heavily doped crystal Si layer 31 serving as the selective emitter is formed along the shape of the opening, the depth of the opening determines the formation depth of the selective emitter.
  • a selective emitter can be formed in a deeper region than in the first embodiment, and as a result, carrier recombination can be reduced.
  • ⁇ Solar cell manufacturing method> 4 (a) to 4 (j) are a top view and a cross-sectional view showing a method for manufacturing a solar battery cell according to the second embodiment.
  • each process of the manufacturing method of the photovoltaic cell of this Example 2 is demonstrated based on Fig.4 (a)-FIG.4 (j).
  • FIG. 4A shows a top view of the structure after formation
  • FIG. 4B shows a cross-sectional view thereof.
  • FIG. 4C A top view of the structure after formation is shown in FIG. 4C, and a cross-sectional view is shown in FIG. 4D.
  • FIG. 4D shows a structure in which the opening reaches the surface side of the crystalline Si substrate 11. The opening can be formed by dry etching, wet etching, laser processing, or the like.
  • the crystalline Si substrate 11 has a (100) plane
  • the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 are utilized by utilizing the difference in etching rate depending on the plane orientation.
  • crystalline Si a method of performing anisotropic etching with an alkaline solution is known.
  • crystal Ge a method of performing anisotropic etching with hydrogen peroxide solution or a mixed solution of hydrogen peroxide solution and hydrofluoric acid is known.
  • FIG. 4E shows a top view of the structure after formation
  • FIG. 4F shows a cross-sectional view.
  • the highly doped crystal Si layer 31 is formed by a CVD method, an epitaxial growth method, or the like.
  • FIG. 4 (f) shows a structure in which the heavily doped crystal Si layer 31 is formed only on the front surface side, but depending on the method of forming the heavily doped crystal Si layer 31, a high concentration is also formed on the back surface side. Doped crystal Si layer 31 may be formed. In that case, it is necessary to remove the heavily doped crystalline Si layer 31 on the back side.
  • the passivation layer 16 on the back surface side is removed, and further, the front surface electrode 21 and the back surface electrode 22 are formed.
  • a top view of the structure after formation is shown in FIG. 4G, and a cross-sectional view is shown in FIG. 4H. Removal of the passivation layer 16 and formation of the front electrode 21 and the back electrode 22 are performed in the same manner as in the first embodiment.
  • a mask 34 is formed.
  • the width of the mask 34 is desirably larger than the width of the openings formed in the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15.
  • the surface electrode 21 and the heavily doped crystalline Si layer 31 thereunder are removed by etching using the mask 34.
  • a top view of the structure after removal is shown in FIG. 4 (i), and a cross-sectional view is shown in FIG. 4 (j).
  • dry etching In order to simultaneously remove the surface electrode 21 and the heavily doped crystalline Si layer 31 below the surface electrode 21, it is desirable to use dry etching. At that time, it is necessary to select conditions such as etching gas so that the passivation layer 16 below the heavily doped crystal Si layer 31 to be removed is not completely etched.
  • the solar cells shown in FIGS. 3 (a) and 3 (b) are formed. As described above, the solar battery cell of Example 2 can be manufactured.
  • Example 3 of the present invention will be described with reference to FIGS. In the third embodiment, differences from the second embodiment will be mainly described.
  • FIG. 5A and FIG. 5B are a top view and a cross-sectional view showing the solar battery cell according to the third embodiment.
  • FIG. 5A is a top view
  • FIG. 5B is a cross-sectional view.
  • a Ge buffer layer 12 a crystalline Ge layer 13, a crystalline Si 1-x Ge x layer 14, a crystalline Si layer 15, and a passivation layer 16 are formed on a crystalline Si substrate 11, An opening is formed with respect to the above-described layer, and the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31 are formed on the sidewall of the opening.
  • the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31 are: They are formed at positions in contact with the Ge buffer layer 12 or the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, the crystalline Si layer 15 or the crystalline Si substrate 11, respectively.
  • the selective emitter is composed of only the heavily doped crystal Si layer 31.
  • the selective emitter is the heavily doped crystal Ge layer 33, the heavily doped crystal.
  • the crystal Si 1-x Ge x layer 32 and the highly doped crystal Si layer 31 are composed of three layers.
  • the depth of the opening formed for the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, the crystalline Si layer 15, and the passivation layer 16 as in the second embodiment. Therefore, for example, when the opening is formed only in two layers of the crystalline Si layer 15 and the passivation layer 16, the selective emitter is formed in the side portion of the crystalline Si layer 15. Only the heavily doped crystal Si layer 31 is provided.
  • Example 3 since wet etching can be used when processing the surface electrode 21 as described later, the case of Example 2 in which dry etching is used when processing the surface electrode 21 is used. In comparison, the damage introduced into the passivation layer 16 is reduced. Thereby, the recombination loss at the interface between the passivation layer 16 and the crystalline Si layer 15 can be reduced.
  • a method for manufacturing the solar battery cell of Example 3 will be described.
  • ⁇ Solar cell manufacturing method> 6 (a) to 6 (f) are a top view and a cross-sectional view showing a method for manufacturing a solar battery cell according to the third embodiment.
  • each process of the manufacturing method of the photovoltaic cell of this Example 3 is demonstrated based on Fig.6 (a)-FIG.6 (f).
  • the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, the crystalline Si layer 15, and the passivation layer 16 are formed on the surface of the crystalline Si substrate 11. These are formed in order, and openings are formed by patterning the above layers.
  • a top view of the structure after formation is shown in FIG. 6A, and a cross-sectional view is shown in FIG. 6B.
  • FIG. 6C A top view of the structure after formation is shown in FIG. 6C, and a cross-sectional view is shown in FIG. 6D.
  • the passivation layer 16 on the surface side can be used as a mask.
  • an ion beam is incident on the wafer in an oblique direction at the time of ion implantation.
  • FIG. 6E A top view of the structure after formation is shown in FIG. 6E, and a cross-sectional view is shown in FIG. 6F.
  • FIG. 6E and FIG. 6F show the structure after the surface electrode 21 is patterned.
  • a method using dry etching is desirable. Only the surface electrode 21 needs to be removed, and therefore wet etching can be used. As described above, when the surface electrode 21 is processed by wet etching, damage introduced into the passivation layer 16 is reduced as compared with dry etching.
  • the solar battery cell of Example 3 can be manufactured.
  • Example 4 of the present invention will be described with reference to FIGS. In the fourth embodiment, differences from the first embodiment will be mainly described.
  • FIG. 7A and FIG. 7B are a top view and a cross-sectional view showing the solar battery cell according to the fourth embodiment.
  • FIG. 7A is a top view
  • FIG. 7B is a cross-sectional view.
  • a buried oxide film 36, a crystalline Ge layer 13, and a crystalline Si 1-x Ge x layer 14 are formed on a crystalline Si substrate 11, and an opening is formed with respect to the above layer.
  • the solar cell is formed and further has a crystalline Si layer 15 and a passivation layer 16 formed on the opening, and has a front electrode 21 and a back electrode 22 as electrodes.
  • FIG. 7B shows a structure in which a buried oxide film 36 and a crystalline Si layer 15 are formed between the crystalline Si substrate 11 and the crystalline Ge layer 13. That is, a structure is shown in which the width of the opening of the buried oxide film 36 is larger than the width of the opening of the crystalline Ge layer 13 when the opening is formed. In order to reduce the series resistance of the solar battery cell, it is desirable that the width of the opening of the buried oxide film 36 is larger than the width of the opening of the crystalline Ge layer 13 as shown in FIG. The width of the opening of the oxide film 36 may be equal to or smaller than the width of the opening of the crystalline Ge layer 13.
  • the solar cell of the fourth embodiment since the Ge buffer layer 12 in the structure of the first embodiment is not necessary to form the crystalline Ge layer 13, the carriers generated inside the solar cell are Ge. It becomes possible to avoid recombination loss associated with passing through the buffer layer 12.
  • the solar cell of the fourth embodiment also uses the same method as in the first, second, and third embodiments in the inside of the selected emitter. It is possible to reduce the recombination loss at.
  • the manufacturing method of the photovoltaic cell of Example 4 will be described.
  • ⁇ Solar cell manufacturing method> 8A to 8N are a top view and a cross-sectional view showing a method for manufacturing a solar battery cell according to the fourth embodiment.
  • each process of the manufacturing method of the photovoltaic cell of this Example 3 is demonstrated based on FIG. 8A-FIG. 8N.
  • a Germanium On Insulator substrate (hereinafter referred to as a GeOI substrate) in which a buried oxide film 36 and a crystalline Ge layer 13 are formed in this order on a crystalline Si substrate 11 may be used. good.
  • the GeOI substrate is manufactured by a method such as the Smart Cut method using epitaxial growth of a crystalline Ge film, bonding of the substrates, and peeling.
  • FIG. 8A shows a top view after formation
  • FIG. 8B shows a cross-sectional view. Formation of the crystalline Si 1-x Ge x layer 14 can be performed by the same method as in the first embodiment.
  • openings are formed in the crystalline Ge layer 13 and the crystalline Si 1-x Ge x layer 14.
  • the opening can be formed by dry etching, wet etching, laser processing, or the like.
  • an opening is formed in the buried oxide film 36.
  • FIG. 8C shows a top view after formation
  • FIG. 8D shows a cross-sectional view.
  • the opening is preferably formed by wet etching. The reason for this is that if wet etching is used, unlike the methods such as dry etching and laser processing, side etching is performed on the buried oxide film 36 to reduce the width of the opening of the buried oxide film 36 to the crystalline Ge layer 13. This is because the width of the opening of the crystalline Si 1-x Ge x layer 14 can be made larger. Increasing the width of the opening of the buried oxide film 36 increases the contact area between the crystalline Si layer 15 and the crystalline Si substrate 11 to be formed thereafter, so that the series resistance of the solar cell can be reduced. it can.
  • FIG. 8E shows a top view after formation
  • FIG. 8F shows a cross-sectional view.
  • the crystalline Si layer 15 can be formed by an epitaxial growth method, a CVD method, or the like, as in the first embodiment.
  • FIG. 8G shows a top view after formation
  • FIG. 8H shows a cross-sectional view.
  • FIG. 8 (i) A top view of the structure after formation is shown in FIG. 8 (i), and a cross-sectional view is shown in FIG. 8 (j).
  • 8 (i) and 8 (j) show the structure after the surface electrode 21 is patterned.
  • the patterning of the surface electrode 21 can be performed by a method such as dry etching or wet etching.
  • the width of the region of the passivation layer 16 that is not removed is the opening of the crystalline Si 1-x Ge x layer 14. It is desirable to be larger than the width of.
  • the surface electrode 21 has a crystalline Si 1-x Ge x layer. This is because it is necessary to be formed so as to straddle the ends of the 14 openings, which increases the risk of disconnection.
  • the solar battery cell of Example 4 can be manufactured.
  • Example 5 of the present invention will be described with reference to FIG.
  • the fifth embodiment is an example of a solar battery system using the solar battery cells described in the first, second, third, and fourth embodiments.
  • FIG. 11 is a configuration diagram illustrating a solar battery system using the solar battery cells according to the fifth embodiment.
  • the fifth embodiment is a solar battery system using the solar battery cells of the first, second, third, and fourth embodiments.
  • the solar cell system includes a solar cell panel 41, a connection box 42, a current collection box 43, a power conditioner 44, and a transformer 45.
  • the solar battery panel 41 is a solar battery panel in which a plurality of the solar battery cells described in Examples 1, 2, 3, and 4 are arranged.
  • the solar cell panel 41 is a panel that generates electric power by sunlight.
  • the connection box 42 is a connection box that transmits the electric power generated by the solar cell panel 41 to the current collection box 43.
  • the current collection box 43 is a current collection box that collects the electric power transmitted from the connection box 42 and transmits it to the power conditioner 44.
  • the power conditioner 44 is a converter that converts the electric power transmitted from the current collection box 43 from direct current to alternating current and transmits the electric power to the transformer 45.
  • the transformer 45 is a transformer that transforms the voltage of the AC power transmitted from the power conditioner 44 and transmits it to the commercial power system 46.
  • three power conditioners 44 and a current collection box 43 are connected to one transformer 45 connected to the commercial power system 46. Further, a three-system connection box 42 and a solar cell panel 41 are connected to each one-system power conditioner 44 and current collection box 43.
  • the electric power generated by the solar cell panel 41 is transmitted to the connection box 42 and collected by the current collection box 43. Thereafter, the power conditioner 44 converts the voltage from direct current to alternating current, collectively transforms the voltage with the transformer 45, and connects to the commercial power system 46.
  • the said structure is a structural example of the mega solar system with many panel numbers especially in a solar cell system. In the case of a residential system with a relatively small number of panels, it is directly connected to the power conditioner 44 from the connection box 42.
  • the solar cell system of Example 5 can be realized.
  • the solar cell system of Example 5 it is possible to increase the efficiency of solar power generation by taking advantage of the effect of the solar cell structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Energy (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)

Abstract

This solar cell is configured such that the solar cell has: a first-polarity crystalline Si substrate 11; a Ge buffer layer 12 formed on a surface of the first-polarity crystalline Si substrate 11; a crystalline Ge layer 13 formed on a surface of the Ge buffer layer 12; a second-polarity crystalline Si1-xGex layer 14 formed on a surface of the crystalline Ge layer 13; a second-polarity crystalline Si layer 15 formed on a surface of the second-polarity crystalline Si1-xGex layer 14; a passivation layer 16 formed on a surface 15 of the second-polarity crystalline Si layer, said passivation layer being formed of an insulating material; a second-polarity high concentration doped crystalline Si layer 31 formed within a same plane where the second-polarity crystalline Si layer 15 is formed; and a surface electrode 21 formed on a surface of the second-polarity high concentration doped crystalline Si layer 31. The solar cell is also configured such that the width of the second-polarity high concentration doped crystalline Si layer 31 at the interface between the second-polarity high concentration doped crystalline Si layer 31 and the surface electrode 21 is larger than the width of the second-polarity high concentration doped crystalline Si layer 31 at the interface between the second-polarity high concentration doped crystalline Si layer 31 and the second-polarity crystalline Si1-xGex layer 14. Consequently, the highly efficient solar cell, wherein both use of multiexciton generation and carrier recombination loss reduction are achieved, is provided.

Description

太陽電池セルSolar cells
 本発明は、太陽電池セルに関する。 The present invention relates to a solar battery cell.
 太陽電池セルを高効率化する技術として、近年、マルチエキシトン生成が注目されている。以下、マルチエキシトン生成について簡単に述べる。太陽光は幅広い波長域の光から構成されており、そのうち、太陽電池セルが吸収できる光は、発電層の半導体材料のバンドギャップ以上のエネルギーを有する光である。吸収された光のエネルギーによって、電子正孔対が生成され、電子と正孔とがそれぞれ別の電極に収集されることで、電極間に電位差が生じ、電力が発生する、というのが、太陽電池セルの動作原理である。ここで、バンドギャップ(以下、Egと記す)を上回る余剰エネルギーは、一般的な太陽電池セルでは、熱として散逸される。これに対して、マルチエキシトン生成とは、余剰エネルギーがEgの2倍(以下、2Egと記す)以上である場合に、余剰エネルギーによって、さらに電子正孔対が生成されるという現象である。この現象を利用することで、従来は熱として散逸されていた余剰エネルギーを電力に変換することが可能となり、太陽電池セルの高効率化が可能と期待されている。 In recent years, the production of multi-exciton has attracted attention as a technology for improving the efficiency of solar cells. Hereinafter, multi-exciton generation will be briefly described. Sunlight is composed of light in a wide wavelength range, and light that can be absorbed by the solar battery cell is light having energy equal to or higher than the band gap of the semiconductor material of the power generation layer. Electron-hole pairs are generated by the energy of the absorbed light, and electrons and holes are collected in separate electrodes, creating a potential difference between the electrodes and generating power. This is the operation principle of the battery cell. Here, surplus energy exceeding the band gap (hereinafter referred to as Eg) is dissipated as heat in a general solar battery cell. On the other hand, multi-exciton generation is a phenomenon in which electron-hole pairs are further generated by surplus energy when the surplus energy is twice or more Eg (hereinafter referred to as 2Eg). By utilizing this phenomenon, surplus energy that has been dissipated as heat in the past can be converted into electric power, which is expected to increase the efficiency of solar cells.
 例えば、特許文献1には、結晶シリコン(以下、結晶Siと記す)太陽電池セルにおいて、マルチエキシトン生成を利用する方法が開示されている。それによれば、結晶Siのpn接合と、その太陽光受光面(以下、表面と記す)側のパッシベーション膜として熱酸化法により形成されたSiO膜とを有する太陽電池セルにおいて、内部量子効率が1を超える現象が観測された。内部量子効率とは、太陽電池セル内部で吸収された光子1個から発生し、電極に収集された電子と正孔の数を表す。従って、内部量子効率が1を超えるということは、太陽電池セル内部でマルチエキシトン生成が発生していることを示している。 For example, Patent Document 1 discloses a method of using multi-exciton generation in a crystalline silicon (hereinafter referred to as crystalline Si) solar battery cell. According to this, in a solar cell having a pn junction of crystalline Si and a SiO 2 film formed by a thermal oxidation method as a passivation film on the solar light receiving surface (hereinafter referred to as surface) side, the internal quantum efficiency is More than 1 phenomenon was observed. The internal quantum efficiency represents the number of electrons and holes generated from one photon absorbed inside the solar battery cell and collected by the electrode. Therefore, an internal quantum efficiency exceeding 1 indicates that multi-exciton generation occurs inside the solar battery cell.
 前記特許文献1によれば、結晶Si太陽電池セルにおいて、マルチエキシトン生成の発生に必要な光のエネルギーは、Siのバンド構造によって決定される。具体的には、光のエネルギーが、Γ点での伝導帯と価電子帯とのエネルギー差を超える場合に、マルチエキシトン生成が発生する。以下、伝導帯と価電子帯とのエネルギー差をエネルギーギャップと記し、Γ点でのエネルギーギャップをΔΓと記す。結晶Siの場合、ΔΓ=3.4eV、2Eg=2.2eVである。上述したマルチエキシトン生成の原理によれば、光のエネルギーが2Eg以上の場合に、マルチエキシトン生成が発生することが期待される。しかしながら、実際には、結晶SiではΓ点において強い光吸収が発生すること、及び、マルチエキシトン生成の過程において、エネルギーと運動量の両者が保存される必要があることの結果として、光のエネルギーが2Eg以上かつΔΓ以下の場合には、内部量子効率が1を超える現象は観測されない。 According to Patent Document 1, the energy of light necessary for generating multi-exciton generation in a crystalline Si solar battery cell is determined by the Si band structure. Specifically, multi-exciton generation occurs when the energy of light exceeds the energy difference between the conduction band and the valence band at the Γ point. Below, it noted the energy gap of the energy difference between the conduction band and the valence band, the energy gap at the Γ point referred to as the Δ Γ. In the case of crystalline Si, Δ Γ = 3.4 eV, 2Eg = 2.2 eV. According to the principle of multi-exciton generation described above, it is expected that multi-exciton generation occurs when the energy of light is 2 Eg or more. However, in practice, in crystalline Si, strong light absorption occurs at the Γ point, and in the process of multi-exciton production, both energy and momentum need to be preserved, resulting in light energy in the case of inclusive cutlet delta gamma 2EG, a phenomenon that the internal quantum efficiency is greater than 1 is not observed.
 また、マルチエキシトン生成は、高エネルギーの光により発生する現象であり、一般に、高エネルギーの光は太陽電池セルの表面付近で吸収されることから、前記特許文献1によれば、マルチエキシトン生成を利用するためには、高品質の表面パッシベーション膜が必要であると記載されている。低品質の表面パッシベーション膜を用いた場合、すなわち、表面パッシベーション膜と発電層との界面に再結合準位が多数存在する場合には、マルチエキシトン生成によって発生した電子と正孔は、電極に収集される前に、再結合によって消滅する確率が高い。前記特許文献1の構造では、高品質なパッシベーション膜として、熱酸化法により形成されたSiO膜を用いている。 In addition, multi-exciton generation is a phenomenon that occurs due to high-energy light. Generally, high-energy light is absorbed near the surface of a solar battery cell. It is described that a high-quality surface passivation film is necessary for use. When a low-quality surface passivation film is used, that is, when there are many recombination levels at the interface between the surface passivation film and the power generation layer, electrons and holes generated by multi-exciton generation are collected at the electrode. There is a high probability of disappearing by recombination before being done. In the structure of Patent Document 1, a SiO 2 film formed by a thermal oxidation method is used as a high-quality passivation film.
 一方、例えば、非特許文献1には、SiとGeの混晶(以下、結晶Si1-xGeと記す。ここでxはGeの組成比であり、0≦x≦1の値をとる。)における、ΔΓとEgの計算結果が記載されている。それによれば、ΔΓとEgは、いずれもxに対して単調に減少し、さらに、ΔΓ-2Egの値も、xに対して単調減少する。特に、x=0.68においてΔΓ-2Eg=0となり、x<0.68ではΔΓ-2Eg>0、x>0.68ではΔΓ-2Eg<0である。 On the other hand, for example, Non-Patent Document 1 describes a mixed crystal of Si and Ge (hereinafter referred to as crystalline Si 1-x Ge x . Here, x is a composition ratio of Ge and takes a value of 0 ≦ x ≦ 1. The calculation results of ΔΓ and Eg are described in FIG. According to this, both Δ Γ and Eg monotonously decrease with respect to x, and furthermore, the value of Δ Γ -2Eg monotonously decreases with respect to x. In particular, x = Δ Γ -2Eg = 0 becomes in 0.68, x <0.68 in Δ Γ -2Eg> is 0, x> in 0.68 Δ Γ -2Eg <0.
 非特許文献2には、結晶Si基板上に結晶Si1-xGe膜を形成する方法として、組成傾斜バッファ層を用いる方法が記載されている。組成傾斜バッファ層とは、結晶Si基板と結晶Si1-xGe膜との間に形成されるSi1-xGe膜であり、そのGe組成xは、膜厚方向に傾斜状に形成されている。すなわち、組成傾斜バッファ層のうち、結晶Si基板との界面から、結晶Si1-xGe膜との界面に向かうにつれて、Ge組成xが増加するように形成される。一般的に、結晶Si基板上に、直接、結晶Si1-xGe膜を形成すると、結晶Siと結晶Si1-xGeの格子定数の差に起因した結晶欠陥が、結晶Si基板と結晶Si1-xGe膜の界面、および、結晶Si1-xGe膜内部に発生することが知られている。非特許文献2によれば、組成傾斜バッファ層を用いることにより、結晶Si基板上に、直接、結晶Si1-xGe膜を形成する場合と比べて、結晶Si1-xGe膜の結晶欠陥密度を低減することが可能である。 Non-Patent Document 2 describes a method using a composition gradient buffer layer as a method of forming a crystalline Si 1-x Ge x film on a crystalline Si substrate. The composition graded buffer layer, a Si 1-x Ge x film formed between the crystalline Si substrate and the crystal Si 1-x Ge x film, the Ge composition x is formed in an inclined shape in the thickness direction Has been. That is, the composition gradient buffer layer is formed such that the Ge composition x increases from the interface with the crystalline Si substrate toward the interface with the crystalline Si 1-x Ge x film. Generally, when a crystalline Si 1-x Ge x film is formed directly on a crystalline Si substrate, crystal defects due to the difference in lattice constant between crystalline Si and crystalline Si 1-x Ge x are interface of the crystal Si 1-x Ge x film, and it has been known to occur within the crystal Si 1-x Ge x film. According to Non-Patent Document 2, by using the composition graded buffer layer, on a crystalline Si substrate, directly, as compared with the case of forming a crystalline Si 1-x Ge x film, the crystalline Si 1-x Ge x film It is possible to reduce the crystal defect density.
 特許文献2には、結晶Si基板上に結晶Ge膜を形成する方法として、Geバッファ層を用いる方法が記載されている。それによれば、結晶Si基板上に、まずGeバッファ層を形成し、熱処理を加えることで、Geバッファ層を格子緩和させる。その後に、Geバッファ層上に、結晶Ge層を形成する。特許文献2によれば、Geバッファ層を用いることにより、結晶Si基板上に、結晶欠陥密度の低い結晶Ge層を形成することが可能となる。 Patent Document 2 describes a method using a Ge buffer layer as a method of forming a crystalline Ge film on a crystalline Si substrate. According to this, a Ge buffer layer is first formed on a crystalline Si substrate, and the Ge buffer layer is lattice-relaxed by applying heat treatment. Thereafter, a crystalline Ge layer is formed on the Ge buffer layer. According to Patent Document 2, it is possible to form a crystalline Ge layer having a low crystal defect density on a crystalline Si substrate by using a Ge buffer layer.
 特許文献3には、結晶Si1-xGe中のリンの拡散係数が記載されている。それによれば、結晶Si1-xGeのGe組成xが高いほど、リンの拡散係数が大きくなる傾向があり、特に、結晶Ge中のリンの拡散係数は、結晶Si中のリンの拡散係数の10倍以上である。 Patent Document 3 describes the diffusion coefficient of phosphorus in crystalline Si 1-x Ge x . According to this, the higher the Ge composition x of the crystalline Si 1-x Ge x , the larger the diffusion coefficient of phosphorus, and in particular, the diffusion coefficient of phosphorus in crystalline Ge is the diffusion coefficient of phosphorus in crystalline Si. 10 5 times or more.
米国特許第5,693,151号明細書US Pat. No. 5,693,151 特開2006-344937号公報JP 2006-344937 A 特開2009-182109号公報JP 2009-182109 A
 上述した通り、前記特許文献1に開示された結晶Si太陽電池セルにおいて、光のエネルギーが2Eg以上かつΔΓ以下の場合には、内部量子効率が1を超える現象は観測されない。結晶Siにおいては、ΔΓ=3.4eV、2Eg=2.2eVであり、2Eg以上かつΔΓ以下のエネルギー帯は、太陽光強度の比較的高い領域である。このため、前記特許文献1の構造は、マルチエキシトン生成を利用することはできるものの、2Eg以上かつΔΓ以下のエネルギー帯の光を有効利用することができないために、太陽電池セルとして高い変換効率を実現することは困難である。すなわち、マルチエキシトン生成を利用し、かつ、それによって高い変換効率を実現する手法は、従来はなかった。 As described above, in the crystal Si solar cell disclosed in Patent Document 1, when the energy of light is less than cutlet delta gamma 2EG, a phenomenon that the internal quantum efficiency is greater than 1 is not observed. In crystalline Si, Δ Γ = 3.4 eV, 2Eg = 2.2 eV, and an energy band of 2 Eg or more and Δ Γ or less is a region having a relatively high sunlight intensity. For this reason, although the structure of the said patent document 1 can utilize multi-exciton production | generation, since it cannot utilize effectively the light of the energy band below 2Eg and (DELTA) Γ, it is high conversion efficiency as a photovoltaic cell. It is difficult to realize. In other words, there has been no conventional method that uses multi-exciton generation and thereby achieves high conversion efficiency.
 また、結晶Si、結晶Si1-xGe、および結晶Geの積層膜を発電層とする太陽電池セルにおいて、以下の2つの課題がある。第1の課題は、結晶Si1-xGe膜の形成方法に関する。前記非特許文献1に記載された、組成傾斜バッファ層を用いた結晶Si1-xGe膜の形成方法には、結晶Si1-xGe膜のGe組成xが高くなるほど、組成傾斜バッファ層を厚く形成する必要がある。組成傾斜バッファ層は欠陥密度の高い膜であるため、太陽電池セル動作時に、組成傾斜バッファ層を通過するキャリアが再結合する確率が高い。また、組成傾斜バッファ層を厚く形成しても、その上に形成される結晶Si1-xGe膜の結晶欠陥密度は、Ge組成xとともに高くなる。このため、太陽電池セル動作時の結晶Si1-xGe膜内部でのキャリア再結合も、Ge組成xが高いほど、発生しやすくなる。従って、組成傾斜バッファ層を用いて、Ge組成xの高い結晶Si1-xGe膜を発電層とする太陽電池セルを作製すると、キャリア再結合確率が高いという課題がある。 In addition, there are the following two problems in a solar cell using a stacked film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge as a power generation layer. The first problem relates to a method for forming a crystalline Si 1-x Ge x film. In the method of forming a crystalline Si 1-x Ge x film using a composition gradient buffer layer described in Non-Patent Document 1, the composition gradient buffer is increased as the Ge composition x of the crystalline Si 1-x Ge x film is increased. It is necessary to form a thick layer. Since the composition gradient buffer layer is a film having a high defect density, there is a high probability that carriers passing through the composition gradient buffer layer will recombine during solar cell operation. Further, even when the composition gradient buffer layer is formed thick, the crystal defect density of the crystalline Si 1-x Ge x film formed thereon increases with the Ge composition x. For this reason, carrier recombination inside the crystalline Si 1-x Ge x film during solar cell operation is more likely to occur as the Ge composition x is higher. Therefore, when a solar cell using a crystalline Si 1-x Ge x film having a high Ge composition x as a power generation layer using a composition gradient buffer layer, there is a problem that the carrier recombination probability is high.
 第2の課題は、結晶Si、結晶Si1-xGe、および結晶Geの積層膜に対する、選択エミッタの形成方法に関する。まず選択エミッタの定義について述べる。選択エミッタとは、太陽電池セルの光受光面(以下、表面と記す)側に形成されるエミッタのうち、表面電極下部にのみ局所的に形成されるものを指す。ここで、図10で後述するように、マルチエキシトン生成を利用するには、選択エミッタを形成することが必要である。しかしながら、結晶Si、結晶Si1-xGe、および結晶Geの積層膜に選択エミッタを形成する際には、以下の課題がある。 The second problem relates to a method of forming a selective emitter for a stacked film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge. First, the definition of the selective emitter will be described. The selective emitter refers to an emitter formed locally only on the lower part of the surface electrode among the emitters formed on the light receiving surface (hereinafter referred to as surface) side of the solar battery cell. Here, as will be described later with reference to FIG. 10, it is necessary to form a selective emitter in order to use multi-exciton generation. However, when forming a selective emitter in a stacked film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge, there are the following problems.
 一般的に、エミッタのドーピング濃度が高いほど、エミッタ内部でのキャリア再結合確率は増大するが、一方で、エミッタのドーピング濃度が高いほど、エミッタ内部、および、エミッタと電極とのコンタクト抵抗は低下する。また、エミッタのドーピング濃度が高いほど、電子にとっての、選択エミッタ領域のポテンシャルエネルギーが下がるため、キャリア収集効率が向上する。以上を考慮し、太陽電池セルにおいては、表面全面には、ドーピング濃度の比較的低いエミッタを形成し、表面電極に遮蔽され光の入射しない領域である表面電極下部にのみ、ドーピング濃度の比較的高い選択エミッタをコンタクト孔を覆うように形成して、エミッタと電極とのコンタクト抵抗を低減するという手法が用いられることが多い。 In general, the higher the doping concentration of the emitter, the higher the carrier recombination probability inside the emitter, while the higher the doping concentration of the emitter, the lower the contact resistance between the emitter and the emitter and the electrode. To do. In addition, the higher the doping concentration of the emitter, the lower the potential energy of the selected emitter region for the electrons, thereby improving the carrier collection efficiency. In consideration of the above, in the solar cell, an emitter having a relatively low doping concentration is formed on the entire surface, and the doping concentration is relatively low only in the lower part of the surface electrode that is shielded by the surface electrode and does not receive light. A technique of reducing the contact resistance between the emitter and the electrode is often used by forming a high selective emitter so as to cover the contact hole.
 次に、選択エミッタとマルチエキシトン生成との関係について述べる。図10は、本発明に先立って、本発明者らによって行われた実験の結果であり、縦軸を結晶Si太陽電池セルの波長290nmでの内部量子効率、横軸を選択エミッタの表面リン濃度とするグラフである。内部量子効率とは、太陽電池セル内部で吸収された光子1個あたりの、電極に収集された電子正孔対の数である。つまり、マルチエキシトン生成が起こり、かつ、その結果として発生した電子正孔対が電極に収集された場合に、内部量子効率が1を超える。本実験において、選択エミッタ以外の、表面全面に形成されるエミッタの表面リン濃度は3.5×1018cm-3である。このため、図10において、選択エミッタの表面リン濃度が最も低いデータは、選択エミッタの無い、表面全面に同一濃度のエミッタが形成された太陽電池セルの特性を表わしている。図10によれば、表面全面に同一濃度のエミッタを有する太陽電池セルでは、内部量子効率が1を超えず、よりリン濃度の高い選択エミッタを形成することにより、内部量子効率が1を超える。この原因は、上述の通り、選択エミッタの形成により、キャリア収集効率が向上することにあると考えられる。図10のデータは、太陽電池セルにおいて、マルチエキシトン生成を利用するには、選択エミッタを形成することが必要であることを意味している。図10において、内部量子効率が1を超えるのは、選択エミッタの表面リン濃度が、8×1018cm-3以上、かつ、7×1019cm-3以下の場合である。 Next, the relationship between the selective emitter and multi-exciton generation will be described. FIG. 10 shows the results of experiments conducted by the present inventors prior to the present invention. The vertical axis represents the internal quantum efficiency at a wavelength of 290 nm of the crystalline Si solar cell, and the horizontal axis represents the surface phosphorous concentration of the selected emitter. It is a graph. The internal quantum efficiency is the number of electron-hole pairs collected by the electrode per photon absorbed inside the solar battery cell. That is, the internal quantum efficiency exceeds 1 when multi-exciton generation occurs and the resulting electron-hole pairs are collected at the electrode. In this experiment, the surface phosphorus concentration of the emitter formed on the entire surface other than the selected emitter is 3.5 × 10 18 cm −3 . For this reason, in FIG. 10, the data with the lowest surface phosphorous concentration of the selected emitter represents the characteristics of the solar cell in which the emitter of the same concentration is formed on the entire surface without the selected emitter. According to FIG. 10, in the solar cell having the same concentration of emitter on the entire surface, the internal quantum efficiency does not exceed 1, and the internal quantum efficiency exceeds 1 by forming a selective emitter having a higher phosphorus concentration. As described above, the cause is considered to be that the carrier collection efficiency is improved by forming the selective emitter. The data in FIG. 10 means that it is necessary to form a selective emitter in order to utilize multi-exciton production in a solar cell. In FIG. 10, the internal quantum efficiency exceeds 1 when the surface phosphor concentration of the selective emitter is 8 × 10 18 cm −3 or more and 7 × 10 19 cm −3 or less.
 しかし、結晶Si、結晶Si1-xGe、および結晶Geの積層膜に対して選択エミッタを形成する場合、結晶Si1-xGeのGe組成xによって、ドーパントの拡散係数が異なり、その結果、形成される選択エミッタの、膜面内方向の幅が、結晶Si、結晶Si1-xGe、および結晶Geの各層の間で異なる課題がある。具体的には、リンをドーパントとして用いる場合、前記特許文献3によれば、リンの拡散係数は、Ge組成xが高いほど大きい傾向があるため、リンの拡散によって形成される選択エミッタの幅は、結晶Ge層において最も大きく、結晶Si層において最も小さい。 However, when forming a selective emitter for a stacked film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge, the diffusion coefficient of the dopant differs depending on the Ge composition x of crystalline Si 1-x Ge x , As a result, there is a problem that the width of the selective emitter to be formed in the in-plane direction is different among the crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge layers. Specifically, when phosphorus is used as a dopant, according to Patent Document 3, since the diffusion coefficient of phosphorus tends to increase as the Ge composition x increases, the width of the selective emitter formed by phosphorus diffusion is The largest in the crystalline Ge layer and the smallest in the crystalline Si layer.
 従って、太陽電池セルの表面から順に、結晶Si、結晶Si1-xGe、および結晶Geが積層されている場合、結晶Si層の選択エミッタが、コンタクト孔を覆うように形成される場合、リンの拡散係数の違いにより、結晶Ge層の選択エミッタの幅は、結晶Siの選択エミッタの幅より大きく、従って、コンタクト孔の幅より大きくなる。その結果、図9に示すように、結晶Ge層の選択エミッタの幅が、表面電極の幅よりも大きくなり、選択エミッタの一部が、表面電極に遮蔽されない領域に形成されてしまうおそれがある
  以上に述べた、結晶Si、結晶Si1-xGe、および結晶Geの積層膜を発電層とする太陽電池セルの課題をまとめると、第1に、組成傾斜バッファ層を用いて、Ge組成xの高い結晶Si1-xGe膜を発電層とする太陽電池セルを作製すると、キャリア再結合確率が高いという課題がある。第2に、結晶Si、結晶Si1-xGe、および結晶Geの積層膜に対して選択エミッタを形成する場合、リンの拡散係数の違いにより、選択エミッタの一部が、表面電極に遮蔽されない領域に形成され、キャリア再結合による損失が発生するという課題がある。
Therefore, when crystal Si, crystal Si 1-x Ge x , and crystal Ge are stacked in order from the surface of the solar battery cell, when the selective emitter of the crystal Si layer is formed so as to cover the contact hole, Due to the difference in the diffusion coefficient of phosphorus, the width of the selective emitter of the crystalline Ge layer is larger than the width of the selective emitter of crystalline Si and therefore larger than the width of the contact hole. As a result, as shown in FIG. 9, the width of the selective emitter of the crystalline Ge layer becomes larger than the width of the surface electrode, and a part of the selective emitter may be formed in a region that is not shielded by the surface electrode. Summarizing the problems of the solar cell using the stacked film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge described above as the power generation layer, first, the composition of Ge using the composition gradient buffer layer is as follows. When a solar cell using a crystalline Si 1-x Ge x film having a high x as a power generation layer is produced, there is a problem that the carrier recombination probability is high. Second, when a selective emitter is formed for a stacked film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge, a part of the selective emitter is shielded by the surface electrode due to the difference in phosphorus diffusion coefficient. There is a problem that a loss due to carrier recombination occurs in a region that is not formed.
 本発明の代表的な目的は、マルチエキシトン生成の利用と、キャリア再結合損失の低減を両立することで、高効率な太陽電池セルを実現するものである。本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。 A typical object of the present invention is to realize a highly efficient solar cell by making use of multi-exciton generation and reducing carrier recombination loss at the same time. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
 本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記の通りである。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
 第1に、太陽電池セルであって、第1極性の結晶Si基板と、第1極性の結晶Si基板の表面に形成されるGeバッファ層と、Geバッファ層の表面に形成される結晶Ge層と、結晶Ge層の表面に形成される第2極性の結晶Si1-xGe層と、第2極性の結晶Si1-xGe層の表面に形成される第2極性の結晶Si層と、第2極性の結晶Si層の表面に絶縁材にて形成されるパッシベーション層と、第2極性の結晶Si層と同一平面内に形成される第2極性の高濃度ドープ結晶Si層と、第2極性の高濃度ドープ結晶Si層の表面に形成される表面電極と、を有し、第2極性の高濃度ドープ結晶Si層と表面電極との界面における第2極性の高濃度ドープ結晶Si層の幅は、第2極性の高濃度ドープ結晶Si層と第2極性の結晶Si1-xGe層との界面における第2極性の高濃度ドープ結晶Si層の幅よりも大きいことを特徴とする。 First, a solar cell, a first polar crystalline Si substrate, a Ge buffer layer formed on the surface of the first polar crystalline Si substrate, and a crystalline Ge layer formed on the surface of the Ge buffer layer A second polarity crystalline Si 1-x Ge x layer formed on the surface of the crystalline Ge layer, and a second polarity crystalline Si layer formed on the surface of the second polarity crystalline Si 1-x Ge x layer A passivation layer formed of an insulating material on the surface of the second polar crystalline Si layer, a second polar highly doped crystalline Si layer formed in the same plane as the second polar crystalline Si layer, A surface electrode formed on the surface of the second polarity highly doped crystal Si layer, and the second polarity highly doped crystal Si at the interface between the second polarity highly doped crystal Si layer and the surface electrode The width of the layer is such that the heavily doped crystalline Si layer of the second polarity is connected to the second polarity. Si 1-x Ge x is larger than the second polarity of the width of the heavily doped crystalline Si layer at the interface between the said layers.
 第2に、太陽電池セルであって、第1極性の結晶Si基板と、第1極性の結晶Si基板の表面に形成されるGeバッファ層と、Geバッファ層の表面に形成される結晶Ge層と、結晶Ge層の表面に形成される第2極性の結晶Si1-xGe層と、第2極性の結晶Si1-xGe層の表面に形成される第2極性の結晶Si層と、第2極性の結晶Si層の表面に絶縁材にて形成されるパッシベーション層と、パッシベーション層、第2極性の結晶Si層、第2極性の結晶Si1-xGe層、結晶Ge層、前記Geバッファ層、前記第1極性の結晶Si基板のうち、複数の層と接する第2極性の高濃度ドープ層と、第2極性の高濃度ドープ層の表面に形成される表面電極と、を有することを特徴とする。 Second, a solar cell, a first polar crystalline Si substrate, a Ge buffer layer formed on the surface of the first polar crystalline Si substrate, and a crystalline Ge layer formed on the surface of the Ge buffer layer A second polarity crystalline Si 1-x Ge x layer formed on the surface of the crystalline Ge layer, and a second polarity crystalline Si layer formed on the surface of the second polarity crystalline Si 1-x Ge x layer A passivation layer formed of an insulating material on the surface of the second polar crystalline Si layer, a passivation layer, a second polar crystalline Si layer, a second polar crystalline Si 1-x Ge x layer, a crystalline Ge layer A second polar heavily doped layer in contact with a plurality of layers of the Ge buffer layer and the first polar crystalline Si substrate; and a surface electrode formed on the surface of the second polar heavily doped layer; It is characterized by having.
 第3に、太陽電池セルであって、第1極性の結晶Si基板と、第1極性の結晶Si基板の表面に形成される絶縁膜と、絶縁膜の表面に形成される結晶Ge層と、結晶Ge層の表面に形成される第2極性の結晶Si1-xGe層と、第2極性の結晶Si1-xGe層の表面に形成される第2極性の結晶Si層と、第2極性の結晶Si層の表面に絶縁材にて形成されるパッシベーション層と、第2極性の結晶Si層の表面に形成される表面電極と、を有し、第2極性の結晶Si層は、第1極性の結晶Si基板および結晶Ge層と接することを特徴とする。 Third, a solar cell, a first polar crystalline Si substrate, an insulating film formed on the surface of the first polar crystalline Si substrate, a crystalline Ge layer formed on the surface of the insulating film, A second polarity crystalline Si 1-x Ge x layer formed on the surface of the crystalline Ge layer, a second polarity crystalline Si layer formed on the surface of the second polarity crystalline Si 1-x Ge x layer, A passivation layer formed of an insulating material on the surface of the second polar crystalline Si layer, and a surface electrode formed on the surface of the second polar crystalline Si layer, wherein the second polar crystalline Si layer is The first polar crystalline Si substrate and the crystalline Ge layer are in contact with each other.
 本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、マルチエキシトン生成の利用と、キャリア再結合損失の低減を両立することで、高効率な太陽電池セルを実現することができる。 To briefly explain the effects obtained by typical inventions among the inventions disclosed in the present application, a high-efficiency solar cell can be obtained by simultaneously using multi-exciton generation and reducing carrier recombination loss. Can be realized.
本発明の実施例1に係る太陽電池セルを示す上面図である。It is a top view which shows the photovoltaic cell which concerns on Example 1 of this invention. 本発明の実施例1に係る太陽電池セルを示す断面図である。It is sectional drawing which shows the photovoltaic cell which concerns on Example 1 of this invention. 本発明の実施例1に係る太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of the photovoltaic cell which concerns on Example 1 of this invention. 本発明の実施例1に係る太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the photovoltaic cell which concerns on Example 1 of this invention. 図2(a)に続く、太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of a photovoltaic cell following Fig.2 (a). 図2(b)に続く、太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of a photovoltaic cell following FIG.2 (b). 図2(c)に続く、太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.2 (c). 図2(d)に続く、太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of a photovoltaic cell following FIG.2 (d). 図2(e)に続く、太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of a photovoltaic cell following FIG.2 (e). 図2(f)に続く、太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the photovoltaic cell following FIG.2 (f). 図2(g)に続く、太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.2 (g). 図2(h)に続く、太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of a photovoltaic cell following FIG.2 (h). 図2(i)に続く、太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.2 (i). 図2(j)に続く、太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the photovoltaic cell following FIG.2 (j). 本発明の実施例2に係る太陽電池セルを示す上面図である。It is a top view which shows the photovoltaic cell which concerns on Example 2 of this invention. 本発明の実施例2に係る太陽電池セルを示す断面図である。It is sectional drawing which shows the photovoltaic cell which concerns on Example 2 of this invention. 本発明の実施例2に係る太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of the photovoltaic cell which concerns on Example 2 of this invention. 本発明の実施例2に係る太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the photovoltaic cell which concerns on Example 2 of this invention. 図4(a)に続く、太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of a photovoltaic cell following Fig.4 (a). 図4(b)に続く、太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the photovoltaic cell following FIG.4 (b). 図4(c)に続く、太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.4 (c). 図4(d)に続く、太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of a photovoltaic cell following FIG.4 (d). 図4(e)に続く、太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.4 (e). 図4(f)に続く、太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of a photovoltaic cell following FIG.4 (f). 図4(g)に続く、太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.4 (g). 図4(h)に続く、太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the photovoltaic cell following FIG.4 (h). 本発明の実施例3に係る太陽電池セルを示す上面図である。It is a top view which shows the photovoltaic cell which concerns on Example 3 of this invention. 本発明の実施例3に係る太陽電池セルを示す断面図である。It is sectional drawing which shows the photovoltaic cell which concerns on Example 3 of this invention. 本発明の実施例3に係る太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of the photovoltaic cell which concerns on Example 3 of this invention. 本発明の実施例3に係る太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the photovoltaic cell which concerns on Example 3 of this invention. 図6(a)に続く、太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of a photovoltaic cell following Fig.6 (a). 図6(b)に続く、太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of a photovoltaic cell following FIG.6 (b). 図6(c)に続く、太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.6 (c). 図6(d)に続く、太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the photovoltaic cell following FIG.6 (d). 本発明の実施例4に係る太陽電池セルを示す上面図である。It is a top view which shows the photovoltaic cell which concerns on Example 4 of this invention. 本発明の実施例4に係る太陽電池セルを示す断面図である。It is sectional drawing which shows the photovoltaic cell which concerns on Example 4 of this invention. 本発明の実施例4に係る太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of the photovoltaic cell which concerns on Example 4 of this invention. 本発明の実施例4に係る太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the photovoltaic cell which concerns on Example 4 of this invention. 図8(a)に続く、太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of the photovoltaic cell following Fig.8 (a). 図8(b)に続く、太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the photovoltaic cell following FIG.8 (b). 図8(c)に続く、太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.8 (c). 図8(d)に続く、太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the photovoltaic cell following FIG.8 (d). 図8(e)に続く、太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.8 (e). 図8(f)に続く、太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the photovoltaic cell following FIG.8 (f). 図8(g)に続く、太陽電池セルの製造方法を示す上面図である。It is a top view which shows the manufacturing method of the photovoltaic cell following FIG.8 (g). 図8(h)に続く、太陽電池セルの製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the photovoltaic cell following FIG.8 (h). 結晶Si、結晶Si1-xGe、および結晶Geの積層膜に対して、従来技術により選択エミッタを形成した場合の太陽電池セルを示す上面図である。FIG. 6 is a top view showing a solar cell in the case where a selective emitter is formed by a conventional technique with respect to a laminated film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge. 結晶Si、結晶Si1-xGe、および結晶Geの積層膜に対して、従来技術により選択エミッタを形成した場合の太陽電池セルを示す断面図である。FIG. 6 is a cross-sectional view showing a solar cell in the case where a selective emitter is formed by a conventional technique with respect to a laminated film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge. 結晶Si太陽電池セルにおける、波長290nmでの内部量子効率と、選択エミッタの表面リン濃度との関係を示すグラフである。It is a graph which shows the relationship between the internal quantum efficiency in wavelength 290nm, and the surface phosphorus density | concentration of a selective emitter in a crystalline Si photovoltaic cell. 本発明の実施例5に係る太陽電池セルを用いた太陽電池システムを示す構成図である。It is a block diagram which shows the solar cell system using the photovoltaic cell which concerns on Example 5 of this invention.
 本発明の実施例1に係る太陽電池セルについて、図1~図2を用いて説明する。 A solar battery cell according to Example 1 of the present invention will be described with reference to FIGS.
 <太陽電池セルの構造>
図1(a)および図1(b)はそれぞれ、本実施例1に係る太陽電池セルを示す上面図および断面図である。図1(a)の上面図には、図1(b)の断面図との対応関係を分かり易くするために断面図と同じハッチングを付している(以降の上面図においても同様である)。本実施例1の太陽電池セルは、結晶Si基板11上に、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、結晶Si層15、およびパッシベーション層16が形成された太陽電池セルであり、電極として、表面電極21と裏面電極22を有する。また、結晶Ge層13、結晶Si1-xGe層14、および結晶Si層15とそれぞれ同一平面内に、高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31が形成される。高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31は、その内部における、リンやボロンなどのドーパントの濃度が、それぞれ、結晶Ge層13、結晶Si1-xGe層14、および結晶Si層15の内部におけるドーパント濃度よりも高い。
<Solar cell structure>
FIG. 1A and FIG. 1B are a top view and a cross-sectional view, respectively, showing the solar battery cell according to the first embodiment. The top view of FIG. 1A is hatched in the same manner as the cross-sectional view for easy understanding of the correspondence with the cross-sectional view of FIG. . In the solar battery cell of Example 1, the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, the crystalline Si layer 15, and the passivation layer 16 were formed on the crystalline Si substrate 11. It is a solar battery cell, and has a front electrode 21 and a back electrode 22 as electrodes. Further, in the same plane as the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15, respectively, a highly doped crystalline Ge layer 33, a highly doped crystalline Si 1-x Ge x layer 32, Then, a heavily doped crystal Si layer 31 is formed. The heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31 each have a concentration of a dopant such as phosphorus or boron in the crystalline Ge layer. 13, higher than the dopant concentration inside the crystalline Si 1-x Ge x layer 14 and the crystalline Si layer 15.
 ここで、高濃度ドープ結晶Ge層33は、その平面方向の幅が、表面電極21の幅よりも小さいことを特徴とする。また、高濃度ドープ結晶Si層31と表面電極21との界面における、高濃度ドープ結晶Si層31の幅は、パッシベーション層16の開口部の幅よりも大きいことを特徴とする。さらに、高濃度ドープ結晶Si層31と高濃度ドープ結晶Si1-xGe層32との界面における、高濃度ドープ結晶Si層31の幅は、高濃度ドープ結晶Si層31と表面電極21との界面における、高濃度ドープ結晶Si層31の幅よりも小さいことを特徴とする。これらの特徴がもたらす効果については以下に述べる。 Here, the heavily doped crystal Ge layer 33 is characterized in that the width in the planar direction is smaller than the width of the surface electrode 21. In addition, the width of the heavily doped crystal Si layer 31 at the interface between the heavily doped crystal Si layer 31 and the surface electrode 21 is larger than the width of the opening of the passivation layer 16. Further, the width of the heavily doped crystal Si layer 31 at the interface between the heavily doped crystal Si layer 31 and the heavily doped crystal Si 1-x Ge x layer 32 is as follows. It is characterized in that it is smaller than the width of the heavily doped crystalline Si layer 31 at the interface. The effects brought about by these features are described below.
 図1(a)および図1(b)には、表面電極21が、一般的な太陽電池セルと同様に、上面から見て直線状に形成されている場合の構造が示されているが、表面電極21は、異なる上面形状を有してもよい。また、一般的な太陽電池セルと同様に、パッシベーション層16はパターニングされており、本実施例1の構造では、パッシベーション層16の存在しない開口部において、表面電極21と高濃度ドープ結晶Si層31とが接続される。パッシベーション層16の存在しない開口部の上面形状は任意であり、上面から見て直線状であってもよく、あるいは、上面から見て円状の開口が複数存在してもよい。また、高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31の上面形状も任意であり、上面から見て直線状であってもよく、あるいは、上面から見て円状の開口が複数存在してもよい。 In FIG. 1A and FIG. 1B, the structure in the case where the surface electrode 21 is formed in a straight line when viewed from above is shown, as in a general solar battery cell. The surface electrode 21 may have a different top surface shape. Further, like the general solar battery cell, the passivation layer 16 is patterned, and in the structure of the first embodiment, the surface electrode 21 and the heavily doped crystalline Si layer 31 are formed in the opening where the passivation layer 16 does not exist. And are connected. The shape of the upper surface of the opening where the passivation layer 16 does not exist is arbitrary, and may be linear when viewed from the upper surface, or there may be a plurality of circular openings when viewed from the upper surface. Further, the top surface shape of the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31 is arbitrary, and may be linear when viewed from above. Alternatively, there may be a plurality of circular openings as viewed from the top.
 また、結晶Si基板11と裏面電極22とが接続されているが、一般的な太陽電池セルと同様に、結晶Si基板11と裏面電極22との界面にBack Surface Field(BSF)層を設けてもよく、裏面パッシベーション膜をさらに追加し、ポイントコンタクト構造としてもよい。 In addition, the crystalline Si substrate 11 and the back electrode 22 are connected, but a back surface field (BSF) layer is provided at the interface between the crystalline Si substrate 11 and the back electrode 22 as in a general solar battery cell. Alternatively, a back contact passivation film may be further added to form a point contact structure.
 本実施例1の太陽電池セルを構成する半導体の導電型について述べる。以下のp型とn型とが逆であっても良い。結晶Si基板11はp型であり、結晶Si層15、高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31の4層はn型である。結晶Ge層13、結晶Si1-xGe層14の2層は、ともにn型でも、ともにi型でもよいし、あるいは、2層の表面側がn型、基板側がi型であって、2層の内部のいずれかの面にn型とi型の界面が存在してもよい。 The conductivity type of the semiconductor constituting the solar battery cell of Example 1 will be described. The following p-type and n-type may be reversed. The crystalline Si substrate 11 is p-type, and the four layers of the crystalline Si layer 15, the highly doped crystalline Ge layer 33, the highly doped crystalline Si 1-x Ge x layer 32, and the highly doped crystalline Si layer 31 are n-type. It is. The two layers of the crystalline Ge layer 13 and the crystalline Si 1-x Ge x layer 14 may be both n-type or i-type, or the two layers may be n-type on the surface side and i-type on the substrate side, and 2 There may be an n-type and i-type interface on either side of the layer.
 <太陽電池セルの材料>
本実施例1の太陽電池セルを構成する材料について述べる。結晶Si基板11、結晶Ge層13、結晶Si1-xGe層14、結晶Si層15、高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31は、単結晶、多結晶、微結晶などの構造をとり得る。パッシベーション層16の材料は、SiO、SiN(窒化シリコン)、アモルファスSi、SiC(炭化シリコン)、CdSなどの絶縁体、あるいは、これら絶縁体の積層構造である。表面電極21および裏面電極22の材料は、Ag、Al、Ti、Pd、Ni、Cuなどの金属、あるいは、これら金属の積層構造である。
<Material of solar cell>
The material which comprises the photovoltaic cell of the present Example 1 is described. Crystal Si substrate 11, Crystal Ge layer 13, Crystal Si 1-x Ge x layer 14, Crystal Si layer 15, Highly doped crystal Ge layer 33, Highly doped crystal Si 1-x Ge x layer 32, and Highly doped The crystalline Si layer 31 can have a single crystal structure, a polycrystal structure, a microcrystal structure, or the like. The material of the passivation layer 16 is an insulator such as SiO 2 , SiN (silicon nitride), amorphous Si, SiC (silicon carbide), CdS, or a laminated structure of these insulators. The material of the front electrode 21 and the back electrode 22 is a metal such as Ag, Al, Ti, Pd, Ni, or Cu, or a laminated structure of these metals.
 本実施例1の効果を得るためには、特に、パッシベーション層16としてSiOを用いるのが望ましい。その背景には、結晶SiとSiOとの界面が、結晶Si1-xGeとSiOとの界面と比較して、界面再結合が抑制されるためである。以下、上記材料を用いた場合を例にとり、本実施例1の効果について述べる。 In order to obtain the effect of the first embodiment, it is particularly desirable to use SiO 2 as the passivation layer 16. In the background, the interface between the crystalline Si and SiO 2, compared with the interface between the crystalline Si 1-x Ge x and SiO 2, because the interface recombination is suppressed. Hereinafter, the effect of the first embodiment will be described by taking the case of using the above materials as an example.
 <太陽電池セルの効果>
本実施例1によれば、マルチエキシトン生成の利用と、キャリア再結合損失の低減を両立することで、高効率な太陽電池セルを実現することができる。
<Effects of solar cells>
According to the first embodiment, a highly efficient solar battery cell can be realized by using both the use of multi-exciton generation and the reduction of carrier recombination loss.
 まず、マルチエキシトン生成の利用について述べる。本実施例1の構造において、マルチエキシトン生成が発生し得る箇所は、結晶Si基板11、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、および結晶Si層15である。上述の通り、マルチエキシトン生成の利用効率向上のためには、バンド構造におけるΔΓ-2Egの値を小さくすることが有効であり、また、結晶Si1-xGeにおいては、ΔΓ-2Egの値は、xに対して単調に減少する。従って、本実施例1の構造において、結晶Si1-xGe層14を、マルチエキシトン生成の主な発生層とすることで、結晶Si太陽電池セルに比べ、マルチエキシトン生成の利用効率を向上することができる。結晶Si1-xGe層14を、マルチエキシトン生成の主な発生層とするには、結晶Si1-xGeの2Eg以上のエネルギーを有する光を、できるだけ多く、結晶Si1-xGe層14の内部で吸収させる必要があり、これは、後述のように、結晶Si1-xGe層14と結晶Si層15との膜厚と、結晶Si1-xGe層14におけるGe組成xとを適切に選択することにより、可能となる。 First, the use of multi-exciton generation will be described. In the structure of the first embodiment, the locations where multi-exciton generation can occur are the crystalline Si substrate 11, the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15. . As described above, in order to improve the utilization efficiency of multi-exciton production, it is effective to reduce the value of Δ Γ -2Eg in the band structure, and in the crystalline Si 1-x Ge x , Δ Γ -2Eg The value of decreases monotonically with respect to x. Therefore, in the structure of Example 1, the crystal Si 1-x Ge x layer 14 is used as a main generation layer for multi-exciton generation, thereby improving the use efficiency of multi-exciton generation compared to the crystal Si solar cell. can do. The crystal Si 1-x Ge x layer 14, to the main generating layer Maruchiekishiton generated light having a higher energy 2Eg crystal Si 1-x Ge x, as many crystal Si 1-x Ge It is necessary to absorb the inside of the x layer 14, as will be described later. This is because the film thicknesses of the crystalline Si 1-x Ge x layer 14 and the crystalline Si layer 15 and the crystalline Si 1-x Ge x layer 14 This is possible by appropriately selecting the Ge composition x.
 次に、キャリア再結合損失の低減について述べる。以下、3種類のキャリア再結合損失について述べる。第1のキャリア再結合損失は、結晶Si層15とパッシベーション層16との界面での再結合による損失である。上述の通り、結晶Si1-xGe/SiO界面準位密度は、結晶Si/SiO界面準位密度よりも高く、その結果として、結晶Si1-xGe太陽電池セルには、高品質な表面パッシベーション膜形成が困難であるという課題がある。これに対し本実施例1の構造においては、パッシベーション層16と結晶Si1-xGe層14との間に、結晶Si層15が存在する。このため、表面パッシベーションは、結晶Si/SiO界面において行われることになり、高品質な表面パッシベーション膜形成が可能となる。 Next, reduction of carrier recombination loss will be described. Hereinafter, three types of carrier recombination loss will be described. The first carrier recombination loss is a loss due to recombination at the interface between the crystalline Si layer 15 and the passivation layer 16. As described above, the crystalline Si 1-x Ge x / SiO 2 interface state density is higher than the crystalline Si / SiO 2 interface state density, and as a result, the crystalline Si 1-x Ge x solar cell has There is a problem that it is difficult to form a high-quality surface passivation film. On the other hand, in the structure of the first embodiment, the crystalline Si layer 15 exists between the passivation layer 16 and the crystalline Si 1-x Ge x layer 14. For this reason, surface passivation is performed at the crystalline Si / SiO 2 interface, and a high-quality surface passivation film can be formed.
 第2のキャリア再結合損失は、結晶Si1-xGe層14の形成時に結晶Si1-xGe層14の内部、および、結晶Si1-xGe層14と結晶Si基板11との間の領域に発生する結晶欠陥による再結合損失である。上述の通り、結晶Si1-xGe層14の形成方法として、組成傾斜バッファ層を用いる方法を適用すると、結晶Si1-xGe層14のGe組成xが高い場合に、上記再結合損失が大きい。そこで、本実施例1の太陽電池セルにおいては、Geバッファ層12を用いることにより、結晶Si基板11上に、結晶Ge層13を形成し、その後、結晶Ge層13上に結晶Si1-xGe層14を形成する。この方法によれば、結晶欠陥密度の低い結晶Ge層13を形成することができる。このため、結晶Si1-xGe層14のGe組成xが高い場合には、結晶Ge層13上に形成される結晶Si1-xGe層14の結晶欠陥密度も低減可能である。また、上述の組成傾斜バッファ層を用いた方法と比較すると、Geバッファ層12の膜厚は、組成傾斜バッファ層の膜厚よりも小さいため、Geバッファ層12の内部でのキャリア再結合は、組成傾斜バッファ層の内部でのキャリア再結合よりも抑制される。 Recombination loss second carrier, the interior of the crystal Si 1-x Ge crystal Si during the formation of the x layer 14 1-x Ge x layer 14, and the crystal Si 1-x Ge x layer 14 and the crystal Si substrate 11 It is a recombination loss due to a crystal defect generated in a region between. As described above, as a method for forming the crystalline Si 1-x Ge x layer 14, applying the method of using the composition graded buffer layer, when the crystal Si 1-x Ge x layer 14 of the Ge composition x is high, the recombination The loss is great. Therefore, in the solar battery cell of Example 1, the Ge buffer layer 12 is used to form the crystalline Ge layer 13 on the crystalline Si substrate 11, and then the crystalline Si 1-x on the crystalline Ge layer 13. A Ge x layer 14 is formed. According to this method, the crystalline Ge layer 13 having a low crystal defect density can be formed. Therefore, when the Ge composition x of the crystalline Si 1-x Ge x layer 14 is high, the crystal defect density of the crystalline Si 1-x Ge x layer 14 formed on the crystalline Ge layer 13 can also be reduced. Moreover, since the film thickness of the Ge buffer layer 12 is smaller than the film thickness of the composition gradient buffer layer as compared with the method using the composition gradient buffer layer described above, carrier recombination inside the Ge buffer layer 12 is This is suppressed more than the carrier recombination inside the composition gradient buffer layer.
 第3のキャリア再結合は、選択エミッタ内部での再結合損失である。本実施例1の構造においては、高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31の3層が選択エミッタを形成する。上述のように、結晶Si、結晶Si1-xGe、および結晶Geの積層膜に対して選択エミッタを形成する場合、リンの拡散係数の違いにより、選択エミッタの一部が、表面電極に遮蔽されない領域に形成され、キャリア再結合による損失が発生する。本実施例1の構造においては、選択エミッタ形成時に、開口幅の異なる複数のマスクを用いた多段階ドーパント注入を行うことで、選択エミッタが、表面電極21に遮蔽された領域に形成される。製造方法の詳細は後述するが、概要は以下の通りである。まず第1段階として、高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31の3層にわたる深さの選択エミッタを、開口幅の狭いマスクを用いて形成する。この際、上記3層のうち、高濃度ドープ結晶Ge層33の幅が、表面電極21の幅よりも小さくなるように、マスクの開口幅を設定する。次に第2段階として、高濃度ドープ結晶Si層31の表面領域にのみ、選択エミッタを、開口幅の広いマスクを用いて形成する。この際、高濃度ドープ結晶Si層31の幅が、パッシベーション層16の開口部の幅よりも大きくなるように、マスクの開口幅を設定する。こうした多段階ドーパント注入の結果、図1(a)に示すように、高濃度ドープ結晶Si層31と高濃度ドープ結晶Si1-xGe層32との界面における、高濃度ドープ結晶Si層31の幅は、高濃度ドープ結晶Si層31と表面電極21との界面における、高濃度ドープ結晶Si層31の幅よりも小さくなる。以上の方法で形成された選択エミッタは、表面電極21に遮蔽された領域に形成されるため、図9に示す構造と異なり、選択エミッタ内部でのキャリア再結合損失増大は発生しない。 The third carrier recombination is a recombination loss inside the selective emitter. In the structure of the first embodiment, three layers of the highly doped crystal Ge layer 33, the highly doped crystal Si 1-x Ge x layer 32, and the highly doped crystal Si layer 31 form a selective emitter. As described above, when a selective emitter is formed for a stacked film of crystalline Si, crystalline Si 1-x Ge x , and crystalline Ge, a part of the selective emitter becomes a surface electrode due to a difference in diffusion coefficient of phosphorus. It is formed in a region that is not shielded, and loss due to carrier recombination occurs. In the structure of the first embodiment, the selective emitter is formed in a region shielded by the surface electrode 21 by performing multi-step dopant implantation using a plurality of masks having different opening widths when forming the selective emitter. Details of the manufacturing method will be described later, but the outline is as follows. First, as a first step, a selective emitter having a depth extending over three layers of a heavily doped crystal Ge layer 33, a heavily doped crystal Si 1-x Ge x layer 32, and a heavily doped crystal Si layer 31 is formed with a narrow opening width. It is formed using a mask. At this time, the opening width of the mask is set so that the width of the heavily doped crystal Ge layer 33 among the three layers is smaller than the width of the surface electrode 21. Next, as a second step, a selective emitter is formed only in the surface region of the heavily doped crystal Si layer 31 using a mask having a wide opening width. At this time, the opening width of the mask is set so that the width of the heavily doped crystal Si layer 31 is larger than the width of the opening of the passivation layer 16. As a result of such multistage dopant implantation, as shown in FIG. 1A, the heavily doped crystal Si layer 31 at the interface between the heavily doped crystal Si layer 31 and the heavily doped crystal Si 1-x Ge x layer 32 is obtained. Is smaller than the width of the heavily doped crystalline Si layer 31 at the interface between the heavily doped crystalline Si layer 31 and the surface electrode 21. Since the selective emitter formed by the above method is formed in a region shielded by the surface electrode 21, unlike the structure shown in FIG. 9, there is no increase in carrier recombination loss inside the selective emitter.
 以上より、本実施例1の構造においては、結晶Si層15とパッシベーション層16との界面での再結合損失、結晶Si1-xGe層14の形成時に生じる結晶欠陥による再結合損失、および、選択エミッタ内部での再結合損失の3つを低減することが可能である。この結果、本実施例1により、マルチエキシトン生成の利用と、キャリア再結合損失の低減を両立することで、高効率な太陽電池セルを実現することができる。 As described above, in the structure of the first embodiment, the recombination loss at the interface between the crystalline Si layer 15 and the passivation layer 16, the recombination loss due to crystal defects generated when the crystalline Si 1-x Ge x layer 14 is formed, and It is possible to reduce three of the recombination losses inside the selective emitter. As a result, according to the first embodiment, it is possible to realize a highly efficient solar battery cell by satisfying both the use of multi-exciton generation and the reduction of carrier recombination loss.
 <効果を得るためのパラメータ>
以下、本実施例1の構造において、本実施例1の効果を得る上で、特に重要な3つのパラメータの数値範囲について述べる。
<Parameters for obtaining effects>
Hereinafter, the numerical ranges of three parameters that are particularly important in obtaining the effects of the first embodiment in the structure of the first embodiment will be described.
 第1のパラメータは、結晶Si1-xGe層14のGe組成xである。xの値の決定に際しては、マルチエキシトン生成の利用効率向上と、結晶Si1-xGe層14の形成条件との2点を考慮する必要がある。 The first parameter is the Ge composition x of the crystalline Si 1-x Ge x layer 14. In determining the value of x, it is necessary to consider two points: improvement in utilization efficiency of multi-exciton generation and formation conditions of the crystalline Si 1-x Ge x layer 14.
 まず、マルチエキシトン生成の利用効率向上のためには、上述の通り、ΔΓ-2Egの値を小さくする必要がある。結晶Si1-xGeにおいては、0<x<0.68ではΔΓ-2Eg>0、x=0.68においてΔΓ-2Eg=0となり、x>0.68ではΔΓ-2Eg<0である。ΔΓ-2Eg<0の場合、Γ点での光吸収で発生した電子と正孔とは、マルチエキシトン生成を発生させることができない。従って、マルチエキシトン生成を利用するためには、ΔΓ-2Egの値は0以上であり、かつできるだけ小さいのが望ましい。その点で、xの値は、0<x≦0.68の範囲内であるのが望ましく、特に、上記範囲内で、xの値ができるだけ大きいのが望ましい。 First, in order to improve the utilization efficiency of multi-exciton generation, it is necessary to reduce the value of Δ Γ -2Eg as described above. In crystalline Si 1-x Ge x, 0 <x <0.68 in Δ Γ -2Eg> 0, the x = 0.68 Δ Γ -2Eg = 0 becomes, x> 0.68 In Δ Γ -2Eg < 0. When Δ Γ -2Eg <0, electrons and holes generated by light absorption at the Γ point cannot generate multi-exciton production. Therefore, in order to utilize multi-exciton production, it is desirable that the value of Δ Γ -2Eg is 0 or more and as small as possible. In this respect, the value of x is preferably in the range of 0 <x ≦ 0.68, and in particular, the value of x is preferably as large as possible within the above range.
 次に、結晶Si1-xGe層14の形成条件について述べる。本実施例1においては、結晶Ge層13の上に結晶Si1-xGe層14を形成するため、結晶Ge層13と結晶Si1-xGe層14との間で、格子定数の差が小さいことが望ましい。このため、xの値が大きい方が、エピタキシャル成長を容易に行うことができる。以上より、0<x≦0.68の範囲内であるのが望ましく、特に、上記範囲内で、xの値ができるだけ大きいのが望ましい。 Next, conditions for forming the crystalline Si 1-x Ge x layer 14 will be described. In Example 1, since the crystalline Si 1-x Ge x layer 14 is formed on the crystalline Ge layer 13, the lattice constant between the crystalline Ge layer 13 and the crystalline Si 1-x Ge x layer 14 is changed. It is desirable that the difference is small. For this reason, epitaxial growth can be easily performed when the value of x is large. From the above, it is desirable that the range is 0 <x ≦ 0.68, and it is particularly desirable that the value of x is as large as possible within the above range.
 第2のパラメータは、結晶Si1-xGe層14の膜厚である。結晶Si1-xGe層14の膜厚の決定に際しては、結晶Si1-xGe層14での光吸収と、結晶Si1-xGe層14の形成条件との2点を考慮する必要がある。 The second parameter is the film thickness of the crystalline Si 1-x Ge x layer 14. In the thickness of the determination of the crystal Si 1-x Ge x layer 14, consideration of the two points of the light absorption in the crystal Si 1-x Ge x layer 14, the formation conditions of the crystal Si 1-x Ge x layer 14 There is a need to.
 まず、結晶Si1-xGe層14での光吸収について述べる。上述の通り、本実施例1の構造においては、結晶Si1-xGe層14を、マルチエキシトン生成の主な発生層とすることが重要である。このため、マルチエキシトン生成の発生に用いられる高エネルギー光が、エミッタ層12でできるだけ多く吸収されることが望ましい。例えば、2eV以上のエネルギーを有する光を、結晶Si1-xGe層14のみで吸収させるのに必要な結晶Si1-xGe層14の膜厚は、光吸収係数から、2μmと見積もられる。 First, light absorption in the crystalline Si 1-x Ge x layer 14 will be described. As described above, in the structure of the first embodiment, it is important that the crystalline Si 1-x Ge x layer 14 is a main generation layer for multi-exciton generation. For this reason, it is desirable that the high energy light used for generating multi-exciton is absorbed by the emitter layer 12 as much as possible. For example, light having energy higher than 2 eV, the thickness of the crystal Si 1-x Ge x layer 14 only required to absorb crystal Si 1-x Ge x layer 14, the light absorption coefficient, estimated to 2μm It is.
 一方で、結晶Si1-xGe層14の形成条件の観点からは、例えば、上述のようにエピタキシャル成長法を用いる場合を考えると、結晶Si1-xGe層14の膜厚が小さい方が望ましい。従って、結晶Si1-xGe層14の膜厚は、太陽電池セル特性上は、2μm以下であるのが望ましく、特に、上記範囲内で、結晶Si1-xGe層14の膜厚ができるだけ大きいのが望ましいが、最終的には、形成条件を考慮した上で結晶Si1-xGe層14の膜厚を決定する必要がある。 On the other hand, from the viewpoint of the formation conditions of the crystalline Si 1-x Ge x layer 14, for example, considering the case where the epitaxial growth method is used as described above, the one where the thickness of the crystalline Si 1-x Ge x layer 14 is smaller Is desirable. Therefore, the film thickness of the crystalline Si 1-x Ge x layer 14 is desirably 2 μm or less in terms of solar cell characteristics, and particularly within the above range, the film thickness of the crystalline Si 1-x Ge x layer 14 Is desirably as large as possible, but ultimately it is necessary to determine the film thickness of the crystalline Si 1-x Ge x layer 14 in consideration of the formation conditions.
 第3のパラメータは、結晶Si層15の膜厚である。結晶Si層15の膜厚の決定に際しては、結晶Si1-xGe層14での光吸収と、結晶Si1-xGe層14からのGeの拡散との2点を考慮する必要がある。 The third parameter is the film thickness of the crystalline Si layer 15. In determining the thickness of the crystal Si layer 15, the light absorption in the crystal Si 1-x Ge x layer 14, is necessary to consider two points and diffusion of Ge from the crystal Si 1-x Ge x layer 14 is there.
 まず、結晶Si1-xGe層14での光吸収について述べる。上述の通り、本実施例1においては、マルチエキシトン生成の発生に用いられる高エネルギー光が、結晶Si1-xGe層14でできるだけ多く吸収されることが望ましい。このため、結晶Si層15での光吸収を抑制するために、結晶Si層15の膜厚はできるだけ小さいことが望ましい。特に、本実施例1の構造においては、上記光吸収の目的から、結晶Si層15の膜厚は、結晶Si1-xGe層14の膜厚よりも小さい。これは、本実施例1の構造が有する、上述の先行技術文献に開示された構造に対する際立った特徴といえる。 First, light absorption in the crystalline Si 1-x Ge x layer 14 will be described. As described above, in the first embodiment, it is desirable that the high-energy light used for generating the multi-exciton is absorbed as much as possible by the crystalline Si 1-x Ge x layer 14. For this reason, in order to suppress light absorption in the crystalline Si layer 15, it is desirable that the thickness of the crystalline Si layer 15 be as small as possible. In particular, in the structure of the first embodiment, the thickness of the crystalline Si layer 15 is smaller than the thickness of the crystalline Si 1-x Ge x layer 14 for the purpose of light absorption. This can be said to be an outstanding feature with respect to the structure disclosed in the above-described prior art document, which the structure of the first embodiment has.
 次に、結晶Si1-xGe層14からのGeの拡散について述べる。後述する本実施例1の太陽電池セルの製造過程において、結晶Si1-xGe層14の形成後に、試料に高温の熱処理を行う工程では、結晶Si1-xGe層14からのGeの拡散が生じる。特に、上述のように、高品質な表面パッシベーション膜形成のために、パッシベーション層16として、熱酸化法により形成されたSiO膜を用いる場合、熱酸化中の、結晶Si1-xGe層14からのGeの拡散を考慮する必要がある。 Next, the diffusion of Ge from the crystalline Si 1-x Ge x layer 14 will be described. In the manufacturing process of the solar cell of the embodiment 1 to be described later, after formation of the crystalline Si 1-x Ge x layer 14, in the step of performing heat treatment of high temperature in the sample, Ge from the crystal Si 1-x Ge x layer 14 Diffusion occurs. In particular, as described above, when an SiO 2 film formed by a thermal oxidation method is used as the passivation layer 16 for forming a high-quality surface passivation film, the crystalline Si 1-x Ge x layer during thermal oxidation is used. It is necessary to consider the diffusion of Ge from 14.
 一例として、温度900℃のもとで5400秒の酸化処理を行う場合を考える。温度900℃のもとでの、結晶Si中のGeの拡散係数は10-16cm-1であるから、拡散距離は、√(10-16×5400)=7×10-7cm=7nmとなる。もし、結晶Si層15の膜厚が7nm以下の場合には、本実施例1の太陽電池セルの製造過程終了時点において、結晶Si層15とパッシベーション層16との界面にGeが存在し、その結果、パッシベーション品質が低下することが懸念される。結晶Si層15の膜厚を7nm以上とすることで、高品質な表面パッシベーション膜形成が可能となる。以上より、結晶Si層15の膜厚は、7nm以上であるのが望ましく、特に、上記範囲内で、結晶Si層15の膜厚ができるだけ小さいのが望ましい。 As an example, consider a case where an oxidation treatment is performed at a temperature of 900 ° C. for 5400 seconds. Since the diffusion coefficient of Ge in crystalline Si at a temperature of 900 ° C. is 10 −16 cm 2 s −1 , the diffusion distance is √ (10 −16 × 5400) = 7 × 10 −7 cm = 7 nm. If the film thickness of the crystalline Si layer 15 is 7 nm or less, Ge is present at the interface between the crystalline Si layer 15 and the passivation layer 16 at the end of the manufacturing process of the solar cell of the first embodiment. As a result, there is a concern that the quality of the passivation is lowered. By setting the thickness of the crystalline Si layer 15 to 7 nm or more, a high-quality surface passivation film can be formed. From the above, the film thickness of the crystalline Si layer 15 is desirably 7 nm or more. In particular, the film thickness of the crystalline Si layer 15 is desirably as small as possible within the above range.
 <太陽電池セルの製造方法>
図2(a)~図2(l)は、本実施例1に係る太陽電池セルの製造方法を示す上面図および断面図である。以下、図2(a)~図2(l)に基づいて、本実施例1の太陽電池セルの製造方法の各工程を説明する。
<Solar cell manufacturing method>
FIG. 2A to FIG. 2L are a top view and a cross-sectional view showing a method for manufacturing a solar battery cell according to the first embodiment. Hereafter, each process of the manufacturing method of the photovoltaic cell of this Example 1 is demonstrated based on Fig.2 (a)-FIG.2 (l).
 まず、結晶Si基板11の表面に、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、および結晶Si層15を、この順に形成する。Geバッファ層12の形成後には、水素雰囲気中での熱処理を加えることで、Geバッファ層12を格子緩和させ、その上に形成される結晶Ge層13の結晶欠陥を低減することが望ましい。Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、および結晶Si層15の形成方法は、結晶欠陥低減のためにエピタキシャル成長法により行うのが望ましいが、上記の一部の層をCVD法などの他の成膜法により行ってもよい。上述の通り、結晶Ge層13、結晶Si1-xGe層14、および結晶Si層15の少なくとも一部は、全面にわたってドーピングされたエミッタである。そのドーピングは、上記成膜時に行ってもよいし、上記成膜後に、イオン注入、気相拡散、あるいは固相拡散といった方法により行ってもよい。 First, a Ge buffer layer 12, a crystalline Ge layer 13, a crystalline Si 1-x Ge x layer 14, and a crystalline Si layer 15 are formed in this order on the surface of the crystalline Si substrate 11. After the formation of the Ge buffer layer 12, it is desirable to apply a heat treatment in a hydrogen atmosphere to relax the lattice of the Ge buffer layer 12 and reduce crystal defects in the crystalline Ge layer 13 formed thereon. The formation method of the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 is preferably performed by an epitaxial growth method to reduce crystal defects. The layer may be formed by other film forming methods such as a CVD method. As described above, at least a part of the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 is an emitter doped over the entire surface. The doping may be performed during the film formation, or may be performed by a method such as ion implantation, gas phase diffusion, or solid phase diffusion after the film formation.
 次に、結晶Si層15の表面に、マスク34を形成する。マスク34の材料は、フォトリソグラフィーや電子線リソグラフィーで用いられるレジスト、SiOなどの絶縁膜、あるいはこれらの積層膜である。マスク34の開口は、リソグラフィーとエッチング、あるいはレーザー加工などにより行う。あるいは、スクリーン印刷法などにより、マスク34の開口部分に、はじめからマスク34が形成されない方法を用いてもよい。マスク34の形成後の構造の上面図を図2(a)に、断面図を図2(b)に、それぞれ示す。 Next, a mask 34 is formed on the surface of the crystalline Si layer 15. Material of the mask 34, the resist used in photolithography or electron beam lithography, which is an insulating film or a laminated film, such as SiO 2. The opening of the mask 34 is performed by lithography and etching or laser processing. Alternatively, a method in which the mask 34 is not initially formed in the opening portion of the mask 34 by a screen printing method or the like may be used. A top view of the structure after forming the mask 34 is shown in FIG. 2A, and a cross-sectional view is shown in FIG. 2B.
 その後、高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31を形成する。形成後の構造の上面図を図2(c)に、断面図を図2(d)に、それぞれ示す。高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31の形成は、イオン注入法や、気相拡散などの拡散法により行うことができる。イオン注入法を用いる場合には、ドーパントの注入後の活性化を、熱処理またはレーザー処理により行う。図2(c)および図2(d)には、ドーパントの活性化後の状態が示されている。上述のように、結晶Si1-xGeのGe組成xによって、ドーパントの拡散係数が異なり、特に、Ge組成xが高いほど、リンの拡散係数が大きいため、図2(d)に示すように、高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31の3層のうち、高濃度ドープ結晶Ge層33の幅が最も大きく、高濃度ドープ結晶Si層31の幅が最も小さい。 Thereafter, a heavily doped crystal Ge layer 33, a heavily doped crystal Si 1-x Ge x layer 32, and a heavily doped crystal Si layer 31 are formed. A top view of the structure after formation is shown in FIG. 2C, and a cross-sectional view is shown in FIG. Formation of the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31 can be performed by a diffusion method such as ion implantation or vapor phase diffusion. . In the case of using an ion implantation method, activation after dopant implantation is performed by heat treatment or laser treatment. FIG. 2C and FIG. 2D show the state after activation of the dopant. As described above, the diffusion coefficient of the dopant varies depending on the Ge composition x of the crystalline Si 1-x Ge x , and in particular, the higher the Ge composition x, the larger the diffusion coefficient of phosphorus. Therefore, as shown in FIG. Further, among the three layers of the highly doped crystal Ge layer 33, the highly doped crystal Si 1-x Ge x layer 32, and the highly doped crystal Si layer 31, the width of the heavily doped crystal Ge layer 33 is the largest, The width of the heavily doped crystal Si layer 31 is the smallest.
 次に、マスク34を除去し、その後に、より大きな開口幅を有するマスク35を形成する。形成後の構造の上面図を図2(e)に、断面図を図2(f)に、それぞれ示す。マスク35の除去は、マスク35がレジストであればアッシングなどの処理により、マスク35が絶縁膜であればエッチングなどの処理により、それぞれ行うことができる。再形成されるマスク35は、1回目に用いたマスク34と同じ材料および形成方法を用いることができる。 Next, the mask 34 is removed, and then a mask 35 having a larger opening width is formed. A top view of the structure after formation is shown in FIG. 2 (e), and a cross-sectional view is shown in FIG. 2 (f). The mask 35 can be removed by a process such as ashing if the mask 35 is a resist, or by a process such as etching if the mask 35 is an insulating film. The mask 35 to be re-formed can use the same material and formation method as the mask 34 used for the first time.
 その後、マスク35を用いて、結晶Si層15の表面部分に、高濃度ドープ結晶Si層31を形成する。形成後の構造の上面図を図2(g)に、断面図を図2(h)に、それぞれ示す。結晶Si層15の表面部分に、高濃度ドープ結晶Si層31が形成された結果、図2(h)に示すように、高濃度ドープ結晶Si層31と高濃度ドープ結晶Si1-xGe層32との界面における、高濃度ドープ結晶Si層31の幅は、高濃度ドープ結晶Si層31と表面電極21との界面における、高濃度ドープ結晶Si層31の幅よりも小さくなる。高濃度ドープ結晶Si層31の形成は、上述の、高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31の3層を形成した際と同様、イオン注入法や、気相拡散などの拡散法により行うことができる。但し、今回の高濃度ドープ結晶Si層31形成の際には、ドーパントが結晶Si1-xGe層14および結晶Ge層13に拡散しないよう、例えば、ドーパントの活性化の熱処理を短時間化するなどの手段を用いる必要がある。 Thereafter, the heavily doped crystalline Si layer 31 is formed on the surface portion of the crystalline Si layer 15 using the mask 35. A top view of the structure after formation is shown in FIG. 2G, and a cross-sectional view is shown in FIG. As a result of the formation of the heavily doped crystalline Si layer 31 on the surface portion of the crystalline Si layer 15, as shown in FIG. 2 (h), the heavily doped crystalline Si layer 31 and the heavily doped crystalline Si 1-x Ge x are formed. The width of the heavily doped crystal Si layer 31 at the interface with the layer 32 is smaller than the width of the heavily doped crystal Si layer 31 at the interface between the heavily doped crystal Si layer 31 and the surface electrode 21. The highly doped crystal Si layer 31 is formed when the above-described three layers of the highly doped crystal Ge layer 33, the highly doped crystal Si 1-x Ge x layer 32, and the highly doped crystal Si layer 31 are formed. Similarly to the above, it can be carried out by an ion implantation method or a diffusion method such as vapor phase diffusion. However, in forming the heavily doped crystalline Si layer 31 this time, for example, the heat treatment for activating the dopant is shortened so that the dopant does not diffuse into the crystalline Si 1-x Ge x layer 14 and the crystalline Ge layer 13. It is necessary to use means such as.
 次に、マスク35を除去し、その後に、パッシベーション層16を形成する。パッシベーション層16の形成は、熱酸化法、プラズマ酸化法、CVD法などにより行う。上述の通り、高品質な表面パッシベーション膜形成のためにはパッシベーション層16の形成を熱酸化法により行うことが望ましいが、熱酸化法を用いると、結晶Si基板11の裏面側にも、パッシベーション層16が形成される。これに対し、例えば、プラズマCVD法を用いた場合には、結晶Si基板11の裏面側にはパッシベーション層16が形成されない。 Next, the mask 35 is removed, and then the passivation layer 16 is formed. The passivation layer 16 is formed by a thermal oxidation method, a plasma oxidation method, a CVD method, or the like. As described above, in order to form a high-quality surface passivation film, it is desirable to form the passivation layer 16 by a thermal oxidation method. However, if the thermal oxidation method is used, the passivation layer 16 is also formed on the back surface side of the crystalline Si substrate 11. 16 is formed. On the other hand, for example, when the plasma CVD method is used, the passivation layer 16 is not formed on the back side of the crystalline Si substrate 11.
 その後、結晶Si基板11の裏面側に、裏面電極22を形成する。形成後の構造の上面図を図2(i)に、断面図を図2(j)に、それぞれ示す。裏面電極22の形成は、印刷法、蒸着法、めっき法、スパッタ法、CVD法などの成膜法により行う。なお、上記パッシベーション層16の形成過程において、結晶Si基板11の裏面側にもパッシベーション層16が形成される場合には、裏面電極22を形成する前に、パッシベーション層16のうち、結晶Si基板11の裏面側の領域を除去する必要がある。 Thereafter, a back electrode 22 is formed on the back side of the crystalline Si substrate 11. A top view of the structure after formation is shown in FIG. 2 (i), and a cross-sectional view is shown in FIG. 2 (j). The back electrode 22 is formed by a film forming method such as a printing method, a vapor deposition method, a plating method, a sputtering method, or a CVD method. In the process of forming the passivation layer 16, when the passivation layer 16 is formed also on the back surface side of the crystalline Si substrate 11, the crystalline Si substrate 11 in the passivation layer 16 is formed before the back surface electrode 22 is formed. It is necessary to remove the area on the back side of the.
 次に、パッシベーション層16に開口部を形成する。パッシベーション層16の開口部の形成は、リソグラフィーとエッチングを用いたパターニング法、あるいは、エッチングペーストを用いたパターニング法により行ってもよい。パッシベーション層16の開口部の幅は、高濃度ドープ結晶Si層31の最表面における幅よりも小さい必要がある。もし、パッシベーション層16の開口部の幅が、高濃度ドープ結晶Si層31の最表面における幅よりも大きく、その結果、結晶Si層15の上部にも、パッシベーション層16の開口部が存在すると、ドーピング濃度が比較的低い層である結晶Si層15と表面電極21とが直接接することになり、その接触界面におけるキャリア再結合損失が発生する。 Next, an opening is formed in the passivation layer 16. The opening of the passivation layer 16 may be formed by a patterning method using lithography and etching, or a patterning method using an etching paste. The width of the opening of the passivation layer 16 needs to be smaller than the width at the outermost surface of the heavily doped crystal Si layer 31. If the width of the opening of the passivation layer 16 is larger than the width at the outermost surface of the heavily doped crystalline Si layer 31, and as a result, the opening of the passivation layer 16 also exists above the crystalline Si layer 15, The crystalline Si layer 15, which is a layer having a relatively low doping concentration, and the surface electrode 21 are in direct contact, and carrier recombination loss occurs at the contact interface.
 最後に、表面電極21を形成する。形成後の構造の上面図を図2(k)に、断面図を図2(l)に、それぞれ示す。表面電極21の形成は、印刷法、蒸着法、めっき法、スパッタ法、CVD法などの成膜法により行う。 Finally, the surface electrode 21 is formed. A top view of the structure after formation is shown in FIG. 2 (k), and a cross-sectional view is shown in FIG. 2 (l). The surface electrode 21 is formed by a film forming method such as a printing method, a vapor deposition method, a plating method, a sputtering method, or a CVD method.
 上記の製造方法では、パッシベーション層16に開口部を形成し、その後に表面電極21を形成するが、その代わりに、パッシベーション層16に対する開口部形成を行わず、表面電極21の形成後に焼成を行い、表面電極21と高濃度ドープ結晶Si層31とを電気的に導通させる、いわゆるファイアスルーを用いる方法により行ってもよい。ファイアスルーを用いる方法の場合、パッシベーション層16の開口部の上面から見た形状は、表面電極21の上面から見た形状と同一になる。一方、パッシベーション層16に開口部を形成する方法によれば、表面電極21と高濃度ドープ結晶Si層31との接触面積を低減することが可能である。表面電極21と高濃度ドープ結晶Si層31との接触面積低減は、再結合抑制の効果があることが知られているが、一方で、接触抵抗の増大をもたらすため、再結合と接触抵抗の2点を考慮して、接触面積を最適化する必要がある。 In the above manufacturing method, an opening is formed in the passivation layer 16 and then the surface electrode 21 is formed. Instead, the opening is not formed in the passivation layer 16, and baking is performed after the surface electrode 21 is formed. Alternatively, the surface electrode 21 and the heavily doped crystal Si layer 31 may be electrically connected to each other by a method using a so-called fire-through. In the case of the method using fire-through, the shape seen from the upper surface of the opening of the passivation layer 16 is the same as the shape seen from the upper surface of the surface electrode 21. On the other hand, according to the method of forming the opening in the passivation layer 16, it is possible to reduce the contact area between the surface electrode 21 and the heavily doped crystal Si layer 31. Although it is known that a reduction in contact area between the surface electrode 21 and the heavily doped crystal Si layer 31 has an effect of suppressing recombination, on the other hand, an increase in contact resistance is caused. It is necessary to optimize the contact area in consideration of two points.
 以上が、本実施例1の太陽電池セルの製造方法である。上記工程に加えて、各々の膜の結晶性や膜質の改善のため、あるいは隣接膜との界面の質を向上させるための熱処理、プラズマ処理などを適宜追加してもよい。 The above is the method for manufacturing the solar battery cell of Example 1. In addition to the above steps, heat treatment, plasma treatment, etc. may be added as appropriate to improve the crystallinity and film quality of each film or to improve the quality of the interface with the adjacent film.
 本発明の実施例2について、図3~図4を用いて説明する。本実施例2では、前記実施例1と違う点を主に説明する。 Example 2 of the present invention will be described with reference to FIGS. In the second embodiment, differences from the first embodiment will be mainly described.
 <太陽電池セルの構造、材料および効果>
図3(a)および図3(b)は、本実施例2に係る太陽電池セルを示す上面図および断面図である。図3(a)は上面図であり、図3(b)は断面図である。本実施例2の太陽電池セルは、結晶Si基板11上に、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、結晶Si層15、およびパッシベーション層16が形成され、さらに、上記の層のうち複数の層と接する高濃度ドープ結晶Si層31が形成された太陽電池セルであり、電極として、表面電極21と裏面電極22を有する。本実施例2の太陽電池セルにおいては、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、結晶Si層15、およびパッシベーション層16のうち、表面に近い層から順に、少なくとも2つの層に対して、パターニングにより開口部が形成される。図3(b)には、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、および結晶Si層15がいずれもパターニングされた構造が示されているが、例えば、結晶Si層15と、結晶Si1-xGe層14の表面側のみがパターニングされ、その他の領域はパターニングされなくてもよい。また、図3(b)に示すように、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、および結晶Si層15がいずれもパターニングされ、同時に、結晶Si基板11の表面部分にも開口部が形成されてもよい。また、図3(b)には、上記開口部の形状が四角形の場合が示されているが、丸型や三角形など、他の形状の開口部を形成してもよい。
<Structure, material and effect of solar cell>
FIG. 3A and FIG. 3B are a top view and a cross-sectional view showing the solar battery cell according to the second embodiment. 3A is a top view, and FIG. 3B is a cross-sectional view. In the solar battery cell of Example 2, a Ge buffer layer 12, a crystalline Ge layer 13, a crystalline Si 1-x Ge x layer 14, a crystalline Si layer 15, and a passivation layer 16 are formed on a crystalline Si substrate 11, Furthermore, it is a solar cell in which a highly doped crystalline Si layer 31 in contact with a plurality of layers among the above layers is formed, and has a front electrode 21 and a back electrode 22 as electrodes. In the solar cell of the second embodiment, the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, the crystalline Si layer 15, and the passivation layer 16, in order from the layer closest to the surface, Openings are formed by patterning for at least two layers. FIG. 3B shows a structure in which the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 are all patterned. Only the surface side of the Si layer 15 and the crystalline Si 1-x Ge x layer 14 is patterned, and other regions may not be patterned. Further, as shown in FIG. 3B, the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 are all patterned, and at the same time, the crystalline Si substrate 11 An opening may be formed in the surface portion. Further, FIG. 3B shows a case where the shape of the opening is a quadrangle, but an opening having another shape such as a round shape or a triangle may be formed.
 前記実施例1との違いは、2点ある。第1の点は、前記実施例1においては、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、および結晶Si層15は、パターニングされないのに対して、本実施例2においては、上記4つの層のいずれかがパターニングされるということである。第2の点は、前記実施例1においては、選択エミッタは、高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31の3層からなるのに対して、本実施例2においては、選択エミッタは、高濃度ドープ結晶Si層31のみからなるということである。これら2点の違いがもたらす結果については、以下で述べる。 There are two differences from the first embodiment. The first point is that the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 are not patterned in the first embodiment, whereas the first embodiment 2 indicates that any of the four layers is patterned. The second point is that, in the first embodiment, the selective emitter is composed of three layers of the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31. In contrast, in the second embodiment, the selective emitter is composed of only the heavily doped crystal Si layer 31. The consequences of these two differences are discussed below.
 本実施例2の太陽電池セルによれば、前記実施例1の場合と比べて、第1に、選択エミッタの形成に伴うパターニングの回数を低減することができる。第2に、太陽電池セル表面を基準として、より深い領域にも、選択エミッタを形成することができる。以下、これらの効果について述べる。 According to the solar cell of the second embodiment, firstly, the number of times of patterning associated with the formation of the selective emitter can be reduced as compared with the case of the first embodiment. Second, the selective emitter can be formed in a deeper region with respect to the surface of the solar battery cell. Hereinafter, these effects will be described.
 まず、第1の効果である、選択エミッタの形成に伴うパターニングの回数低減について述べる。前記実施例1の場合には、選択エミッタを形成するために、開口幅の異なるマスク34を用いた2回のパターニングを行う。さらに、選択エミッタ形成後に、パッシベーション層16の開口部を形成するパターニングも必要である。これに対して、本実施例2の場合には、後述する製造方法を用いることにより、選択エミッタを形成するためには、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、および結晶Si層15に開口部を形成するための1回のパターニングのみが必要であり、さらに、選択エミッタ形成後に、パッシベーション層16の開口部を形成するパターニングは不要である。従って、本実施例2により、前記実施例1の場合よりも、太陽電池セルの製造に必要なパターニングの回数を低減できるため、より低コストでの製造が可能となる。 First, the first effect, the reduction in the number of times of patterning associated with the formation of the selective emitter, will be described. In the case of the first embodiment, patterning is performed twice using a mask 34 having different opening widths in order to form a selective emitter. Further, after forming the selective emitter, patterning for forming an opening of the passivation layer 16 is also necessary. On the other hand, in the case of the second embodiment, a Ge buffer layer 12, a crystalline Ge layer 13, a crystalline Si 1-x Ge x layer are used to form a selective emitter by using a manufacturing method described later. 14 and only one patterning for forming an opening in the crystalline Si layer 15 is necessary, and further, the patterning for forming the opening of the passivation layer 16 is unnecessary after the selective emitter is formed. Therefore, according to the second embodiment, the number of times of patterning necessary for manufacturing the solar battery cell can be reduced as compared with the case of the first embodiment, so that the manufacturing at a lower cost is possible.
 次に、第2の効果である、太陽電池セル表面を基準として、より深い領域にも、選択エミッタを形成することができるという点について述べる。選択エミッタを、表面から深い領域に形成することで、太陽電池セル内部で発生したキャリアが、選択エミッタに到達するまでの距離を低減し、その結果、キャリア再結合損失を低減することが可能となる。前記実施例1の場合には、選択エミッタの形成深さは、イオン注入法や拡散法によるドーパントの到達距離により決定される。具体的には、イオン注入のエネルギーが高いほど、また、拡散や活性化の温度が高く、時間が長いほど、より深い領域に選択エミッタが形成される。しかしながら、これらのパラメータを変更すると、形成される選択エミッタの幅も変わってしまうため、選択エミッタの深さだけを制御することは困難であった。 Next, the second effect that the selective emitter can be formed in a deeper region with the solar cell surface as a reference will be described. By forming the selective emitter in a deep region from the surface, it is possible to reduce the distance until carriers generated inside the solar cell reach the selective emitter, and as a result, it is possible to reduce carrier recombination loss. Become. In the case of the first embodiment, the formation depth of the selective emitter is determined by the reach distance of the dopant by the ion implantation method or the diffusion method. Specifically, the higher the ion implantation energy, the higher the diffusion and activation temperatures, and the longer the time, the more selective emitters are formed in deeper regions. However, if these parameters are changed, the width of the formed selective emitter is also changed, so that it is difficult to control only the depth of the selected emitter.
 これに対して、本実施例2の場合には、上述の通り、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、結晶Si層15、およびパッシベーション層16のうち、パッシベーション層16と、その他の層のうち、表面に近い層から順に、少なくとも1つの層に対して、パターニングにより開口部が形成される。上記開口部の形成の際に、ドライエッチングや、結晶の面方位によってエッチングレートの異なるウェットエッチングなどを用いれば、開口部の深さを比較的広範囲にわたって制御することが可能である。選択エミッタとなる高濃度ドープ結晶Si層31は、上記開口部の形状に沿って形成されるため、上記開口部の深さが、選択エミッタの形成深さを決定する。特に、上記開口部がGeバッファ層12を貫通して、結晶Si基板11に到達する程度に深く形成される場合、結晶Si基板11の内部で発生した少数キャリアは、Geバッファ層12を通過せずに、高濃度ドープ結晶Si層31を介して表面電極21に収集されるので、キャリア再結合損失が低減される。以上より、本実施例2により、前記実施例1の場合と比べて、より深い領域にも、選択エミッタを形成することができ、その結果、キャリア再結合の低減が可能になる。 On the other hand, in the case of the second embodiment, as described above, among the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, the crystalline Si layer 15, and the passivation layer 16, Among the passivation layer 16 and other layers, an opening is formed by patterning in at least one layer in order from the layer closest to the surface. When the opening is formed, the depth of the opening can be controlled over a relatively wide range by using dry etching or wet etching having a different etching rate depending on the crystal orientation. Since the heavily doped crystal Si layer 31 serving as the selective emitter is formed along the shape of the opening, the depth of the opening determines the formation depth of the selective emitter. In particular, when the opening is formed deep enough to penetrate the Ge buffer layer 12 and reach the crystalline Si substrate 11, minority carriers generated inside the crystalline Si substrate 11 cannot pass through the Ge buffer layer 12. Without being collected by the surface electrode 21 via the heavily doped crystal Si layer 31, the carrier recombination loss is reduced. As described above, according to the second embodiment, a selective emitter can be formed in a deeper region than in the first embodiment, and as a result, carrier recombination can be reduced.
 <太陽電池セルの製造方法>
図4(a)~図4(j)は、本実施例2に係る太陽電池セルの製造方法を示す上面図および断面図である。以下、図4(a)~図4(j)に基づいて、本実施例2の太陽電池セルの製造方法の各工程を説明する。
<Solar cell manufacturing method>
4 (a) to 4 (j) are a top view and a cross-sectional view showing a method for manufacturing a solar battery cell according to the second embodiment. Hereafter, each process of the manufacturing method of the photovoltaic cell of this Example 2 is demonstrated based on Fig.4 (a)-FIG.4 (j).
 まず、前記実施例1と同様に、結晶Si基板11の表面に、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、および結晶Si層15を、この順に形成し、さらに、パッシベーション層16を形成する。 次に、表面側のパッシベーション層16に対して、パターニングにより開口部を形成する。形成後の構造の上面図を図4(a)に、断面図を図4(b)に、それぞれ示す。 First, similarly to Example 1, a Ge buffer layer 12, a crystalline Ge layer 13, a crystalline Si 1-x Ge x layer 14, and a crystalline Si layer 15 are formed in this order on the surface of the crystalline Si substrate 11, Further, a passivation layer 16 is formed. Next, an opening is formed by patterning the surface-side passivation layer 16. FIG. 4A shows a top view of the structure after formation, and FIG. 4B shows a cross-sectional view thereof.
 その後、パッシベーション層16をマスクとして、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、および結晶Si層15に開口部を形成する。形成後の構造の上面図を図4(c)に、断面図を図4(d)に、それぞれ示す。図4(d)には上記開口部が、結晶Si基板11の表面側にも到達する場合の構造が示されている。上記開口部の形成は、ドライエッチング、ウェットエッチング、レーザー加工などにより行うことができる。ウェットエッチングの一例として、結晶Si基板11が(100)面の場合、面方位によるエッチングレートの違いを利用して、結晶Ge層13、結晶Si1-xGe層14、および結晶Si層15の(111)面を露出させる異方性エッチングを用いるという方法がある。結晶Siに対しては、アルカリ溶液により異方性エッチングを行う方法が知られている。結晶Geに対しては、過酸化水素水、あるいは、過酸化水素水とフッ酸の混合液により異方性エッチングを行う方法が知られている。 Thereafter, openings are formed in the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 using the passivation layer 16 as a mask. A top view of the structure after formation is shown in FIG. 4C, and a cross-sectional view is shown in FIG. 4D. FIG. 4D shows a structure in which the opening reaches the surface side of the crystalline Si substrate 11. The opening can be formed by dry etching, wet etching, laser processing, or the like. As an example of wet etching, when the crystalline Si substrate 11 has a (100) plane, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15 are utilized by utilizing the difference in etching rate depending on the plane orientation. There is a method of using anisotropic etching that exposes the (111) plane. For crystalline Si, a method of performing anisotropic etching with an alkaline solution is known. For crystal Ge, a method of performing anisotropic etching with hydrogen peroxide solution or a mixed solution of hydrogen peroxide solution and hydrofluoric acid is known.
 次に、高濃度ドープ結晶Si層31を形成する。形成後の構造の上面図を図4(e)に、断面図を図4(f)に、それぞれ示す。高濃度ドープ結晶Si層31の形成は、CVD法やエピタキシャル成長法などにより行う。図4(f)には、高濃度ドープ結晶Si層31が表面側にのみ形成された構造が示されているが、高濃度ドープ結晶Si層31の形成法によっては、裏面側にも高濃度ドープ結晶Si層31が形成される場合がある。その場合は、裏面側の高濃度ドープ結晶Si層31を除去する必要がある。 Next, a heavily doped crystal Si layer 31 is formed. FIG. 4E shows a top view of the structure after formation, and FIG. 4F shows a cross-sectional view. The highly doped crystal Si layer 31 is formed by a CVD method, an epitaxial growth method, or the like. FIG. 4 (f) shows a structure in which the heavily doped crystal Si layer 31 is formed only on the front surface side, but depending on the method of forming the heavily doped crystal Si layer 31, a high concentration is also formed on the back surface side. Doped crystal Si layer 31 may be formed. In that case, it is necessary to remove the heavily doped crystalline Si layer 31 on the back side.
 その後、形成されている場合は裏面側のパッシベーション層16を除去し、さらに、表面電極21および裏面電極22を形成する。形成後の構造の上面図を図4(g)に、断面図を図4(h)に、それぞれ示す。パッシベーション層16の除去、および、表面電極21と裏面電極22の形成は、前記実施例1と同様に行う。 After that, if formed, the passivation layer 16 on the back surface side is removed, and further, the front surface electrode 21 and the back surface electrode 22 are formed. A top view of the structure after formation is shown in FIG. 4G, and a cross-sectional view is shown in FIG. 4H. Removal of the passivation layer 16 and formation of the front electrode 21 and the back electrode 22 are performed in the same manner as in the first embodiment.
 次に、マスク34を形成する。マスク34の幅は、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、および結晶Si層15に形成された開口部の幅より大きいことが望ましい。その後、マスク34を用いたエッチングにより、表面電極21、および、その下部の高濃度ドープ結晶Si層31を除去する。除去後の構造の上面図を図4(i)に、断面図を図4(j)に、それぞれ示す。表面電極21、および、その下部の高濃度ドープ結晶Si層31を同時に除去するには、ドライエッチングを用いるのが望ましい。その際、除去される高濃度ドープ結晶Si層31の下部のパッシベーション層16が完全にエッチングされないよう、エッチングガス等の条件を選択する必要がある。 Next, a mask 34 is formed. The width of the mask 34 is desirably larger than the width of the openings formed in the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, and the crystalline Si layer 15. Thereafter, the surface electrode 21 and the heavily doped crystalline Si layer 31 thereunder are removed by etching using the mask 34. A top view of the structure after removal is shown in FIG. 4 (i), and a cross-sectional view is shown in FIG. 4 (j). In order to simultaneously remove the surface electrode 21 and the heavily doped crystalline Si layer 31 below the surface electrode 21, it is desirable to use dry etching. At that time, it is necessary to select conditions such as etching gas so that the passivation layer 16 below the heavily doped crystal Si layer 31 to be removed is not completely etched.
 最後に、マスク34を除去すると、図3(a)および図3(b)に示す太陽電池セルができる。以上のようにして、本実施例2の太陽電池セルを製造することができる。 Finally, when the mask 34 is removed, the solar cells shown in FIGS. 3 (a) and 3 (b) are formed. As described above, the solar battery cell of Example 2 can be manufactured.
 本発明の実施例3について、図5~図6を用いて説明する。本実施例3では、前記実施例2と違う点を主に説明する。 Example 3 of the present invention will be described with reference to FIGS. In the third embodiment, differences from the second embodiment will be mainly described.
 <太陽電池セルの構造、材料および効果>
図5(a)および図5(b)は、本実施例3に係る太陽電池セルを示す上面図および断面図である。図5(a)は上面図であり、図5(b)は断面図である。本実施例3の太陽電池セルは、結晶Si基板11上に、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、結晶Si層15、およびパッシベーション層16が形成され、上記の層に対して開口部が形成され、さらに、開口部の側壁に、高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31の3層が形成された太陽電池セルであり、電極として、表面電極21と裏面電極22を有する。後述するように、選択エミッタをイオン注入法や拡散法により形成するため、高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31は、それぞれ、Geバッファ層12または結晶Ge層13、結晶Si1-xGe層14、結晶Si層15または結晶Si基板11と接する位置に形成される。
<Structure, material and effect of solar cell>
FIG. 5A and FIG. 5B are a top view and a cross-sectional view showing the solar battery cell according to the third embodiment. FIG. 5A is a top view and FIG. 5B is a cross-sectional view. In the solar cell of Example 3, a Ge buffer layer 12, a crystalline Ge layer 13, a crystalline Si 1-x Ge x layer 14, a crystalline Si layer 15, and a passivation layer 16 are formed on a crystalline Si substrate 11, An opening is formed with respect to the above-described layer, and the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31 are formed on the sidewall of the opening. It is a solar cell in which three layers are formed, and has a front electrode 21 and a back electrode 22 as electrodes. As will be described later, since the selective emitter is formed by ion implantation or diffusion, the heavily doped crystal Ge layer 33, the heavily doped crystal Si 1-x Ge x layer 32, and the heavily doped crystal Si layer 31 are: They are formed at positions in contact with the Ge buffer layer 12 or the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, the crystalline Si layer 15 or the crystalline Si substrate 11, respectively.
 前記実施例2との違いを述べる。前記実施例2の構造では、選択エミッタは、高濃度ドープ結晶Si層31のみで構成されていたが、本実施例3の構造では、選択エミッタは、高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31の3層から構成される。但し、前記実施例2と同様に、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、結晶Si層15、およびパッシベーション層16に対して形成される開口部の深さには自由度があるため、例えば、上記開口部が、結晶Si層15とパッシベーション層16の2層にのみ形成される場合には、選択エミッタは、結晶Si層15の側部に形成される高濃度ドープ結晶Si層31のみとなる。 Differences from the second embodiment will be described. In the structure of the second embodiment, the selective emitter is composed of only the heavily doped crystal Si layer 31. However, in the structure of the third embodiment, the selective emitter is the heavily doped crystal Ge layer 33, the heavily doped crystal. The crystal Si 1-x Ge x layer 32 and the highly doped crystal Si layer 31 are composed of three layers. However, the depth of the opening formed for the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, the crystalline Si layer 15, and the passivation layer 16 as in the second embodiment. Therefore, for example, when the opening is formed only in two layers of the crystalline Si layer 15 and the passivation layer 16, the selective emitter is formed in the side portion of the crystalline Si layer 15. Only the heavily doped crystal Si layer 31 is provided.
 本実施例3の太陽電池セルによれば、後述のように、表面電極21の加工時に、ウェットエッチングを用いることができるため、表面電極21の加工時にドライエッチングを用いる前記実施例2の場合と比べて、パッシベーション層16に導入されるダメージが低減される。これにより、パッシベーション層16と結晶Si層15との界面での再結合損失を低減することができる。以下、本実施例3の太陽電池セルの製造方法について述べる。 According to the solar cell of Example 3, since wet etching can be used when processing the surface electrode 21 as described later, the case of Example 2 in which dry etching is used when processing the surface electrode 21 is used. In comparison, the damage introduced into the passivation layer 16 is reduced. Thereby, the recombination loss at the interface between the passivation layer 16 and the crystalline Si layer 15 can be reduced. Hereinafter, a method for manufacturing the solar battery cell of Example 3 will be described.
 <太陽電池セルの製造方法>
図6(a)~図6(f)は、本実施例3に係る太陽電池セルの製造方法を示す上面図および断面図である。以下、図6(a)~図6(f)に基づいて、本実施例3の太陽電池セルの製造方法の各工程を説明する。
<Solar cell manufacturing method>
6 (a) to 6 (f) are a top view and a cross-sectional view showing a method for manufacturing a solar battery cell according to the third embodiment. Hereafter, each process of the manufacturing method of the photovoltaic cell of this Example 3 is demonstrated based on Fig.6 (a)-FIG.6 (f).
 まず、前記実施例2と同様に、結晶Si基板11の表面に、Geバッファ層12、結晶Ge層13、結晶Si1-xGe層14、結晶Si層15、およびパッシベーション層16を、この順に形成し、上記の層に対してパターニングにより開口部を形成する。形成後の構造の上面図を図6(a)に、断面図を図6(b)に、それぞれ示す。 First, similarly to Example 2, the Ge buffer layer 12, the crystalline Ge layer 13, the crystalline Si 1-x Ge x layer 14, the crystalline Si layer 15, and the passivation layer 16 are formed on the surface of the crystalline Si substrate 11. These are formed in order, and openings are formed by patterning the above layers. A top view of the structure after formation is shown in FIG. 6A, and a cross-sectional view is shown in FIG. 6B.
 次に、上記開口部の底部および側部に対してドーピングを行い、高濃度ドープ結晶Ge層33、高濃度ドープ結晶Si1-xGe層32、および高濃度ドープ結晶Si層31を形成する。形成後の構造の上面図を図6(c)に、断面図を図6(d)に、それぞれ示す。ドーピングの際に、表面側のパッシベーション層16をマスクとして用いることができる。また、上記開口部の側部に対してドーピングを行うには、イオン注入時に、ウエハに対して斜め方向にイオンビームを入射する方法が有効である。 Next, the bottom and sides of the opening are doped to form a highly doped crystal Ge layer 33, a heavily doped crystal Si 1-x Ge x layer 32, and a heavily doped crystal Si layer 31. . A top view of the structure after formation is shown in FIG. 6C, and a cross-sectional view is shown in FIG. 6D. At the time of doping, the passivation layer 16 on the surface side can be used as a mask. In order to dope the side portions of the opening, an ion beam is incident on the wafer in an oblique direction at the time of ion implantation.
 最後に、裏面側のパッシベーション層16を除去し、表面電極21と裏面電極22を形成する。形成後の構造の上面図を図6(e)に、断面図を図6(f)に、それぞれ示す。図6(e)および図6(f)には、表面電極21がパターン加工された後の構造が示されている。前記実施例2の場合には、表面電極21と、その下部の高濃度ドープ結晶Si層31をともに除去する必要があるため、ドライエッチングを用いる方法が望ましいが、本実施例3の場合には、表面電極21のみを除去すればよく、従って、ウェットエッチングを用いることが可能となる。上述のように、表面電極21の加工をウェットエッチングにより行うことで、ドライエッチングの場合と比べ、パッシベーション層16に導入されるダメージが低減される。 Finally, the passivation layer 16 on the back surface side is removed, and the front surface electrode 21 and the back surface electrode 22 are formed. A top view of the structure after formation is shown in FIG. 6E, and a cross-sectional view is shown in FIG. 6F. FIG. 6E and FIG. 6F show the structure after the surface electrode 21 is patterned. In the case of the second embodiment, since it is necessary to remove both the surface electrode 21 and the heavily doped crystal Si layer 31 therebelow, a method using dry etching is desirable. Only the surface electrode 21 needs to be removed, and therefore wet etching can be used. As described above, when the surface electrode 21 is processed by wet etching, damage introduced into the passivation layer 16 is reduced as compared with dry etching.
 以上のようにして、本実施例3の太陽電池セルを製造することができる。 As described above, the solar battery cell of Example 3 can be manufactured.
 本発明の実施例4について、図7~図8を用いて説明する。本実施例4では、前記実施例1と違う点を主に説明する。 Example 4 of the present invention will be described with reference to FIGS. In the fourth embodiment, differences from the first embodiment will be mainly described.
 <太陽電池セルの構造、材料および効果>
図7(a)および図7(b)は、本実施例4に係る太陽電池セルを示す上面図および断面図である。図7(a)は上面図であり、図7(b)は断面図である。本実施例4の太陽電池セルは、結晶Si基板11上に、埋め込み酸化膜36、結晶Ge層13、および結晶Si1-xGe層14が形成され、上記の層に対して開口部が形成され、さらに、上記開口部上に、結晶Si層15、およびパッシベーション層16が形成された太陽電池セルであり、電極として、表面電極21と裏面電極22を有する。図7(b)には、結晶Si基板11と結晶Ge層13との間に、埋め込み酸化膜36と結晶Si層15が形成された構造が示されている。すなわち、上記開口部形成の際、埋め込み酸化膜36の開口部の幅が、結晶Ge層13の開口部の幅よりも大きい場合の構造が示されている。太陽電池セルの直列抵抗低減のためには、図7(b)のように、埋め込み酸化膜36の開口部の幅が、結晶Ge層13の開口部の幅よりも大きいことが望ましいが、埋め込み酸化膜36の開口部の幅が、結晶Ge層13の開口部の幅以下であってもよい。
<Structure, material and effect of solar cell>
FIG. 7A and FIG. 7B are a top view and a cross-sectional view showing the solar battery cell according to the fourth embodiment. FIG. 7A is a top view, and FIG. 7B is a cross-sectional view. In the solar cell of Example 4, a buried oxide film 36, a crystalline Ge layer 13, and a crystalline Si 1-x Ge x layer 14 are formed on a crystalline Si substrate 11, and an opening is formed with respect to the above layer. The solar cell is formed and further has a crystalline Si layer 15 and a passivation layer 16 formed on the opening, and has a front electrode 21 and a back electrode 22 as electrodes. FIG. 7B shows a structure in which a buried oxide film 36 and a crystalline Si layer 15 are formed between the crystalline Si substrate 11 and the crystalline Ge layer 13. That is, a structure is shown in which the width of the opening of the buried oxide film 36 is larger than the width of the opening of the crystalline Ge layer 13 when the opening is formed. In order to reduce the series resistance of the solar battery cell, it is desirable that the width of the opening of the buried oxide film 36 is larger than the width of the opening of the crystalline Ge layer 13 as shown in FIG. The width of the opening of the oxide film 36 may be equal to or smaller than the width of the opening of the crystalline Ge layer 13.
 本実施例4の太陽電池セルによれば、結晶Ge層13を形成するために、前記実施例1の構造におけるGeバッファ層12が不要であるため、太陽電池セル内部で発生したキャリアが、Geバッファ層12を通過することに伴う再結合損失を回避することが可能となる。以下、本実施例4では、選択エミッタ内部での再結合損失について述べないが、本実施例4の太陽電池セルにおいても、前記実施例1、2、および3と同様の手法により、選択エミッタ内部での再結合損失を低減することが可能である。以下、本実施例4の太陽電池セルの製造方法について述べる。 According to the solar cell of the fourth embodiment, since the Ge buffer layer 12 in the structure of the first embodiment is not necessary to form the crystalline Ge layer 13, the carriers generated inside the solar cell are Ge. It becomes possible to avoid recombination loss associated with passing through the buffer layer 12. Hereinafter, although the recombination loss inside the selective emitter will not be described in the fourth embodiment, the solar cell of the fourth embodiment also uses the same method as in the first, second, and third embodiments in the inside of the selected emitter. It is possible to reduce the recombination loss at. Hereinafter, the manufacturing method of the photovoltaic cell of Example 4 will be described.
 <太陽電池セルの製造方法>
図8A~図8Nは、本実施例4に係る太陽電池セルの製造方法を示す上面図および断面図である。以下、図8A~図8Nに基づいて、本実施例3の太陽電池セルの製造方法の各工程を説明する。
<Solar cell manufacturing method>
8A to 8N are a top view and a cross-sectional view showing a method for manufacturing a solar battery cell according to the fourth embodiment. Hereafter, each process of the manufacturing method of the photovoltaic cell of this Example 3 is demonstrated based on FIG. 8A-FIG. 8N.
 まず、本実施例4においては、結晶Si基板11上に、埋め込み酸化膜36と結晶Ge層13とが、この順に形成された、Germanium On Insulator基板(以下、GeOI基板と記す)を用いても良い。GeOI基板の作製は、結晶Ge膜のエピタキシャル成長と、基板の貼り合わせ、および剥離を用いたSmart Cut法などの方法により行う。 First, in Example 4, a Germanium On Insulator substrate (hereinafter referred to as a GeOI substrate) in which a buried oxide film 36 and a crystalline Ge layer 13 are formed in this order on a crystalline Si substrate 11 may be used. good. The GeOI substrate is manufactured by a method such as the Smart Cut method using epitaxial growth of a crystalline Ge film, bonding of the substrates, and peeling.
 次に、結晶Ge層13の上部に、結晶Si1-xGe層14を形成する。形成後の上面図を図8(a)に、断面図を図8(b)に、それぞれ示す。結晶Si1-xGe層14の形成は、前記実施例1と同様の方法により行うことができる。 Next, a crystalline Si 1-x Ge x layer 14 is formed on the crystalline Ge layer 13. FIG. 8A shows a top view after formation, and FIG. 8B shows a cross-sectional view. Formation of the crystalline Si 1-x Ge x layer 14 can be performed by the same method as in the first embodiment.
 その後、結晶Ge層13、および、結晶Si1-xGe層14に開口部を形成する。上記開口部の形成は、ドライエッチング、ウェットエッチング、レーザー加工などにより行うことができる。次に、埋め込み酸化膜36に開口部を形成する。形成後の上面図を図8(c)に、断面図を図8(d)に、それぞれ示す。上記開口部の形成は、ウェットエッチングにより行うのが望ましい。その理由は、ウェットエッチングを用いれば、ドライエッチングやレーザー加工などの方法と異なり、埋め込み酸化膜36に対してサイドエッチングを行うことで、埋め込み酸化膜36の開口部の幅を、結晶Ge層13および結晶Si1-xGe層14の開口部の幅よりも大きくすることが可能であるためである。埋め込み酸化膜36の開口部の幅を大きくすることで、その後に形成される、結晶Si層15と結晶Si基板11との接触面積が増大するため、太陽電池セルの直列抵抗を低減することができる。 Thereafter, openings are formed in the crystalline Ge layer 13 and the crystalline Si 1-x Ge x layer 14. The opening can be formed by dry etching, wet etching, laser processing, or the like. Next, an opening is formed in the buried oxide film 36. FIG. 8C shows a top view after formation, and FIG. 8D shows a cross-sectional view. The opening is preferably formed by wet etching. The reason for this is that if wet etching is used, unlike the methods such as dry etching and laser processing, side etching is performed on the buried oxide film 36 to reduce the width of the opening of the buried oxide film 36 to the crystalline Ge layer 13. This is because the width of the opening of the crystalline Si 1-x Ge x layer 14 can be made larger. Increasing the width of the opening of the buried oxide film 36 increases the contact area between the crystalline Si layer 15 and the crystalline Si substrate 11 to be formed thereafter, so that the series resistance of the solar cell can be reduced. it can.
 その後、結晶Si層15を形成する。形成後の上面図を図8(e)に、断面図を図8(f)に、それぞれ示す。結晶Si層15の形成は、前記実施例1と同様に、エピタキシャル成長法やCVD法などにより行うことができる。 Thereafter, a crystalline Si layer 15 is formed. FIG. 8E shows a top view after formation, and FIG. 8F shows a cross-sectional view. The crystalline Si layer 15 can be formed by an epitaxial growth method, a CVD method, or the like, as in the first embodiment.
 次に、前記実施例1と同様の方法により、パッシベーション層16を形成する。形成後の上面図を図8(g)に、断面図を図8(h)に、それぞれ示す。 Next, the passivation layer 16 is formed by the same method as in the first embodiment. FIG. 8G shows a top view after formation, and FIG. 8H shows a cross-sectional view.
 最後に、裏面側のパッシベーション層16を除去し、表面電極21と裏面電極22を形成する。形成後の構造の上面図を図8(i)に、断面図を図8(j)に、それぞれ示す。図8(i)および図8(j)には、表面電極21がパターン加工された後の構造が示されている。表面電極21のパターン加工は、ドライエッチングやウェットエッチングなどの方法により行うことができる。また、表面側のパッシベーション層16の開口部を形成する際、図8(j)に示すように、パッシベーション層16のうち除去されない領域の幅が、結晶Si1-xGe層14の開口部の幅よりも大きいことが望ましい。その理由は、もし、パッシベーション層16のうち除去されない領域の幅が、結晶Si1-xGe層14の開口部の幅よりも小さい場合、表面電極21が、結晶Si1-xGe層14の開口部の端部を跨ぐように形成される必要があり、断線のリスクが高くなるためである。 Finally, the backside passivation layer 16 is removed, and the front electrode 21 and the back electrode 22 are formed. A top view of the structure after formation is shown in FIG. 8 (i), and a cross-sectional view is shown in FIG. 8 (j). 8 (i) and 8 (j) show the structure after the surface electrode 21 is patterned. The patterning of the surface electrode 21 can be performed by a method such as dry etching or wet etching. Further, when forming the opening of the passivation layer 16 on the surface side, as shown in FIG. 8 (j), the width of the region of the passivation layer 16 that is not removed is the opening of the crystalline Si 1-x Ge x layer 14. It is desirable to be larger than the width of. The reason for this is that if the width of the non-removed region of the passivation layer 16 is smaller than the width of the opening of the crystalline Si 1-x Ge x layer 14, the surface electrode 21 has a crystalline Si 1-x Ge x layer. This is because it is necessary to be formed so as to straddle the ends of the 14 openings, which increases the risk of disconnection.
 以上のようにして、本実施例4の太陽電池セルを製造することができる。 As described above, the solar battery cell of Example 4 can be manufactured.
 本発明の実施例5について、図11を用いて説明する。本実施例5は、前記実施例1、2、3および4で説明した太陽電池セルを用いた太陽電池システムの例である。 Example 5 of the present invention will be described with reference to FIG. The fifth embodiment is an example of a solar battery system using the solar battery cells described in the first, second, third, and fourth embodiments.
 <太陽電池システム>
図11は、本実施例5に係る太陽電池セルを用いた太陽電池システムを示す構成図である。本実施例5は、前記実施例1、2、3および4の太陽電池セルを用いた太陽電池システムである。太陽電池システムは、太陽電池パネル41と、接続箱42と、集電箱43と、パワーコンディショナー44と、変圧器45とを有する。
<Solar cell system>
FIG. 11 is a configuration diagram illustrating a solar battery system using the solar battery cells according to the fifth embodiment. The fifth embodiment is a solar battery system using the solar battery cells of the first, second, third, and fourth embodiments. The solar cell system includes a solar cell panel 41, a connection box 42, a current collection box 43, a power conditioner 44, and a transformer 45.
 太陽電池パネル41は、前記実施例1、2、3および4で説明した太陽電池セルを複数配置した太陽電池パネルである。この太陽電池パネル41は、太陽光により電力を発電するパネルである。接続箱42は、太陽電池パネル41により発電された電力を集電箱43へ送電する接続箱である。集電箱43は、接続箱42から送電されてきた電力を集約してパワーコンディショナー44へ送電する集電箱である。パワーコンディショナー44は、集電箱43から送電されてきた電力を直流から交流へ変換して変圧器45へ送電する変換器である。変圧器45は、パワーコンディショナー44から送電されてきた交流電力の電圧を変圧して商用電力系統46へ送電する変圧器である。 The solar battery panel 41 is a solar battery panel in which a plurality of the solar battery cells described in Examples 1, 2, 3, and 4 are arranged. The solar cell panel 41 is a panel that generates electric power by sunlight. The connection box 42 is a connection box that transmits the electric power generated by the solar cell panel 41 to the current collection box 43. The current collection box 43 is a current collection box that collects the electric power transmitted from the connection box 42 and transmits it to the power conditioner 44. The power conditioner 44 is a converter that converts the electric power transmitted from the current collection box 43 from direct current to alternating current and transmits the electric power to the transformer 45. The transformer 45 is a transformer that transforms the voltage of the AC power transmitted from the power conditioner 44 and transmits it to the commercial power system 46.
 図11の例では、商用電力系統46に接続される1つの変圧器45に対して、3系統のパワーコンディショナー44および集電箱43が接続されている。さらに、各1系統のパワーコンディショナー44および集電箱43に対して、3系統の接続箱42および太陽電池パネル41が接続されている。 11, three power conditioners 44 and a current collection box 43 are connected to one transformer 45 connected to the commercial power system 46. Further, a three-system connection box 42 and a solar cell panel 41 are connected to each one-system power conditioner 44 and current collection box 43.
 本実施例5に係る太陽電池システムにおいて、太陽電池パネル41で発電された電力は、接続箱42へと送電され、集電箱43で集約される。その後、パワーコンディショナー44で、直流から交流へと変換され、纏めて変圧器45で電圧を変圧し、商用電力系統46に接続される。なお、上記構成は、太陽電池システムの中でも、特に、パネル枚数の多いメガソーラーシステムの構成例である。パネル枚数の比較的少ない住宅用システムの場合には、接続箱42から直接、パワーコンディショナー44へと接続される。 In the solar cell system according to the fifth embodiment, the electric power generated by the solar cell panel 41 is transmitted to the connection box 42 and collected by the current collection box 43. Thereafter, the power conditioner 44 converts the voltage from direct current to alternating current, collectively transforms the voltage with the transformer 45, and connects to the commercial power system 46. In addition, the said structure is a structural example of the mega solar system with many panel numbers especially in a solar cell system. In the case of a residential system with a relatively small number of panels, it is directly connected to the power conditioner 44 from the connection box 42.
 以上のようにして、本実施例5の太陽電池システムを実現することができる。本実施例5の太陽電池システムでは、太陽電池セルの構造による効果を活かして、太陽光発電の高効率化が可能となる。 As described above, the solar cell system of Example 5 can be realized. In the solar cell system of Example 5, it is possible to increase the efficiency of solar power generation by taking advantage of the effect of the solar cell structure.
 以上、本発明者によってなされた発明をその実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
11…結晶Si基板
12…Geバッファ層
13…結晶Ge層
14…結晶Si1-xGe
15…結晶Si層
16…パッシベーション層
21…表面電極
22…裏面電極
31…高濃度ドープ結晶Si層
32…高濃度ドープ結晶Si1-xGe
33…高濃度ドープ結晶Ge層
34…マスク
35…マスク
36…埋め込み酸化膜
41…太陽電池パネル
42…接続箱
43…集電箱
44…パワーコンディショナー
45…変圧器
46…商用電力系統
DESCRIPTION OF SYMBOLS 11 ... Crystal Si substrate 12 ... Ge buffer layer 13 ... Crystal Ge layer 14 ... Crystal Si 1-x Ge x layer 15 ... Crystal Si layer 16 ... Passivation layer 21 ... Surface electrode 22 ... Back electrode 31 ... Highly doped crystal Si layer 32 ... Highly doped crystal Si 1-x Ge x layer 33 ... Highly doped crystal Ge layer 34 ... Mask 35 ... Mask 36 ... Embedded oxide film 41 ... Solar cell panel 42 ... Connection box 43 ... Current collection box 44 ... Power conditioner 45 ... Transformer 46 ... Commercial power system

Claims (15)

  1.  第1極性の結晶Si基板と、
     前記第1極性の結晶Si基板の表面に形成されるGeバッファ層と、
     前記Geバッファ層の表面に形成される結晶Ge層と、
     前記結晶Ge層の表面に形成される第2極性の結晶Si1-xGe層と、
     前記第2極性の結晶Si1-xGe層の表面に形成される第2極性の結晶Si層と、
     前記第2極性の結晶Si層の表面に絶縁材にて形成されるパッシベーション層と、
     前記第2極性の結晶Si層と同一平面内に形成される第2極性の高濃度ドープ結晶Si層と、
     前記第2極性の高濃度ドープ結晶Si層の表面に形成される表面電極と、を有し、
     前記第2極性の高濃度ドープ結晶Si層と前記表面電極との界面における前記第2極性の高濃度ドープ結晶Si層の幅は、前記第2極性の高濃度ドープ結晶Si層と前記第2極性の結晶Si1-xGe層との界面における前記第2極性の高濃度ドープ結晶Si層の幅よりも大きいことを特徴とする太陽電池セル。
    A first polar crystalline Si substrate;
    A Ge buffer layer formed on a surface of the first polar crystalline Si substrate;
    A crystalline Ge layer formed on a surface of the Ge buffer layer;
    A second polar crystalline Si 1-x Ge x layer formed on the surface of the crystalline Ge layer;
    A second polar crystalline Si layer formed on a surface of the second polar crystalline Si 1-x Ge x layer;
    A passivation layer formed of an insulating material on the surface of the second polar crystalline Si layer;
    A second polar highly doped crystalline Si layer formed in the same plane as the second polar crystalline Si layer;
    A surface electrode formed on the surface of the second-polarity heavily doped crystal Si layer,
    The width of the heavily doped crystalline Si layer of the second polarity at the interface between the heavily doped crystalline Si layer of the second polarity and the surface electrode is the same as the width of the heavily doped crystalline Si layer of the second polarity and the second polarity. A solar cell characterized by being larger than the width of the second-polarity heavily doped crystalline Si layer at the interface with the crystalline Si 1-x Ge x layer.
  2.  請求項1において、
     前記第2極性の結晶Si1-xGe層と同一平面内に形成される第2極性の高濃度ドープ結晶Si1-xGe層をさらに有し、
     前記第2極性の高濃度ドープ結晶Si1-xGe層の幅は、前記表面電極の幅よりも小さいことを特徴とする太陽電池セル。
    In claim 1,
    Further comprising a heavily doped crystalline Si 1-x Ge x layer of the second polarity formed on the second polar crystal Si 1-x Ge x layer and in the same plane,
    The solar cell according to claim 1 , wherein a width of the second-polarity highly doped crystal Si 1-x Ge x layer is smaller than a width of the surface electrode.
  3.  請求項1において、
     前記結晶Ge層と同一平面内に形成される第2極性の高濃度ドープ結晶Ge層をさらに有し、
     前記第2極性の高濃度ドープ結晶Ge層の幅は、前記表面電極の幅よりも小さいことを特徴とする太陽電池セル。
    In claim 1,
    A second polarity heavily doped crystalline Ge layer formed in the same plane as the crystalline Ge layer;
    The solar cell according to claim 1, wherein a width of the heavily doped crystal Ge layer having the second polarity is smaller than a width of the surface electrode.
  4.  請求項1において、
     前記第2極性の結晶Si1-xGe層におけるxの値は、0<x≦0.68の範囲内であることを特徴とする太陽電池セル。
    In claim 1,
    The solar cell according to claim 1, wherein a value of x in the second polar crystalline Si 1-x Ge x layer is in a range of 0 <x ≦ 0.68.
  5.  請求項1において、
     前記パッシベーション層は、SiOであることを特徴とする太陽電池セル。
    In claim 1,
    The solar cell, wherein the passivation layer is SiO 2 .
  6.  請求項1において、
     前記第2極性の結晶Si層の膜厚は、7nm以上であることを特徴とする太陽電池セル。
    In claim 1,
    The thickness of the second polar crystalline Si layer is 7 nm or more.
  7.  請求項1において、
     前記第2極性の結晶Si1-xGe層の膜厚は、2μm以下であることを特徴とする太陽電池セル。
    In claim 1,
    The solar cell, wherein the second polar crystalline Si 1-x Ge x layer has a thickness of 2 μm or less.
  8.  請求項1において、
     前記第2極性の高濃度ドープ結晶Si層と前記表面電極との界面における前記第2極性の高濃度ドープ結晶Si層のドーピング濃度は、8×1018cm-3以上、かつ、7×1019cm-3以下であることを特徴とする太陽電池セル。
    In claim 1,
    The doping concentration of the heavily doped crystalline Si layer of the second polarity at the interface between the heavily doped crystalline Si layer of the second polarity and the surface electrode is 8 × 10 18 cm −3 or more and 7 × 10 19. A solar battery cell having a cm −3 or less.
  9.  第1極性の結晶Si基板と、
     前記第1極性の結晶Si基板の表面に形成されるGeバッファ層と、
     前記Geバッファ層の表面に形成される結晶Ge層と、
     前記結晶Ge層の表面に形成される第2極性の結晶Si1-xGe層と、
     前記第2極性の結晶Si1-xGe層の表面に形成される第2極性の結晶Si層と、
     前記第2極性の結晶Si層の表面に絶縁材にて形成されるパッシベーション層と、
     前記パッシベーション層、前記第2極性の結晶Si層、前記第2極性の結晶Si1-xGe層、前記結晶Ge層、前記Geバッファ層、前記第1極性の結晶Si基板のうち、複数の層と接する第2極性の高濃度ドープ層と、
     前記第2極性の高濃度ドープ層の表面に形成される表面電極と、を有する太陽電池セル。
    A first polar crystalline Si substrate;
    A Ge buffer layer formed on a surface of the first polar crystalline Si substrate;
    A crystalline Ge layer formed on a surface of the Ge buffer layer;
    A second polar crystalline Si 1-x Ge x layer formed on the surface of the crystalline Ge layer;
    A second polar crystalline Si layer formed on a surface of the second polar crystalline Si 1-x Ge x layer;
    A passivation layer formed of an insulating material on the surface of the second polar crystalline Si layer;
    Among the passivation layer, the second polar crystalline Si layer, the second polar crystalline Si 1-x Ge x layer, the crystalline Ge layer, the Ge buffer layer, and the first polar crystalline Si substrate. A second heavily doped layer in contact with the layer;
    And a surface electrode formed on a surface of the second heavily doped layer having the second polarity.
  10.  請求項9記載の太陽電池セルにおいて、
     前記第2極性の高濃度ドープ層は、第2極性の高濃度ドープ結晶Si層であることを特徴とする太陽電池セル。
    The solar battery cell according to claim 9, wherein
    The high-concentration doped layer of the second polarity is a high-concentration doped crystalline Si layer of the second polarity.
  11.  請求項9記載の太陽電池セルにおいて、
     前記パッシベーション層と前記表面電極の間に前記第2極性の高濃度ドープ層が形成されることを特徴とする太陽電池セル。
    The solar battery cell according to claim 9, wherein
    The solar cell, wherein the second polarity heavily doped layer is formed between the passivation layer and the surface electrode.
  12.  請求項9記載の太陽電池セルにおいて、
     前記第2極性の高濃度ドープ層のうち、前記第2極性の結晶Si層または前記第1極性の結晶Si基板と接する領域は、第2極性の高濃度ドープ結晶Si層であり、
     前記第2極性の高濃度ドープ層のうち、前記第2極性の結晶Si1-xGe層と接する領域は、第2極性の高濃度ドープ結晶Si1-xGe層であり、
     前記第2極性の高濃度ドープ層のうち、前記結晶Ge層またはGeバッファ層と接する領域は、第2極性の高濃度ドープ結晶Ge層であることを特徴とする太陽電池セル。
    The solar battery cell according to claim 9, wherein
    Of the heavily doped layer of the second polarity, a region in contact with the crystalline Si layer of the second polarity or the crystalline Si substrate of the first polarity is a heavily doped crystalline Si layer of the second polarity,
    A region of the second polarity heavily doped layer that is in contact with the second polarity crystalline Si 1-x Ge x layer is a second polarity heavily doped crystalline Si 1-x Ge x layer,
    The solar cell, wherein a region in contact with the crystalline Ge layer or the Ge buffer layer in the second polarity highly doped layer is a second polarity highly doped crystalline Ge layer.
  13.  請求項9記載の太陽電池セルにおいて、
     前記第2極性の高濃度ドープ層は、前記第1極性の結晶Si基板と接することを特徴とする太陽電池セル。
    The solar battery cell according to claim 9, wherein
    The high-concentration doped layer of the second polarity is in contact with the crystalline Si substrate of the first polarity.
  14.  第1極性の結晶Si基板と、
     前記第1極性の結晶Si基板の表面に形成される絶縁膜と、
     前記絶縁膜の表面に形成される結晶Ge層と、
     前記結晶Ge層の表面に形成される第2極性の結晶Si1-xGe層と、
     前記第2極性の結晶Si1-xGe層の表面に形成される第2極性の結晶Si層と、
     前記第2極性の結晶Si層の表面に絶縁材にて形成されるパッシベーション層と、
     前記第2極性の結晶Si層の表面に形成される表面電極と、を有し、
     前記第2極性の結晶Si層は、第1極性の結晶Si基板および前記結晶Ge層と接することを特徴とする太陽電池セル。
    A first polar crystalline Si substrate;
    An insulating film formed on the surface of the first polar crystalline Si substrate;
    A crystalline Ge layer formed on the surface of the insulating film;
    A second polar crystalline Si 1-x Ge x layer formed on the surface of the crystalline Ge layer;
    A second polar crystalline Si layer formed on a surface of the second polar crystalline Si 1-x Ge x layer;
    A passivation layer formed of an insulating material on the surface of the second polar crystalline Si layer;
    A surface electrode formed on the surface of the second polar crystalline Si layer,
    The solar cell, wherein the second polar crystalline Si layer is in contact with the first polar crystalline Si substrate and the crystalline Ge layer.
  15.  請求項14記載の太陽電池セルにおいて、
     前記結晶Ge層は、前記第2極性の結晶Si層を介して第1極性の結晶Si基板と電気的に接続されることを特徴とする太陽電池セル。
    The solar battery cell according to claim 14, wherein
    The solar cell, wherein the crystalline Ge layer is electrically connected to a crystalline Si substrate having a first polarity via the crystalline Si layer having a second polarity.
PCT/JP2014/079521 2014-11-07 2014-11-07 Solar cell WO2016072005A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2014/079521 WO2016072005A1 (en) 2014-11-07 2014-11-07 Solar cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2014/079521 WO2016072005A1 (en) 2014-11-07 2014-11-07 Solar cell

Publications (1)

Publication Number Publication Date
WO2016072005A1 true WO2016072005A1 (en) 2016-05-12

Family

ID=55908757

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/079521 WO2016072005A1 (en) 2014-11-07 2014-11-07 Solar cell

Country Status (1)

Country Link
WO (1) WO2016072005A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006073833A (en) * 2004-09-02 2006-03-16 Sharp Corp Solar battery cell and method of manufacturing the same
WO2010075606A1 (en) * 2008-12-29 2010-07-08 Shaun Joseph Cunningham Improved photo-voltaic device
WO2010094919A2 (en) * 2009-02-19 2010-08-26 Iqe Silicon Compounds Limited Photovoltaic cell
WO2011012382A2 (en) * 2009-07-31 2011-02-03 International Business Machines Corporation Silicon wafer based structure for heterostructure solar cells
US20110120538A1 (en) * 2009-10-23 2011-05-26 Amberwave, Inc. Silicon germanium solar cell

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006073833A (en) * 2004-09-02 2006-03-16 Sharp Corp Solar battery cell and method of manufacturing the same
WO2010075606A1 (en) * 2008-12-29 2010-07-08 Shaun Joseph Cunningham Improved photo-voltaic device
WO2010094919A2 (en) * 2009-02-19 2010-08-26 Iqe Silicon Compounds Limited Photovoltaic cell
WO2011012382A2 (en) * 2009-07-31 2011-02-03 International Business Machines Corporation Silicon wafer based structure for heterostructure solar cells
US20110120538A1 (en) * 2009-10-23 2011-05-26 Amberwave, Inc. Silicon germanium solar cell

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
J.WEBER: "Near-band-gap photoluminescence of Si-Ge alloys", PHYSICAL REVIEW B, vol. 40, no. 8, 1989, pages 5683 - 5693 *
M.WOLF: "Solar cell efficiency and carrier multiplication in Sil-xGex alloys", JOURNAL OF APPLIED PHYSICS, vol. 83, no. 8, 1998, pages 4213 - 4221, XP012045017, DOI: doi:10.1063/1.367177 *
R.OSHIMA: "Fabrication of 0.9 eV bandgap a- Si/c-Sil-xGex heterojunction solar cells", IEEE 40TH PHOTOVOLTAIC SPECIALIST CONFERENCE, 2014, pages 0202 - 0205 *

Similar Documents

Publication Publication Date Title
JP6746854B2 (en) Solar cell having emitter region containing wide bandgap semiconductor material
KR101991791B1 (en) Hybrid polysilicon heterojunction back contact cell
US20150007879A1 (en) Solar cell and method for manufacturing the same
JP2005310830A (en) Solar cell and manufacturing method thereof
JP6410362B2 (en) Photoactive device having a low bandgap active layer configured to improve efficiency and related methods
KR20100138565A (en) Sollar cell and fabrication method thereof
JP2024511224A (en) Selective contact area embedded solar cell and its backside contact structure
KR20120110728A (en) Solar cell and method for manufacturing the same
EP2731146B1 (en) Photoelectric device and the manufacturing method thereof
JP2009206375A (en) Solar cell and method of manufacturing the same
JP6053764B2 (en) Method for producing photovoltaic cell with selective emitter
JP6336517B2 (en) Solar cell and manufacturing method thereof
US10141467B2 (en) Solar cell and method for manufacturing the same
JP2007019259A (en) Solar cell and its manufacturing method
KR101024322B1 (en) Method of manufacturing wafer for solar cell, a wafer for solar cell manufactured by the method and method of manufacturing solar cell using the wafer
JP5917129B2 (en) Electrode manufacturing method and photoelectric conversion device manufacturing method
KR101198438B1 (en) Bifacial Photovoltaic Localized Emitter Solar Cell and Method for Manufacturing Thereof
WO2016072005A1 (en) Solar cell
JP2018170482A (en) Solar battery cell, and method for manufacturing solar battery cell
KR101181625B1 (en) Localized Emitter Solar Cell and Method for Manufacturing Thereof
KR20090019600A (en) High-efficiency solar cell and manufacturing method thereof
JP2016039246A (en) Photoelectric conversion element
KR101199649B1 (en) Localized Emitter Solar Cell and Method for Manufacturing Thereof
WO2015186167A1 (en) Solar cell, solar cell manufacturing method, and solar cell system
JP2017157781A (en) Photoelectric conversion element and method for manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14905660

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14905660

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP