WO2016070669A1 - 一种数据转换方法、装置及存储介质 - Google Patents

一种数据转换方法、装置及存储介质 Download PDF

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WO2016070669A1
WO2016070669A1 PCT/CN2015/087558 CN2015087558W WO2016070669A1 WO 2016070669 A1 WO2016070669 A1 WO 2016070669A1 CN 2015087558 W CN2015087558 W CN 2015087558W WO 2016070669 A1 WO2016070669 A1 WO 2016070669A1
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data
storage
read
write
module array
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PCT/CN2015/087558
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English (en)
French (fr)
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刘飞
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中兴通讯股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor

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  • the present invention relates to data processing technologies, and in particular, to a data conversion method, apparatus, and storage medium.
  • the Optical Transport Network is a transport network that organizes networks in the optical layer based on WDM technology.
  • OTN needs to carry 100 Gigabit Eehernet (GE) services. Data, therefore, the encapsulation mapping of the 100GE service to the OTN service is required.
  • the GE service is characterized by variable packet length and variable traffic.
  • the OTN service is characterized by a fixed rate. Therefore, the Ethernet packet is encapsulated into the OTN service.
  • the GE service needs to be adapted to a fixed ONT rate by the Frame Mapped Generic Framing Procedure (GFP); wherein the GFP data is in a time division format, that is, the data is transmitted by channel; any rate optical channel data unit (Optical Channel Transport) Unit Flex, ODU flex)
  • GFP Frame Mapped Generic Framing Procedure
  • F6 F6 F6 28 28 28 is the frame header
  • MFAS is the multiframe number
  • FF is the overhead part
  • D is the data
  • ODUflex data is the space division format
  • ie Data is transmitted in time slots, and each byte of one beat data input per channel can be mapped to any one of the time slots.
  • each channel can occupy 80 Any one or more of the time slots; calculating a mapping rule according to the correspondence between the channel number and the time slot, and converting the time division format data into the space division format data according to the calculated mapping rule; wherein the format conversion GFP data is performed For the fixed rate Ethernet packet after processing, that is, the GFP bandwidth is fixed, the number of channels is limited, and the GFP data is framed and then mapped to the fixed time slot OTN service, resulting in limited flexibility of data services; When calculating the mapping rules, it takes up a lot of chip resources and increases the cost of converting time-division format data into space-division format data.
  • the embodiments of the present invention are directed to providing a data conversion method, apparatus, and storage medium, which can reduce the cost of data conversion and improve the flexibility of data services while converting time-division format data into space-division format data.
  • An embodiment of the present invention provides a data conversion method.
  • the method includes: when inputting data according to a first transmission mode, constructing a write strategy according to parameters of the input data, and writing the input data to the storage module array according to the write policy.
  • the storage module array constructs a read strategy according to the parameters of the input data, and outputs and encapsulates the data in the storage module array according to the read strategy according to the second transmission manner.
  • the method further includes: sending an idle request signal according to the traffic size of the output data of the storage module array, where the idle request signal is used to notify the first transmission mode. The time to insert an idle frame when entering data.
  • the constructing the write strategy according to the parameter of the input data comprises: calculating a write period according to the number of slots occupied by each channel and the bit width of the input data according to the input data, and according to the write period and each channel
  • the counting result of the counter constructs a write strategy; wherein the write strategy comprises: sequentially inputting the input data into the storage unit having the storage identifier in the storage module array according to the input cycle, and the position difference between the storage units of the storage data is writing A storage unit that is an integer multiple of the cycle has the same storage identifier.
  • the constructing the read strategy according to the parameters of the input data includes: calculating a read period of each channel according to the number of slots occupied by each channel and the bit width of the input data when the data is input, and constructing according to the read period a read strategy, wherein the read strategy includes: sequentially outputting data in the storage module array in each time slot according to the order of the storage unit identification; each time slot The number of memory cells occupied by the data in the array of output memory modules is the value of the read cycle.
  • the number of rows of the storage module array is the number of slots of the storage module array output data frame
  • the number of columns of the storage module array is the bit width of the input data frame
  • the embodiment of the present invention further provides a data conversion device, where the device includes: a first framing module, a read/write control module, a storage module array, and a second framing module;
  • the first framing module is configured to input data according to the first transmission mode, and write data that is input by the first input mode according to the write policy into the storage module array;
  • the read/write control module is configured to construct a write policy according to the parameter of the input data, and trigger the first framing module to write the input data into the storage module array according to the write policy; according to the input data
  • the parameter constructs a read strategy, and triggers the storage module array to output data in the storage module array according to the read strategy according to the second transmission manner;
  • the storage module array is configured to store data input by the first framing module, and output data stored by itself according to the read strategy according to the second transmission mode;
  • the second framing module is configured to encapsulate data output by the storage module array.
  • the second framing module is further configured to send an idle request signal according to the traffic size of the output data of the storage module array
  • the first framing module is further configured to insert an idle frame according to the idle request signal.
  • the read/write control module is specifically configured to calculate a write period according to the number of slots occupied by each channel and the bit width of the input data according to the input data, and according to the write period and the counter of each channel.
  • the result is a write strategy
  • the writing strategy includes: sequentially inputting the input data into the storage unit having the storage identifier in the storage module array according to the input cycle, and the storage unit having the position difference between the storage units of the storage data having the integer multiple of the write cycle has the same storage.
  • logo
  • the read/write control module is specifically configured to each pass according to the input data. Calculating the read cycle of each channel by calculating the number of time slots occupied by the track and the bit width of the input data, and constructing a read strategy according to the read cycle;
  • the read strategy includes: sequentially outputting data in the storage module array in each time slot according to the order of the storage unit identification; and the number of storage units occupied by data in the storage module array outputted in each time slot The value of the read cycle.
  • the number of rows of the storage module array is the number of slots of the storage module output data frame
  • the number of columns of the storage module array is the bit width of the input data frame
  • the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores a computer program for executing the data conversion method of the embodiment of the present invention.
  • the data conversion method, device and storage medium when inputting data according to the first transmission mode, construct a write strategy according to parameters of the input data, and write the input data into the storage module array according to the write strategy; When the storage module reaches the output threshold, the storage module constructs a read policy according to the parameters of the input data, and outputs and encapsulates the data in the storage module array according to the read strategy according to the second transmission manner.
  • MCU Micro Control Unit
  • FIG. 2 is a schematic diagram of a basic processing flow of a data conversion method according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a memory module array
  • FIG. 4 is a schematic flowchart of detailed processing of a data conversion method according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a data storage structure of a RAM according to an embodiment of the present invention.
  • FIG. 6 is a schematic flowchart of detailed processing of a data conversion method according to Embodiment 2 of the present invention.
  • FIG. 7 is a schematic diagram of a data storage structure of a RAM according to Embodiment 2 of the present invention.
  • FIG. 8 is a schematic flowchart of detailed processing of a data conversion method according to Embodiment 3 of the present invention.
  • FIG. 9 is a schematic diagram of a data storage structure of a RAM according to Embodiment 3 of the present invention.
  • FIG. 10 is a schematic structural diagram of a structure of a data conversion apparatus according to an embodiment of the present invention.
  • a write strategy is constructed according to parameters of the input data, and the input data is written into the storage module array according to the write strategy; and the storage capacity of the storage module array is reached.
  • a read strategy is constructed according to the parameters of the input data, and the data in the storage module array is output and encapsulated according to the read strategy according to the second transmission manner.
  • the basic processing flow of the data conversion method in the embodiment of the present invention, as shown in FIG. 2, includes the following steps:
  • Step 101 When inputting data according to the first transmission mode, construct a write strategy according to parameters of the input data, and write the input data into the storage module array according to the write strategy;
  • the first framing module inputs data according to the first transmission mode; the read/write control module calculates a write period according to the number of slots occupied by each channel and the bit width of the input data when inputting data, and configures one channel counter for each channel.
  • the method for counting the channel is the first input data; after constructing the write strategy according to the statistics of the write cycle and the counter, triggering the first framing module to write the input data to the storage module array according to the write strategy;
  • the first framing module writes the data input by the first input mode into the storage module array according to the write strategy;
  • the first transmission mode may be a channel-by-channel transmission mode, and the first framing module may perform data write control in a very multiplexed manner;
  • g_SlotNumber indicates the number of slots occupied by each channel when inputting data, W indicates the bit width of the input data, and k is W and The maximum common divisor of g_SlotNumber;
  • the minimum write period is 1, and the maximum write period is determined by the number of slots divided by the second framing module;
  • the write strategy includes: writing the input data to the storage module array in order according to the input period
  • the storage unit storing the identifier, the storage unit with the difference of the storage unit between the storage units of the storage data having the integer multiple of the write period has the same storage identifier; when there are multiple channels for transmitting data, because the number of slots occupied by different channels is different,
  • the storage module array may be a random access memory (RAM) array, a schematic structural diagram of the storage module array, as shown in FIG. 3, the storage module array is composed of a plurality of storage units. Each storage unit is 8 bits wide, and the number of rows of the storage module array is the number of slots of the output data frame of the storage module array, and the number of columns of the storage module array is the bit width of the input data frame, and the data of each beat is Just stored in N 8-bit wide memory cells, each row of memory cells are in one-to-one correspondence with X time slots.
  • RAM random access memory
  • Step 102 When the storage capacity reaches the output threshold, the storage module array constructs a read policy according to the parameter of the input data, and outputs and encapsulates the data in the storage module array according to the read policy according to the second transmission manner;
  • the read/write control module calculates the read period of each channel according to the number of slots occupied by each channel and the bit width of the input data when inputting data, according to The read cycle constructs a read policy, and triggers the storage module array to output data in the storage module array according to the read policy according to the second transmission manner; the storage module array outputs itself according to the read strategy according to the second transmission mode.
  • Stored data; the second framing module encapsulates data output by the storage module array;
  • the second transmission mode may be a time slot transmission mode;
  • the number of time slots occupied by each channel, k is the greatest common divisor of W and g_SlotNumber;
  • the read strategy includes: according to the storage unit The sequence of identification sequentially outputs data in the array of storage modules in each time slot; the number of storage units occupied by data in the array of memory modules outputted by each time slot is a value of a read cycle; In the case of data, since the number of slots occupied by different channels is different, the read cycles of different channels are also different.
  • the first framing module when the first transmission mode is a channel-by-channel transmission mode, the first framing module is a GFP framing module, and the input data rate is dynamically changed; when the second transmission mode is a time slot transmission mode, The second framing module is an ODUflex framing module, and the output data rate is constant; the second framing module divides the second framing module 14 into X time slots to ensure continuous data stream input.
  • the second framing module can send an idle request signal to the first framing module according to the data traffic size output by the storage module array every X times per slot, the idle request signal is used to notify the first framing module to insert
  • the data service uses one channel for transmission, the channel is mapped to time slot 0-2, the input data bit width is 320 bits, the first framing module is a GFP framing module, the second framing module is an ODUflex framing module, and the ODUflex framing module
  • the detailed processing flow of the data conversion method in the first embodiment of the present invention includes the following steps:
  • Step 201 The read/write control module calculates a first write period according to the number of slots occupied by each channel and the bit width of the input data when the data is input, and constructs a first write strategy according to the first write period;
  • the first write strategy is: storing the 320-bit data of the first cycle into the black-identified storage unit of the first row and the first column of the storage module array, and storing the 320-bit data of the second cycle to the storage module array.
  • Row 3 of the backslash identified in the storage unit will be the third cycle
  • the 320-bit data is stored in the storage unit of the first row and the second column of the storage module array
  • the 320-bit data of the fourth cycle is stored in the black-marked storage unit of the first row and the fourth column of the storage module array.
  • the five-cycle 320-bit data is stored in the storage unit identified by the back-slash of the first row and the sixth column of the storage module array, and the 320-bit data of the sixth cycle is stored to the storage of the circular array of the first row and the fifth column of the storage module array. In the unit, and so on; that is, stored in a three-shot cycle.
  • Step 202 When the GFP framing module inputs data by the channel, the RAM array writes the data into the RAM array according to the first write strategy.
  • FIG. 5 a schematic diagram of a data storage structure of a RAM in the embodiment of the present invention is shown in FIG. 5.
  • Step 203 when the storage capacity of the RAM reaches half of its total capacity, the read/write control module calculates the first read period of each channel according to the number of slots occupied by each channel and the bit width of the input data according to the input data, according to the first a read cycle to build a read strategy;
  • the first read strategy is: the read address sequence of the time slot 0 in the memory module array is the first row of the RAM array, 1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36, 39, 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38 columns; the read address sequence of slot 1 in the memory module array is the second row of the RAM array, 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 1 , 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36 39 columns; the reading order of slot 2 is the third row of the RAM array, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36, 39, 2, 5, 8, 11 14, 14, 17, 20, 23, 26, 29, 32, 35, 38, 1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40 columns.
  • Step 204 The RAM array outputs the data to the ODUflex framing mode according to the first read strategy.
  • an idle request counter is set in the read/write control module, counting from 0-80. After receiving the idle request signal from the ODUflex framing module, the read/write control module counts 1-3 after the counter Sending an idle request signal to the GFP framing module, informing the GFP framing module to insert the idle frame, and ensuring that there is a continuous stream input; wherein the counters 1-3 are data corresponding to one channel in the first embodiment of the present invention and mapped to the time slot 0. -2.
  • the data service uses one channel for transmission, the channel is mapped to time slot 0-79, the input data bit width is 320 bits, the first framing module is GFP framing module, the second framing module is ODUflex framing module, ODUflex framing module.
  • the detailed processing flow of the data conversion method in the second embodiment of the present invention, as shown in FIG. 6, includes the following steps:
  • Step 301 The read/write control module calculates a second write period according to the number of slots occupied by each channel and the bit width of the input data when the data is input, and constructs a second write strategy according to the second write period.
  • g_SlotNumber 2 80
  • k 2 is the greatest common divisor of W and g_SlotNumber 2 40
  • the second write strategy is: storing the 320-bit data of the first cycle into the black-identified storage unit of the storage module array, and storing the 320-bit data of the second cycle to the storage unit of the back-slash identification of the storage module array.
  • the 320-bit data of the third period is stored in the black-marked storage unit of the storage module array
  • the 320-bit data of the fourth period is stored in the storage unit of the back-slash identifier of the storage module array, and so on; That is, the storage is performed in a two-shot cycle.
  • Step 302 when the GFP framing module inputs data according to the channel, the RAM array writes the data into the RAM array according to a second write strategy;
  • FIG. 7 a schematic diagram of a data storage structure of the RAM of the second embodiment of the present invention is shown in FIG. 7.
  • Step 303 when the storage capacity of the RAM reaches half of its total capacity, the read/write control mode
  • the block calculates a second read period of each channel according to the number of slots occupied by each channel and the bit width of the input data according to the input data, and constructs a read strategy according to the second read period;
  • g_SlotNumber 2 80
  • k 2 is the greatest common divisor 40 of W and g_SlotNumber 2
  • the second read strategy is: slot 0 in the storage module array read address is the first row and first column, slot 1 in the storage module array read address is the second row and second column, slot 2 in the storage module array
  • the read address is the third row and the third column.
  • the read address of the time slot 39 in the memory module array is the 40th row and the 40th column, and the read address of the time slot 40 in the memory module array is the 41st row and the 1st column.
  • 41 The read address of the memory module array is the 42nd row and the 2nd column...
  • the read address of the time slot 79 in the memory module array is the 80th row and the 40th column.
  • Step 304 The RAM array outputs the data to an ODUflex framing module according to a first read policy; the ODUflex framing module encapsulates the data into data frames.
  • an idle request counter is set in the read/write control module, counting from 0-80. After receiving the idle request signal from the ODUflex framing module, the read/write control module is at the counter count value of 1-80.
  • the GFP framing module sends an idle request signal to notify the GFP framing module to insert the idle frame to ensure that there is a continuous stream input.
  • the counter count 1-80 is a data corresponding to a channel in the second embodiment of the present invention. 0-79.
  • the data service uses two channels for transmission, the first channel is mapped to time slots 0-5, the second channel is mapped to time slots 8, 9, and 11, the input data bit width is 320 bits, and the first framing module is a GFP framing module.
  • the second framing module is an ODUflex framing module, and the ODUflex framing module is divided into 80 time slots as an example.
  • Step 401 The read/write control module calculates a third write period and a fourth write period according to the number of slots occupied by each channel and the bit width of the input data according to the input data, according to the third write period and the fourth write
  • the third write strategy and the fourth write strategy are respectively constructed in the cycle
  • g_SlotNumber 3 6, so k 3 is the greatest common divisor of W and g_SlotNumber 3
  • g_SlotNumber 4 3
  • k 4 is the greatest common divisor of W and g_SlotNumber 4
  • the third write strategy is: for the first channel, the 320-bit data of the first cycle is stored in the black-identified storage unit of the first row and the first column of the storage module array, and the 320-bit data of the second cycle is stored to In the storage unit identified by the first row and the third column backslash of the storage module array, the 320-bit data of the third period is stored in the storage unit of the first row and the fifth column of the storage module array, and the fourth period is The 320-bit data is stored in the black-marked storage unit of the first row and the seventh column of the storage module array, and so on; that is, stored in three beats and one cycle; for the second channel, the 320-bit data in the first cycle is stored to In the black-marked storage unit of the ninth row and the first column of the storage module array, the 320-bit data of the second cycle is stored in the storage unit of the ninth row and the third column of the storage module array, and the third cycle is performed.
  • the 320-bit data is stored in the storage unit of the ninth row and the second column of the storage module array, and the 320-bit data of the fourth cycle is stored to the black of the ninth row and the fourth column of the storage module array.
  • Step 402 When the GFP framing module inputs data by the channel, the RAM array writes the data into the RAM array according to the third write strategy and the fourth write strategy.
  • FIG. 9 a schematic diagram of a data storage structure of the RAM of the third embodiment of the present invention is shown in FIG. 9.
  • Step 403 when the storage capacity of the RAM reaches half of its total capacity, the read/write control module calculates the third read period and the second of the first channel according to the number of slots occupied by each channel and the bit width of the input data when the data is input.
  • a fourth read cycle of the channel the read strategy is constructed according to the third read cycle and the fourth read cycle;
  • the third read strategy is: the read address sequence of the time slot 0 in the memory module array is the first row of the RAM array, 1, 7, 13, 19, 25, 31, 37, 3, 9, 15, 21, 27, 33, 39, 5, 11, 17, 23, 29, 35 columns; the read address sequence of slot 1 in the memory module array is the second row of the RAM array, 2, 8, 14, 20, 26, 32, 38, 4, 10 , 16, 22, 28, 34, 40, 6, 12, 18, 24, 30, 36 columns; the read address sequence of the time slot 2 in the memory module array is the third row, the third, the third, the third, the fifth, the 27, 33, 39, 5, 11, 17, 23, 29, 35, 1, 7, 13, 19, 25, 31, 37 columns; slot 3 in the memory module array read address sequence is the fourth row of the RAM array Columns 4, 10, 16, 22, 28, 40, 6, 12, 18, 24, 30, 36, 2, 8, 14, 20, 26, 32, 38; slot 4 in the read address of the memory module array The order is 5th row, 5th, 11th, 17th, 23rd, 29th, 35th, 41st, 13, 13, 19, 25, 31, 37, 3, 9, 15, 21, 27, 33
  • the fourth read strategy is: the read address sequence of the time slot 8 in the memory module array is the 9th row of the RAM array, 1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36, 39, 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38 columns; the read address sequence of the slot 9 in the memory module array is the 10th row of the RAM array, 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 1 , 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36 39 columns; the read address sequence of the time slot 11 in the memory module array is the 12th row of the RAM array, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36, 39, 2. 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40 columns.
  • Step 404 The RAM array outputs the data to the ODUflex framing module according to the third read policy and the fourth read policy; the ODUflex framing module encapsulates the data into data frames.
  • an idle request counter is set in the read/write control module, counting from 0-80.
  • the first channel is counted in the counter by the read/write control module.
  • the GFP framing module sends an idle request signal to inform the GFP framing module to insert the idle frame to ensure continuous stream input; the second channel framing the GFP after the counter counts 9, 10, and 12 in the read/write control module.
  • the module sends an idle request signal, wherein the counter count 1-6 is corresponding to the data of the first channel in the third embodiment of the present invention mapped to the time slot 0-5, and the counter counts 9, 10, 12 are corresponding to the third embodiment of the present invention.
  • the data of the second channel is mapped to time slots 8, 9, and 11.
  • the embodiment of the present invention can be used to map multi-channel GFP frame data of any bandwidth to OUDflex frame data of any rate, and realize any pairing of channel input data and time slot input, thereby increasing service flexibility.
  • each channel is divided into a storage space for storing data mapping rules, and the data mapping rules are updated according to service requirements, so that each channel is completely independent and does not interfere with each other.
  • the embodiment of the present invention further provides a data conversion device.
  • the composition of the device is as shown in FIG. 10, and includes: a first framing module 11, a read/write control module 12, and a storage module array 13. And a second framing module 14; wherein
  • the first framing module 11 is configured to input data according to the first transmission mode, and write the data input by the first input mode according to the write strategy into the storage module array 12;
  • the read/write control module 12 is configured to construct a write policy according to the parameters of the input data, and trigger the first framing module 11 to write the input data into the storage module array 13 according to the write policy;
  • the parameter of the input data constructs a read strategy, and triggers the storage module array 13 to output the data in the storage module array 13 according to the read strategy according to the second transmission manner;
  • the storage module array 13 is configured to store data input by the first framing module 11 and output data stored by itself according to the read strategy according to the second transmission mode;
  • the second framing module 14 is configured to encapsulate data output by the storage module array 13.
  • the second framing module 14 is further configured to send an idle request signal according to the traffic size of the output data of the storage module array;
  • the first framing module 11 is further configured to insert an idle frame according to the idle request signal.
  • the read/write control module 12 is configured to calculate a write period according to the number of slots occupied by each channel and the bit width of the input data according to the input data, and construct a write according to the write period and the count result of the counter in each channel. Strategy; among them,
  • the write strategy includes: sequentially inputting the input data into the storage unit having the storage identifier in the storage module array 13 according to the input cycle, and the storage unit having the position difference between the storage units of the storage data having the integer multiple of the write cycle has the same Store the ID.
  • the read/write control module 12 is configured to calculate a read period of each channel according to the number of slots occupied by each channel and the bit width of the input data when the data is input, and construct a read strategy according to the read period;
  • the read strategy includes: sequentially outputting data in the storage module array 13 in each time slot according to the order of the storage unit identification; and storing the storage unit occupied by the data in the storage module array 13 outputted in each time slot
  • the number is the value of the read cycle.
  • the number of rows of the storage module array 13 is the number of slots of the storage module output data frame, and the number of columns of the storage module array is the bit width of the input data frame.
  • the first framing module 11 inputs data according to the first transmission mode; the read/write control module 12 calculates the write period according to the number of slots occupied by each channel and the bit width of the input data when inputting data, for each channel. Configuring a channel counter for counting the input data of the channel for the first time; after constructing the write strategy according to the statistics of the write cycle and the counter, triggering the first framing module 11 to write the input data according to the write strategy Into the storage module array 13; the first framing module 11 according to the write strategy to write its own input data in the first input mode to the memory module array 13;
  • the first transmission mode may be a channel-by-channel transmission mode, and the first framing module 11 may perform data write control in a very multiplexed manner
  • the storage module array 13 is composed of a plurality of storage units, each storage unit is 8 bits wide, and the number of rows of the storage module array is the number of slots of the storage module array output data frame, and the storage is performed.
  • the number of columns of the module array is the bit width of the input data frame, and each beat data is just stored in N 8-bit wide storage units, and each row of storage units is in one-to-one correspondence with X time slots.
  • the read/write control module 12 calculates each channel according to the number of slots occupied by each channel and the bit width of the input data when inputting data.
  • a read cycle a read policy is constructed according to the read cycle, and the memory module array 13 is triggered to output data in the memory module array 13 according to the read strategy according to the read strategy; the memory module array 13 is configured according to the read strategy.
  • Outputting the data stored by itself according to the second transmission mode; the second framing module encapsulates the data output by the storage module array 13;
  • the second transmission mode may be a time slot transmission mode
  • W represents the bit width of the input data
  • g_SlotNumber represents the number of slots occupied by each channel when inputting data
  • k is the greatest common divisor of W and g_SlotNumber
  • the read strategy includes: in each order according to the order of the storage unit identification The slots sequentially output data in the memory module array 13; the number of memory cells occupied by data in the memory module array 13 outputted by each time slot is a value of a read cycle; when there are multiple channels for transmitting data, due to different The number of slots occupied by the channel is different, so the read cycles of different channels are also different.
  • the first transmission mode is a per-channel transmission mode
  • the first framing module 11 is a GFP framing module
  • the input data rate is dynamically changed
  • the second transmission mode is transmission by time slot.
  • the second framing module 14 is an ODUflex framing module, and the output data rate is constant; the second framing module 14 divides the second framing module 14 to ensure continuous data stream input.
  • the second framing module 14 can send an idle request signal to the first framing module 11 according to the data traffic size output by the memory module array 13 every X times per time slot, and the idle request signal is used for the idle request signal.
  • the time when the first framing module 11 is inserted into the idle frame is notified to avoid the collision of the idle request signal sent by each channel; the number of times the idle request is sent per X beat of each channel is determined by the number of slots occupied by the channel.
  • the storage module array 13 in the data conversion device provided in the embodiment of the present invention may be implemented by a storage device, such as a hard disk; the first framing module 11, the read/write control module 12, and the second framing module 14 may all be processed.
  • the device can be implemented, of course, by a specific logic circuit; in practical applications, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP) or a field programmable gate array. (FPGA), etc.
  • the above data conversion method is implemented in the form of a software function module and sold or used as a stand-alone product, it may also be stored in a computer readable storage medium.
  • the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product stored in a storage medium, including a plurality of instructions.
  • Make a computer device (can be a A person computer, server, or network device, etc.) performs all or part of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk.
  • program codes such as a USB flash drive, a mobile hard disk, a read only memory (ROM), a magnetic disk, or an optical disk.
  • the embodiment of the present invention further provides a computer storage medium, where the computer storage medium stores a computer program, and the computer program is used to execute the data conversion method of the embodiment of the present invention.

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Abstract

本发明公开了一种数据转换方法，包括：按第一传输方式输入数据时，根据输入数据的参数构建写策略，依据所述写策略将所述输入数据写入存储模块阵列；所述存储模块阵列在存储容量达到输出阈值时，根据输入数据的参数构建读策略，依据所述读策略按第二传输方式将所述存储模块阵列内的数据输出并封装。本发明还同时公开了一种数据转换装置及存储介质。

Description

一种数据转换方法、装置及存储介质 技术领域
本发明涉及数据处理技术，尤其涉及一种数据转换方法、装置及存储介质。
背景技术
光传送网(Optical Transport Network，OTN)是以波分复用技术为基础，在光层组织网络的传送网；在100G网络时代，OTN需要承载100吉比特以太网(Gigabit Eehernet，GE)的业务数据，因此，需要进行100GE业务到OTN业务的封装映射；GE业务的特点是包长可变、流量可变，OTN业务的特点是速率固定，故将以太网包封装到OTN业务的过程中，需通过通用成帧规程(Frame Mapped Generic Framing Procedure，GFP)将GE业务适配到固定的ONT速率；其中，GFP数据为时分格式，即数据按通道发送；任意速率光通道数据单元(Optical Channel Transport Unit Flex，ODU flex)数据的结构示意图，如图1所示，F6 F6 F6 28 28 28为帧头，MFAS为复帧编号，FF为开销部分，D为数据；ODUflex数据为空分格式，即数据按时隙发送，每个通道输入的一拍数据的每个字节可以映射到任意一个时隙。
目前，将时分格式数据转换为空分格式数据时，需要知道各个通道与时隙的对应关系；例如，100G OTN包括80个时隙，GFP数据帧包含多个通道，每个通道可以占用80个时隙中的任意一个或多个；根据通道号与时隙的对应关系来计算映射规则，再根据计算得到的映射规则将时分格式数据转换为空分格式数据；其中，进行格式转换的GFP数据为经过处理后的固定速率的以太网包，即GFP带宽固定，通道数受限制，GFP数据成帧后再映射到固定时隙的OTN业务中，导致数据业务的灵活性受限；并且，在 计算映射规则时，占用了大量的芯片资源，增加了时分格式数据向空分格式数据转换的成本。
发明内容
有鉴于此，本发明实施例期望提供一种数据转换方法、装置及存储介质，在实现时分格式数据转换为空分格式数据的同时，能够降低数据转换的成本，提高数据业务的灵活性。
本发明实施例的技术方案是这样实现的：
本发明实施例提供了一种数据转换方法，所述方法包括：按第一传输方式输入数据时，根据输入数据的参数构建写策略，依据所述写策略将所述输入数据写入存储模块阵列；所述存储模块阵列在存储容量达到输出阈值时，根据输入数据的参数构建读策略，依据所述读策略按第二传输方式将所述存储模块阵列内的数据输出并封装。
上述方案中，所述按第一输入方式输入数据后，所述方法还包括：根据所述存储模块阵列输出数据的流量大小发送空闲请求信号，所述空闲请求信号用于通知按第一传输方式输入数据时，插入空闲帧的时间。
上述方案中，所述根据输入数据的参数构建写策略，包括：根据输入数据时每个通道占用的时隙数和输入数据的位宽计算写周期，并依据所述写周期和每个通道内计数器的计数结果构建写策略；其中，所述写策略包括：将输入的数据按输入周期依次写入存储模块阵列中具有存储标识的存储单元，所述存储数据的存储单元间的位置差为写周期整数倍的存储单元具有相同的存储标识。
上述方案中，所述根据输入数据的参数构建读策略，包括：根据输入数据时每个通道占用的时隙数和输入数据的位宽计算每个通道的读周期，并依据所述读周期构建读策略；其中，所述读策略包括：按照所述存储单元标识的顺序在每个时隙依次输出所述存储模块阵列内的数据；每个时隙 输出的所述存储模块阵列内的数据占用的存储单元的数量为读周期的值。
上述方案中，所述存储模块阵列的行数为存储模块阵列输出数据帧的时隙数，所述存储模块阵列的列数为输入数据帧的位宽。
本发明实施例还提供一种数据转换装置，所述装置包括：第一成帧模块、读写控制模块、存储模块阵列和第二成帧模块；其中，
所述第一成帧模块，配置为根据第一传输方式输入数据，根据写策略将自身按第一输入方式输入的数据写入存储模块阵列；
所述读写控制模块，配置为根据所述输入数据的参数构建写策略，并触发所述第一成帧模块依据所述写策略将所述输入数据写入存储模块阵列；根据所述输入数据的参数构建读策略，并触发所述存储模块阵列依据所述读策略按第二传输方式输出所述存储模块阵列内的数据；
所述存储模块阵列，配置为存储所述第一成帧模块输入的数据，依据所述读策略按第二传输方式输出自身存储的数据；
所述第二成帧模块，配置为封装所述存储模块阵列输出的数据。
上述方案中，所述第二成帧模块，还配置为根据存储模块阵列输出数据的流量大小发送空闲请求信号；
相应的，所述第一成帧模块，还配置为根据所述空闲请求信号插入空闲帧。
上述方案中，所述读写控制模块，具体配置为根据输入数据时每个通道占用的时隙数和输入数据的位宽计算写周期，并依据所述写周期和每个通道内计数器的计数结果构建写策略；其中，
所述写策略包括：将输入的数据按输入周期依次写入存储模块阵列中具有存储标识的存储单元，所述存储数据的存储单元间的位置差为写周期整数倍的存储单元具有相同的存储标识。
上述方案中，所述读写控制模块，具体配置为根据输入数据时每个通 道占用的时隙数和输入数据的位宽计算每个通道的读周期，并依据所述读周期构建读策略；其中，
所述读策略包括：按照所述存储单元标识的顺序在每个时隙依次输出所述存储模块阵列内的数据；每个时隙输出的所述存储模块阵列内的数据占用的存储单元的数量为读周期的值。
上述方案中，所述存储模块阵列的行数为存储模块输出数据帧的时隙数，所述存储模块阵列的列数为输入数据帧的位宽。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质存储有计算机程序，该计算机程序用于执行本发明实施例的上述数据转换方法。
本发明实施例所提供的数据转换方法、装置及存储介质，按第一传输方式输入数据时，根据输入数据的参数构建写策略，依据所述写策略将所述输入数据写入存储模块阵列；在所述存储模块阵列在存储容量达到输出阈值时，根据输入数据的参数构建读策略，依据所述读策略按第二传输方式将所述存储模块阵列内的数据输出并封装。如此，通过在微控制单元(Micro Control Unit，MCU)构建写策略和读策略，减少了芯片资源的使用，降低了时分格式数据向空分格式数据转换的成本；利用存储模块阵列存储输入的数据，实现了将多通道任意带宽的GFP数据映射到任意速率的ODU flex帧，提高了数据业务的灵活性。
附图说明
图1为ODU flex数据的结构示意图；
图2为本发明实施例数据转换方法的基本处理流程示意图；
图3为存储模块阵列的结构示意图；
图4为本发明实施例一数据转换方法的详细处理流程示意图；
图5为本发明实施例一RAM的数据存储结构示意图；
图6为本发明实施例二数据转换方法的详细处理流程示意图；
图7为本发明实施例二RAM的数据存储结构示意图；
图8为本发明实施例三数据转换方法的详细处理流程示意图；
图9为本发明实施例三RAM的数据存储结构示意图；
图10为本发明实施例数据转换装置的组成结构示意图。
具体实施方式
本发明实施例中，按第一传输方式输入数据时，根据输入数据的参数构建写策略，依据所述写策略将所述输入数据写入存储模块阵列；在所述存储模块阵列在存储容量达到输出阈值时，根据输入数据的参数构建读策略，依据所述读策略按第二传输方式将所述存储模块阵列内的数据输出并封装。
本发明实施例数据转换方法的基本处理流程，如图2所示，包括以下步骤：
步骤101，按第一传输方式输入数据时，根据输入数据的参数构建写策略，依据所述写策略将所述输入数据写入存储模块阵列；
具体地，第一成帧模块按第一传输方式输入数据；读写控制模块根据输入数据时每个通道占用的时隙数和输入数据的位宽计算写周期，为每个通道配置一个通道计数器，用于统计该通道是第几次输入数据；依据所述写周期和计数器的统计结果构建写策略后，触发第一成帧模块依据所述写策略将所述输入数据写入存储模块阵列；第一成帧模块根据所述写策略将自身按第一输入方式输入的数据写入存储模块阵列；
其中，所述第一传输方式可以为按通道的传输方式，第一成帧模块可采用十分复用的方式进行数据写控制；所述写周期为相同写策略出现的周期，以WriteRound表示，WriteRound＝g_SlotNumber/k；g_SlotNumber表示输入数据时每个通道占用的时隙数，W表示输入数据的位宽，k为W和 g_SlotNumber的最大公约数；最小写周期为1，最大写周期由第二成帧模块被划分的时隙数确定；所述写策略包括：将输入的数据按输入周期依次写入存储模块阵列中具有存储标识的存储单元，所述存储数据的存储单元间的位置差为写周期整数倍的存储单元具有相同的存储标识；有多个通道传输数据时，由于不同通道占用的时隙数不同，所以，不同通道的写周期也不同；
这里，所述存储模块阵列可以为随机存取存储器(Random-Access Memory，RAM)阵列，所述存储模块阵列的结构示意图，如图3所示，所述存储模块阵列由多个存储单元组成，每个存储单元为8bit位宽，所述存储模块阵列的行数为存储模块阵列输出数据帧的时隙数，所述存储模块阵列的列数为输入数据帧的位宽，每一拍的数据刚好存储到N个8bit位宽的存储单元，每一行存储单元分别与X个时隙一一对应。
步骤102，所述存储模块阵列在存储容量达到输出阈值时，根据输入数据的参数构建读策略，依据所述读策略按第二传输方式将所述存储模块阵列内的数据输出并封装；
具体地，所述存储模块阵列在存储容量达到自身总容量的一半时，读写控制模块根据输入数据时每个通道占用的时隙数和输入数据的位宽计算每个通道的读周期，依据所述读周期构建读策略，并触发存储模块阵列依据所述读策略按第二传输方式输出所述存储模块阵列内的数据；所述存储模块阵列依据所述读策略按第二传输方式输出自身存储的数据；第二成帧模块对所述存储模块阵列输出的数据进行封装；
其中，所述第二传输方式可以为按时隙的传输方式；所述读周期为相同读策略出现的周期，以ReadRound表示，ReadRound＝W/k；W表示输入数据的位宽，g_SlotNumber表示输入数据时每个通道占用的时隙数，k为W和g_SlotNumber的最大公约数；所述读策略包括：按照所述存储单元标 识的顺序在每个时隙依次输出所述存储模块阵列内的数据；每个时隙输出的所述存储模块阵列内的数据占用的存储单元的数量为读周期的值；有多个通道传输数据时，由于不同通道占用的时隙数不同，所以，不同通道的读周期也不同。
进一步地，在第一传输方式为按通道的传输方式时，所述第一成帧模块为GFP成帧模块，输入的数据速率是动态变化的；第二传输方式为按时隙的传输方式时，所述第二成帧模块为ODUflex成帧模块，输出的数据速率是恒定的；所述第二成帧模块为保证有连续的数据流输入，将第二成帧模块14划分为X个时隙，第二成帧模块在即每个时隙每X拍可根据存储模块阵列输出的数据流量大小向第一成帧模块发送一次空闲请求信号，所述空闲请求信号用于通知第一成帧模块插入空闲帧的时间，以避免各个通道发送的空闲请求信号冲突；每个通道每X拍发送空闲请求的次数由通道占用的时隙数决定。
实施例一
以数据业务使用一个通道传输，通道映射到时隙0-2，输入数据位宽为320bit，第一成帧模块为GFP成帧模块，第二成帧模块为ODUflex成帧模块，ODUflex成帧模块被划分为80个时隙为例，本发明实施例一数据转换方法的详细处理流程，如图4所示，包括以下步骤：
步骤201，读写控制模块根据输入数据时每个通道占用的时隙数和输入数据的位宽计算第一写周期，依据所述第一写周期构建第一写策略；
具体地，W＝320/8＝40，g_SlotNumber1＝3，所以，k1为W和g_SlotNumber1的最大公约数1，WriteRound1＝g_SlotNumber1/k1＝3/1＝3；
所述第一写策略为：将第一个周期的320bit数据存储至存储模块阵列第1行第1列的黑色标识的存储单元中，将第二个周期的320bit数据存储至存储模块阵列第1行第3列反斜线标识的存储单元中，将第三个周期的 320bit数据存储至存储模块阵列第1行第2列圆形标识的存储单元中，将第四个周期的320bit数据存储至存储模块阵列第1行第4列的黑色标识的存储单元中，将第五个周期的320bit数据存储至存储模块阵列第1行第6列反斜线标识的存储单元中，将第六个周期的320bit数据存储至存储模块阵列第1行第5列圆形标识的存储单元中，以此类推；即以三拍为周期进行存储。
步骤202，GFP成帧模块按通道输入的数据时，RAM阵列按第一写策略将所述数据写入RAM阵列；
具体地，本发明实施例一RAM的数据存储结构示意图，如图5所示。
步骤203，在RAM的存储容量达到自身总容量的一半时，读写控制模块根据输入数据时每个通道占用的时隙数和输入数据的位宽计算每个通道的第一读周期，依据第一读周期构建读策略；
具体地，W＝320/8＝40，g_SlotNumber1＝3，所以，k1为W和g_SlotNumber1的最大公约数1，ReadRound1＝W/k1＝40/1＝40；
第一读策略为：时隙0在存储模块阵列的读地址顺序为RAM阵列第1行第1、4、7、10、13、16、19、22、25、28、31、34、37、40、3、6、9、12、15、18、21、24、27、30、33、36、39、2、5、8、11、14、17、20、23、26、29、32、35、38列；时隙1在存储模块阵列的读地址顺序为RAM阵列第2行第2、5、8、11、14、17、20、23、26、29、32、35、38、1、4、7、10、13、16、19、22、25、28、31、34、37、40、3、6、9、12、15、18、21、24、27、30、33、36、39列；时隙2的读顺序为RAM阵列第3行第3、6、9、12、15、18、21、24、27、30、33、36、39、2、5、8、11、14、17、20、23、26、29、32、35、38、1、4、7、10、13、16、19、22、25、28、31、34、37、40列。
步骤204；RAM阵列按第一读策略将所述数据输出至ODUflex成帧模 块；ODUflex成帧模块将所述数据封装成数据帧。
本发明实施例一中，在读写控制模块内设置一个空闲请求计数器，从0-80计数，当收到来自ODUflex成帧模块的空闲请求信号后，读写控制模块在计数器计数1-3后向GFP成帧模块发出空闲请求信号，通知GFP成帧模块插入空闲帧，保证有连续流输入；其中，计数器计数1-3是对应本发明实施例一中的一个通道的数据映射到时隙0-2。
实施例二
以数据业务使用一个通道传输，通道映射到时隙0-79，输入数据位宽为320bit，第一成帧模块为GFP成帧模块，第二成帧模块为ODUflex成帧模块，ODUflex成帧模块被划分为80个时隙为例，本发明实施例二数据转换方法的详细处理流程，如图6所示，包括以下步骤：
步骤301，读写控制模块根据输入数据时每个通道占用的时隙数和输入数据的位宽计算第二写周期，依据所述第二写周期构建第二写策略；
具体地，W＝320/8＝40，g_SlotNumber2＝80，所以，k2为W和g_SlotNumber2的最大公约数40，WriteRound2＝g_SlotNumber2/k2＝80/40＝2；
所述第二写策略为：将第一个周期的320bit数据存储至存储模块阵列的黑色标识的存储单元中，将第二个周期的320bit数据存储至存储模块阵列的反斜线标识的存储单元中，将第三个周期的320bit数据存储至存储模块阵列的黑色标识的存储单元中，将第四个周期的320bit数据存储至存储模块阵列的反斜线标识的存储单元中，以此类推；即以二拍为周期进行存储。
步骤302，GFP成帧模块按通道输入的数据时，RAM阵列按第二写策略将所述数据写入RAM阵列；
具体地，本发明实施例二RAM的数据存储结构示意图，如图7所示。
步骤303，在RAM的存储容量达到自身总容量的一半时，读写控制模 块根据输入数据时每个通道占用的时隙数和输入数据的位宽计算每个通道的第二读周期，依据第二读周期构建读策略；
具体地，W＝320/8＝40，g_SlotNumber2＝80，所以，k2为W和g_SlotNumber2的最大公约数40，ReadRound2＝W/k2＝40/40＝1；
第二读策略为：时隙0在存储模块阵列的读地址为第1行第1列，时隙1在存储模块阵列的读地址为第2行第2列，时隙2在存储模块阵列的读地址为第3行第3列...时隙39在存储模块阵列的读地址为第40行第40列，时隙40在存储模块阵列的读地址为第41行第1列，时隙41在存储模块阵列的读地址为第42行第2列...时隙79在存储模块阵列的读地址为第80行第40列。
步骤304；RAM阵列按第一读策略将所述数据输出至ODUflex成帧模块；ODUflex成帧模块将所述数据封装成数据帧。
本发明实施例二中，在读写控制模块内设置一个空闲请求计数器，从0-80计数，当收到来自ODUflex成帧模块的空闲请求信号后，读写控制模块在计数器计数值1-80后向GFP成帧模块发出空闲请求信号，通知GFP成帧模块插入空闲帧，保证有连续流输入；其中，计数器计数1-80是对应本发明实施例二中的一个通道的数据映射到时隙0-79。
实施例三
以数据业务使用两个通道传输，第一通道映射到时隙0-5，第二通道映射到时隙8、9、11，输入数据位宽为320bit，第一成帧模块为GFP成帧模块，第二成帧模块为ODUflex成帧模块，ODUflex成帧模块被划分为80个时隙为例，本发明实施例三数据转换方法的详细处理流程，如图8所示，包括以下步骤：
步骤401，读写控制模块根据输入数据时每个通道占用的时隙数和输入数据的位宽计算第三写周期和第四写周期，依据所述第三写周期和第四写 周期分别构建第三写策略和第四写策略；
具体地，W＝320/8＝40，g_SlotNumber3＝6，所以，k3为W和g_SlotNumber3的最大公约数2，WriteRound3＝g_SlotNumber3/k3＝6/2＝3；g_SlotNumber4＝3，k4为W和g_SlotNumber4的最大公约数1，WriteRound4＝g_SlotNumber4/k4＝6/1＝6；
所述第三写策略为：对于第一通道，将第一个周期的320bit数据存储至存储模块阵列第一行第一列的黑色标识的存储单元中，将第二个周期的320bit数据存储至存储模块阵列第一行第三列反斜线标识的存储单元中，将第三个周期的320bit数据存储至存储模块阵列第一行第五列圆形标识的存储单元中，将第四个周期的320bit数据存储至存储模块阵列第一行第七列的黑色标识的存储单元中，以此类推；即以三拍一周期进行存储；对于第二通道，将第一个周期的320bit数据存储至存储模块阵列第九行第一列的黑色标识的存储单元中，将第二个周期的320bit数据存储至存储模块阵列第九行第三列反斜线标识的存储单元中，将第三个周期的320bit数据存储至存储模块阵列第九行第二列圆形标识的存储单元中，将第四个周期的320bit数据存储至存储模块阵列第九行第四列的黑色标识的存储单元中，以此类推；即以三拍为周期进行存储。
步骤402，GFP成帧模块按通道输入的数据时，RAM阵列按第三写策略和第四写策略将所述数据写入RAM阵列；
具体地，本发明实施例三RAM的数据存储结构示意图，如图9所示。
步骤403，在RAM的存储容量达到自身总容量的一半时，读写控制模块根据输入数据时每个通道占用的时隙数和输入数据的位宽计算第一通道的第三读周期和第二通道的第四读周期，依据第三读周期和第四读周期构建读策略；
具体地，W＝320/8＝40，g_SlotNumber3＝6，所以，k3为W和 g_SlotNumber3的最大公约数2，ReadRound3＝W/k3＝40/2＝20；g_SlotNumber4＝3，所以，k4为W和g_SlotNumber4的最大公约数1，ReadRound4＝W/k4＝40/1＝40；
第三读策略为：时隙0在存储模块阵列的读地址顺序为RAM阵列第1行第1、7、13、19、25、31、37、3、9、15、21、27、33、39、5、11、17、23、29、35列；时隙1在存储模块阵列的读地址顺序为RAM阵列第2行第2、8、14、20、26、32、38、4、10、16、22、28、34、40、6、12、18、24、30、36列；时隙2在存储模块阵列的读地址顺序为RAM阵列第3行第3、9、15、21、27、33、39、5、11、17、23、29、35、1、7、13、19、25、31、37列；时隙3在存储模块阵列的读地址顺序为RAM阵列第4行第4、10、16、22、28、40、6、12、18、24、30、36、2、8、14、20、26、32、38列；时隙4在存储模块阵列的读地址顺序为RAM阵列第5行第5、11、17、23、29、35、41、7、13、19、25、31、37、3、9、15、21、27、33、39列；时隙5在在存储模块阵列的读地址顺序为RAM阵列第6行第6、、12、18、24、30、36、2、8、14、20、26、32、38、4、10、16、22、28、34、40列；
第四读策略为：时隙8在存储模块阵列的读地址顺序为RAM阵列第9行第1、4、7、10、13、16、19、22、25、28、31、34、37、40、3、6、9、12、15、18、21、24、27、30、33、36、39、2、5、8、11、14、17、20、23、26、29、32、35、38列；时隙9在存储模块阵列的读地址顺序为RAM阵列第10行第2、5、8、11、14、17、20、23、26、29、32、35、38、1、4、7、10、13、16、19、22、25、28、31、34、37、40、3、6、9、12、15、18、21、24、27、30、33、36、39列；时隙11在存储模块阵列的读地址顺序为RAM阵列第12行第3、6、9、12、15、18、21、24、27、30、33、36、39、2、5、8、11、14、17、20、23、26、29、32、35、38、1、4、7、 10、13、16、19、22、25、28、31、34、37、40列。
步骤404；RAM阵列按第三读策略和第四读策略将所述数据输出至ODUflex成帧模块；ODUflex成帧模块将所述数据封装成数据帧。
本发明实施例三中，在读写控制模块内设置一个空闲请求计数器，从0-80计数，当收到来自ODUflex成帧模块的空闲请求信号后，第一通道在读写控制模块在计数器计数1-6后向GFP成帧模块发出空闲请求信号，通知GFP成帧模块插入空闲帧，保证有连续流输入；第二通道在读写控制模块在计数器计数9、10、12后向GFP成帧模块发出空闲请求信号；其中，计数器计数1-6是对应本发明实施例三中的第一通道的数据映射到时隙0-5，计数器计数9、10、12是对应本发明实施例三中的第二通道的数据映射到时隙8、9、11。
本发明实施例可用于将多通道任意带宽的GFP帧数据映射到任意速率的OUDflex帧数据，实现了通道输入数据与时隙输入出具的任意配对，增加了业务的灵活性。本发明实施例中，每个通道分别划分一块存储空间用于存储数据映射规则，并根据业务需要更新数据映射规则，使得各个通道完全独立，互不干扰。
为实现上述数据转换方法，本发明实施例还提供一种数据转换装置，所述装置的组成结构如图10所示，包括：第一成帧模块11、读写控制模块12、存储模块阵列13和第二成帧模块14；其中，
所述第一成帧模块11，配置为根据第一传输方式输入数据，根据写策略将自身按第一输入方式输入的数据写入存储模块阵列12；
所述读写控制模块12，配置为根据所述输入数据的参数构建写策略，并触发所述第一成帧模块11依据所述写策略将所述输入数据写入存储模块阵列13；根据所述输入数据的参数构建读策略，并触发所述存储模块阵列13依据所述读策略按第二传输方式输出所述存储模块阵列13内的数据；
所述存储模块阵列13，配置为存储所述第一成帧模块11输入的数据，依据所述读策略按第二传输方式输出自身存储的数据；
所述第二成帧模块14，配置为封装所述存储模块阵列13输出的数据。
上述实现方案中，所述第二成帧模块14，还配置为根据存储模块阵列输出数据的流量大小发送空闲请求信号；
相应的，所述第一成帧模块11，还配置为根据所述空闲请求信号插入空闲帧。所述读写控制模块12，具体配置为根据输入数据时每个通道占用的时隙数和输入数据的位宽计算写周期，并依据所述写周期和每个通道内计数器的计数结果构建写策略；其中，
所述写策略包括：将输入的数据按输入周期依次写入存储模块阵列13中具有存储标识的存储单元，所述存储数据的存储单元间的位置差为写周期整数倍的存储单元具有相同的存储标识。
所述读写控制模块12，具体配置为根据输入数据时每个通道占用的时隙数和输入数据的位宽计算每个通道的读周期，并依据所述读周期构建读策略；其中，
所述读策略包括：按照所述存储单元标识的顺序在每个时隙依次输出所述存储模块阵列13内的数据；每个时隙输出的所述存储模块阵列13内的数据占用的存储单元的数量为读周期的值。
上述实现方案中，所述存储模块阵列13的行数为存储模块输出数据帧的时隙数，所述存储模块阵列的列数为输入数据帧的位宽。
上述实现方案中，第一成帧模块11按第一传输方式输入数据；读写控制模块12根据输入数据时每个通道占用的时隙数和输入数据的位宽计算写周期，为每个通道配置一个通道计数器，用于统计该通道是第几次输入数据；依据所述写周期和计数器的统计结果构建写策略后，触发第一成帧模块11依据所述写策略将所述输入数据写入存储模块阵列13；第一成帧模块 11根据所述写策略将自身按第一输入方式输入的数据写入存储模块阵列13；
上述实现方案中，所述第一传输方式可以为按通道的传输方式，第一成帧模块11可采用十分复用的方式进行数据写控制；所述写周期为相同写策略出现的周期，以WriteRound表示，WriteRound＝g_SlotNumber/k；g_SlotNumber表示输入数据时每个通道占用的时隙数，W表示输入数据的位宽，k为W和g_SlotNumber的最大公约数；最小写周期为1，最大写周期由第二成帧模块被划分的式系数确定；所述写策略包括：将输入的数据按输入周期依次写入存储模块阵列中具有存储标识的存储单元，所述存储数据的存储单元间的位置差为写周期整数倍的存储单元具有相同的存储标识；有多个通道传输数据时，由于不同通道占用的时隙数不同，所以，不同通道的写周期也不同；
上述实现方案中，所述存储模块阵列13由多个存储单元组成，每个存储单元为8bit位宽，所述存储模块阵列的行数为存储模块阵列输出数据帧的时隙数，所述存储模块阵列的列数为输入数据帧的位宽，每一拍的数据刚好存储到N个8bit位宽的存储单元，每一行存储单元分别与X个时隙一一对应。
上述实现方案中，所述存储模块阵列13在存储容量达到自身总容量的一半时，读写控制模块12根据输入数据时每个通道占用的时隙数和输入数据的位宽计算每个通道的读周期，依据所述读周期构建读策略，并触发存储模块阵列13依据所述读策略按第二传输方式输出所述存储模块阵列13内的数据；所述存储模块阵列13依据所述读策略按第二传输方式输出自身存储的数据；第二成帧模块对所述存储模块阵列13输出的数据进行封装；
上述实现方案中，所述第二传输方式可以为按时隙的传输方式；所述读周期为相同读策略出现的周期，以ReadRound表示，ReadRound＝W/k； W表示输入数据的位宽，g_SlotNumber表示输入数据时每个通道占用的时隙数，k为W和g_SlotNumber的最大公约数；所述读策略包括：按照所述存储单元标识的顺序在每个时隙依次输出所述存储模块阵列13内的数据；每个时隙输出的所述存储模块阵列13内的数据占用的存储单元的数量为读周期的值；有多个通道传输数据时，由于不同通道占用的时隙数不同，所以，不同通道的读周期也不同。
上述实现方案中，在第一传输方式为按通道的传输方式时，所述第一成帧模块11为GFP成帧模块，输入的数据速率是动态变化的；第二传输方式为按时隙的传输方式时，所述第二成帧模块14为ODUflex成帧模块，输出的数据速率是恒定的；所述第二成帧模块14为保证有连续的数据流输入，将第二成帧模块14划分为X个时隙，第二成帧模块14在即每个时隙每X拍可根据存储模块阵列13输出的数据流量大小向第一成帧模块11发送一次空闲请求信号，所述空闲请求信号用于通知第一成帧模块11插入空闲帧的时间，以避免各个通道发送的空闲请求信号冲突；每个通道每X拍发送空闲请求的次数由通道占用的时隙数决定。
本发明实施例中提出的数据转换装置中的存储模块阵列13可以通过存储设备实现，如硬盘等；第一成帧模块11、读写控制模块12、和第二成帧模块14都可以通过处理器来实现，当然也可通过具体的逻辑电路实现；在实际应用中，处理器可以为中央处理器(CPU)、微处理器(MPU)、数字信号处理器(DSP)或现场可编程门阵列(FPGA)等。
本发明实施例中，如果以软件功能模块的形式实现上述数据转换方法，并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个 人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read Only Memory，ROM)、磁碟或者光盘等各种可以存储程序代码的介质。这样，本发明实施例不限制于任何特定的硬件和软件结合。
相应地，本发明实施例还提供一种计算机存储介质，该计算机存储介质中存储有计算机程序，该计算机程序用于执行本发明实施例的上述数据转换方法。
以上所述仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。

Claims (11)

  1. 一种数据转换方法，所述方法包括：
    按第一传输方式输入数据时，根据输入数据的参数构建写策略，依据所述写策略将所述输入数据写入存储模块阵列；
    所述存储模块阵列在存储容量达到输出阈值时，根据输入数据的参数构建读策略，依据所述读策略按第二传输方式将所述存储模块阵列内的数据输出并封装。
  2. 根据权利要求1所述数据转换方法，其中，所述按第一输入方式输入数据后，所述方法还包括：
    根据所述存储模块阵列输出数据的流量大小发送空闲请求信号，所述空闲请求信号用于通知按第一传输方式输入数据时，插入空闲帧的时间。
  3. 根据权利要求1所述数据转换方法，其中，所述根据输入数据的参数构建写策略，包括：
    根据输入数据时每个通道占用的时隙数和输入数据的位宽计算写周期，并依据所述写周期和每个通道内计数器的计数结果构建写策略；其中，
    所述写策略包括：将输入的数据按输入周期依次写入存储模块阵列中具有存储标识的存储单元，所述存储数据的存储单元间的位置差为写周期整数倍的存储单元具有相同的存储标识。
  4. 根据权利要求1所述数据转换方法，其中，所述根据输入数据的参数构建读策略，包括：
    根据输入数据时每个通道占用的时隙数和输入数据的位宽计算每个通道的读周期，并依据所述读周期构建读策略；其中，
    所述读策略包括：按照所述存储单元标识的顺序在每个时隙依次输出所述存储模块阵列内的数据；每个时隙输出的所述存储模块阵列内的数据 占用的存储单元的数量为读周期的值。
  5. 根据权利要求1所述数据转换方法，其中，所述存储模块阵列的行数为存储模块阵列输出数据帧的时隙数，所述存储模块阵列的列数为输入数据帧的位宽。
  6. 一种数据转换装置，所述装置包括：第一成帧模块、读写控制模块、存储模块阵列和第二成帧模块；其中，
    所述第一成帧模块，配置为根据第一传输方式输入数据，根据写策略将自身按第一输入方式输入的数据写入存储模块阵列；
    所述读写控制模块，配置为根据所述输入数据的参数构建写策略，并触发所述第一成帧模块依据所述写策略将所述输入数据写入存储模块阵列；根据所述输入数据的参数构建读策略，并触发所述存储模块阵列依据所述读策略按第二传输方式输出所述存储模块阵列内的数据；
    所述存储模块阵列，配置为存储所述第一成帧模块输入的数据，依据所述读策略按第二传输方式输出自身存储的数据；
    所述第二成帧模块，配置为封装所述存储模块阵列输出的数据。
  7. 根据权利要求6所述数据转换装置，其中，所述第二成帧模块，还配置为根据存储模块阵列输出数据的流量大小发送空闲请求信号；
    相应的，所述第一成帧模块，还配置为根据所述空闲请求信号插入空闲帧。
  8. 根据权利要求6所述数据转换装置，其中，所述读写控制模块，配置为根据输入数据时每个通道占用的时隙数和输入数据的位宽计算写周期，并依据所述写周期和每个通道内计数器的计数结果构建写策略；其中，
    所述写策略包括：将输入的数据按输入周期依次写入存储模块阵列中具有存储标识的存储单元，所述存储数据的存储单元间的位置差为写周期整数倍的存储单元具有相同的存储标识。
  9. 根据权利要求6所述数据转换装置，其中，所述读写控制模块，配置为根据输入数据时每个通道占用的时隙数和输入数据的位宽计算每个通道的读周期，并依据所述读周期构建读策略；其中，
    所述读策略包括：按照所述存储单元标识的顺序在每个时隙依次输出所述存储模块阵列内的数据；每个时隙输出的所述存储模块阵列内的数据占用的存储单元的数量为读周期的值。
  10. 根据权利要求6所述数据转换装置，其中，所述存储模块阵列的行数为存储模块输出数据帧的时隙数，所述存储模块阵列的列数为输入数据帧的位宽。
  11. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，该计算机可执行指令用于执行权利要求1至5任一项所述的数据转换方法。
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