WO2016049245A1 - Cellules solaires à contact passivé et procédés de fabrication - Google Patents

Cellules solaires à contact passivé et procédés de fabrication Download PDF

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Publication number
WO2016049245A1
WO2016049245A1 PCT/US2015/051809 US2015051809W WO2016049245A1 WO 2016049245 A1 WO2016049245 A1 WO 2016049245A1 US 2015051809 W US2015051809 W US 2015051809W WO 2016049245 A1 WO2016049245 A1 WO 2016049245A1
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WIPO (PCT)
Prior art keywords
layer
silicon
silicon substrate
heavily doped
doped polycrystalline
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PCT/US2015/051809
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English (en)
Inventor
Atul Gupta
Ajeet Rohatgi
Vijay Nag YELUNDUR
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Suniva, Inc.
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Application filed by Suniva, Inc. filed Critical Suniva, Inc.
Publication of WO2016049245A1 publication Critical patent/WO2016049245A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0368—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This disclosure relates generally to semiconductor devices, and more particularly to solar cells and methods for manufacturing solar cells.
  • Solar cells are devices that can convert solar radiation to electrical energy. On a clear day, the sun provides approximately one thousand watts of energy per square meter almost everywhere on the planet's surface.
  • Various solar cell structures have been described over the last few decades of research; however, to date, photovoltaic or solar cells typically have a relative low overall efficiency.
  • the performance or efficiency of a solar cell is typically described as a product of three (3) interdependent electrical parameters, namely short circuit current density (Jsc), open circuit voltage (Voc) and fill factor (FF).
  • the invention provides a device having a front side and a back side opposite to the front side, comprising: a) a silicon substrate, wherein at least a portion of the substrate is textured; b) a first heavily doped polycrystalline silicon layer superposed on the silicon substrate on the front side; c) a second heavily doped polycrystalline silicon layer superposed on the silicon substrate on the back side and having a doping type of an opposite polarity to the first heavily doped polycrystalline silicon layer; d) a first dielectric layer interposed between the first heavily doped polycrystalline silicon layer and the silicon substrate; and e) and a first metal contact positioned on the front side and a second metal contact positioned on the back side.
  • the invention also relates to a solar cell having a front side and a back side opposite to the front side comprising: a) a silicon substrate textured on the front side; b) an emitter layer comprising a first heavily doped polycrystalline silicon layer superposed on the silicon substrate on the front side, wherein the emitter layer forms a front junction with the silicon substrate; c) a first dielectric layer interposed between the emitter layer and the silicon substrate; d) a first metal contact making an electrical connection to the emitter layer on the front side of the solar cell; e) a second metal contact making an electrical connection to the substrate on the back side of the solar cell; and f) and the first metal contact and the second metal contact being configured to allow an external electrical circuit to be powered by the solar cell; and wherein the solar cell exhibits an efficiency of at least 20%.
  • the invention is also directed to a method of forming a device having a front side and a back side opposite to the front side comprising: a) providing a silicon substrate; b) texturing at least a portion of the silicon substrate; c) forming a first dielectric layer on the front side of the silicon substrate; d) forming a first heavily doped polycrystalline silicon layer and a second heavily doped polycrystalline silicon layer, wherein the first heavily doped polycrystalline silicon layer has a thickness of greater than about 20 nm to about 5 ⁇ , and wherein the first heavily doped polycrystalline silicon forms a junction with the front side of the substrate; e) forming at least one coating layer, wherein the at least one coating layer comprises: i) an antireflective coating positioned over the first heavily doped polycrystalline silicon layer on the front side; ii) a back reflector positioned over the second heavily doped polycrystalline silicon layer on the back side; or iii) a combination thereof; f) forming at least one coating layer, wherein the
  • FIG. 1 illustrates a cross-sectional view of a passivated contact device, in accordance with an exemplary aspect of the present invention.
  • FIG. 2 illustrates a flow chart for one aspect of a solar cell fabrication process.
  • FIG. 3 illustrates a flow chart for another aspect of a solar cell fabrication process.
  • the terms “about” and “at or about” mean that the amount or value in question can be the value designated some other value approximately or about the same. It is generally understood, as used herein, that it is the nominal value indicated up to ⁇ 10% variation unless otherwise indicated or implied. The term is intended to convey that similar values promote equivalent results or effects recited in the claims. That is, it is understood that amounts, sizes, formulations, parameters, and other quantities and characteristics are not and need not be exact, but can be approximate and/or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art.
  • an amount, size, formulation, parameter or other quantity or characteristic is “about” or “approximate” whether or not expressly stated to be such. It is understood that where "about” is used before a quantitative value, the parameter also includes the specific quantitative value itself, unless specifically stated otherwise.
  • Ranges can be expressed herein as from “about” one particular value, and/or to "about” another particular value. When such a range is expressed, another aspect includes from the one particular value and/or to the other particular value. Similarly, when values are expressed as approximations, by use of the antecedent 'about,' it will be understood that the particular value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint. It is also understood that there are a number of values disclosed herein, and that each value is also herein disclosed as “about” that particular value in addition to the value itself. For example, if the value “10” is disclosed, then “about 10" is also disclosed.
  • any subset or combination of these is also disclosed.
  • the subgroup of A-E, B-F, and C-E would be considered disclosed.
  • This concept applies to all aspects of this application including, but not limited to, steps in methods of making and using the compositions of the invention.
  • steps in methods of making and using the compositions of the invention are a variety of additional steps that can be performed it is understood that each of these additional steps can be performed with any specific aspect or combination of aspects of the methods of the invention.
  • the term or phrase "sufficient,” “sufficient thickness,” “sufficient amount,” or “conditions sufficient to” refers to such thickness, amount or condition that is capable of performing the function or property for which a sufficient thickness or amount is expressed.
  • the exact thickness, amount, or particular condition required can vary from one aspect to another, depending on recognized variables such as the materials employed and the processing conditions observed; however, it should be understood that an appropriate effective thickness, amount, or condition could be readily determined by one of ordinary skill in the art in possession of this disclosure using only routine
  • the term "substantially,” when used in reference to a composition, refers to more than about 98% by weight, more than about 98.5% by weight, more than about 99 % by weight, more than about 99.5 % by weight, or more than about 99.9 % by weight, based on the total weight of the composition, of a specified feature or component.
  • Solar energy is an ideal resource because it is clean and reliable.
  • Solar cells are devices that convert solar energy into electrical energy. These devices are also often called photovoltaic (PV) cells.
  • Solar cells are manufactured from a wide variety of semiconductors.
  • One common semiconductor material frequently used in solar cells is crystalline silicon.
  • a typical solar cell comprises at least three main elements: (1) a substrate; (2) a semiconductor junction; and (3) conductive contacts.
  • Semiconductors, such as silicon, can be doped with a charge carrier, which can be an n-type or a p-type dopant.
  • p-n junction When an n-type silicon and a p-type silicon are formed in contact with one another, the region in the solar cell where they meet is referred to as a semiconductor junction, or "p-n junction.”
  • the semiconductor can absorb light, and the light energy can be transferred to the valence electron of an atom in a silicon layer, allowing the valence electron to escape its bound state and leave a hole. These photo-generated electrons and holes are separated by the electric field associated with the p-n junction.
  • the conductive contacts allow current to flow from the solar cell to an external circuit.
  • the device described herein can comprise a first surface and an opposing second surface.
  • the first surface can be located on a front side of the device.
  • the first surface can comprise a front surface.
  • the second surface can be located opposite to the first surface, for example, on a back side of the device.
  • the second surface is a back surface.
  • the present disclosure relates, in one aspect, to a device having a front side and a back side opposite to the front side, comprising: (a) a silicon substrate, wherein at least a portion of the substrate is textured; (b) a first heavily doped polycrystalline silicon layer having a first doping type superposed on the silicon substrate on the front side; (c) a second heavily doped polycrystalline silicon layer superposed on the silicon substrate on the back side and having a second doping type of an opposite polarity to the first heavily doped polycrystalline silicon layer; (d) a first dielectric layer interposed between the first heavily doped polycrystalline silicon layer and the silicon substrate; and e) a first metal contact positioned on the front side and a second metal contact positioned on the back side.
  • FIG. 1 schematically illustrates a cross-section of a passivated contact device 100 in accordance with an aspect of the present invention.
  • the device 100 comprises an absorber layer or a silicon substrate 101, having a front side (an exemplary first surface) 102 and a back side (an exemplary second surface) 103 opposite to the front side.
  • the silicon substrate 101 is a crystalline silicon.
  • the silicon substrate 101 can comprise a monocrystalline silicon.
  • the silicon substrate 101 can comprise a multicrystalline silicon.
  • the silicon substrate 101 can comprise an n-type doped silicon or a p-type doped silicon.
  • the silicon substrate 101 is an n-type silicon.
  • the silicon substrate 101 is a p-type silicon.
  • at least a portion of the silicon substrate 101 is textured.
  • fabrication of a high-efficiency silicon solar cell can require the presence of textured surfaces capable of reducing reflectance, since optical losses due to reflectance of incident solar radiation are one of the most important factors limiting cell efficiency.
  • the device schematically shown on FIG.1 satisfies at least one of conditions (l)-(3): (1) the at least a portion of the silicon substrate 101 can be textured on the front side to form a front side 102 that is textured; (2) the at least a portion of the silicon substrate 101 can be textured to form a back side 103 that is textured; (3) the at least a portion of the substrate 101 can be textured on the front side 102 and the back side 103.
  • at least a portion of the front side 102 is textured
  • at least a portion of the back side 103 is planarized.
  • the back side 103 is planarized.
  • the textured substrate comprises a plurality of atomically smooth facets.
  • the atomically smooth facets can comprise a plurality of pyramid shaped structures on the surface of the textured substrate.
  • such pyramid shaped structures are randomly formed pyramids.
  • such pyramid shaped structures can be ordered in a predetermined pattern.
  • the n-type silicon substrate comprises a long lifetime n-type silicon wafer having a thickness of about 100 ⁇ to about 250 ⁇ , including exemplary values of about 110 ⁇ , about 120 ⁇ , about 130 ⁇ , about 140 ⁇ , about 150 ⁇ , about 160 ⁇ , about 170 ⁇ , about 180 ⁇ , about 190 ⁇ , about 200 ⁇ , about 210 ⁇ , about 220 ⁇ , about 230 ⁇ , and about 240 ⁇ , as measured from the back side surface 103 to a tip of the textured front side surface of the substrate 102.
  • the device can further comprise a first heavily doped polycrystalline silicon 105 having a first polarity on the first surface of the silicon substrate.
  • the first heavily doped polycrystalline silicon can have a doping type comprising an n-type or a p-type.
  • the first heavily doped polycrystalline silicon 105 has an n-type doping.
  • the first heavily doped polycrystalline silicon 105 has a p-type doping.
  • the first heavily doped polycrystalline silicon 105 has a doping type of an opposite polarity to the silicon substrate.
  • the first heavily doped polycrystalline silicon 105 has a doping type of the same polarity as the silicon substrate. In another aspect, the first heavily doped polycrystalline silicon 105 can further comprise carbon. In one aspect, the first heavily doped polycrystalline silicon layer has an active dopant concentration greater than about lxlO 19 at/cm 3 , or greater than about lxlO 20 at/cm 3 . In another aspect, the active dopant concentration is about 2xl0 21 at/cm 3 or less.
  • the first heavily doped polycrystalline silicon can have a sheet resistance of from about 40 Ohm/sq to about 1000 Ohm/sq, including exemplary values of about 50 Ohm/sq, about 75 Ohm/sq, about 100 Ohm/sq, about 125 Ohm/sq, about 150 Ohm/sq, about 170 Ohm/sq, about 200 Ohm/sq, about 220 Ohm/sq, about 250 Ohm/sq, about 270 Ohm/sq, about 300 Ohm/sq, about 320 Ohm/sq, about 350 Ohm/sq, about 400 Ohm/sq, about 500 Ohm/sq, about 600 Ohm/sq, about 700 Ohm/sq, and about 800 Ohm/sq.
  • the first heavily doped polycrystalline silicon layer forms a front side pn junction with the silicon substrate.
  • the first heavily doped polycrystalline silicon layer is compatible with high temperatures required in the manufacturing of the silicon based devices.
  • the band structure of the first heavily doped polycrystalline silicon layer is substantially identical to the silicon substrate.
  • the first heavily doped polycrystalline silicon layer exhibits an indirect bandgap.
  • the indirect bandgap of the first heavily doped polycrystalline silicon layer can enable the use of a thicker layer without significant losses due to absorption in the first heavily doped polycrystalline silicon layer.
  • the first heavily doped polycrystalline silicon layer can serve as a front surface field forming a high-low junction.
  • the first heavily doped polycrystalline silicon layer comprises the carbon doping
  • the first heavily doped polycrystalline silicon layer has a larger bandgap than the substrate.
  • the disclosed device allows more light to pass through the first heavily doped polycrystalline silicon layer with absorption losses therein.
  • the device can comprise a second heavily doped polycrystalline silicon layer 106 having a second polarity on the second surface of the silicon substrate.
  • the second heavily doped polycrystalline silicon layer 106 can have a doping type of an opposite polarity to the first heavily doped polycrystalline silicon layer.
  • the second heavily doped polycrystalline silicon can comprise an n-type or a p-type dopants.
  • the second heavily doped polycrystalline silicon 106 has an n-type doping, when the first heavily doped polycrystalline silicon 105 has a p-type doping.
  • the second heavily doped polycrystalline silicon 106 has a p-type doping, when the first heavily doped polycrystalline silicon 105 has an n-type doping.
  • the thickness of the first heavily doped polycrystalline silicon layer is greater than about 20 nm to about 5 ⁇ , including exemplary values of about 50 nm, about 100 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, about 350 nm, about 400 nm, about 450 nm, about 500 nm, about 550 nm, about 600 nm, about 650 nm, about 700 nm, about 750 nm, about 800 nm, about 850 nm, about 900 nm, about 950 nm, about 1 ⁇ , about 1.5 ⁇ , about 2 ⁇ , about 2.5 ⁇ , about 3 ⁇ , about 3.5 ⁇ , about 4 ⁇ , and about 4.5 ⁇ .
  • the thickness of the of the first heavily doped polycrystalline silicon can be determined by one of ordinary skill in the art to ensure a lateral conductivity sufficient to enable higher efficiency in the cell while being sufficiently thin to minimize carrier absorption. In one aspect, the thickness can be determined by a sheet resistance of the polycrystalline silicon layer. In some aspects, the sheet resistance of the first heavily doped polycrystalline silicon layer is from about 40 Ohm/sq to about 200 Ohm/sq if the first heavily doped polycrystalline silicon has an opposite polarity to the substrate and, from about 40 Ohm/sq to about 1,000 Ohm/sq if the first heavily doped polycrystalline silicon has the same polarity as the substrate.
  • the thickness of the second heavily doped polycrystalline silicon layer can be same or thinner than the thickness of the first heavily doped polycrystalline silicon layer.
  • the thickness of the second heavily doped polycrystalline silicon layer is about 10 nm or greater to about 1 ⁇ or less, including exemplary values of about 15 nm, about 20 nm, about 25 nm, about 30 nm, about 35 nm, about 40 nm, about 45 nm, about 50 nm, about 55 nm, about 60 nm, about 65 nm, about 70 nm, about 75 nm, about 80 nm, about 85 nm, about 90 nm, about 95 nm, about 100 nm, 150 nm, about 200 nm, about 250 nm, about 300 nm, about 350 nm, about 400 nm, about 450 nm, about 500 nm, about 550 nm, about 600 nm, about 650 nm, about 700
  • the device can further comprise a first dielectric layer 104 that is interposed between the first heavily doped polycrystalline silicon 105 and the silicon substrate 101.
  • the first dielectric layer can comprise a chemical oxide layer or a thermal oxide layer.
  • the first dielectric layer can be deposited by the methods described below.
  • the first dielectric layer comprises a tunneling dielectric layer.
  • the first dielectric layer 104 needs to be sufficiently thin to allow selective transport of holes or electrons through the dielectric layer.
  • the first dielectric layer 104 can exhibit passivation qualities.
  • the first dielectric layer has a thickness from about 0.5 to about 3.5 nm, including exemplary values of about 0.6 nm, about 0.7 nm, about 0.8 nm, about 0.9 nm, about 1.0 nm, about 1.1 nm, about 1.2 nm, about 1.3 nm, about 1.4 nm, about 1.5 nm, about 1.6 nm, about 1.7 nm, about 1.8 nm, about 1.9 nm, about 2.0 nm, about 2.1 nm, about 2.2 nm, about 2.3 nm, about 2.4 nm, about 2.5 nm, about 2.6 nm, about 2.7 nm, about 2.8 nm, about 2.9 nm, about 3.0 nm, about 3.1 nm, about 3.2 nm, about 3.3 nm, and about 3.4 nm.
  • the first dielectric layer 104 has a bandgap at least about 0.2 eV larger than the silicon substrate 101. In some aspects, the first dielectric layer 104 has a bandgap at least about 0.5 eV, at least about 1 eV, at least about 1.5 eV, at least about 2 eV, at least about 2.5 eV, at least about 3 eV, at least about 3.5 eV, at least about 4 eV, at least about 4.5 eV, at least about 5 eV, at least about 5.5.
  • the first dielectric layer 104 can comprise a silicon oxide film (SiOx), a silicon oxynitride film (SiOxNy), an aluminum oxide film (AlOx), a hafnium oxide film (HfOx), or a combination thereof.
  • the device of the current invention can further comprise a second dielectric layer 104a interposed between the second heavily doped polycrystalline silicon layer and the silicon substrate.
  • the second dielectric layer is the same as or different from the first dielectric layer.
  • the larger bandgap of the first dielectric layer 104 and/or the second dielectric layer 104a introduces positive offsets in the conduction and/or valence bands relative to the silicon substrate 101.
  • the offsets in the valence and conduction bands can provide effective barriers to minority carrier transport across the dielectric layer while selectively allowing majority carrier transport (in the heavily doped poly crystalline silicon layers across the dielectric layer). This selective nature of carrier transport enables excellent surface passivation characteristics for the absorber layer and can significantly reduce recombination current densities in the junctions to allow formation of a device exhibiting high cell open circuit voltages.
  • the inventive device can eliminate the negative effects of having photo-generated carrier recombination in the first and the second heavily doped polycrystalline silicon layers surrounding the silicon substrate by preventing the photo-generated carriers from crossing over to the regions having a higher dopant concentration.
  • the first and/or the second dielectric layers can be "optically transparent.”
  • the term “optically transparent” refers to the substantially low absorption of photons.
  • the first 104 and the second dielectric 104a layers interposed between the silicon substrate 101 and the first 105 and the second 106 heavily doped polycrystalline silicon layers, respectively are stable at high temperature processes and can withstand a processing temperature of at least about 700 °C, at least about 750 °C, at least about 800 °C, at least about 850 °C, at least about 900 °C, at least about 950 °C, or at least about 1,000 °C.
  • the first and the second dielectric layer exhibit very few atomic defects and/or electrical states within the bandgap.
  • the first and/or the second dielectric layers are not optically transparent.
  • the device can further comprise at least one coating layer.
  • the device can further comprise a first coating and a second coating.
  • the first coating can be disposed on the first surface.
  • the second coating can be disposed on the second surface.
  • the at least one coating layer can be an antireflective coating 107 that is positioned over the first heavily doped polycrystalline silicon layer on the front side.
  • the antireflective coating helps improve solar radiation collection efficiency.
  • the antireflective coating 107 comprises a film that is selected from the group consisting of silicon nitride (SiNx), silicon oxide (S1O 2 ), aluminum oxide (AlOx), and titanium oxide (T1O 2 ) films.
  • the antireflective coating 107 is a silicon nitride film.
  • the silicon nitride film exhibits a refractive index of from about 1.9 to about 2.3, including exemplary values of about 1.95, about 2.0, about 2.05, about 2.1, about 2.15, about 2.2, and about 2.25.
  • the antireflective film can comprise a graded index silicon nitride film.
  • the antireflective coating comprises titanium oxide with a refractive index of from about 2.1 to about 2.4, including exemplary values of about 2.15, about 2.2, about 2.25, about 2.3, and about 2.35.
  • the antireflective film has a thickness of from about 40 nm to about 90 nm, including exemplary values of about 45 nm, about 50 nm, about 55 nm, about 60 nm, about 65 nm, about 70 nm, about 75 nm, about 80 nm, and about 85 nm.
  • the at least one coating layer comprises a back reflector film 107a positioned over the second heavily doped polycrystalline silicon layer on the back side.
  • the back reflector 107a comprises a film that is selected from the group consisting of silicon nitride (SiNx), silicon oxide (S1O 2 ), aluminum oxide (AlOx), titanium oxide (T1O 2 ), graphene, carbon nanotubes, and a transparent conductive oxide (TCO).
  • the transparent conductive oxide layer can comprise indium tin oxide (ITO), fluorine doped ZnO (FTO), aluminum doped zinc oxide (AZO), indium gallium oxide (IGO), or any combination thereof.
  • the at least one coating layer positioned over the second heavily doped polycrystalline silicon layer on the back side does not comprise a transparent conductive oxide (TCO).
  • the back reflector film has a thickness from about 30 nm to about 200 nm, including exemplary values of about 40 nm, about 50 nm, about 60 nm, about 70 nm, about 80 nm, about 90 nm, about 100 nm, about 110 nm, about 120 nm, about 130 nm, about 140 nm, about 150 nm, about 160 nm, about 170 nm, about 180 nm, and about 190 nm.
  • the inventive device comprises at least two coating layers, wherein the two coating layers comprise an antireflective coating and a back reflector.
  • the device comprises at least one first metal contact 108 making an electrical connection with the first heavily doped polycrystalline silicon layer.
  • the at least one first metal contact is screen printed.
  • the at least one first metal contact 108 comprises a pattern with gridlines to collect the current from the contact layer and transport to the interconnect points that connect one cell to the next in a panel.
  • the at least one first metal contact is silver (Ag).
  • the at least one first metal contact is aluminum (Al).
  • the at least one first metal contact is an alloy of aluminum and silver.
  • the at least one first metal contact has a size sufficient to minimize the sum of resistive and optical power losses in the panel.
  • the at least one first metal contact comprises a substantially rectangular grid pattern with thin gridlines having width of from about 30 ⁇ to about 150 ⁇ .
  • the at least one first metal contact comprises a substantially rectangular grid pattern with thing gridlines spaced from about 0.3 mm to about 2.5 mm apart ending in perpendicularly oriented busbars.
  • the width of the first metal contact comprises a substantially rectangular grid pattern with thing gridlines spaced from about 0.3 mm to about 2.5 mm apart ending in perpendicularly oriented busbars.
  • the perpendicularly oriented busbars can be from about 0.1 mm to about 3 mm.
  • the at least one first metal contact can comprise an array or a wire capable of carrying the current away from the gridlines to the next cell.
  • the array or the wire capable of carrying current away from the gridline to the next cell comprises a copper ribbon.
  • the interconnect points that connect one cell to the next in a panel can comprise a copper ribbon.
  • the copper ribbon has a rectangular cross-section.
  • the device can comprise at least one second metal contact 108a.
  • the at least one second metal contact is the same as or different from a first metal contact comprising silver metal (Ag), aluminum metal (Al), or Ag/Al metal alloys as a conducting material.
  • the second metal contact can comprise copper.
  • the at least one second metal contact can be screen printed or deposited by physical vapor deposition (PVD) techniques that can include but are not limited to sputtering, evaporation, and the like; or electrochemical deposition techniques that can include but are not limited to electroplating, electroless plating, light induced plating, and the like; or any combination of thereof.
  • PVD physical vapor deposition
  • the device disclosed herein is a solar cell.
  • the solar cell is having a front side and a back side opposite to the front side comprising: a) a silicon substrate textured on the front side; b) an emitter layer comprising a first heavily doped polycrystalline silicon layer superposed on the silicon substrate on the front side, wherein the emitter layer forms a front junction with the silicon substrate; c) a first dielectric layer interposed between the emitter layer and the silicon substrate; d) a first metal contact making an electrical connection to the emitter layer on the front side of the solar cell; e) a second metal contact making an electrical connection to the substrate on the back side of the solar cell; and f) the first metal contact and the second metal contact being configured to allow an external electrical circuit to be powered by the solar cell; and wherein the solar cell exhibits an efficiency of at least 20%.
  • the front side emitter has an emitter saturation current of less than about 100 fA/cm 2 , less than about 80 fA/cm 2 ; less than about 60 fA/cm 2 , less than about 40 fA/cm 2 , less than about 30 fA/cm 2 , less than about 20 fA/cm 2 , less than about 10 fA/cm 2 , less than about 5 fA/cm 2 , less than about 2 fA/cm 2 , or less than about 1 fA/cm 2 .
  • the emitter dopant profile can be a substantially uniform profile with a peak doping
  • concentration of from about 1x10 to about 1x10 at cm with electrically active carrier
  • the emitter profile can be a Gaussian profile with a peak doping concentration at the surface of from about lxlO 20 to about lxlO 21 at/cm 3 and a junction depth of about 1 ⁇ .
  • the front side emitter has a sheet resistance of about 10 Ohm/sq to about 500 Ohm/sq.
  • the front side emitter has a sheet resistance of less than about 200 Ohm/sq, including exemplary values of less than about 150 Ohm/sq, less than about 140 Ohm/sq, less than about 130 Ohm/sq, less than about 120 Ohm/sq, less than about 1 10 Ohm/sq, less than about 100 Ohm/sq, less than about 90 Ohm/sq, less than about 80 Ohm/sq, less than about 70 Ohm/sq, less than about 60 Ohm/sq, less than about 50 Ohm/sq, less than about 40 Ohm/sq, less than about 30 Ohm/sq, and less than about 20 Ohm/sq.
  • the solar cell disclosed herein does not comprise transparent conductive layers (TCO).
  • the first dielectric layer interposed between the emitter layer and the silicon layer comprises a tunnel oxide.
  • the tunnel oxide layer does not hinder majority charge carrier transport across its barrier, providing the solar cell fill factors (FFs) above about 80%.
  • the inventive solar cell structure allows a cell Voc higher than about 670 mV.
  • the solar cell disclosed herein comprises a first metal contact and a second metal contact that are configured to allow an external electrical circuit to be powered by the solar cell; and wherein the solar cell exhibits an efficiency of at least 20%, including exemplary values of at least about 20.1%, at least about 20.2 %, at least about 20.3 %, at least about 20.4%, at least about 20.5 %, at least about 20.6%, at least about 20.7%, at least about 20.8%, at least about 20.9%, at least about 21.0%, at least about 21.1%, at least about 21.2 %, at least about 21.3 %, at least about 21.4%, at least about 21.5 %, at least about 21.6%, at least about 21.7%, at least about 21.8%, at least about 21.9%, at least about 22.0%, at least about 22.1%, at least about 22.2 %, at least about 22.3 %, at least about 22.4%, at least about 22.5 %, at least about 22.6%, at
  • Also disclosed herein is a process comprising: forming a device having a front side and a back side opposite to the front side comprising: a) providing a silicon substrate; b) texturing at least a portion of the silicon substrate; c) forming a first dielectric layer on the front side of the silicon substrate; d) forming a first heavily doped polycrystalline silicon layer and a second heavily doped polycrystalline silicon layer, wherein the first heavily doped polycrystalline silicon layer has a thickness of greater than about 20 nm to about less than about 1 ⁇ , and wherein the first heavily doped polycrystalline silicon forms a junction with the front side of the substrate; e) forming at least one coating layer, wherein the at least one coating layer comprises: i) an antireflective coating positioned over the first heavily doped polycrystalline silicon layer on the front side; ii) a back reflector positioned over the second heavily doped polycrystalline silicon layer on the back side; or iii) a combination thereof; f) forming at least
  • FIG. 2 schematically illustrates an exemplary process for the fabrication of the device 100 shown in FIG. 1.
  • a silicon substrate is provided.
  • approximately 75% of the cost of manufacturing silicon solar cells is in the cost of the silicon wafer itself.
  • the more wafer that can be sliced from an ingot the more cost savings may be realized.
  • the device 100 can be manufactured utilizing the silicon substrate having a thickness of about 100 ⁇ to about 250 ⁇ , including exemplary values of about 110 ⁇ , about 120 ⁇ , about 130 ⁇ , about 140 ⁇ , about 150 ⁇ , about 160 ⁇ , about 170 ⁇ , about 180 ⁇ , about 190 ⁇ , about 200 ⁇ , about 210 ⁇ , about 220 ⁇ , about 230 ⁇ , and about 240 ⁇ . It is understood that in order to ensure reproducibility of the manufacturing process and to remove undesired impurities and defects, the provided silicon substrate can undergo any cleaning procedure commonly known to one of ordinary skill in the art.
  • the undesirable defects can be the result of a sawing process used by the wafer vendor to slice the substrate from its ingot.
  • undesired impurities can include without limitation dust, water marks, metal impurities, organic residues, and the like.
  • the provided silicon substrate is a crystalline substrate 200.
  • the silicon substrate is a monocrystalline silicon substrate.
  • the silicon substrate is a multicrystalline silicon substrate.
  • the silicon substrate can comprise an n-type or a p-type silicon substrate.
  • the at least a portion of the silicon substrate is textured 201.
  • texturing can be present on the first surface or a portion thereof.
  • texturing can be present on the second surface or a portion thereof.
  • texturing can be present on at least a portion of the first and at least a portion of the second surface.
  • the texturing of the at least a portion of the silicon substrate is performed on a front side, back side, or a combination thereof.
  • the texturing of the at least a portion of the silicon substrate is performed on the front side.
  • at least a portion of the silicon substrate on the back side is substantially planarized.
  • texturing the silicon substrate comprises exposing at least a portion of the silicon substrate to a liquid capable of forming a textured silicon substrate, a plasma etching process, a laser etching process, a mechanical etching process, or any combination thereof.
  • texturing can be performed in a liquid capable of forming a textured silicon substrate.
  • at least a portion of an outer silicon layer is removed from the silicon substrate surface. Upon removal the outer silicon layer, a clean contaminant- free silicon surface is exposed.
  • the liquid can comprise an alkaline solution.
  • the alkaline solution comprises a solution of potassium hydroxide and isopropyl alcohol.
  • etching in an alkaline solution can result in formation of random crystallographic grain orientations and high selectivity of etching along specific directions on the silicon surface.
  • the liquid comprises an acid solution.
  • texturing comprises the use of an acid solution comprising, for example, a mixture of hydrofluoric acid and nitric acid (HF-HNO 3 ), the resulting textured surface can comprise randomly distributed grains of different
  • crystallographic orientation In yet another aspect, precise control of a processing temperature can be useful.
  • texturing can comprise use of plasma etching.
  • plasma etching can comprise a reactive ion etching (RIE) or inductively coupled plasma (ICP) etching technique.
  • texturing can comprise a mechanical etching technique.
  • texturing can be accomplished by the use of a laser etching technique.
  • a coherent and monochromatic laser beam focused on a small spot can produce high power densities that allow evaporation and removal of the thin material layer in the form of neutral atoms and molecules, positive and negative ions from material surface exposed to laser radiation and thus, forming a
  • a sacrificial layer can be deposited on the silicon substrate prior to texturing.
  • such a sacrificial layer can be an oxide layer that can be removed by any previously described texturing technique.
  • texturing forms a uniform or substantially uniform surface.
  • texturing forms an atomically smooth or substantially atomically smooth surface.
  • the first dielectric layer can be formed on the front side of the silicon substrate. In one aspect, the first dielectric layer can be positioned on the textured substrate surface. In another aspect, the first dielectric layer can be formed by methods comprising chemical oxidation of at least a portion of the silicon substrate, or deposition via atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD). In yet another aspect, the first dielectric layer is a tunnel oxide. In one aspect, the chemical oxidation of the silicon substrate can be performed by immersing at least a portion of the silicon substrate in an oxidizing environment at temperatures elevated above 25 °C. In some aspects, the first dielectric layer can comprise aluminum oxide (AlOx), hafnium oxide (HfOx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy) films.
  • AlOx aluminum oxide
  • HfOx hafnium oxide
  • SiOx silicon oxide
  • SiOxNy silicon oxynitride
  • the oxidizing environment can include, but is not limited to, hydrogen peroxide, sulfuric acid, nitric acid, ozone, ozonated water, and the like.
  • the first dielectric layer has a thickness sufficiently low to allow selective tunneling of holes or electrons through the dielectric layer to the contact layer that will be subsequently deposited on the other side of the dielectric layer. Without wishing to be bound by theory, it is understood that since tunneling probability decreases exponentially with increasing thickness, and good passivation requires a minimum thickness to provide a stable process, the first dielectric layer thickness can be determined by one of ordinary skill in the art based on the specific needs of a given device and/or process.
  • the thickness of the first dielectric layer is from about 0.5 to about 3.5 nm, including exemplary values of about 0.6 nm, about 0.7 nm, about 0.8 nm, about 0.9 nm, about 1.0 nm, about 1.1 nm, about 1.2 nm, about 1.3 nm, about 1.4 nm, about 1.5 nm, about 1.6 nm, about 1.7 nm, about 1.8 nm, about 1.9 nm, about 2.0 nm, about 2.1 nm, about 2.2 nm, about 2.3 nm, about 2.4 nm, about 2.5 nm, about 2.6 nm, about 2.7 nm, about 2.8 nm, about 2.9 nm, about 3.0 nm, about 3.1 nm, about 3.2 nm, about 3.3 nm, and about 3.4 nm.
  • the method can further comprise forming a second dielectric layer, wherein the second dielectric layer is formed on the back side of the silicon substrate, 202.
  • the second dielectric layer can be formed simultaneously with the first dielectric layer.
  • the second dielectric layer is formed separately from the first dielectric layer.
  • the second dielectric layer is the same as or different from the first dielectric layer.
  • forming the first and the second heavily doped polycrystalline silicon layers further comprises depositing a first undoped layer on the front side and a second undoped silicon layer on the back side.
  • the first and the second undoped silicon layers are deposited simultaneously or separately.
  • the first and the second undoped silicon layers are deposited using low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), or any combination thereof.
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • hydrogenation of the tunnel oxide layers is possible during the deposition.
  • the first undoped silicon layer can be positioned on the first dielectric layer.
  • the second undoped silicon layer can be positioned on the second dielectric layer.
  • the first undoped polycrystalline silicon layer has a thickness greater than about 20 nm to about 5 ⁇ .
  • the thickness of the first undoped polycrystalline silicon layer can be sufficient to exhibit a desirable lateral conductivity in order to enable higher efficiency in the cells. Without wishing to be bound by theory, it is speculated that higher cell efficiency can be achieved, in part, by minimizing power loss due to the resistance in the contact layers to the grid, especially on the front side since the metal gridlines are limited in coverage area, to minimize shading losses.
  • the thickness of the first undoped polycrystalline silicon layer can be sufficiently thin to minimize carrier absorption within the top contact layer. In some aspects, to achieve the highest efficiency cells, all or substantially all of the incident light can be absorbed in the silicon substrate. In other aspects, the thickness of the second undoped polycrystalline silicon layer can be same as or different from the thickness of the first undoped polycrystalline silicon layer. [0069] In further aspects, the methods described herein can further comprise doping the first and/or the second undoped silicon layers to form a first heavily doped polycrystalline silicon layer 204 having a first polarity and a second heavily doped polycrystalline silicon layer 205 having a second (opposing) polarity.
  • the first and the second undoped silicon layers when doped, can advantageously have an opposite doping polarity.
  • the first heavily doped polycrystalline silicon layer 204 can have a doping type that has same polarity as the silicon substrate.
  • the first heavily doped polycrystalline silicon layer 204 can have a doping type that has an opposite polarity to the silicon substrate.
  • the silicon substrate is n-type
  • the first heavily doped polycrystalline silicon layer 204 can be a p-type doped
  • the second heavily doped polycrystalline silicon layer 205 can be an n-type doped.
  • the p- type doping is achieved by introducing group III elements including boron (B), aluminum (Al), gallium (Ga), or indium (In) as doping elements.
  • group III elements including boron (B), aluminum (Al), gallium (Ga), or indium (In) as doping elements.
  • boron (B) atoms are used as the dopant element.
  • the n-type doping is achieved by introducing group V elements, including phosphorous (P), arsenic (As), antimony (Sb) atoms, as a doping agent.
  • phosphorus (P) atoms are used as the dopant element.
  • doping can be accomplished through single side doping techniques, such as an ion implantation or a doped glass deposition (APCVD or PECVD), enabling different dopant types to be placed into/onto the contact layers.
  • doping can be performed via ion implantation.
  • the active dopant concentration in the first heavily doped polycrystalline silicon layer is greater than about lxlO 19 at/cm 3 .
  • a dose of the ion implantation needed to form a heavily doped layers is equal to or greater than about lxlO 15 at/cm 2 to less than or equal to about 2xl0 16 at/cm 2 .
  • doping comprises doped glass deposition.
  • a doped glass deposition can be performed by plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), or a combination thereof.
  • PECVD plasma enhanced chemical vapor deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • the doping level of the second undoped polycrystalline silicon can be the same or different than the doping level of the first undoped silicon layer.
  • doping of the second undoped layer is performed simultaneously with doping of the first undoped layer.
  • the methods described herein can further comprise annealing 206 of the contact layers comprising the first and the second heavily doped polycrystalline silicon layers having opposite polarity.
  • annealing can comprise diffusing and activating dopants.
  • annealing can be performed in a tube furnace.
  • annealing can be performed by a laser or a flash lamp.
  • annealing can be performed at a temperature equal to or greater than about 700 °C, including exemplary values of greater than about 750 °C, greater than about 800 °C, greater than about 850 °C, greater than about 900 °C, greater than about 950 °C, and greater than about 1000 °C.
  • the temperature greater than about 800 °C can be desired so as to achieve a sufficient activation of the dopants within the contact layers.
  • the dopants can diffuse at least partially into the silicon substrate, potentially leading to performance degradation of the cell due to increased recombination.
  • a passivating oxide can be grown during the annealing on top of the doped contact layers.
  • the doping can be performed simultaneously (i.e., in-situ) with the deposition of the first and/or the second undoped silicon layers to form the first and the second heavily doped layers.
  • the polysilicon deposition can be done with in-situ doping of the first polarity on at least a first surface (303), when the steps 304-311 are substantially similar to the steps 205-212.
  • In-situ doping, if performed, can be performed using any suitable technique known in the art.
  • the in-situ doped silicon layers can be subsequently annealed to increase conductivity of the layers.
  • an amorphous silicon layer is doped in-situ and subsequently annealed to allow recrystallization of at least a portion of amorphous silicon into a large grain polycrystalline silicon exhibiting optical and conductive properties substantially identical to optical and conductive properties of monocrystalline silicon.
  • the doping of the first doped polycrystalline silicon layer can be n or p type, wherein the doping of the second doped polycrystalline silicon layer can be p or n type, to allow formation of the disclosed device having opposite polarities.
  • the desired of polarity of each doped polycrystalline silicon layer can be achieved via a single side doping techniques followed by the annealing process.
  • a successful annealing process can allow accomplishment of multiple effects that include but are not limited to a dopant activation or crystallization of at least a portion of the deposited silicon layers.
  • a passivating oxide can be grown on the surface of the polycrystalline silicon during the annealing step.
  • the methods of the present invention can further comprise the deposition of at least one coating layer.
  • the at least one coating layer is a first coating layer deposited on the first surface of the silicon substrate 207.
  • at least one coating can comprise a second coating layer deposited on the second surface of the silicon substrate 208.
  • at least one coating layer can comprise an antireflective coating positioned over the first heavily doped polycrystalline silicon layer on the front side and can be selected from the group consisting of silicon nitride (SiNx), silicon oxide (S1O 2 ), aluminum oxide (AlOx), or titanium oxide (T1O 2 ).
  • At least one coating layer can comprise a back reflector positioned over the second heavily doped polycrystalline silicon layer on the back side and can be selected from the group consisting of silicon nitride (SiNx), silicon oxide (S1O 2 ), aluminum oxide (AlOx), titanium oxide (T1O 2 ), graphene, carbon nanotubes, or a transparent conductive oxide (TCO).
  • the TCO if used, can comprise indium tin oxide (ITO), fluorine doped ZnO (FTO), aluminum doped zinc oxide (AZO), indium gallium oxide (IGO), or any combination thereof.
  • the at least one coating layer does not comprise a transparent conductive oxide (TCO).
  • an antireflective coating can exhibit a refractive index about 1.9 to about 2.3.
  • a graded index SiNx layer or T1O 2 or any materials known in the art having a refractive index of about 2.1 to about 2.4 can also be used.
  • the thickness of the antireflective coating can be about 40 to about 90 nm.
  • the methods can further comprise forming at least two coating layers, wherein the two coating layers comprise an antireflective coating and a back reflector.
  • the at least two coating layers can be deposited in a single machine, or via a single step or technique, with multiple chambers for front and back layers or via double side deposition process as low pressure plasma chemical vapor deposition (LPCVD).
  • LPCVD low pressure plasma chemical vapor deposition
  • the methods can further comprise forming at least one metal contact.
  • at least one metal contact formed on at least a portion of the front side can be a first metal contact.
  • at least one metal contact formed on at least a portion of the back side can be a second metal contact.
  • at least one metal contact formed both on the at least a portion of the front side and at least a portion of the back side can be a first metal contact and a second metal contact.
  • At least one first metal contact can be formed by screen printing using a metal paste on the first surface of the antireflection layer 207. In another aspect, at least one first metal contact can be formed by screen printing using a metal paste 209 on the front surface of the antireflection layer 207.
  • the metal paste can comprise a silver paste. In other aspects, the metal paste can comprise a silver/aluminum paste. As one of ordinary skill in the art would readily appreciate, the silver paste can be selected because of its high electrical conductivity to limit shadowing effects that can lower solar cell efficiency. Various commercial silver pastes are available for this purpose, and can be easily accessible to one of ordinary skill in the art.
  • the gridlines are printed to have widths of less than about 200 ⁇ , for example in the range of from about 30 to about70 ⁇ range.
  • at least one first metal contact is making an electrical connection with the first heavily doped polycrystalline silicon layer.
  • the printed gridlines are capable of collecting the current from the contact layer and transporting it to the interconnect points that connect one cell to the next in a panel.
  • the at least one first metal contact can comprise an array or a wire capable of carrying the current away from the gridlines to the next cell.
  • the array or the wire capable of carrying current away from the gridline to the next cell comprises a copper ribbon.
  • the interconnect points that connect one cell to the next in a panel can comprise a copper ribbon.
  • the copper ribbon has a rectangular cross-section.
  • At least one second contact is formed on the second coating layer on the second surface 208.
  • at least one second contact comprises a pattern that is same as or different from one or more of the first metal contacts.
  • a second contact is formed by screen printing.
  • screen printing is performed using a the metal paste 210.
  • a second metal contact can be formed by physical vapor deposition, sputtering, or evaporation.
  • a second metal contact can also comprise copper, aluminum, or any metal alloys thereof.
  • the metal alloys can comprise substantially aluminum.
  • the metal alloys can comprise substantially copper.
  • the metal alloys can comprise both aluminum and copper.
  • the metal alloys can comprise any metals that can form an alloy with copper. In a yet further aspect, the metal alloys can comprise any metals that can for an alloy with aluminum. In a still further aspect, the metal alloys can comprise any metals that can form an alloy with both copper and aluminum. As one of ordinary skill in the art would appreciate, when a second metal contact comprising copper, aluminum, or any metal alloys thereof is not formed by a screen printing process, additional processing steps such as the development of vias can be utilized.
  • the methods disclosed herein can further comprise firing 211 the first and second metal contacts at a temperature equal to or greater than about 700 °C.
  • solar cells can be manufactured by the methods described herein.
  • such solar cells can be tested 212 and sorted.
  • the cells having substantially identical characteristics, including but not limited to a current, a voltage, and a cell efficiency can be connected to form a panel having a plurality of the tested solar cells.
  • the panel can be deployed into a photovoltaic (PV) system.
  • PV photovoltaic

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Abstract

L'invention concerne un dispositif ayant des contacts passivés et capable de résister à des températures de traitement supérieures à 700 °C, ainsi qu'une cellule solaire ayant des contacts passivés et étant capable de convertir l'énergie solaire en énergie électrique avec une efficacité d'au moins 20 %. L'invention concerne également des procédés de réalisation du dispositif et de la cellule solaire selon l'invention.
PCT/US2015/051809 2014-09-24 2015-09-24 Cellules solaires à contact passivé et procédés de fabrication WO2016049245A1 (fr)

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US11329172B2 (en) 2013-04-03 2022-05-10 Lg Electronics Inc. Solar cell
US11482629B2 (en) 2013-04-03 2022-10-25 Lg Electronics Inc. Solar cell
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US10749069B2 (en) 2014-11-04 2020-08-18 Lg Electronics Inc. Solar cell and method for manufacturing the same
US11239379B2 (en) 2014-11-28 2022-02-01 Lg Electronics Inc. Solar cell and method for manufacturing the same
US11133426B2 (en) 2014-11-28 2021-09-28 Lg Electronics Inc. Solar cell and method for manufacturing the same
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US11362221B2 (en) 2017-02-06 2022-06-14 Alliance For Sustainable Energy, Llc Doped passivated contacts
CN108831953A (zh) * 2017-05-04 2018-11-16 上海凯世通半导体股份有限公司 太阳能电池的制作方法
CN109755330B (zh) * 2018-12-27 2020-11-24 中国科学院宁波材料技术与工程研究所 用于钝化接触结构的预扩散片及其制备方法和应用
CN109755330A (zh) * 2018-12-27 2019-05-14 中国科学院宁波材料技术与工程研究所 用于钝化接触结构的预扩散片及其制备方法和应用
CN111477696A (zh) * 2020-04-07 2020-07-31 苏州腾晖光伏技术有限公司 一种基于钝化接触的太阳能电池片及其制备方法
CN114050105A (zh) * 2022-01-13 2022-02-15 海宁正泰新能源科技有限公司 一种TopCon电池的制备方法

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