WO2016045254A1 - Procédé de fabrication d'une couche mince de silicium polycristallin à basse température, couche mince de silicium polycristallin à basse température et dispositif l'utilisant - Google Patents

Procédé de fabrication d'une couche mince de silicium polycristallin à basse température, couche mince de silicium polycristallin à basse température et dispositif l'utilisant Download PDF

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Publication number
WO2016045254A1
WO2016045254A1 PCT/CN2015/070498 CN2015070498W WO2016045254A1 WO 2016045254 A1 WO2016045254 A1 WO 2016045254A1 CN 2015070498 W CN2015070498 W CN 2015070498W WO 2016045254 A1 WO2016045254 A1 WO 2016045254A1
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WIPO (PCT)
Prior art keywords
layer
low
temperature polysilicon
substrate
alkali metal
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PCT/CN2015/070498
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English (en)
Chinese (zh)
Inventor
张慧娟
刘建宏
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京东方科技集团股份有限公司
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Publication of WO2016045254A1 publication Critical patent/WO2016045254A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/30—Organic light-emitting transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour
    • H10K71/421—Thermal treatment, e.g. annealing in the presence of a solvent vapour using coherent electromagnetic radiation, e.g. laser annealing

Definitions

  • the invention relates to the field of display panel manufacturing, in particular to a low-temperature polysilicon film and a manufacturing method thereof, a low-temperature polysilicon thin film transistor, an array substrate and a display device.
  • OLEDs Organic light-emitting displays
  • AMOLED active matrix organic light-emitting display
  • polycrystalline silicon thin film transistors are often used in AMOLED backplane technology.
  • the polysilicon thin film transistor has the advantages of low power consumption and large electron mobility.
  • Early polysilicon thin film transistors have process temperatures as high as 1000 ° C, so the choice of substrate material is greatly limited. Recently, due to the development of lasers, the process temperature of polysilicon thin film transistors can be reduced to below 600 ° C.
  • Polycrystalline silicon thin film transistors fabricated by such a process are also referred to as low temperature polysilicon thin film transistors (LTPS TFTs).
  • one of the steps is to form a polysilicon film on the substrate, and the subsequent process will form the source/drain regions and the channel region of the thin film transistor based on the polysilicon film.
  • the key technology for LTPS TFT fabrication is the crystallization method for converting amorphous silicon into polycrystalline silicon.
  • These methods can be divided into two types: non-laser crystallization and laser annealing.
  • non-laser crystallization method the simplest method is solid phase crystallization (SPC), but SPC needs to be annealed at 600 ° C for 10 hr, which is not suitable for large-area glass substrates.
  • SPC solid phase crystallization
  • laser annealing methods the most widely used is excimer laser annealing (ELA) because of its extremely high crystallinity, fast crystallization rate, and high mobility.
  • ELA excimer laser annealing
  • the electrical properties of the low temperature polysilicon thin film transistor include mobility, mobility, and threshold voltage stability.
  • the input voltage corresponding to the midpoint of the turning region in which the output voltage of the thin film transistor transmission characteristic curve abruptly changes with the change of the input voltage is generally referred to as a threshold voltage.
  • the threshold voltage of a thin film transistor is related to many factors including the doping of the underlying crystalline silicon layer, the thickness of the dielectric, the gate material, and the state of charge at the interface of the dielectric or dielectric and the semiconductor.
  • movable alkali metal ions Na + , etc.
  • the polysilicon film prepared by the prior art often contains more movable alkali metal ions, so that the threshold voltage drift of the thin film transistor made of the polysilicon film affects the performance of the thin film transistor.
  • embodiments of the present invention provide a low temperature polysilicon film and a method for fabricating the same, a low temperature polysilicon thin film transistor, an array substrate, and a display device for reducing alkali metal ions in a low temperature polysilicon film, thereby effectively preventing low temperature polysilicon thin film transistors Threshold voltage drift.
  • a method for fabricating a low temperature polysilicon film including the following steps:
  • Excimer laser annealing is performed on the substrate on which the alkali metal ion adsorption layer is formed, and the amorphous silicon layer is converted into a polysilicon layer;
  • the alkali metal ion adsorption layer is removed to form a polysilicon film on the substrate.
  • the material of the alkali metal ion adsorption layer may be, for example, a phosphosilicate glass.
  • forming an alkali metal ion adsorption layer on the amorphous silicon layer includes the following steps:
  • P is doped into the SiO 2 film by ion implantation to form a phosphosilicate glass layer.
  • the thickness of the SiO 2 film may be, for example, 80 to 150 nm.
  • ion implantation may be performed using a phosphine gas, and P may be doped into the SiO 2 film, and an implantation energy at the time of ion implantation is 15 to 25 keV, and an implantation concentration is 0.8 to 1.2 E 15 /cm 2 .
  • the substrate on which the alkali metal ion adsorption layer is formed is subjected to an excimer laser Annealing includes the following steps:
  • the substrate on which the phosphosilicate glass layer was formed was subjected to laser annealing at a laser pulse frequency of 500 Hz and a laser energy density of 350 to 450 mJ/cm 2 .
  • removing the alkali metal ion absorbing layer includes the following steps:
  • the substrate subjected to excimer laser annealing is treated with a hydrofluoric acid solution having a concentration of 1-5 wt% to remove the phosphosilicate glass layer on the substrate.
  • a step of forming a buffer layer on the substrate is further included before forming the amorphous silicon layer, and then the amorphous silicon layer is formed on the buffer layer.
  • the amorphous silicon layer may have a thickness of, for example, 40 to 80 nm.
  • a low temperature polysilicon film which is fabricated by the above-described fabrication method.
  • a low temperature polysilicon thin film transistor which is produced by using the above low temperature polysilicon film.
  • an array substrate comprising the above-described low temperature polysilicon thin film transistor formed on a base substrate.
  • a display device comprising the above array substrate.
  • an alkali metal ion adsorption layer is formed on the amorphous silicon layer, so that when the excimer laser annealing is performed, the alkali metal ion adsorption layer can adsorb the formed polysilicon layer.
  • the alkali metal ion adsorption layer can also function as a heat insulating layer, which can make the temperature of the silicon layer uniform during the crystallization process, and is favorable for forming a polysilicon layer having a uniform grain size.
  • FIG. 1 is a schematic flow chart of a method for fabricating a low temperature polysilicon film according to an embodiment of the present invention
  • FIG. 2 is a schematic flow chart of a method for fabricating a low temperature polysilicon film according to a specific embodiment of the present invention
  • FIG. 3 is a schematic view showing ion implantation of a SiO 2 layer in a specific embodiment of the present invention.
  • FIG. 4 is a schematic view showing excimer laser annealing of a substrate on which a phosphosilicate glass layer is formed in a specific embodiment of the present invention.
  • Embodiments of the present invention provide a low temperature polysilicon film and a method for fabricating the same, a low temperature polysilicon thin film transistor, an array substrate, and a display device for reducing alkali metal ions in a low temperature polysilicon film, thereby effectively preventing threshold voltage drift of the low temperature polysilicon thin film transistor.
  • a method for fabricating a low temperature polysilicon film is provided. As shown in FIG. 1, the manufacturing method includes:
  • Step a forming an amorphous silicon layer on the substrate
  • Step b forming an alkali metal ion adsorption layer on the amorphous silicon layer
  • Step c performing excimer laser annealing on the substrate on which the alkali metal ion adsorption layer is formed, and converting the amorphous silicon layer into a polysilicon layer;
  • Step d removing the alkali metal ion adsorption layer to form a polysilicon film on the substrate.
  • an alkali metal ion adsorption layer is formed on the amorphous silicon layer, so that the polycrystalline silicon can be adsorbed by the alkali metal ion adsorption layer during excimer laser annealing.
  • the alkali metal ions in the layer reduce the alkali metal ions in the low-temperature polysilicon film, thereby effectively preventing the threshold voltage drift of the low-temperature polysilicon thin film transistor.
  • the alkali metal ion adsorption layer can also function as a heat insulating layer, so that the temperature of the silicon layer is uniform during the crystallization process, which is favorable for forming a polysilicon layer having a uniform grain size.
  • the material of the alkali metal ion adsorption layer may be, for example, a phosphosilicate glass.
  • Phosphorus silica glass is a SiO 2 containing P element which acts against alkali metal ions. In the PSG, a part of silicon in SiO 2 is replaced with a pentavalent phosphorus atom to form a negative electric center, thereby being capable of trapping an alkali metal ion such as Na + .
  • the step b includes:
  • P is doped into the SiO 2 film by ion implantation to form a phosphosilicate glass layer.
  • the thickness of the SiO 2 film may be, for example, 80 to 150 nm.
  • ion implantation may be performed using a phosphine gas, and P may be doped into the SiO 2 film, and the implantation energy at the time of ion implantation is, for example, 15 to 25 keV, and the implantation concentration is, for example, 0.8 to 1.2 E 15 /cm 2 .
  • the step c includes:
  • the substrate on which the phosphosilicate glass layer is formed is subjected to laser annealing, wherein the laser pulse frequency is, for example, 500 Hz, and the laser energy density is, for example, 350 to 450 mJ/cm 2 .
  • the alkali metal ion in the formed polysilicon layer can be adsorbed by the alkali metal ion adsorption layer, thereby reducing the alkali metal ions in the low temperature polysilicon film, thereby effectively preventing the threshold voltage drift of the low temperature polysilicon thin film transistor.
  • the step d includes:
  • the substrate subjected to the step c is treated with a hydrofluoric acid solution having a concentration of 1-5 wt% to remove the phosphosilicate glass layer on the substrate.
  • a step of forming a buffer layer on the substrate is further included, and then the amorphous silicon layer is formed on the buffer layer.
  • the amorphous silicon layer may have a thickness of, for example, 40 to 80 nm.
  • a low temperature polysilicon film which is fabricated by the above-described fabrication method.
  • a low temperature polysilicon thin film transistor which is produced by using the above low temperature polysilicon film.
  • an array substrate comprising the low temperature polysilicon thin film transistor as described above formed on a base substrate.
  • a display device comprising the array substrate as described above.
  • the display device may be, for example, a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED display panel, an OLED display, a digital photo frame, a mobile phone, a tablet computer, or the like, or any product or component having a display function.
  • the method for fabricating the low temperature polysilicon film of the present embodiment includes the following steps.
  • Step 21 A buffer layer 2 is deposited on the base substrate 1.
  • the base substrate 1 may be a glass substrate or a quartz substrate.
  • the buffer layer 2 may be a single layer structure or a two layer structure.
  • the upper layer of the buffer layer is a SiO 2 film
  • the lower layer of the buffer layer is a SiNx film.
  • the thickness of the SiNx film may be 50-150 nm
  • the thickness of the SiO 2 film may be 200-400 nm.
  • the buffer layer 2 has a single layer structure
  • the buffer layer 2 is a SiNx film or a SiO 2 film.
  • the thickness of the SiNx film may be 50-150 nm, and the thickness of the SiO 2 film may be 200-400 nm.
  • Step 22 depositing an amorphous silicon layer 3 on the buffer layer 2.
  • a layer of a-Si (amorphous silicon) is deposited on the buffer layer 2 to form an amorphous silicon layer 3.
  • the amorphous silicon layer 3 may have a thickness of 40 to 80 nm.
  • Step 23 depositing a thin film 4 of SiO 2 on the amorphous silicon layer 3.
  • the SiO 2 film 4 may have a thickness of 80 to 150 nm.
  • Step 24 P is doped into the SiO 2 film 4 by ion implantation using a phosphine gas.
  • P is doped into the SiO 2 film 4 at an implantation concentration of 0.8 to 1.2 E 15 /cm 2 at a implantation concentration of 15 to 25 keV using a phosphine gas PH 3 having a concentration of 10%. PSG layer.
  • the implantation energy at the time of ion implantation may be 20 keV, and the implantation concentration may be 1E 15 /cm 2 .
  • Step 25 Excimer laser annealing is performed on the substrate subjected to the above steps as shown in FIG.
  • the laser pulse frequency may be 500 Hz
  • the laser energy density may be 350-450 mJ/cm 2 .
  • the crystallization process of the amorphous silicon to the polycrystalline silicon is completed, and the PSG layer absorbs the alkali metal ions in the crystalline silicon layer, thereby reducing the alkali metal ions in the formed low-temperature polysilicon film, thereby effectively preventing the use of the Threshold voltage drift of a low temperature polysilicon thin film transistor made of a low temperature polysilicon film.
  • the PSG layer can also function as a heat insulating layer, which can make the temperature of the silicon layer uniform during the crystallization process, and is favorable for forming a polysilicon layer having a uniform grain size.
  • Step 26 The PSG layer was removed in the HF solution.
  • Hydrofluoric acid is capable of dissolving silica to form gaseous silicon tetrafluoride but does not react directly with silicon. Therefore, this embodiment utilizes a hydrofluoric acid solution having a concentration of 1-5 wt% for the substrate subjected to step 25 Process it.
  • the PSG layer formed on the substrate was placed face down in a pickling apparatus, and the PSG layer was removed using a roller with a hydrofluoric acid solution.
  • a protective film may be coated on the surface of the glass substrate.
  • the processing time can be, for example, 10-60 s, and the PSG layer on the polysilicon layer can be removed to obtain a polysilicon film.
  • the technical solution of the embodiment makes the process of adsorbing alkali metal ions by PSG and the excimer laser annealing process simultaneously, and the process is simple and easy to operate.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un procédé de fabrication d'une couche mince de silicium polycristallin à basse température, une couche mince de silicium polycristallin à basse température et un dispositif l'utilisant, qui concernent le domaine de la fabrication de panneau d'affichage. Le procédé de fabrication d'une couche mince de silicium polycristallin à basse température comprend les étapes suivantes : la formation d'une couche de silicium amorphe (3) sur un substrat (1) ; la formation d'une couche d'adsorption d'ions de métal alcalin (4) sur la couche de silicium amorphe (3) ; la réalisation d'un recuit laser quasi moléculaire sur le substrat (1) sur lequel est formée la couche d'adsorption d'ions de métal alcalin (4), pour convertir la couche de silicium amorphe (3) en une couche de silicium polycristallin ; et le retrait de la couche d'adsorption d'ions de métal alcalin (4) pour former une couche mince de silicium polycristallin sur le substrat (1).
PCT/CN2015/070498 2014-09-23 2015-01-12 Procédé de fabrication d'une couche mince de silicium polycristallin à basse température, couche mince de silicium polycristallin à basse température et dispositif l'utilisant WO2016045254A1 (fr)

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CN201410492155.1A CN104253246B (zh) 2014-09-23 2014-09-23 低温多晶硅薄膜的制作方法、低温多晶硅薄膜及相关器件
CN201410492155.1 2014-09-23

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CN104253246B (zh) * 2014-09-23 2016-08-17 京东方科技集团股份有限公司 低温多晶硅薄膜的制作方法、低温多晶硅薄膜及相关器件
CN110085511A (zh) * 2019-04-08 2019-08-02 深圳市华星光电技术有限公司 多晶硅薄膜的制备方法和薄膜晶体管

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CN1260809C (zh) * 2003-03-25 2006-06-21 旺宏电子股份有限公司 集成电路护层及其制造方法
KR100965778B1 (ko) * 2008-01-16 2010-06-24 서울대학교산학협력단 고효율 다결정 실리콘 태양전지 및 그 제조방법
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CN102655089B (zh) * 2011-11-18 2015-08-12 京东方科技集团股份有限公司 一种低温多晶硅薄膜的制作方法
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US20020105029A1 (en) * 2001-02-02 2002-08-08 Po-Sheng Shih Poly-silicon thin film transistor and method for fabricating thereof
US20020192884A1 (en) * 2001-03-06 2002-12-19 United Microelectronics Corp. Method for forming thin film transistor with reduced metal impurities
CN1512248A (zh) * 2002-12-28 2004-07-14 Lg.菲利浦Lcd株式会社 薄膜晶体管阵列衬底及其制造方法
CN102683338A (zh) * 2011-09-13 2012-09-19 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板及其制造方法
CN104253246A (zh) * 2014-09-23 2014-12-31 京东方科技集团股份有限公司 低温多晶硅薄膜的制作方法、低温多晶硅薄膜及相关器件

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