WO2016038986A1 - Image pickup device - Google Patents

Image pickup device Download PDF

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Publication number
WO2016038986A1
WO2016038986A1 PCT/JP2015/068690 JP2015068690W WO2016038986A1 WO 2016038986 A1 WO2016038986 A1 WO 2016038986A1 JP 2015068690 W JP2015068690 W JP 2015068690W WO 2016038986 A1 WO2016038986 A1 WO 2016038986A1
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Prior art keywords
amplification transistor
transistor
imaging device
imaging apparatus
semiconductor
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PCT/JP2015/068690
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French (fr)
Japanese (ja)
Inventor
悠介 東
鈴木　正道
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株式会社 東芝
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Publication of WO2016038986A1 publication Critical patent/WO2016038986A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • Embodiments described herein relate generally to an imaging apparatus.
  • CMOS Complementary Metal Oxide Semiconductor
  • the pixel area is reduced in order to improve the resolution.
  • the size of the transistor included in the pixel is also reduced, but this increases the noise of the transistor.
  • Embodiments provide an imaging apparatus capable of reducing noise.
  • the imaging device includes a photoelectric conversion element and an amplification transistor that amplifies a signal from the photoelectric conversion element.
  • the amplification transistor has a buried channel structure and a structure capable of adjusting a threshold value.
  • FIG. 1 is a block diagram of an imaging apparatus according to a first embodiment.
  • FIG. 2 is a circuit diagram of the pixel shown in FIG. 1.
  • FIG. 2 is a cross-sectional view of the pixel shown in FIG. 1.
  • FIG. 5 is a schematic diagram illustrating a writing operation of an amplification transistor. The graph explaining the threshold value change of an amplification transistor.
  • 6 is a flowchart for explaining the operation of the imaging apparatus according to the first embodiment.
  • 9 is a flowchart for explaining the operation of the imaging apparatus according to the second embodiment.
  • 9 is a flowchart for explaining the operation of an imaging apparatus according to a third embodiment.
  • FIG. 1 is a block diagram of an imaging device 10 according to the first embodiment.
  • the imaging device 10 includes a pixel array unit 12, a row selection circuit 13, a plurality of signal processing circuits 14, a column selection circuit 16, an output circuit 17, a voltage generation circuit 18, and a control circuit 19.
  • the pixel array unit 12 includes a plurality of pixels 11 arranged in a matrix. Each pixel 11 includes a photoelectric conversion element. A specific configuration of the pixel 11 will be described later.
  • a plurality of control signal line groups 20, a plurality of write line groups 21, and a plurality of vertical signal lines 22 are disposed.
  • the control signal line group 20 includes control signal lines that send a transfer signal TRA, a reset signal RES, and a selection signal SEL, which will be described later, to the pixel array unit 12.
  • the write line group 21 includes write lines that send write signals PG 1 and PG 2 to be described later to the pixel array unit 12.
  • the row selection circuit 13 sequentially scans the rows of the pixel array unit 12.
  • the row selection circuit 13 sends a control signal and a write signal to the selected row.
  • the plurality of signal processing circuits 14 are connected to the plurality of vertical signal lines 22, respectively. Each signal processing circuit 14 processes a signal read from the pixel.
  • the signal processing circuit 14 includes an AD converter 15 that converts an analog signal into a digital signal.
  • the signal processing circuit 14 includes a CDS (Correlated Sampling) circuit, a column selection switch, and the like.
  • the column selection circuit 16 selects a column of the pixel array unit 12 and sends a column selection signal to the signal processing circuit 14.
  • the output circuit 17 is connected to the plurality of signal processing circuits 14 via the horizontal signal line 23.
  • the output circuit 17 is composed of, for example, a buffer, and outputs the pixel signal sent from the signal processing circuit 14 to the outside.
  • the voltage generation circuit 18 generates a plurality of voltages necessary for various operations of the imaging device 10.
  • the control circuit 19 comprehensively controls the operation of the imaging device 10.
  • FIG. 2 is a circuit diagram of the pixel 11 shown in FIG.
  • the pixel 11 includes a photoelectric conversion element 30, a floating diffusion FD as a charge storage region, a transfer transistor 31, a reset transistor 32, an amplification transistor 33, a first selection transistor 34, a second selection transistor 35, a first write transistor 37, a second A write transistor 38 and a third write transistor 39 are provided.
  • the transistors 31 to 35 and 37 to 39 for example, N-channel MOS transistors are used.
  • the photoelectric conversion element 30 is composed of, for example, a photodiode.
  • the photodiode 30 converts incident light into electric charges (electrons) and accumulates them.
  • the anode of the photodiode 30 is grounded.
  • the transfer transistor 31 has one end of the current path connected to the cathode of the photodiode 30 and the other end of the current path connected to the floating diffusion FD.
  • the transfer signal TRA is supplied from the control circuit 19 to the gate of the transfer transistor 31 via the control signal line.
  • the transfer transistor 31 transfers the charge accumulated in the photodiode 30 to the floating diffusion FD when the transfer signal TRA is asserted.
  • the reset transistor 32 has one end of the current path connected to the power supply terminal Vdd and the other end of the current path connected to the floating diffusion FD.
  • a reset signal RES is supplied from the control circuit 19 to the gate of the reset transistor 32 via a control signal line.
  • the reset transistor 32 sets the voltage of the floating diffusion FD to the power supply voltage Vdd when the reset signal RES is asserted.
  • the amplification transistor 33 has one end (drain) of the current path connected to the power supply terminal Vdd via the first selection transistor 34, the other end (source) of the current path connected to the vertical signal line 22, and a gate connected to the floating diffusion FD. Connected to.
  • the vertical signal line 22 is connected to a constant current source 36 as a load element through a second selection transistor 35.
  • the amplification transistor 33 constitutes a source follower circuit, and the voltage of the vertical signal line 22 follows the voltage fluctuation of the floating diffusion FD. As a result, a voltage corresponding to the charge amount (signal) of the floating diffusion FD and determined by the gate voltage of the amplification transistor 33 appears on the vertical signal line 22.
  • the amplifying transistor 33 is composed of a buried channel transistor whose threshold (threshold voltage) can be adjusted. A specific structure of the amplification transistor 33 will be described later.
  • the selection signal SEL is supplied from the control circuit 19 to the gate of the first selection transistor 34 via the control signal line.
  • the first selection transistor 34 applies the power supply voltage Vdd to the drain of the amplification transistor 33 when the selection signal SEL is asserted.
  • a selection signal SEL is supplied from the control circuit 19 to the gate of the second selection transistor 35 via a control signal line.
  • the second selection transistor 35 connects the constant current source 36 to the source of the amplification transistor 33 when the selection signal SEL is asserted.
  • the pixel 11 further includes a writing circuit.
  • the write circuit is for adjusting the threshold value of the amplification transistor 33, and includes a first write transistor 37, a second write transistor 38, and a third write transistor 39.
  • the transistors 37 to 39 function as switching elements.
  • the first write transistor 37 has one end of the current path connected to the power supply terminal Vpgm and the other end of the current path connected to the gate of the amplification transistor 33.
  • a write signal PG1 is supplied from the control circuit 19 to the gate of the first write transistor 37 via a write line.
  • the first write transistor 37 applies the write voltage Vpgm to the gate of the amplification transistor 33 when the write signal PG1 is asserted.
  • one end of the current path is connected to the power supply terminal Vdp, and the other end of the current path is connected to the drain of the amplification transistor 33.
  • a write signal PG2 is supplied from the control circuit 19 to the gate of the second write transistor 38 via a write line.
  • the second write transistor 38 applies the drain voltage Vdp to the drain of the amplification transistor 33 when the write signal PG2 is asserted.
  • the third write transistor 39 one end of the current path is connected to the source of the amplification transistor 33, and the other end of the current path is grounded.
  • a write signal PG ⁇ b> 2 is supplied from the control circuit 19 to the gate of the third write transistor 39 via the write line.
  • the third write transistor 39 applies the ground voltage Vss (0 V) to the source of the amplification transistor 33 when the write signal PG ⁇ b> 2 is asserted.
  • FIG. 3 is a cross-sectional view of the pixel 11 shown in FIG.
  • An element isolation insulating layer 42 is provided on a surface region of a semiconductor substrate as a semiconductor layer, for example, a P-type semiconductor substrate 41.
  • a photodiode 30 is provided in the P-type semiconductor substrate 41.
  • the photodiode 30 includes an N + type semiconductor region 30A and a P + type semiconductor region 30B. By forming the P + -type semiconductor region 30B on the N + -type semiconductor region 30A, the photodiode 30 can be embedded, and dark current generated on the substrate surface can be reduced.
  • the floating diffusion FD is composed of an N + type semiconductor region.
  • a transfer transistor 31 is provided between the photodiode 30 and the floating diffusion FD.
  • the transfer transistor 31 includes a gate insulating film 31A and a gate electrode 31B.
  • the amplification transistor 33 is composed of a buried channel transistor whose threshold value can be adjusted.
  • a memory transistor flash memory cell having a charge storage layer is used.
  • the amplifying transistor 33 includes a source region 33A and a drain region 33B that are provided separately in the semiconductor substrate 41, and a buried channel (channel dope region) 33C that is provided between the source region 33A and the drain region 33B. And a gate.
  • the buried channel 33C is provided in the surface region of the semiconductor substrate 41 and is in contact with the source region 33A and the drain region 33B.
  • the source region 33A and the drain region 33B are composed of N + type semiconductor regions, and the buried channel 33C is composed of an N ⁇ type semiconductor region.
  • the stacked gate of the amplification transistor 33 is configured by stacking a first insulating film 33D, a charge storage layer 33E, a second insulating film 33F, and a control gate electrode 33G.
  • the first insulating film 33D is called a tunnel insulating film.
  • the amplification transistor 33 may be any of a floating gate type, a MONOS (Metal-Oxide-Nitride-Silicon) type, and a SONOS (Silicon-Oxide-Nitride-Silicon) type.
  • the charge storage layer 33E is a floating gate electrode made of polycrystalline silicon or the like, and the second insulating film 33F is called an inter-gate insulating film.
  • the charge storage layer 33E is an insulating film made of silicon nitride or the like, and the second insulating film 33F is called a block insulating film.
  • An interlayer insulating layer 43 is provided on the semiconductor substrate 41, and a wiring layer (not shown) is provided on the interlayer insulating layer 43.
  • a color filter 44 is provided on the back side of the semiconductor substrate 41, and a condensing lens 45 is provided on the color filter 44. That is, the imaging apparatus of FIG.
  • FIG. 4 is a schematic diagram for explaining the write operation of the amplification transistor 33.
  • the threshold value of the amplification transistor 33 is adjusted by programming the amplification transistor 33.
  • the writing (programming) of the amplification transistor 33 is performed by hot carrier injection, for example.
  • the control circuit 19 asserts the write signal PG2, and thereby the second write transistor 38 and the third write transistor 39 are turned on.
  • the control circuit 19 asserts the write signal PG1, thereby turning on the first write transistor 37.
  • Vpgm for example, about 10 V
  • the control circuit 19 can perform control so that the transfer transistor 31 is turned off.
  • FIG. 5 is a graph for explaining a change in threshold value of the amplification transistor 33. Since the amplification transistor 33 is a buried channel transistor, it is a depletion type that is turned on when the gate voltage is 0V. That is, in the erased state where the amplification transistor 33 is not programmed, the threshold value of the amplification transistor 33 is relatively low. On the other hand, when the amplification transistor 33 is programmed, the threshold value of the amplification transistor 33 becomes relatively high, and the amplification transistor 33 can perform the same operation as the enhancement type.
  • the threshold value lowered by the buried channel can be increased, and the amplifying transistor 33 can be operated under a normal bias condition.
  • the erase operation of the amplification transistor 33 is performed as follows.
  • the erasing operation is performed by, for example, FN (Fowler-Nordheim) tunneling.
  • the second write transistor 38 and the third write transistor 39 are turned off. Subsequently, 0 V is applied to the semiconductor substrate 41 shown in FIG. 4 (or a well formed in the semiconductor substrate 41). Subsequently, the first write transistor 37 is turned on, and an erase voltage Vera is applied to the drain of the first write transistor 37 instead of Vpgm.
  • the erase voltage Vera is a negative voltage, for example, about ⁇ 20V.
  • FIG. 6 is a flowchart for explaining the operation of the imaging apparatus 10 according to the first example.
  • the imaging device 10 is manufactured as a semiconductor chip (step S100). Subsequently, the control circuit 19 performs a write operation for adjusting the threshold value of the amplification transistor 33 (step S101). This write operation is as described with reference to FIGS. Subsequently, the imaging device 10 is shipped from the factory (step S102).
  • the threshold value of the amplification transistor 33 may be adjusted before shipment from the factory.
  • the first embodiment is effective when the retention characteristic of the amplification transistor 33 is good.
  • FIG. 7 is a flowchart for explaining the operation of the imaging apparatus 10 according to the second embodiment.
  • the imaging device 10 is assumed to be mounted on a camera.
  • the control circuit 19 performs a verify operation for confirming the threshold value of the amplification transistor 33 (step S201).
  • the control circuit 19 executes a normal read mode, and further measures the source voltage of the amplification transistor 33 via the vertical signal line 22. Thereby, the threshold value of the amplification transistor 33 can be confirmed.
  • the control circuit 19 determines whether or not the threshold value confirmed in step S201 is within an allowable range (step S202).
  • the allowable range of the threshold can be arbitrarily set according to the specification of the imaging device 10, and is set to be equivalent to the characteristics of the N-channel MOS transistor included in the pixel, for example. If it is not within the allowable range in step S202, the control circuit 19 performs a write operation for adjusting the threshold value of the amplification transistor 33 (step S203). On the other hand, if it is within the allowable range in step S202, the write operation in step S203 is skipped.
  • control circuit 19 performs a normal operation according to the user's operation (step S204). Subsequently, the user turns off the camera (step S205).
  • the threshold value of the amplification transistor 33 may be adjusted each time the power supply of the imaging device 10 is turned on. According to the second embodiment, the threshold value of the amplification transistor 33 can be maintained at a desired value.
  • FIG. 8 is a flowchart for explaining the operation of the imaging apparatus 10 according to the third example.
  • the camera is turned on by the user (step S300). Subsequently, the control circuit 19 performs a normal operation according to the user's operation (step S301). Subsequently, the control circuit 19 receives a power-off signal from, for example, a controller of a camera on which the imaging device 10 is mounted (step S302).
  • control circuit 19 performs a verify operation for confirming the threshold value of the amplification transistor 33 (step S303). Subsequently, the control circuit 19 determines whether or not the threshold value confirmed in step S303 is within an allowable range (step S304). If it is not within the allowable range in step S304, the control circuit 19 performs a write operation for adjusting the threshold value of the amplification transistor 33 (step S305). On the other hand, if it is within the allowable range in step S304, the write operation in step S305 is skipped. Subsequently, the camera is turned off (step S306).
  • the threshold value of the amplification transistor 33 may be adjusted immediately before the power of the camera on which the imaging device 10 is mounted is turned off.
  • the pixel 11 includes the amplification transistor 33 that amplifies the charge of the photodiode 30.
  • the amplification transistor 33 has a buried channel structure and a structure capable of adjusting a threshold value.
  • the channel of the amplification transistor 33 can be separated from the interface state which is a noise source. Therefore, since the noise of the amplification transistor 33 can be reduced, the operating characteristics of the imaging device 10 can be improved. In addition, the size of the amplification transistor 33 can be further reduced, and the photodiode 30 can be configured to be larger by the reduction. As a result, the sensitivity of the pixel 11 can be improved.
  • the threshold value of the amplification transistor 33 can be set to an arbitrary value, the amplification transistor 33 can be operated under the same bias condition as that of a normal MOS transistor (surface channel transistor). This eliminates the need to change the operating voltage (bias condition) of the amplification transistor 33 in normal operation.
  • the threshold value of the transistor shifts to the negative side, and a current flows even when the voltage between the gate and the source is 0 V, which causes a problem in the operation of the imaging device.
  • the AD converter 15 shown in FIG. FIG. 9 is a circuit diagram of the comparator 50 included in the AD converter 15.
  • the comparator 50 includes P-channel MOS transistors 51, 52, and 57, N-channel MOS transistors 53 and 54, and constant current sources 55 and 58.
  • the transistors 53 and 54 are constituted by buried channel transistors whose thresholds can be adjusted.
  • the structure of the transistors 53 and 54 is the same as that of the amplification transistor 33 in FIG.
  • the semiconductor layer in which the transistors 53 and 54 are formed may be the same as or different from the semiconductor layer (P-type semiconductor substrate 41) in which the amplification transistor 33 is formed.
  • Transistors 51 and 52 constitute a current mirror circuit.
  • the transistor 51 has a source connected to the power supply terminal Vdd and a gate connected to the drain.
  • the transistor 52 has a source connected to the power supply terminal Vdd and a gate connected to the gate of the transistor 51.
  • the drain is connected to the drain of the transistor 51, the source is connected to the constant current source 55, and the input voltage Vin1 is input to the gate.
  • the drain is connected to the connection node 59 and the drain of the transistor 52, the source is connected to the constant current source 55, and the input voltage Vin2 is input to the gate.
  • the transistor 57 and the constant current source 58 constitute an output circuit.
  • the transistor 57 has a source connected to the power supply terminal Vdd, a gate connected to the connection node 59, and a drain connected to the output terminal 56 and the constant current source 58.
  • the comparator 50 configured as described above compares the input voltage Vin1 and the input voltage Vin2, and outputs the comparison result from the output terminal 56.
  • the noise of the transistors 53 and 54 included in the AD converter 15 can be reduced. Thereby, the operating characteristic of the imaging device 10 can be improved.
  • the size of the transistors 53 and 54 can be reduced while reducing the noise. Thereby, the size of the AD converter 15 can be reduced.
  • DESCRIPTION OF SYMBOLS 10 ... Imaging device, 11 ... Pixel, 12 ... Pixel array part, 13 ... Row selection circuit, 14 ... Signal processing circuit, 15 ... AD converter, 16 ... Column selection circuit, 17 ... Output circuit, 18 ... Voltage generation circuit, 19 DESCRIPTION OF SYMBOLS ... Control circuit, 20 ... Control signal line group, 21 ... Write line group, 22 ... Vertical signal line, 23 ... Horizontal signal line, 30 ... Photoelectric conversion element, 31 ... Transfer transistor, 32 ... Reset transistor, 33 ... Amplification transistor, 34 ... selection transistor, 35 ... selection transistor, 36 ... constant current source, 37-39 ... writing transistor, 41 ... semiconductor substrate, 42 ... element isolation insulating layer, 43 ... interlayer insulating layer, 44 ... color filter, 45 ... lens, 50: Comparator, 51, 52, 57: P channel MOS transistor, 53, 54: N channel MOS transistor, 55, 58 A constant current source, 56 ... output terminal.

Abstract

To provide an image pickup device whereby noise can be reduced. An image pickup device (10) includes a photoelectric conversion element (30), and an amplifying transistor (33) that amplifies signals transmitted from the photoelectric conversion element (30). The amplifying transistor (33) has an embedded channel structure wherein a threshold value can be adjusted.

Description

撮像装置Imaging device
　本発明の実施形態は、撮像装置に関する。 Embodiments described herein relate generally to an imaging apparatus.
　撮像装置として、ＣＭＯＳ（Complementary Metal Oxide Semiconductor）イメージセンサーが知られている。ＣＭＯＳイメージセンサーでは、解像度を向上させるために、例えば画素の面積が縮小される。画素の縮小に伴い、画素に含まれるトランジスタのサイズも縮小されるが、これにより、トランジスタのノイズが大きくなってしまう。 A CMOS (Complementary Metal Oxide Semiconductor) image sensor is known as an imaging device. In the CMOS image sensor, for example, the pixel area is reduced in order to improve the resolution. As the size of the pixel is reduced, the size of the transistor included in the pixel is also reduced, but this increases the noise of the transistor.
特開２００８－１６６６０７号公報JP 2008-166607 A
　実施形態は、ノイズを低減することが可能な撮像装置を提供する。 Embodiments provide an imaging apparatus capable of reducing noise.
　実施形態に係る撮像装置は、光電変換素子と、前記光電変換素子からの信号を増幅する増幅トランジスタとを具備する。前記増幅トランジスタは、埋め込みチャネル構造を有し、かつ閾値の調整が可能な構造を有する。 The imaging device according to the embodiment includes a photoelectric conversion element and an amplification transistor that amplifies a signal from the photoelectric conversion element. The amplification transistor has a buried channel structure and a structure capable of adjusting a threshold value.
第１実施形態に係る撮像装置のブロック図。1 is a block diagram of an imaging apparatus according to a first embodiment. 図１に示した画素の回路図。FIG. 2 is a circuit diagram of the pixel shown in FIG. 1. 図１に示した画素の断面図。FIG. 2 is a cross-sectional view of the pixel shown in FIG. 1. 増幅トランジスタの書き込み動作を説明する模式図。FIG. 5 is a schematic diagram illustrating a writing operation of an amplification transistor. 増幅トランジスタの閾値変化を説明するグラフ。The graph explaining the threshold value change of an amplification transistor. 第１実施例に係る撮像装置の動作を説明するフローチャート。6 is a flowchart for explaining the operation of the imaging apparatus according to the first embodiment. 第２実施例に係る撮像装置の動作を説明するフローチャート。9 is a flowchart for explaining the operation of the imaging apparatus according to the second embodiment. 第３実施例に係る撮像装置の動作を説明するフローチャート。9 is a flowchart for explaining the operation of an imaging apparatus according to a third embodiment. ＡＤコンバータに含まれるコンパレータの回路図。The circuit diagram of the comparator contained in an AD converter.
　以下、実施形態について図面を参照して説明する。ただし、図面は模式的または概念的なものであり、各図面の寸法および比率などは必ずしも現実のものと同一とは限らない。以下に示す幾つかの実施形態は、本発明の技術思想を具体化するための装置および方法を例示したものであって、構成部品の形状、構造、配置などによって、本発明の技術思想が特定されるものではない。なお、以下の説明において、同一の機能及び構成を有する要素については、同一符号を付し、重複説明は必要な場合にのみ行う。 Hereinafter, embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions and ratios of the drawings are not necessarily the same as actual ones. The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is specified by the shape, structure, arrangement, etc. of components. Is not to be done. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.
　［第１実施形態］
　［１］撮像装置の全体構成
　図１は、第１実施形態に係る撮像装置１０のブロック図である。撮像装置１０は、画素アレイ部１２、行選択回路１３、複数の信号処理回路１４、列選択回路１６、出力回路１７、電圧発生回路１８、及び制御回路１９を備える。 [First Embodiment]
[1] Overall Configuration of Imaging Device FIG. 1 is a block diagram of an imaging device 10 according to the first embodiment. The imaging device 10 includes a pixel array unit 12, a row selection circuit 13, a plurality of signal processing circuits 14, a column selection circuit 16, an output circuit 17, a voltage generation circuit 18, and a control circuit 19.
　画素アレイ部１２は、行列状に配置された複数の画素１１を備える。各画素１１は、光電変換素子を含む。画素１１の具体的な構成については後述する。画素アレイ部１２には、複数の制御信号線群２０、複数の書き込み線群２１、及び複数の垂直信号線２２が配設される。制御信号線群２０は、後述する転送信号ＴＲＡ、リセット信号ＲＥＳ、及び選択信号ＳＥＬを画素アレイ部１２に送る制御信号線を備える。書き込み線群２１は、後述する書き込み信号ＰＧ１、ＰＧ２を画素アレイ部１２に送る書き込み線を備える。 The pixel array unit 12 includes a plurality of pixels 11 arranged in a matrix. Each pixel 11 includes a photoelectric conversion element. A specific configuration of the pixel 11 will be described later. In the pixel array unit 12, a plurality of control signal line groups 20, a plurality of write line groups 21, and a plurality of vertical signal lines 22 are disposed. The control signal line group 20 includes control signal lines that send a transfer signal TRA, a reset signal RES, and a selection signal SEL, which will be described later, to the pixel array unit 12. The write line group 21 includes write lines that send write signals PG 1 and PG 2 to be described later to the pixel array unit 12.
　行選択回路１３は、画素アレイ部１２の行（ロウ）を順次走査する。また、行選択回路１３は、選択された行に、制御信号及び書き込み信号を送る。 The row selection circuit 13 sequentially scans the rows of the pixel array unit 12. The row selection circuit 13 sends a control signal and a write signal to the selected row.
　複数の信号処理回路１４はそれぞれ、複数の垂直信号線２２に接続される。各信号処理回路１４は、画素から読み出された信号を処理する。信号処理回路１４は、アナログ信号をデジタル信号に変換するＡＤコンバータ１５を含む。その他、信号処理回路１４は、ＣＤＳ（Correlated Double Sampling：相関二重サンプリング）回路、及びカラム選択スイッチなどを含む。 The plurality of signal processing circuits 14 are connected to the plurality of vertical signal lines 22, respectively. Each signal processing circuit 14 processes a signal read from the pixel. The signal processing circuit 14 includes an AD converter 15 that converts an analog signal into a digital signal. In addition, the signal processing circuit 14 includes a CDS (Correlated Sampling) circuit, a column selection switch, and the like.
　列選択回路１６は、画素アレイ部１２の列（カラム）を選択し、カラム選択信号を信号処理回路１４に送る。出力回路１７は、水平信号線２３を介して、複数の信号処理回路１４に接続される。出力回路１７は、例えばバッファから構成され、信号処理回路１４から送られる画素信号を外部へ出力する。 The column selection circuit 16 selects a column of the pixel array unit 12 and sends a column selection signal to the signal processing circuit 14. The output circuit 17 is connected to the plurality of signal processing circuits 14 via the horizontal signal line 23. The output circuit 17 is composed of, for example, a buffer, and outputs the pixel signal sent from the signal processing circuit 14 to the outside.
　電圧発生回路１８は、撮像装置１０の各種動作に必要な複数の電圧を生成する。制御回路１９は、撮像装置１０の動作を統括的に制御する。 The voltage generation circuit 18 generates a plurality of voltages necessary for various operations of the imaging device 10. The control circuit 19 comprehensively controls the operation of the imaging device 10.
　［１－１］画素１１の回路構成
　次に、画素１１の回路構成について説明する。図２は、図１に示した画素１１の回路図である。画素１１は、光電変換素子３０、電荷蓄積領域としてのフローティングディフュージョンＦＤ、転送トランジスタ３１、リセットトランジスタ３２、増幅トランジスタ３３、第１選択トランジスタ３４、第２選択トランジスタ３５、第１書き込みトランジスタ３７、第２書き込みトランジスタ３８、及び第３書き込みトランジスタ３９を備える。トランジスタ３１～３５、３７～３９としては、例えばＮチャネルＭＯＳトランジスタが用いられる。 [1-1] Circuit Configuration of Pixel 11 Next, the circuit configuration of the pixel 11 will be described. FIG. 2 is a circuit diagram of the pixel 11 shown in FIG. The pixel 11 includes a photoelectric conversion element 30, a floating diffusion FD as a charge storage region, a transfer transistor 31, a reset transistor 32, an amplification transistor 33, a first selection transistor 34, a second selection transistor 35, a first write transistor 37, a second A write transistor 38 and a third write transistor 39 are provided. As the transistors 31 to 35 and 37 to 39, for example, N-channel MOS transistors are used.
　光電変換素子３０は、例えば、フォトダイオードから構成される。フォトダイオード３０は、入射光を電荷（電子）に変換して蓄積する。フォトダイオード３０のアノードは接地される。 The photoelectric conversion element 30 is composed of, for example, a photodiode. The photodiode 30 converts incident light into electric charges (electrons) and accumulates them. The anode of the photodiode 30 is grounded.
　転送トランジスタ３１は、電流経路の一端がフォトダイオード３０のカソードに接続され、電流経路の他端がフローティングディフュージョンＦＤに接続される。転送トランジスタ３１のゲートには、制御回路１９から、制御信号線を介して転送信号ＴＲＡが供給される。転送トランジスタ３１は、転送信号ＴＲＡがアサートされた場合に、フォトダイオード３０に蓄積された電荷を、フローティングディフュージョンＦＤに転送する。 The transfer transistor 31 has one end of the current path connected to the cathode of the photodiode 30 and the other end of the current path connected to the floating diffusion FD. The transfer signal TRA is supplied from the control circuit 19 to the gate of the transfer transistor 31 via the control signal line. The transfer transistor 31 transfers the charge accumulated in the photodiode 30 to the floating diffusion FD when the transfer signal TRA is asserted.
　リセットトランジスタ３２は、電流経路の一端が電源端子Ｖｄｄに接続され、電流経路の他端がフローティングディフュージョンＦＤに接続される。リセットトランジスタ３２のゲートには、制御回路１９から、制御信号線を介してリセット信号ＲＥＳが供給される。リセットトランジスタ３２は、リセット信号ＲＥＳがアサートされた場合に、フローティングディフュージョンＦＤの電圧を電源電圧Ｖｄｄに設定する。 The reset transistor 32 has one end of the current path connected to the power supply terminal Vdd and the other end of the current path connected to the floating diffusion FD. A reset signal RES is supplied from the control circuit 19 to the gate of the reset transistor 32 via a control signal line. The reset transistor 32 sets the voltage of the floating diffusion FD to the power supply voltage Vdd when the reset signal RES is asserted.
　増幅トランジスタ３３は、電流経路の一端（ドレイン）が第１選択トランジスタ３４を介して電源端子Ｖｄｄに接続され、電流経路の他端（ソース）が垂直信号線２２に接続され、ゲートがフローティングディフュージョンＦＤに接続される。垂直信号線２２は、第２選択トランジスタ３５を介して負荷素子としての定電流源３６に接続される。 The amplification transistor 33 has one end (drain) of the current path connected to the power supply terminal Vdd via the first selection transistor 34, the other end (source) of the current path connected to the vertical signal line 22, and a gate connected to the floating diffusion FD. Connected to. The vertical signal line 22 is connected to a constant current source 36 as a load element through a second selection transistor 35.
　増幅トランジスタ３３は、ソースフォロワ回路を構成し、垂直信号線２２の電圧は、フローティングディフュージョンＦＤの電圧変動に追従する。これにより、垂直信号線２２には、フローティングディフュージョンＦＤの電荷量（信号）に対応しかつ増幅トランジスタ３３のゲート電圧で決まる電圧が現れる。また、本実施形態では、増幅トランジスタ３３は、その閾値（閾値電圧）が調整可能な埋め込みチャネル型トランジスタから構成される。増幅トランジスタ３３の具体的な構造については後述する。 The amplification transistor 33 constitutes a source follower circuit, and the voltage of the vertical signal line 22 follows the voltage fluctuation of the floating diffusion FD. As a result, a voltage corresponding to the charge amount (signal) of the floating diffusion FD and determined by the gate voltage of the amplification transistor 33 appears on the vertical signal line 22. In this embodiment, the amplifying transistor 33 is composed of a buried channel transistor whose threshold (threshold voltage) can be adjusted. A specific structure of the amplification transistor 33 will be described later.
　第１選択トランジスタ３４のゲートには、制御回路１９から、制御信号線を介して選択信号ＳＥＬが供給される。第１選択トランジスタ３４は、選択信号ＳＥＬがアサートされた場合に、電源電圧Ｖｄｄを増幅トランジスタ３３のドレインに印加する。第２選択トランジスタ３５のゲートには、制御回路１９から、制御信号線を介して選択信号ＳＥＬが供給される。第２選択トランジスタ３５は、選択信号ＳＥＬがアサートされた場合に、増幅トランジスタ３３のソースに定電流源３６を接続する。 The selection signal SEL is supplied from the control circuit 19 to the gate of the first selection transistor 34 via the control signal line. The first selection transistor 34 applies the power supply voltage Vdd to the drain of the amplification transistor 33 when the selection signal SEL is asserted. A selection signal SEL is supplied from the control circuit 19 to the gate of the second selection transistor 35 via a control signal line. The second selection transistor 35 connects the constant current source 36 to the source of the amplification transistor 33 when the selection signal SEL is asserted.
　上記説明した基本回路に加えて、画素１１は、さらに書き込み回路を備える。書き込み回路は、増幅トランジスタ３３の閾値を調整するためのものであり、第１書き込みトランジスタ３７、第２書き込みトランジスタ３８、及び第３書き込みトランジスタ３９を備える。トランジスタ３７～３９は、スイッチング素子として機能する。 In addition to the basic circuit described above, the pixel 11 further includes a writing circuit. The write circuit is for adjusting the threshold value of the amplification transistor 33, and includes a first write transistor 37, a second write transistor 38, and a third write transistor 39. The transistors 37 to 39 function as switching elements.
　第１書き込みトランジスタ３７は、電流経路の一端が電源端子Ｖｐｇｍに接続され、電流経路の他端が増幅トランジスタ３３のゲートに接続される。第１書き込みトランジスタ３７のゲートには、制御回路１９から、書き込み線を介して書き込み信号ＰＧ１が供給される。第１書き込みトランジスタ３７は、書き込み信号ＰＧ１がアサートされた場合に、書き込み電圧Ｖｐｇｍを増幅トランジスタ３３のゲートに印加する。 The first write transistor 37 has one end of the current path connected to the power supply terminal Vpgm and the other end of the current path connected to the gate of the amplification transistor 33. A write signal PG1 is supplied from the control circuit 19 to the gate of the first write transistor 37 via a write line. The first write transistor 37 applies the write voltage Vpgm to the gate of the amplification transistor 33 when the write signal PG1 is asserted.
　第２書き込みトランジスタ３８は、電流経路の一端が電源端子Ｖｄｐに接続され、電流経路の他端が増幅トランジスタ３３のドレインに接続される。第２書き込みトランジスタ３８のゲートには、制御回路１９から、書き込み線を介して書き込み信号ＰＧ２が供給される。第２書き込みトランジスタ３８は、書き込み信号ＰＧ２がアサートされた場合に、ドレイン電圧Ｖｄｐを増幅トランジスタ３３のドレインに印加する。 In the second write transistor 38, one end of the current path is connected to the power supply terminal Vdp, and the other end of the current path is connected to the drain of the amplification transistor 33. A write signal PG2 is supplied from the control circuit 19 to the gate of the second write transistor 38 via a write line. The second write transistor 38 applies the drain voltage Vdp to the drain of the amplification transistor 33 when the write signal PG2 is asserted.
　第３書き込みトランジスタ３９は、電流経路の一端が増幅トランジスタ３３のソースに接続され、電流経路の他端が接地される。第３書き込みトランジスタ３９のゲートには、制御回路１９から、書き込み線を介して書き込み信号ＰＧ２が供給される。第３書き込みトランジスタ３９は、書き込み信号ＰＧ２がアサートされた場合に、接地電圧Ｖｓｓ（０Ｖ）を増幅トランジスタ３３のソースに印加する。 In the third write transistor 39, one end of the current path is connected to the source of the amplification transistor 33, and the other end of the current path is grounded. A write signal PG <b> 2 is supplied from the control circuit 19 to the gate of the third write transistor 39 via the write line. The third write transistor 39 applies the ground voltage Vss (0 V) to the source of the amplification transistor 33 when the write signal PG <b> 2 is asserted.
　［１－２］画素１１の断面構造
　次に、画素１１の断面構造について説明する。図３は、図１に示した画素１１の断面図である。 [1-2] Cross-sectional Structure of Pixel 11 Next, the cross-sectional structure of the pixel 11 will be described. FIG. 3 is a cross-sectional view of the pixel 11 shown in FIG.
　半導体層としての半導体基板、例えばＰ型半導体基板４１の表面領域には、素子分離絶縁層４２が設けられる。Ｐ型半導体基板４１内には、フォトダイオード３０が設けられる。フォトダイオード３０は、Ｎ＋型半導体領域３０Ａ及びＰ＋型半導体領域３０Ｂを備える。Ｎ＋型半導体領域３０Ａ上にＰ＋型半導体領域３０Ｂを形成することで、フォトダイオード３０が埋め込み型とされ、基板表面で発生する暗電流を低減することができる。 An element isolation insulating layer 42 is provided on a surface region of a semiconductor substrate as a semiconductor layer, for example, a P-type semiconductor substrate 41. A photodiode 30 is provided in the P-type semiconductor substrate 41. The photodiode 30 includes an N + type semiconductor region 30A and a P + type semiconductor region 30B. By forming the P + -type semiconductor region 30B on the N + -type semiconductor region 30A, the photodiode 30 can be embedded, and dark current generated on the substrate surface can be reduced.
　フローティングディフュージョンＦＤは、Ｎ＋型半導体領域から構成される。フォトダイオード３０とフローティングディフュージョンＦＤとの間には、転送トランジスタ３１が設けられる。転送トランジスタ３１は、ゲート絶縁膜３１Ａ及びゲート電極３１Ｂを備える。 The floating diffusion FD is composed of an N + type semiconductor region. A transfer transistor 31 is provided between the photodiode 30 and the floating diffusion FD. The transfer transistor 31 includes a gate insulating film 31A and a gate electrode 31B.
　前述したように、増幅トランジスタ３３は、閾値が調整可能な埋め込みチャネル型トランジスタから構成される。増幅トランジスタ３３としては、例えば、電荷蓄積層を有するメモリトランジスタ（フラッシュメモリセル）が用いられる。増幅トランジスタ３３は、半導体基板４１内に離間して設けられたソース領域３３Ａ及びドレイン領域３３Ｂと、ソース領域３３Ａ及びドレイン領域３３Ｂとの間に設けられた埋め込みチャネル（チャネルドープ領域）３３Ｃと、積層ゲートとを備える。埋め込みチャネル３３Ｃは、半導体基板４１の表面領域に設けられ、ソース領域３３Ａ及びドレイン領域３３Ｂに接している。ソース領域３３Ａ及びドレイン領域３３Ｂは、Ｎ＋型半導体領域から構成され、埋め込みチャネル３３Ｃは、Ｎ－型半導体領域から構成される。増幅トランジスタ３３の積層ゲートは、第１絶縁膜３３Ｄ、電荷蓄積層３３Ｅ、第２絶縁膜３３Ｆ、及び制御ゲート電極３３Ｇが積層されて構成される。第１絶縁膜３３Ｄは、トンネル絶縁膜と呼ばれる。 As described above, the amplification transistor 33 is composed of a buried channel transistor whose threshold value can be adjusted. As the amplification transistor 33, for example, a memory transistor (flash memory cell) having a charge storage layer is used. The amplifying transistor 33 includes a source region 33A and a drain region 33B that are provided separately in the semiconductor substrate 41, and a buried channel (channel dope region) 33C that is provided between the source region 33A and the drain region 33B. And a gate. The buried channel 33C is provided in the surface region of the semiconductor substrate 41 and is in contact with the source region 33A and the drain region 33B. The source region 33A and the drain region 33B are composed of N + type semiconductor regions, and the buried channel 33C is composed of an N − type semiconductor region. The stacked gate of the amplification transistor 33 is configured by stacking a first insulating film 33D, a charge storage layer 33E, a second insulating film 33F, and a control gate electrode 33G. The first insulating film 33D is called a tunnel insulating film.
　増幅トランジスタ３３は、フローティングゲート型、ＭＯＮＯＳ（Metal-Oxide-Nitride-Silicon）型、及びＳＯＮＯＳ（Silicon-Oxide-Nitride-Silicon）型のいずれでも良い。フローティングゲート型である場合、電荷蓄積層３３Ｅは、多結晶シリコンなどからなる浮遊ゲート電極であり、また、第２絶縁膜３３Ｆは、ゲート間絶縁膜と呼ばれる。ＭＯＮＯＳ型である場合、電荷蓄積層３３Ｅは、シリコン窒化物などからなる絶縁膜であり、また、第２絶縁膜３３Ｆは、ブロック絶縁膜と呼ばれる。 The amplification transistor 33 may be any of a floating gate type, a MONOS (Metal-Oxide-Nitride-Silicon) type, and a SONOS (Silicon-Oxide-Nitride-Silicon) type. In the case of the floating gate type, the charge storage layer 33E is a floating gate electrode made of polycrystalline silicon or the like, and the second insulating film 33F is called an inter-gate insulating film. In the case of the MONOS type, the charge storage layer 33E is an insulating film made of silicon nitride or the like, and the second insulating film 33F is called a block insulating film.
　半導体基板４１上には、層間絶縁層４３が設けられ、層間絶縁層４３上には、図示しない配線層が設けられる。半導体基板４１の裏面側には、カラーフィルター４４が設けられ、カラーフィルター４４上には、集光用のレンズ４５が設けられる。すなわち、図３の撮像装置は、裏面照射型の構成例である。 An interlayer insulating layer 43 is provided on the semiconductor substrate 41, and a wiring layer (not shown) is provided on the interlayer insulating layer 43. A color filter 44 is provided on the back side of the semiconductor substrate 41, and a condensing lens 45 is provided on the color filter 44. That is, the imaging apparatus of FIG.
　［２］増幅トランジスタ３３の書き込み動作
　次に、上記のように構成された撮像装置１０の動作について説明する。図４は、増幅トランジスタ３３の書き込み動作を説明する模式図である。 [2] Write Operation of Amplifying Transistor 33 Next, the operation of the imaging device 10 configured as described above will be described. FIG. 4 is a schematic diagram for explaining the write operation of the amplification transistor 33.
　本実施形態では、増幅トランジスタ３３をプログラムすることで、増幅トランジスタ３３の閾値を調整する。増幅トランジスタ３３の書き込み（プログラム）は、例えば、ホットキャリア注入により行われる。 In this embodiment, the threshold value of the amplification transistor 33 is adjusted by programming the amplification transistor 33. The writing (programming) of the amplification transistor 33 is performed by hot carrier injection, for example.
　図２を参照して、制御回路１９は、書き込み信号ＰＧ２をアサートし、これにより、第２書き込みトランジスタ３８及び第３書き込みトランジスタ３９がオンする。この結果、増幅トランジスタ３３のドレインにドレイン電圧Ｖｄ＝Ｖｄｐ（例えば４Ｖ程度）が印加され、増幅トランジスタ３３のソースにソース電圧Ｖｓ＝０Ｖが印加される。 Referring to FIG. 2, the control circuit 19 asserts the write signal PG2, and thereby the second write transistor 38 and the third write transistor 39 are turned on. As a result, the drain voltage Vd = Vdp (for example, about 4 V) is applied to the drain of the amplification transistor 33, and the source voltage Vs = 0 V is applied to the source of the amplification transistor 33.
　続いて、制御回路１９は、書き込み信号ＰＧ１をアサートし、これにより、第１書き込みトランジスタ３７がオンする。この結果、増幅トランジスタ３３の制御ゲートにゲート電圧Ｖｇ＝Ｖｐｇｍ（例えば１０Ｖ程度）が印加される。これにより、増幅トランジスタ３３の電荷蓄積層３３Ｅに電子が注入され、増幅トランジスタ３３の閾値が正側に変化する。ホットキャリア注入により書き込みを行うことで、電圧Ｖｐｇｍを低く抑えつつ、高効率な書き込みが可能となる。なお、書き込み動作において、フォトダイオード３０にＶｐｇｍが印加されないことが望ましく、この場合、制御回路１９は転送トランジスタ３１をＯＦＦ状態とするように制御を行うことができる。 Subsequently, the control circuit 19 asserts the write signal PG1, thereby turning on the first write transistor 37. As a result, the gate voltage Vg = Vpgm (for example, about 10 V) is applied to the control gate of the amplification transistor 33. As a result, electrons are injected into the charge storage layer 33E of the amplification transistor 33, and the threshold value of the amplification transistor 33 changes to the positive side. By performing writing by hot carrier injection, it is possible to perform highly efficient writing while keeping the voltage Vpgm low. In the write operation, it is desirable that Vpgm is not applied to the photodiode 30. In this case, the control circuit 19 can perform control so that the transfer transistor 31 is turned off.
　図５は、増幅トランジスタ３３の閾値変化を説明するグラフである。増幅トランジスタ３３は、埋め込みチャネル型トランジスタであるため、ゲート電圧が０Ｖでオン状態となるデプレッション型である。すなわち、増幅トランジスタ３３をプログラムしていない消去状態では、増幅トランジスタ３３の閾値が相対的に低い。一方、増幅トランジスタ３３をプログラムした場合、増幅トランジスタ３３の閾値が相対的に高くなり、増幅トランジスタ３３がエンハンスメント型と同じ動作を行うことが可能である。 FIG. 5 is a graph for explaining a change in threshold value of the amplification transistor 33. Since the amplification transistor 33 is a buried channel transistor, it is a depletion type that is turned on when the gate voltage is 0V. That is, in the erased state where the amplification transistor 33 is not programmed, the threshold value of the amplification transistor 33 is relatively low. On the other hand, when the amplification transistor 33 is programmed, the threshold value of the amplification transistor 33 becomes relatively high, and the amplification transistor 33 can perform the same operation as the enhancement type.
　このように、増幅トランジスタ３３をプログラムすることで、埋め込みチャネル化で低くなった閾値を高くでき、通常のバイアス条件下で増幅トランジスタ３３を動作させることが可能となる。 Thus, by programming the amplifying transistor 33, the threshold value lowered by the buried channel can be increased, and the amplifying transistor 33 can be operated under a normal bias condition.
　なお、増幅トランジスタ３３の消去動作は以下のように行われる。消去動作は、例えば、ＦＮ（Fowler-Nordheim）トンネリングにより行われる。 The erase operation of the amplification transistor 33 is performed as follows. The erasing operation is performed by, for example, FN (Fowler-Nordheim) tunneling.
　まず、第２書き込みトランジスタ３８及び第３書き込みトランジスタ３９は、オフされる。続いて、図４に示す半導体基板４１（或いは、半導体基板４１内に形成されたウェル）に０Ｖが印加される。続いて、第１書き込みトランジスタ３７がオンされると共に、第１書き込みトランジスタ３７のドレインには、Ｖｐｇｍに代えて消去電圧Ｖｅｒａが印加される。消去電圧Ｖｅｒａは、負電圧であり、例えば－２０Ｖ程度である。 First, the second write transistor 38 and the third write transistor 39 are turned off. Subsequently, 0 V is applied to the semiconductor substrate 41 shown in FIG. 4 (or a well formed in the semiconductor substrate 41). Subsequently, the first write transistor 37 is turned on, and an erase voltage Vera is applied to the drain of the first write transistor 37 instead of Vpgm. The erase voltage Vera is a negative voltage, for example, about −20V.
　このような電圧制御により、増幅トランジスタ３３の電荷蓄積層３３Ｅに蓄積された電子が半導体基板４１に引き抜かれる。これにより、増幅トランジスタ３３が消去される。 By such voltage control, electrons stored in the charge storage layer 33E of the amplification transistor 33 are extracted to the semiconductor substrate 41. As a result, the amplification transistor 33 is erased.
　［３］撮像装置１０の全体動作
　次に、撮像装置１０の全体動作について説明する。以下に、第１乃至第３実施例に係る撮像装置１０の動作を説明する。 [3] Overall Operation of Imaging Device 10 Next, the overall operation of the imaging device 10 will be described. Hereinafter, the operation of the imaging apparatus 10 according to the first to third embodiments will be described.
　［３－１］第１実施例
　図６は、第１実施例に係る撮像装置１０の動作を説明するフローチャートである。 [3-1] First Example FIG. 6 is a flowchart for explaining the operation of the imaging apparatus 10 according to the first example.
　まず、工場において、半導体チップとして撮像装置１０が作製される（ステップＳ１００）。続いて、制御回路１９は、増幅トランジスタ３３の閾値を調整するための書き込み動作を行う（ステップＳ１０１）。この書き込み動作は、図４及び図５を用いて説明した通りである。続いて、撮像装置１０が工場から出荷される（ステップＳ１０２）。 First, in the factory, the imaging device 10 is manufactured as a semiconductor chip (step S100). Subsequently, the control circuit 19 performs a write operation for adjusting the threshold value of the amplification transistor 33 (step S101). This write operation is as described with reference to FIGS. Subsequently, the imaging device 10 is shipped from the factory (step S102).
　このように、工場出荷前に増幅トランジスタ３３の閾値を調整するようにしても良い。第１実施例は、増幅トランジスタ３３のリテンション特性が良好である場合に有効である。 Thus, the threshold value of the amplification transistor 33 may be adjusted before shipment from the factory. The first embodiment is effective when the retention characteristic of the amplification transistor 33 is good.
　［３－２］第２実施例
　図７は、第２実施例に係る撮像装置１０の動作を説明するフローチャートである。撮像装置１０は、カメラに搭載されているものとする。 [3-2] Second Embodiment FIG. 7 is a flowchart for explaining the operation of the imaging apparatus 10 according to the second embodiment. The imaging device 10 is assumed to be mounted on a camera.
　まず、ユーザによりカメラの電源がオンされる（ステップＳ２００）。続いて、制御回路１９は、増幅トランジスタ３３の閾値を確認するためのベリファイ動作を行う（ステップＳ２０１）。このベリファイ動作では、制御回路１９は、通常の読み出しモードを実行し、さらに、増幅トランジスタ３３のソース電圧を垂直信号線２２を介して測定する。これにより、増幅トランジスタ３３の閾値を確認することができる。 First, the camera is turned on by the user (step S200). Subsequently, the control circuit 19 performs a verify operation for confirming the threshold value of the amplification transistor 33 (step S201). In this verify operation, the control circuit 19 executes a normal read mode, and further measures the source voltage of the amplification transistor 33 via the vertical signal line 22. Thereby, the threshold value of the amplification transistor 33 can be confirmed.
　続いて、制御回路１９は、ステップＳ２０１で確認した閾値が許容範囲内であるか否かを判定する（ステップＳ２０２）。閾値の許容範囲は、撮像装置１０の仕様に応じて任意に設定可能であり、例えば、画素に含まれるＮチャネルＭＯＳトランジスタの特性と同等になるように設定される。ステップＳ２０２において許容範囲内でない場合、制御回路１９は、増幅トランジスタ３３の閾値を調整するための書き込み動作を行う（ステップＳ２０３）。一方、ステップＳ２０２において許容範囲内である場合、ステップＳ２０３の書き込み動作がスキップされる。 Subsequently, the control circuit 19 determines whether or not the threshold value confirmed in step S201 is within an allowable range (step S202). The allowable range of the threshold can be arbitrarily set according to the specification of the imaging device 10, and is set to be equivalent to the characteristics of the N-channel MOS transistor included in the pixel, for example. If it is not within the allowable range in step S202, the control circuit 19 performs a write operation for adjusting the threshold value of the amplification transistor 33 (step S203). On the other hand, if it is within the allowable range in step S202, the write operation in step S203 is skipped.
　続いて、制御回路１９は、ユーザの操作に応じた通常動作を行う（ステップＳ２０４）。続いて、ユーザによりカメラの電源がオフされる（ステップＳ２０５）。 Subsequently, the control circuit 19 performs a normal operation according to the user's operation (step S204). Subsequently, the user turns off the camera (step S205).
　第２実施例のように、撮像装置１０の電源がオンされるごとに、増幅トランジスタ３３の閾値を調整するようにしても良い。第２実施例によれば、増幅トランジスタ３３の閾値を所望の値に維持することが可能である。 As in the second embodiment, the threshold value of the amplification transistor 33 may be adjusted each time the power supply of the imaging device 10 is turned on. According to the second embodiment, the threshold value of the amplification transistor 33 can be maintained at a desired value.
　［３－３］第３実施例
　図８は、第３実施例に係る撮像装置１０の動作を説明するフローチャートである。 [3-3] Third Example FIG. 8 is a flowchart for explaining the operation of the imaging apparatus 10 according to the third example.
　まず、ユーザによりカメラの電源がオンされる（ステップＳ３００）。続いて、制御回路１９は、ユーザの操作に応じた通常動作を行う（ステップＳ３０１）。続いて、制御回路１９は、例えば撮像装置１０が搭載されたカメラのコントローラからパワーオフ信号を受信する（ステップＳ３０２）。 First, the camera is turned on by the user (step S300). Subsequently, the control circuit 19 performs a normal operation according to the user's operation (step S301). Subsequently, the control circuit 19 receives a power-off signal from, for example, a controller of a camera on which the imaging device 10 is mounted (step S302).
　続いて、制御回路１９は、増幅トランジスタ３３の閾値を確認するためのベリファイ動作を行う（ステップＳ３０３）。続いて、制御回路１９は、ステップＳ３０３で確認した閾値が許容範囲内であるか否かを判定する（ステップＳ３０４）。ステップＳ３０４において許容範囲内でない場合、制御回路１９は、増幅トランジスタ３３の閾値を調整するための書き込み動作を行う（ステップＳ３０５）。一方、ステップＳ３０４において許容範囲内である場合、ステップＳ３０５の書き込み動作がスキップされる。続いて、カメラの電源がオフされる（ステップＳ３０６）。 Subsequently, the control circuit 19 performs a verify operation for confirming the threshold value of the amplification transistor 33 (step S303). Subsequently, the control circuit 19 determines whether or not the threshold value confirmed in step S303 is within an allowable range (step S304). If it is not within the allowable range in step S304, the control circuit 19 performs a write operation for adjusting the threshold value of the amplification transistor 33 (step S305). On the other hand, if it is within the allowable range in step S304, the write operation in step S305 is skipped. Subsequently, the camera is turned off (step S306).
　第３実施例のように、撮像装置１０が搭載されたカメラの電源がオフされる直前に、増幅トランジスタ３３の閾値を調整するようにしても良い。 As in the third embodiment, the threshold value of the amplification transistor 33 may be adjusted immediately before the power of the camera on which the imaging device 10 is mounted is turned off.
　［４］効果
　以上詳述したように第１実施形態では、画素１１は、フォトダイオード３０の電荷を増幅する増幅トランジスタ３３を備える。増幅トランジスタ３３は、埋め込みチャネル構造を有し、かつ閾値の調整が可能な構造を有する。 [4] Effect As described in detail above, in the first embodiment, the pixel 11 includes the amplification transistor 33 that amplifies the charge of the photodiode 30. The amplification transistor 33 has a buried channel structure and a structure capable of adjusting a threshold value.
　従って第１実施形態によれば、増幅トランジスタ３３のチャネルをノイズ源である界面準位から離すことができる。これにより、増幅トランジスタ３３のノイズを低減することができるため、撮像装置１０の動作特性を向上させることができる。また、増幅トランジスタ３３のサイズをより小さくすることが可能となり、その削減分だけフォトダイオード３０を大きく構成することが可能となる。この結果、画素１１の感度を向上させることが可能となる。 Therefore, according to the first embodiment, the channel of the amplification transistor 33 can be separated from the interface state which is a noise source. Thereby, since the noise of the amplification transistor 33 can be reduced, the operating characteristics of the imaging device 10 can be improved. In addition, the size of the amplification transistor 33 can be further reduced, and the photodiode 30 can be configured to be larger by the reduction. As a result, the sensitivity of the pixel 11 can be improved.
　また、増幅トランジスタ３３の閾値を任意の値に設定できるため、通常のＭＯＳトランジスタ（表面チャネル型トランジスタ）と同じバイアス条件で増幅トランジスタ３３を動作させることができる。これにより、通常動作において、増幅トランジスタ３３の動作電圧（バイアス条件）を変える必要がない。 Also, since the threshold value of the amplification transistor 33 can be set to an arbitrary value, the amplification transistor 33 can be operated under the same bias condition as that of a normal MOS transistor (surface channel transistor). This eliminates the need to change the operating voltage (bias condition) of the amplification transistor 33 in normal operation.
　一般的に、ＮチャネルＭＯＳトランジスタを埋め込みチャネル構造にすると、トランジスタの閾値が負側にシフトしてしまい、ゲート及びソース間の電圧が０Ｖでも電流が流れる状態となり、撮像装置の動作上問題がある。しかしながら、本実施形態の構成を用いることで、増幅トランジスタ３３のノイズを低減しつつ、増幅トランジスタ３３の動作電圧を最適に設定することが可能である。 In general, when an N-channel MOS transistor has a buried channel structure, the threshold value of the transistor shifts to the negative side, and a current flows even when the voltage between the gate and the source is 0 V, which causes a problem in the operation of the imaging device. . However, by using the configuration of this embodiment, it is possible to optimally set the operating voltage of the amplification transistor 33 while reducing the noise of the amplification transistor 33.
　［第２実施形態］
　第２実施形態は、信号処理回路１４内のＡＤコンバータ１５に含まれるトランジスタに、前述した増幅トランジスタ３３と同様に、閾値が調整可能な埋め込みチャネル型トランジスタを用いるようにしている。 [Second Embodiment]
In the second embodiment, as a transistor included in the AD converter 15 in the signal processing circuit 14, a buried channel transistor whose threshold value can be adjusted is used as in the case of the amplification transistor 33 described above.
　図１に示したＡＤコンバータ１５は、コンパレータ５０を備える。図９は、ＡＤコンバータ１５に含まれるコンパレータ５０の回路図である。コンパレータ５０は、ＰチャネルＭＯＳトランジスタ５１、５２、５７と、ＮチャネルＭＯＳトランジスタ５３、５４と、定電流源５５、５８とを備える。また、トランジスタ５３、５４は、閾値が調整可能な埋め込みチャネル型トランジスタから構成される。 The AD converter 15 shown in FIG. FIG. 9 is a circuit diagram of the comparator 50 included in the AD converter 15. The comparator 50 includes P- channel MOS transistors 51, 52, and 57, N-channel MOS transistors 53 and 54, and constant current sources 55 and 58. The transistors 53 and 54 are constituted by buried channel transistors whose thresholds can be adjusted.
　トランジスタ５３、５４の構造は、図３の増幅トランジスタ３３と同じである。トランジスタ５３、５４が形成される半導体層は、増幅トランジスタ３３が形成される半導体層（Ｐ型半導体基板４１）と同じであっても良いし、異なっていても良い。 The structure of the transistors 53 and 54 is the same as that of the amplification transistor 33 in FIG. The semiconductor layer in which the transistors 53 and 54 are formed may be the same as or different from the semiconductor layer (P-type semiconductor substrate 41) in which the amplification transistor 33 is formed.
　トランジスタ５１、５２は、カレントミラー回路を構成する。トランジスタ５１は、ソースが電源端子Ｖｄｄに接続され、ゲートがドレインに接続される。トランジスタ５２は、ソースが電源端子Ｖｄｄに接続され、ゲートがトランジスタ５１のゲートに接続される。 Transistors 51 and 52 constitute a current mirror circuit. The transistor 51 has a source connected to the power supply terminal Vdd and a gate connected to the drain. The transistor 52 has a source connected to the power supply terminal Vdd and a gate connected to the gate of the transistor 51.
　トランジスタ５３は、ドレインがトランジスタ５１のドレインに接続され、ソースが定電流源５５に接続され、ゲートには入力電圧Ｖｉｎ１が入力される。トランジスタ５４は、ドレインが接続ノード５９及びトランジスタ５２のドレインに接続され、ソースが定電流源５５に接続され、ゲートには入力電圧Ｖｉｎ２が入力される。 In the transistor 53, the drain is connected to the drain of the transistor 51, the source is connected to the constant current source 55, and the input voltage Vin1 is input to the gate. In the transistor 54, the drain is connected to the connection node 59 and the drain of the transistor 52, the source is connected to the constant current source 55, and the input voltage Vin2 is input to the gate.
　トランジスタ５７、及び定電流源５８は、出力回路を構成する。トランジスタ５７は、ソースが電源端子Ｖｄｄに接続され、ゲートが接続ノード５９に接続され、ドレインが出力端子５６及び定電流源５８に接続される。 The transistor 57 and the constant current source 58 constitute an output circuit. The transistor 57 has a source connected to the power supply terminal Vdd, a gate connected to the connection node 59, and a drain connected to the output terminal 56 and the constant current source 58.
　上記のように構成されたコンパレータ５０は、入力電圧Ｖｉｎ１と入力電圧Ｖｉｎ２とを比較し、比較結果を出力端子５６から出力する。 The comparator 50 configured as described above compares the input voltage Vin1 and the input voltage Vin2, and outputs the comparison result from the output terminal 56.
　第２実施形態によれば、ＡＤコンバータ１５に含まれるトランジスタ５３、５４のノイズを低減することができる。これにより、撮像装置１０の動作特性を向上させることができる。 According to the second embodiment, the noise of the transistors 53 and 54 included in the AD converter 15 can be reduced. Thereby, the operating characteristic of the imaging device 10 can be improved.
　また、トランジスタ５３、５４のノイズを低減しつつ、そのサイズを小さくすることができる。これにより、ＡＤコンバータ１５のサイズを小さくすることができる。 Moreover, the size of the transistors 53 and 54 can be reduced while reducing the noise. Thereby, the size of the AD converter 15 can be reduced.
　本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。 Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.
　１０…撮像装置、１１…画素、１２…画素アレイ部、１３…行選択回路、１４…信号処理回路、１５…ＡＤコンバータ、１６…列選択回路、１７…出力回路、１８…電圧発生回路、１９…制御回路、２０…制御信号線群、２１…書き込み線群、２２…垂直信号線、２３…水平信号線、３０…光電変換素子、３１…転送トランジスタ、３２…リセットトランジスタ、３３…増幅トランジスタ、３４…選択トランジスタ、３５…選択トランジスタ、３６…定電流源、３７～３９…書き込みトランジスタ、４１…半導体基板、４２…素子分離絶縁層、４３…層間絶縁層、４４…カラーフィルター、４５…レンズ、５０…コンパレータ、５１，５２，５７…ＰチャネルＭＯＳトランジスタ、５３，５４…ＮチャネルＭＯＳトランジスタ、５５，５８…定電流源、５６…出力端子。 DESCRIPTION OF SYMBOLS 10 ... Imaging device, 11 ... Pixel, 12 ... Pixel array part, 13 ... Row selection circuit, 14 ... Signal processing circuit, 15 ... AD converter, 16 ... Column selection circuit, 17 ... Output circuit, 18 ... Voltage generation circuit, 19 DESCRIPTION OF SYMBOLS ... Control circuit, 20 ... Control signal line group, 21 ... Write line group, 22 ... Vertical signal line, 23 ... Horizontal signal line, 30 ... Photoelectric conversion element, 31 ... Transfer transistor, 32 ... Reset transistor, 33 ... Amplification transistor, 34 ... selection transistor, 35 ... selection transistor, 36 ... constant current source, 37-39 ... writing transistor, 41 ... semiconductor substrate, 42 ... element isolation insulating layer, 43 ... interlayer insulating layer, 44 ... color filter, 45 ... lens, 50: Comparator, 51, 52, 57: P channel MOS transistor, 53, 54: N channel MOS transistor, 55, 58 A constant current source, 56 ... output terminal.

Claims (16)

  1. 　光電変換素子と、
    　前記光電変換素子からの信号を増幅する増幅トランジスタと、
    　を具備し、
    　前記増幅トランジスタは、埋め込みチャネル構造を有し、かつ閾値の調整が可能な構造を有する撮像装置。     A photoelectric conversion element;
    An amplification transistor for amplifying a signal from the photoelectric conversion element;
    Comprising
    The amplifying transistor has an embedded channel structure and a structure capable of adjusting a threshold value.
  2. 　前記増幅トランジスタは、電荷蓄積層を有する請求項１に記載の撮像装置。 The imaging device according to claim 1, wherein the amplification transistor has a charge storage layer.
  3. 　前記増幅トランジスタは、フローティングゲート型、ＭＯＮＯＳ型、及びＳＯＮＯＳ型のいずれかである請求項１に記載の撮像装置。 2. The imaging apparatus according to claim 1, wherein the amplification transistor is one of a floating gate type, a MONOS type, and a SONOS type.
  4. 　ホットキャリア注入により前記増幅トランジスタを書き込む制御回路をさらに具備する請求項１に記載の撮像装置。 The imaging apparatus according to claim 1, further comprising a control circuit that writes the amplification transistor by hot carrier injection.
  5. 　前記増幅トランジスタの電流経路の一端と、ドレイン電圧を供給するための第１端子との間に接続された第１スイッチング素子と、
    　前記増幅トランジスタの電流経路の他端と、ソース電圧を供給するための第２端子との間に接続された第２スイッチング素子と、
    　前記増幅トランジスタのゲートと、書き込み電圧を供給するための第３端子との間に接続された第３スイッチング素子と、
    　をさらに具備する請求項１に記載の撮像装置。     A first switching element connected between one end of the current path of the amplification transistor and a first terminal for supplying a drain voltage;
    A second switching element connected between the other end of the current path of the amplification transistor and a second terminal for supplying a source voltage;
    A third switching element connected between the gate of the amplification transistor and a third terminal for supplying a write voltage;
    The imaging apparatus according to claim 1, further comprising:
  6. 　前記増幅トランジスタは、半導体基板内に離間して設けられたソース領域及びドレイン領域と、前記ソース領域及び前記ドレイン領域間に設けられ、前記ソース領域及び前記ドレイン領域と同じ導電型のチャネルとを含む請求項１に記載の撮像装置。 The amplification transistor includes a source region and a drain region that are provided separately in a semiconductor substrate, and a channel that is provided between the source region and the drain region and has the same conductivity type as the source region and the drain region. The imaging device according to claim 1.
  7. 　前記増幅トランジスタは、消去状態においてデプレッション型である請求項１に記載の撮像装置。 2. The imaging device according to claim 1, wherein the amplification transistor is a depletion type in an erased state.
  8. 　前記増幅トランジスタは、ＮチャネルＭＯＳトランジスタであり、書き込み動作により閾値が正側に変化する請求項１に記載の撮像装置。 The imaging device according to claim 1, wherein the amplification transistor is an N-channel MOS transistor, and the threshold value is changed to a positive side by a writing operation.
  9. 　前記増幅トランジスタにより読み出された信号をアナログ／デジタル変換するＡＤコンバータをさらに具備し、
    　前記ＡＤコンバータは、埋め込みチャネル構造を有し、かつ閾値の調整が可能な構造を有するトランジスタを含む請求項１に記載の撮像装置。     An AD converter for analog / digital conversion of the signal read by the amplification transistor;
    The imaging apparatus according to claim 1, wherein the AD converter includes a transistor having a buried channel structure and a structure capable of adjusting a threshold value.
  10. 　光電変換素子と、
    　前記光電変換素子からの信号を増幅する増幅トランジスタと、
    　を具備し、
    　前記増幅トランジスタは、
    　第１半導体層に互いに離間して設けられた第１導電型の第１及び第２半導体領域と、
    　前記第１及び第２半導体領域の間に設けられた第１導電型の第３半導体領域と、
    　前記第３半導体領域上に設けられた第１ゲート電極と、
    　前記第１ゲート電極と前記第３半導体領域との間に設けられた第１電荷蓄積層と、
    　を備える撮像装置。     A photoelectric conversion element;
    An amplification transistor for amplifying a signal from the photoelectric conversion element;
    Comprising
    The amplification transistor is
    First and second semiconductor regions of a first conductivity type provided in the first semiconductor layer spaced apart from each other;
    A third semiconductor region of a first conductivity type provided between the first and second semiconductor regions;
    A first gate electrode provided on the third semiconductor region;
    A first charge storage layer provided between the first gate electrode and the third semiconductor region;
    An imaging apparatus comprising:
  11. 　前記増幅トランジスタは、フローティングゲート型、ＭＯＮＯＳ型、及びＳＯＮＯＳ型のいずれかである請求項１０に記載の撮像装置。 The imaging apparatus according to claim 10, wherein the amplification transistor is any one of a floating gate type, a MONOS type, and a SONOS type.
  12. 　ホットキャリア注入により前記増幅トランジスタを書き込む制御回路をさらに具備する請求項１０に記載の撮像装置。 The imaging apparatus according to claim 10, further comprising a control circuit that writes the amplification transistor by hot carrier injection.
  13. 　前記増幅トランジスタの第１半導体領域に接続された第１スイッチング素子と、
    　前記増幅トランジスタの第２半導体領域に接続された第２スイッチング素子と、
    　前記増幅トランジスタの第１ゲート電極に接続された第３スイッチング素子と、
    　をさらに具備する請求項１０に記載の撮像装置。     A first switching element connected to a first semiconductor region of the amplification transistor;
    A second switching element connected to a second semiconductor region of the amplification transistor;
    A third switching element connected to the first gate electrode of the amplification transistor;
    The imaging device according to claim 10, further comprising:
  14. 　前記増幅トランジスタは、消去状態においてデプレッション型である請求項１０に記載の撮像装置。 The imaging device according to claim 10, wherein the amplification transistor is a depletion type in an erased state.
  15. 　前記増幅トランジスタは、ＮチャネルＭＯＳトランジスタであり、書き込み動作により閾値が正側に変化する請求項１０に記載の撮像装置。 The imaging device according to claim 10, wherein the amplification transistor is an N-channel MOS transistor, and the threshold value is changed to a positive side by a writing operation.
  16. 　前記増幅トランジスタにより読み出された信号をアナログ／デジタル変換するＡＤコンバータをさらに具備し、
    　前記ＡＤコンバータは、トランジスタを含み、
    　前記トランジスタは、
    　第２半導体層に互いに離間して設けられた第１導電型の第４及び第５半導体領域と、
    　前記第４及び第５半導体領域の間に設けられた第１導電型の第６半導体領域と、
    　前記第６半導体領域上に設けられた第２ゲート電極と、
    　前記第２ゲート電極と前記第６半導体領域との間に設けられた第２電荷蓄積層と、
    　を備える請求項１０に記載の撮像装置。     An AD converter for analog / digital conversion of the signal read by the amplification transistor;
    The AD converter includes a transistor,
    The transistor is
    Fourth and fifth semiconductor regions of the first conductivity type provided in the second semiconductor layer spaced apart from each other;
    A sixth semiconductor region of a first conductivity type provided between the fourth and fifth semiconductor regions;
    A second gate electrode provided on the sixth semiconductor region;
    A second charge storage layer provided between the second gate electrode and the sixth semiconductor region;
    An imaging apparatus according to claim 10.
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