JPH1028240A - Amplifier-type solid state image-pickup element and its fixed pattern noise correction method and correction value writing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the fixed pattern noises by building a storage element into an amplifier type sold-state image-pickup element for storing the correction signals which correct the fixed pattern noises. SOLUTION: The pixel signals are outputted to a vertical signal line 5 from one of both main electrodes of a pixel MOS transistor TR 2 of the row that is selected by a vertical selection pulse ϕV, outputted from a vertical-scanning circuit 3. These output pixel signals are held by a pixel signal load capacity element 8 through the break-make-break actions of a pixel signal operation switch 7. At the same time, the correction signals are outputted from the main electrode of a correction signal memory 19, where the correction value of the fixed pattern noises is written. These correction signals are held by a correction signal capacity element 17 through the break-make-break actions of a correction signal operation switch 18. These held pixel and correction signals are added together by a charge detection circuit 15 via a horizontal signal line 10, when a pixel signal horizontal switch 9 and a correction signal horizontal switch 16 conduct at a time, based on a horizontal scan pulse ϕH that is received from a horizontal shift resistor 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an amplification type solid-state imaging device, a fixed pattern noise correction method thereof, and a correction value writing method.

[0002]

2. Description of the Related Art In recent years, in accordance with a demand for higher resolution of a solid-state imaging device, an amplification type solid-state imaging device which has no smear and can realize fine pixels has been developed instead of a CCD solid-state imaging device. This amplifying solid-state imaging device forms a pixel with an active element (a so-called MOS transistor) such as a MOS structure in order to give each pixel an amplifying action of an optical signal, and charges accumulated in the pixel by photoelectric conversion. A signal is read out as current modulation of the transistor.

[0003]

FIG. 11 shows a comparative example of the amplification type solid-state imaging device proposed above. In FIG. 11, reference numeral 1 denotes an amplification type solid-state imaging device as a whole. 2 is a light receiving element constituting a unit pixel (cell), and in this example, a pixel MO
5 shows an S transistor, in which a plurality of pixel MOS transistors 2 are arranged in a matrix. Reference numeral 4 denotes a control electrode of the pixel MOS transistor 2 for each row, that is, a vertical selection line commonly connected to a gate, and 3 denotes a vertical scanning signal, that is, a vertical selection pulse φV.
A vertical scanning circuit for sequentially providing [φV ₁ , ΔφV _m , φV _{m + 1} , ‥‥]. One main electrodes, i.e., source of the pixel MOS transistor 2 are commonly connected to the vertical signal line 5 for each column, the other main electrode or the drain is connected to a power supply V _D.

Each vertical signal line 5 is connected to a load capacitance element 8 for holding a signal voltage (charge) via an operation switch (for example, a MOS switch) 7, and the connection point is connected to a horizontal switch (for example, a MOS switch) 9. Horizontal signal line 1 through
Connected to 0. The load capacitance element 8 is connected between the vertical signal line 5 and the ground potential. An operation pulse φ _OP is applied to the gate of the operation switch 7. The gates of the horizontal switches 9 are commonly connected and connected to the horizontal shift register 11,
The horizontal shift register 11 sequentially supplies a horizontal switch 9 with a horizontal scanning signal, that is, a horizontal scanning pulse φH [φH ₁ ,.
φH _n , φH _{n + 1} , ‥‥].

Although not shown, a reset switch (for example, a MOS switch) for resetting the load capacitance element 8 and the vertical signal line 5 to an initial voltage is provided on the vertical signal line 5 closer to the operation switch than the load capacitance element 8. Is connected. That is, the source of the reset switch is connected to the vertical signal line 5, the reset bias voltage V _RB is applied to the drain, and the reset pulse φV _RST is supplied to the gate.

Operation switch 7, load capacitance element 8, horizontal switch 9, horizontal shift register 11, and horizontal signal line 10
These form a so-called horizontal scanning circuit 16.

At the output end of the horizontal signal line 10, an output circuit including an operational amplifier 12 using an inverting amplifier, for example, a differential amplifier, a detection capacitor 13, and a reset switch (for example, a MOS switch) 14, A so-called charge detection circuit 15 is connected. That is, the horizontal signal line 10 is connected to the inverting input terminal of the operational amplifier 12 of the charge detection circuit 15,
It is given a predetermined bias voltage V _B to the non-inverting input terminal thereof. This bias voltage V _B is for determining the potential of the horizontal signal line 10. A detection capacitor 13 is connected in parallel with the operational amplifier 12, that is, between the inverting input terminal and the output terminal of the operational amplifier 12, and a reset switch for resetting the horizontal signal line 10 and the detection capacitor 13 to the detection capacitor 13. 14 are connected in parallel. The gate of the reset switch 14, a reset pulse phi _R is applied.

FIG. 12 is a sectional view showing a semiconductor structure of a unit pixel (ie, a pixel MOS transistor) 2. In FIG. 12, reference numeral 31 denotes a semiconductor substrate of a first conductivity type, for example, a p-type semiconductor substrate; 32, a semiconductor well region of a second conductivity type, ie, an n-type semiconductor well region serving as an overflow barrier region; 33, a photoelectrically converted signal charge; 34 are p-type semiconductor well regions.

On the p-type semiconductor well region 33, a ring-shaped gate electrode 38 made of, for example, thin-film polycrystalline silicon which can transmit light is formed via a gate insulating film 37.
The n-type source region 35 and the drain region 3 are formed on the surface of the p-type semiconductor well region 33 corresponding to the inside and outside of the ring-shaped gate electrode 38 by self-line.
6 are formed. Hole 34 accumulated by photoelectric conversion in p-type semiconductor well region 33 immediately below gate electrode 38
Controls the channel current (drain current) Id during the read operation, and the amount of change in the channel current Id becomes a signal output.

In the amplification type solid-state imaging device 1 shown in FIG.
A pixel signal output from the main electrode of the pixel MOS transistor 2 according to the signal charge accumulated by the incident light is sent from the vertical signal line 5 to the load capacitance element 8 via the operation switch 7 and held. Then, during the horizontal scanning period, the horizontal scanning pulse φH [φH ₁ ,.
φH _n , φH _{n + 1} , ‥‥], the horizontal switches 9 are sequentially turned on, and the pixel signals held in the load capacitance element 8 flow as charges on the horizontal signal line 10 and are demodulated into voltages by the charge detection circuit 15. And output to the output terminal t _out as a pixel signal.

In the case of the comparative example shown in FIG. 11, when the horizontal scanning circuit 16 outputs the pixel signal held in the load capacitance element 8 from the horizontal signal line 10 to the charge detection circuit 15 via the horizontal switch 9, the operation is performed. Variations in the threshold voltage Vth of the switch 7 and the horizontal switch 9 appear on the output, appearing on the screen as vertical stripe-shaped fixed pattern noise, deteriorating the image quality.

As a detailed operation, a vertical selection pulse φV [φV ₁ , ΔφV _m , φ
V _{m + 1} , ‥‥], the pixel 2 in the m-th row is selected through the vertical selection line 4, and the operation switch 7 is turned on so that the pixel signal of the selected pixel 2 in the m-th row is a vertical signal. Output to the load capacitance element 8 via the line 5. When the output of the pixel signal is completed, the operation switch 7 enters a cutoff state (off). At this time, the threshold voltage Vt of the operation switch 7 is set.
If there is a variation in h, a voltage corresponding to the variation is added to the signal voltage of the pixel held in the load capacitance element 8, and
The vertical streak-shaped fixed pattern noise appears at the horizontal output circuit, that is, at the output terminal t _out of the charge detection circuit 15.

Similarly, when the pixel signal held in the load capacitance element 8 is sent to the charge detection circuit 15 through the horizontal signal line 10 by sequentially turning on the horizontal switch 9 by the horizontal shift register 11, the horizontal switch 9 If the threshold voltage Vth at the time of transition from the cutoff state (off) to the conduction state (on) varies, a voltage corresponding to the variation is added to the pixel signal by the charge detection circuit 15 through the horizontal signal line 10, and the vertical stripes Fixed pattern noise appears.

The mechanism of the generation of the vertical stripe-shaped fixed pattern noise generated from the horizontal scanning circuit 16 in the XY address type amplification type solid-state imaging device will be described in further detail.

A load capacitance element 8, a horizontal switch 9, and an output circuit (charge detection circuit) 1 of the amplification type solid-state imaging device 1 shown in FIG.
FIG. 14 shows an equivalent circuit in which only 5 is extracted. As a premise of the description, here, the threshold voltage Vth of the horizontal switch 9 is set.
Pay attention to the variation.

The pixel signal held by the load capacitance element 8 shown in FIG. 14 flows as electric charge to the horizontal signal line 10 when the horizontal switch 9 is turned on, and is demodulated into a voltage by the electric charge detection circuit 15 to convert the pixel signal. It is output to the output terminal t _out of the image sensor.

At this time, the horizontal switch 9 and the horizontal signal line 1
Since the capacitance generated during 0 changes greatly when the horizontal switch 9 changes from the cut-off state to the conductive state, the threshold voltage Vth that determines the boundary between the cut-off state and the conductive state of the horizontal switch 9 is: If there is a variation between the horizontal switches in each column, a charge expressed by the product of the variation in the threshold voltage Vth and the amount of change in the capacitance appears on the horizontal signal line 10, so that a vertical stripe corresponding to this charge amount The fixed pattern noise is superimposed on the pixel signal.

This situation will be described with reference to FIG. 15 which shows two equivalent circuits before and after the horizontal switch 9 is converted into a capacitance model before and after the horizontal switch 9 is turned off and on. FIG.
In A, there is a horizontal switch (MOS transistor) 9 disconnected state (OFF), the load capacitor element gate and the pixel signal of the horizontal switch 9 to enter the pulse .phi.H _n from the horizontal shift register 11 as a capacitance model is held 8 Between the gate of the horizontal switch 9 and the horizontal signal line 10, a gate-source capacitance 92 is generated between the gate of the horizontal switch 9 and the horizontal signal line 10, and the load capacitance element 8 and the horizontal signal line 10 are cut off. .

On the other hand, in FIG. 15B, a horizontal switch (MO
S transistor) 9 is in the conductive state (ON), the load capacity element 8 is connected to the horizontal signal line 10, between the gate and the horizontal signal line 10 of the horizontal switch 9 to enter the pulse .phi.H _n from the horizontal shift register 11 A gate-to-channel capacitance 93 occurs. Here, the capacitance of the capacitance 93 is considerably larger than the total capacitance of the capacitances 91 and 92 in FIG. 15A.

[0020] These (state see Figure 15A) 2 two states (A), condition (B) (see the state of FIG. 15B) is horizontal switch 9 Works the voltage pulse .phi.H _n entering the gate of the horizontal switch 9 In order to switch the threshold voltage Vth to the boundary, if there is a variation in the threshold voltage Vth in each horizontal switch 9, the variation in the threshold voltage Vth and the capacitance of the horizontal switch 9 in the state (A) and (B) The product of the difference and the difference appears on the horizontal signal line 10 as uneven charge, and becomes a vertical stripe-like fixed pattern noise.

[0021] Now, the capacity of the capacitance 91,92,93 C _DG, respectively, C _GS, and C _G, the horizontal switch 9
The variation of the threshold voltage Vth is ΔVth, the variation appearing on the horizontal signal line 10 is Δq, the charge detection circuit 15
Let C _{D be} the capacitance of the detection capacitive element 13 and ΔV _out be the vertical streak-shaped fixed pattern noise appearing in the output. The variation charge Δq and the fixed pattern noise ΔV _out are expressed by the following equation (1).

[0022]

(Equation 1)

Specifically, the capacitances C _DG and C _GS are 1 fF, and the capacitance C
_G is 20 fF, variation ΔVth of threshold voltage Vth
0.5pF but 50 mV, the capacitance C _D of the detection capacitor element 13 is
, The fixed pattern noise ΔV _out is 1.8 mV
become.

FIG. 13 shows a drive timing chart of the solid-state imaging device 1 of the comparative example and how the vertical streak-like fixed pattern noise appears. Vertical selection pulse .phi.V for selecting a pixel 2 of the same row _{[φV 1, ‥‥ φV m, φV} m + 1, ‥‥ ] sequentially rising every horizontal blanking period T _HBL, operates in synchronism with the vertical selection pulse .phi.V When the pulse φ _OP rises, the pixel signal is read out to the load capacitance element 8. When a pixel signal of a certain row held by the load capacitance element 8 enters a horizontal video period T _A , the horizontal scanning pulse φ from the horizontal shift register 11
H _{[φH 1, ‥‥ φH n, φH} n + 1, ‥‥ ] By successively rises, becomes sequentially conducting state horizontal switch 9, the pixel signal (output signal) appears at the output terminal t _out.

At this time, for example, the same signal amount is output from any pixel 2, and the threshold voltage Vth of the horizontal switch 9 is output.
If only has variations respectively, a no signal in the output signals S ₁ from the output terminal t _out as in FIG. 10 is constant, appears an output signal as a fixed pattern noise component S _N are superposed.

The XY address type amplifying solid-state imaging device 1 so far requires an external circuit for correcting the fixed pattern noise in order to remove the vertical stripe-shaped fixed pattern noise generated from the horizontal scanning circuit 16. Therefore, the size of the system including the peripheral circuits of the solid-state imaging device and the signal processing circuit becomes large, and there is a disadvantage that the cost of the system increases.

In view of the above, the present invention provides an amplifying solid-state imaging device which removes vertical streak-like fixed pattern noise generated from a horizontal scanning circuit. SUMMARY OF THE INVENTION The present invention provides a fixed pattern noise correction method for an amplification type solid-state imaging device which removes vertical streak-like fixed pattern noise generated from a horizontal scanning circuit. Further, the present invention provides a correction value writing method applied to the fixed pattern noise correction method and the like.

[0028]

An amplifying solid-state imaging device according to the present invention has a storage element for storing a correction signal corresponding to a variation of a switch means in a horizontal scanning circuit, and stores the correction signal in a storage element simultaneously with a pixel signal. The stored correction signal is read out to a horizontal output circuit.

According to this configuration, the correction signal stored in the storage element at the same time as the pixel signal is read out to the horizontal output circuit, so that the correction signal is added or subtracted from the pixel signal containing the fixed pattern noise. Fixed pattern noise can be removed without using a signal processing circuit.

A method of correcting a fixed pattern noise of an amplification type solid-state imaging device according to the present invention is such that a correction value of a fixed pattern noise is stored in a storage element, and a pixel signal and a correction value are mixed and output by a horizontal scanning pulse. Eggplant

The correction value of the fixed pattern noise is stored in the storage element, and the pixel signal and the correction value are mixed and output by the horizontal scanning pulse, thereby removing the fixed pattern noise from the pixel signal and correcting the fixed pattern noise. can do.

In the correction value writing method according to the present invention, a switching element is connected to one main electrode of a storage element composed of a memory transistor, and the correction value is written to the storage element by an on / off operation of the switching element. I do.

By turning on / off a switching element connected to one main electrode of the storage element, the correction value (voltage) stored in the storage element can be changed. or,
A desired correction value can be obtained by adjusting the number of ON / OFF of the switching element or the ON period.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An amplification type solid-state imaging device according to the present invention is an amplification type solid-state imaging device having a horizontal scanning circuit for outputting a pixel signal from a light receiving element to an output terminal for each row.
The horizontal scanning circuit has a storage element for storing a correction signal according to the variation of the switch means, and the correction signal stored in the storage element at the same time as the pixel signal is read out to the horizontal output circuit.

In the amplifying solid-state imaging device according to the present invention, in the amplifying solid-state imaging device, the light receiving elements are arranged in a matrix, and the control electrodes of the light receiving elements in the same row are shared by a vertical selection line from a vertical scanning circuit. The main electrodes of the light receiving elements in the same column are connected in common to a vertical signal line, and the storage elements are arranged in an XY matrix type in which the memory elements are arranged corresponding to each column of the light receiving elements.

As the storage element, a floating gate MOS transistor or a transistor having a MONOS structure can be used.

As the correction signal, a threshold voltage changed by injecting hot electrons into the floating gate of the storage element can be used.

As the correction signal, a threshold voltage changed by injecting or extracting electrons by a tunnel current between the write electrode and the floating gate via the tunnel oxide film to the floating gate of the storage element and using the changed threshold voltage is used. it can.

In the amplification type solid-state image pickup device, the pixel signal and the correction signal of the storage element are respectively held in separate capacitance elements, and are mixed and output on the same horizontal signal line via the switch means.

Each of the capacitance elements is configured such that the capacitance of the capacitance element holding the correction signal of the storage element is smaller than the capacitance of the capacitance element holding the pixel signal.

The correction signal can be obtained using a vertical optical black signal as a reference signal.

According to the fixed pattern noise correction method for an amplification type solid-state imaging device according to the present invention, a fixed value of fixed pattern noise is stored in a storage element, a pixel signal and a correction value are mixed and output by a horizontal scanning pulse, and the fixed value is fixed. Correct pattern noise.

As a reference signal for obtaining this correction value, a vertical optical black signal can be used.

In the correction value writing method according to the present invention, a switching element is connected to one main electrode of a storage element composed of a memory transistor, and writing of the correction value to the storage element is selectively performed by turning on / off the switching element. To do.

As a reference signal for obtaining this correction value, a vertical optical black signal can be used.

An embodiment of the present invention will be described below with reference to a screen.

FIG. 1 shows an embodiment of an amplification type solid-state imaging device according to the present invention. Amplification type solid-state imaging device 41 according to this example
Is a plurality of light receiving elements arranged in a matrix, that is, a pixel transistor constituting a unit pixel (cell), for example, a pixel MO
A vertical selection pulse φV [φV ₁ , ΔφV _m , φV] is applied to a vertical selection line 4 connecting the S transistor 2 and the control electrode (that is, the gate electrode) of the pixel MOS transistor 2 in the same row.
_{m + 1} , ‥‥], a vertical signal line 5 connected to one main electrode (ie, source electrode) of the pixel MOS transistor 2 in the same column, and a vertical signal line 5 connected to the vertical signal line 5. A pixel signal operation switch (for example, a MOS switch) 7, a pixel signal load capacitance element 8, a pixel signal horizontal switch (for example, a MOS switch) 9, a horizontal signal line 10,
Operation switch for correction signal (for example, MOS switch) 1
8, a horizontal scanning circuit 42 including a correction signal capacitance element 17, a correction signal horizontal switch 16, a correction signal memory element 19, a correction signal writing switch (for example, a MOS switch) 20, and a horizontal shift register 11, and a horizontal signal line 10. It comprises an output circuit connected thereto, that is, a charge detection circuit 15.

That is, a plurality of pixel MOS transistors 2 are arranged in a matrix, and
Of the pixel MOS transistors 2 in the same column, that is, the source is commonly connected to the vertical signal line 5, and the other main electrode, that is, the drain is connected. _Are connected to the power supply VD.

The pixel signal load capacitance element 8 for holding the pixel signal of the pixel MOS transistor 2 is connected to the vertical signal line 5 via the pixel signal operation switch 7 controlled by the operation pulse φ _OP. A horizontal shift register 11 is provided between the signal load capacitance element 8 and the horizontal signal line 10.
Horizontal scanning pulse φH [φH ₁ , ΔφH _n , φH
_{n + 1} ,...], the pixel signal horizontal switch 9 to be controlled is connected.

On the other hand, a correction signal memory (for example, a floating gate MOS such as a flash memory and an EPROM)
A transistor 19 or a memory having a MONOS transistor or the like) 19 is provided for each column of the pixel MOS transistors 2. One main electrode (that is, the source electrode) of the correction signal memory 19 is connected to the correction signal capacitor 17 via the correction signal operation switch 18 controlled by the operation pulse φ _OP . 17 between the horizontal signal line 10 and the horizontal scanning pulse φH [φ
H ₁ , _{ φH _n , φH _{n + 1} ,...] Are connected.

One of the main electrodes (source electrodes) of the correction signal memory 19 has a correction signal writing switch (for example, MO
S switch) 20 is connected, the horizontal scanning pulse .phi.H [.phi.H ₁ from the horizontal shift register to the control electrode of the correction signal writing switch _{20, ‥‥ φH n, φH n} + 1, ‥
‥] is given. The other main electrode of each of the correction signal memory 19 corresponding to the times the respective columns (the drain electrode) is connected to the common terminal t _VDC to apply a required voltage V _DC, since the control electrode applying a control voltage V _{GC Are} connected to a common control terminal t _VGC .

As described above, the charge detection circuit 15 connected to the output terminal of the horizontal signal line 10 includes an operational amplifier 12 using an inverting amplifier, for example, a differential amplifier, and a detection capacitor 13.
And a reset switch (for example, a MOS switch) 14. The horizontal signal line 10 is connected to the inverting input terminal of the operational amplifier 12 is given a predetermined bias voltage V _B to the non-inverting input terminal thereof. Detection capacitor element 13 is connected between the inverting input terminal of the operational amplifier 12 and the output terminal, the reset switch (e.g. MOS switch) 14 a reset pulse phi _R is applied in parallel to the detection capacitor element 13 is connected.

Next, the operation of the amplifying solid-state imaging device 41 will be described by dividing it into an imaging operation and an operation of writing a correction value of fixed pattern noise. First, the imaging operation will be described. The vertical selection pulse φV output from the vertical scanning circuit 3
The pixel signal output from one main electrode (source electrode) of the pixel MOS transistor 2 in the row selected by [φV ₁ , {φV _m , φV _{m + 1} , ‥‥] to the vertical signal line 5 is
The pixel signal operation switch 7 performs a cut-off → conduction → cut-off (readout) operation, so that the pixel signal load capacitance element 8 holds the pixel signal. On the other hand, at the same time, the correction signal output from the main electrode (source electrode) of the correction signal memory 19 in which the correction value of the fixed pattern noise has been written is changed by the correction signal operation switch 18 from cut-off → conduction → cut-off (read) By performing the operation, the correction signal is held in the correction signal capacitor 17.

By a series of these operations, the pixel signal and the correction signal held in the pixel signal load capacitance element 8 and the correction signal capacitance element 17 are converted into the horizontal scanning pulse φH [φH ₁ ,. _{ ΦH _n , φH _{n + 1} , ‥
‥], the pixel signal horizontal switch 9 and the correction signal horizontal switch 16 are simultaneously turned on, so that the output circuit, that is, the charge detection circuit 15 is passed through the horizontal signal line 10.
, Thereby removing vertical streak-like fixed pattern noise from the pixel signal.

As shown in FIG. 3, the driving timing chart in this imaging operation is the same as that of the imaging device of the comparative example (see FIG. 10), and the power supply voltage (for example, 5 V) is applied to the terminals t _VGC and t _VDC. It is the same as FIG. 10 except that it is given and that no fixed pattern noise appears at the output terminal t _out .

A vertical selection pulse φV [φV ₁ , ΔφV _m , φV] for selecting the pixel MOS transistor 2 in the same row.
_{m + 1} , ‥‥] sequentially rises every horizontal blanking period T _HBL , and operates in synchronization with the vertical selection pulse φV.
_{The OP} is activated, and the pixel signal is read out and held by the pixel signal load capacitance element 8. At the same time, the correction signal memory 19
Operation switch 1 for the correction signal from the main electrode (source electrode)
The correction signal is read out and held in the correction signal capacitance element by the cut-off → conduction → cut-off operation of 8.

[0057] pixel signal and the correction signal on a line held by the pixel signal for the load capacity element 8 and the correction signal for the capacitor element 17, enters the horizontal video period T _A, the horizontal shift register 1
1 from the horizontal scanning pulse φH [φH ₁ , ΔφH _n , φ
H _{n + 1} , ‥‥] sequentially rises, the pixel signal horizontal switch 9 and the correction signal horizontal switch 16 are simultaneously turned on, and the signal obtained by adding the pixel signal and the correction signal to the output terminal t _out. appear. At this time, for example, the same signal amount is output from any of the pixel MOS transistors 2, and even if the threshold voltage Vth of the horizontal switch 9 varies, the correction signal from the correction signal memory 19 in which the appropriate correction signal is stored. Since the correction signal is added, FIG.
As shown in ( ₂₎ , the signal amount S2 of the output signal becomes constant, and an output signal having no fixed pattern noise component is obtained.

At this time, if the correction signal capacitance element 17 is set to a value, for example, two digits smaller than the pixel signal load capacitance element 8, the correction signal memory 19 is used to correct a fixed pattern noise of 1 mV. 100m correction value stored in
V and a large value, and an error in writing the correction value can be reduced.

Next, the operation of writing a fixed pattern noise correction value will be described. As a fixed pattern noise correction value writing operation, a method is used in which an analog value that just cancels out the fixed pattern noise superimposed on the pixel signal is written to the correction signal memory in the same manner as the flash memory.

FIGS. 2A and 2B show an example of the structure of the correction signal memory 19 and its operation. This correction signal memory 19 is constituted by a so-called floating gate MOS transistor. That is, for example, an n-type source region 52 and a drain region 53 are formed in the p-type semiconductor well region 51, and the p-type semiconductor well region 51 between the source region 52 and the drain region 53 is provided with the first gate insulating film 54 therebetween. Floating electrode (so-called floating gate electrode)
55, and a second gate insulating film 56 is further formed thereon.
Via a control electrode (so-called control gate electrode)
57 are formed. A required control voltage V _GC is applied to a control electrode 57 of the correction signal memory 19 through a common control terminal t _VGC , and a required voltage V _DC is applied to one main electrode, namely, a drain electrode through a common terminal t _VDC. Can be The other main electrode (that is, the source electrode) of the correction signal memory 19 is grounded via the correction signal writing switch 20.

First, a write voltage V _GC (for example, about 12 V) is applied to the control electrode of the correction signal memory 19 through the common control terminal t _VGC , and one main electrode (drain electrode) of the correction signal memory 19 is applied through the common terminal t _VDC . A required voltage V _DC , that is, a power supply voltage (for example, about 6 V) is applied, and a horizontal scanning pulse φH [φH ₁ ,.
[ΦH _n , φH _{n + 1} , ‥‥], the correction signal writing switch 20 is made conductive, and a drain current flows through the correction signal memory 19, and the generated hot electrons 59 are injected into the floating electrode 55 of the correction signal memory 19. , And its potential is controlled (see FIG. 2A).

The value of the correction signal to be written into the correction signal memory 19 is determined by controlling the writing time for determining the hot electron injection amount or the number of times of writing.

When rewriting the correction signal value in the correction signal memory 19, as shown in FIG. 2B, the control voltage V _GC , that is, the erasing voltage (for example, about 0 V) is applied to the common control terminal t _VGC.
And a required voltage V _DC , that is, a high voltage (for example, about 12 V) is applied to the common main electrode through the common terminal t _VDC , and the horizontal scanning pulse φH from the horizontal shift register 11 is not applied to the main electrode of the correction signal memory 19. By bringing the (source electrode) into a floating state, the hot electrons 59 injected into the floating electrodes 55 of all the correction signal memories 19 are once extracted by FN tunneling, and the correction signal memories 19 are removed.
Is erased, and the same write operation as described above is performed again.

FIG. 4 shows an example of a timing chart in the correction value writing operation. Here, the horizontal scanning pulse φH [φH ₁ , φφH from the horizontal shift register 11 is used.
_n , φH _{n + 1} , ‥‥] and the common control terminal t
1 the write voltage pulse V _GC in _{VGC, ‥‥ n, n + 1} ,
An appropriate correction value is written in each correction signal memory 19 by changing the pulse width (correction value memory writing time) for each ‥‥ th pulse.

As a correction value to be written into the correction signal memory 19 in the above correction writing operation, under the condition that the fixed pattern noise ΔV _out appears at 1.8 mV at the output terminal t _out , the correction signal capacitor 17 of the image pickup device is used. in capacity C _c of 4.5FF, capacitance C _D of the detection capacitor element 13 is 0.5p
If F, a correction value (threshold voltage) of 0.2 V may be written in the correction signal memory 19. If the written correction value (threshold voltage) is represented by _ΔVmem , it can be obtained by _Expression 2.

[0066]

(Equation 2)

Incidentally, instead of changing the pulse width as the control of the correction value in the correction signal memory 19, the correction value can be controlled by, for example, changing the number of write voltage pulses having a constant pulse width.

In the above example, the correction signal memory 19 is constituted by a floating MOS transistor.
For example, a transistor having a so-called MONOS structure in which a control electrode is formed on a semiconductor region between a source region and a drain region via an SiO ₂ layer, a SiN layer, and an SiO ₂ layer, and the SiN layer is used as a layer for injecting so-called hot electrons. Can also be used.

Next, FIG. 5 shows another embodiment of the amplification type solid-state imaging device according to the present invention. In this example, the structure of the correction value memory is changed so that +/− writing can be performed instead of batch erasing.

The amplification type solid-state imaging device 61 according to the present embodiment comprises:
A vertical selection pulse φV [φV ₁ , φφV is applied to a vertical selection line 4 that connects a plurality of pixels arranged in a matrix, that is, a pixel MOS transistor 2 and a control electrode (gate electrode) of the pixel MOS transistor 2 in the same row. _m , φV _{m + 1} , ‥‥], a vertical signal line 5 connected to one main electrode (ie, source electrode) of the pixel MOS transistor 2 in the same column, and a vertical signal line 5 , A pixel signal load capacitance element 8, a pixel signal horizontal switch (eg, a MOS switch) 9, a horizontal signal line 10, and a correction signal operation switch (eg, a MOS switch). ) 18, a correction signal capacitance element 17, a correction signal horizontal switch (for example, a MOS switch) 16, a correction signal memory 21, a bootstrap capacitance element 22, Coupling capacitance element 23,2
4. A horizontal scanning circuit 62 including the clamp diode 25 [25a, 25b], the inverter 26 and the horizontal shift register 11, and an output circuit connected to the horizontal signal line 10, that is, a charge detection circuit 15.

That is, as described above, a plurality of pixel MOS transistors 2 are arranged in a matrix, and
The control electrode of the transistor 2, that is, the gate is the vertical selection line 4
They are commonly connected to one of main electrodes of pixels in the same row MOS transistor 2, i.e. with the source is commonly connected to the vertical signal line 5, the other main electrode, i.e. the drain is connected to the power supply V _D.

The pixel signal load capacitance element 8 for holding the pixel signal of the pixel MOS transistor 2 is connected to the vertical signal line 5 via the pixel signal operation switch 7 controlled by the operation pulse φ _OP. A horizontal shift register 11 is provided between the signal load capacitance element 8 and the horizontal signal line 10.
Horizontal scanning pulse φH [φH ₁ , ΔφH _n , φH
_{n + 1} ,...] are connected.

On the other hand, a correction signal memory 21 having a structure described later
Are provided corresponding to each column of the pixel MOS transistors 2, and one main electrode (that is, a source electrode) of the correction signal memory 21 is connected via a correction signal operation switch 18 controlled by the operation pulse φ _OP . The horizontal scanning pulse φH [φH ₁ , ΔφH _n , φH _{n + 1} from the horizontal shift register 11 is connected between the correction signal capacitor 17 and the horizontal signal line 10. , ‥
‥] is connected.

[0074] The other main electrode (i.e., the drain electrode) of the correction signal memory 21 is connected to the power supply V _D. The control electrode (see FIG. 6) 71 of the correction signal memory 21 is connected to the common write pulse terminal W / E via the bootstrap capacitance element 22.
The positive write electrode (see FIG. 6) 72 is connected to the horizontal shift register 1 via the coupling capacitance element 23.
1 and its negative electrode 73 (see FIG. 6) is connected to the horizontal shift register 11 via the coupling capacitance element 24 and the inverter 26. + Writing electrode 72 is connected to power supply V via first clamp diode 25a.
_D , and the negative electrode 73 is grounded via the second clamp diode 25b.

Next, the operation of the amplifying type solid-state imaging device will be described by dividing it into an imaging operation and an operation of writing a correction value of fixed pattern noise.

First, the imaging operation will be described. The vertical selection pulse φV [φV ₁ ,.
[ΦV _m , φV _{m + 1} , ‥‥] from one main electrode of the pixel MOS transistor 2 in the row selected by the vertical signal line 5
Are held in the pixel signal load capacitance element 8 when the pixel signal operation switch 7 performs the cut-off → conduction → cut-off (readout) operation. On the other hand, at the same time, the correction signal output from the main electrode of the correction signal memory 21 in which the correction value of the fixed pattern noise is written is turned off, turned on, and turned off (read) by the correction signal operation switch 18.
By performing the above operation, the correction signal is held in the capacitance element 17.

By these series of operations, the pixel signal and the correction signal held in the pixel signal load capacitor 8 and the correction signal capacitor 17 are converted into the horizontal scanning pulse φH [φH ₁ ,. _{ ΦH _n , φH _{n + 1} , ‥
‥], the pixel signal horizontal switch 9 and the correction signal horizontal switch 16 are simultaneously turned on, so that they are added by the charge detection circuit 15 through the horizontal signal line 10, whereby the vertical streak-like fixed pattern noise is removed from the pixel signal. Can be removed.

The driving timing chart in this imaging operation is the same as that of the above embodiment except that the power supply voltage is applied to the terminals t _VGC and t _VDC in the above-described embodiment, and the write pulse terminal W / E is grounded. The description is omitted because it is the same as that of the example image sensor.

On the other hand, in the correction value writing operation, an analog value which just cancels out the fixed pattern noise superimposed on the pixel signal is transferred to the correction signal memory 21 by the FN tunneling through the tunnel oxide film to the floating gate electrode (FN). A writing method of injecting / extracting FG) is used.

The basic structure of the correction signal memory 21 is shown in FIG.
The detailed operation will be described with reference to FIGS. 7B and 7C and a timing chart of the operation shown in FIG.

First, the correction signal memory 21 is stored in the memory shown in FIGS.
As shown in FIG. 5, an n-type source region 66 and a drain region 67 are formed in a p-type semiconductor well region 65, and a gate insulating film 68 is formed on the p-type semiconductor well region 65 between the source region 66 and the drain region 67. Control electrode in floating state, so-called floating gate electrode (FG) 7
1 and a + write electrode (W) 72 and a − write electrode (E) 73 are arranged in parallel on the floating gate electrode 71 with a tunnel oxide film 74 interposed therebetween. FIG. 6A shows symbols in the correction signal memory 21.

The +/− write operation of the correction signal memory 21 is performed by the floating gate electrode (FG) 71 and the +/− write operation.
Write electrode (W) 72 or -Write electrode (E) 73
By applying a high voltage between the floating gate electrode (FG) 71 and the floating gate electrode (FG) 71.
The correction signal memory 21 of the MOS structure is
Is performed so as to change the potential of the surface channel. At this time, the timing of the write operation to the correction signal memory 21 is shown in FIG.

First, in + writing, a pulse of −10 V from the write pulse terminal W / E enters the bootstrap capacitance element 22 in FIG. 5, and as a result, when the floating gate electrode 71 has the initial voltage of 3.0 V, − 4.0
V. There goes from the horizontal shift register 11 rises the horizontal scanning pulse .phi.H _n, until the voltage is, for example 8.5V to + write electrode (W) 72 of the correction signal memory 21 via the coupling capacitance element 23, + write electrode (W) 72 and the floating gate electrode (F
G) The displacement difference of 71 becomes 12.5V.

+ Tunnel oxide film 74 between write electrode (W) 72 and floating gate electrode (FG) 71
Is set to an oxide film thickness such that FN tunneling occurs at a voltage of about 12 V. Electrons are extracted from the floating gate electrode (FG) 71 to the + write electrode (W) 72, and the floating gate electrode (FG) 71 The potential changes from 3.0 V to, for example, 3.05 V, and the + writing is completed.

On the other hand, in -writing, a pulse of 10 V from the write pulse terminal W / E enters the bootstrap capacitance element 22 in FIG. 5, and as a result, the floating gate electrode (FG) 71 has an initial voltage of 2.0 V. However, it changes to 9.0V. There horizontal shift register 11
Rises the horizontal scanning pulse .phi.H _n from via a coupling capacitive element 24 of the correction signal memory 21 - down to the voltage of the write voltage (E) 73, for example, -3.5 V, - write electrode (E) 72 and a floating The potential difference of the gate electrode (FG) 71 becomes -12.5V. A write electrode (E) 73 and a floating gate electrode (F
F) Tunneling occurs in the tunnel oxide film 74 between the floating gate electrode (G) 71 and the floating gate electrode (FG) 91. The voltage changes from 0 V to, for example, 1.95 V, and the -writing is completed.

By such +/− writing operation, the potential of the floating gate electrode (FG) 71 of the correction signal memory 21 is changed so that the fixed pattern noise superimposed on the pixel signal is just canceled out.
1 controls so as to generate an appropriate correction signal.

According to the above-described embodiment, the amplification type solid-state imaging device is provided with the built-in correction signal memory 19 or 21 for storing the correction signal for correcting the fixed pattern noise.
The fixed pattern noise can be effectively removed without using a signal processing circuit outside the image sensor. As a result, the configuration of the external signal processing circuit is simplified, and low power consumption and low price can be defined.

Electrons are injected into the floating gate electrode 71 of the correction signal memory 21 through the tunnel oxide film 74 from the plus write electrode 72 by a tunnel current, or electrons are drawn from the floating gate 71 to the minus write electrode 73 to change. By using the threshold voltage as the storage signal (that is, the storage voltage), the correction signal stored in the correction signal memory 21 can be changed or changed at any time. It is possible to compensate for the change.

The pixel signals and the storage voltages of the correction signal memories 19 and 21 are held in separate capacitive elements 8 and 17, respectively, and mixed on the same horizontal signal line 10 via column selection switches, ie, horizontal switches 9 and 16. By outputting, the internal circuit of the image sensor can be simplified without the need for an arithmetic circuit for subtracting or adding the correction signal from the pixel signal containing the fixed pattern noise, thereby reducing the power consumption. Cost reduction can be expected by reducing the chip size.

The storage signal (storage voltage) of the correction signal memory 19 or 21 is different from that of the load capacitance element 8 which holds the pixel signal.
By reducing the capacitance of the capacitive element 16 for holding the fixed pattern noise, a very small level of fixed pattern noise can be converted into a large level of the correction signal amount by the correction signal memory 19 or 2.
1, the accuracy of the correction of the vertical stripe-shaped fixed pattern noise is improved.

In the above-described embodiments of FIGS. 1 and 5, as a method of determining the correction value, a correction value can be determined using a signal obtained in a so-called vertical optical black area shown in FIG. 10 as a reference signal. Normally, in an amplification type solid-state imaging device, as shown in FIG.
An optical black area 82 is provided outside the light-receiving unit 1 and covered with a light-shielding layer of, for example, Al, and a signal from the optical black area 82 is used as a black level signal. The optical black region 82 includes a horizontal optical black region 82H provided in a region extending in a row direction of pixels (light receiving portions) arranged in a matrix and a vertical optical black region 82H provided in a region extending in a column direction of pixels. And a black region 82V. In this example, the signal of the vertical optical black 82V that can be extracted as a net vertical streak fixed pattern noise component is used as a reference signal for writing correction.

That is, in contrast to the first embodiment shown in FIG.
As shown in FIG. 7, an amplifier 91 is included in an imaging inspection device 84 used when inspecting the imaging state of the solid-state imaging device before shipment.
, An A / D converter 92, a line memory 93, a circuit 94 for averaging, a comparator 95, and a correction value writing circuit 97 including a write driver 86.
By the correction value writing circuit 97 in the imaging inspection apparatus 84, the correction value can be written to the fixed image pickup device that self-corrects the vertical streak fixed pattern noise of the present invention.

As an operation, for example, at the time of inspection of the solid-state imaging device 41 before shipment, the output terminal t _out of the solid-state imaging device 41 is output.
Of the vertical optical black 8
A 2V signal is input to the correction value writing circuit 84, and a write control pulse output from the write driver 96 is applied to the terminal t _VGC and the terminal t _VDC of the solid-state imaging device 41, so that the correction signal memory 19 can perform appropriate correction. Write the value.

In the embodiment shown in FIG. 8, the correction value of the fixed pattern noise is stored in the correction signal memory 19 during the imaging inspection before shipment.
Therefore, when the solid-state imaging device is assembled into a camera or the like and operated, no processing circuit for correcting fixed pattern noise is required.

For the second embodiment shown in FIG. 5, an amplifier 91, an A / D converter 92, a line memory 93, an averaging circuit 94, and a comparator 95 as shown in FIG.
Then, the correction value can be written to the solid-state imaging device 61 of the present invention which self-corrects the vertical streak fixed pattern noise by the correction value writing circuit 99 including the write driver 96.

As an operation, for example, during the operation of the solid-state imaging device 61, of the signals output from the output terminal t _out of the solid-state imaging device 61, the signal of the vertical optical black 82V is input to the correction value writing circuit 99, and A write control pulse output from the write driver 96 is applied to the terminal W / E of the image sensor 61 to write an appropriate correction value into the correction signal memory 21.

In the embodiment shown in FIG. 9, since a correction value writing pulse is generated based on the signal of the vertical optical black 82V in the imaging state and the correction value of the fixed pattern noise is written to the correction signal memory 21 as needed, There is no need to perform correction during the previous imaging inspection, and the correction signal memory 21
Since the correction value written in the correction value is self-corrected, no error occurs in the correction value even if the temperature drifts or changes over time.

In the above example, the present invention is applied to an XY matrix type amplifying solid-state imaging device. However, the present invention is also applicable to an amplifying solid-state imaging device for a linear sensor.

[0099]

According to the amplifying solid-state imaging device of the present invention, the amplifying solid-state imaging device has a built-in storage element for storing a correction signal for correcting fixed pattern noise.
The fixed pattern noise can be effectively removed without using a signal processing circuit outside the image sensor. As a result, the configuration of the external signal processing circuit is simplified, and low power consumption and low price can be defined.

When a tunnel current is used to inject electrons from the write electrode to the floating gate of the storage element via the tunnel oxide film by a tunnel current, or electrons are extracted from the floating gate to the write electrode, and the changed threshold voltage is used as the storage voltage. The correction signal stored in the storage element can be changed or changed at any time, and it is possible to compensate for the aging of the correction signal amount in the storage element.

The pixel signal and the storage voltage of the storage element are held in separate capacitance elements, respectively, and mixed and output on the same horizontal signal line via a column selection switch, thereby correcting the pixel signal containing fixed pattern noise. An arithmetic circuit for reducing or adding signals is not required, so that the internal circuit of the image sensor can be simplified, power consumption can be reduced, and the cost can be reduced by reducing the chip size.

By making the capacitance of the capacitor holding the storage voltage of the storage element smaller than that of the capacitor holding the pixel signal, a very small level of fixed pattern noise can be reduced.
Since the large-level correction signal amount is stored in the storage element, the accuracy of correcting vertical streak-like fixed pattern noise is increased.

According to the fixed pattern noise correction method for an amplification type solid-state image pickup device according to the present invention, a vertical streak fixed pattern generated from a horizontal scanning circuit is corrected without using a signal processing circuit outside the image pickup device. Can be.

According to the correction value writing method according to the present invention, the correction value can be selectively written in the storage element by using the horizontal scanning circuit, so that only one or two terminals are required for writing. And no special writing circuit is required. In addition, the correction value of the storage element can be erased,
The correction value can be corrected in accordance with the aging of the vertical streak fixed pattern noise level or the correction value. Further, in the second embodiment, the correction value can be corrected even during the continuous imaging operation, so that it can be used for a 24-hour power supply.

When a vertical optical black signal is used as a reference signal for obtaining a correction signal, an appropriate correction value can be written.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of an amplification type solid-state imaging device according to the present invention.

2A and 2B are explanatory diagrams showing an example of the structure and operation of the correction signal memory of FIG. 1;

FIG. 3 is a drive timing chart and an output waveform diagram of the amplification type solid-state imaging device of the first embodiment.

FIG. 4 is a timing chart of a correction value writing operation of the amplification type solid-state imaging device according to the first embodiment.

FIG. 5 is a configuration diagram showing a second embodiment of the amplification type solid-state imaging device according to the present invention.

FIG. 6 is a diagram showing symbols of an A correction signal memory. B is a plan view of a correction signal memory. C is a cross-sectional view of the correction signal memory on the line XX ′.

FIG. 7 is a timing chart of a correction value writing operation according to the second embodiment.

FIG. 8 is a circuit configuration diagram showing an example of a method for determining a correction value according to the present invention.

FIG. 9 is a circuit configuration diagram showing another example of a method for determining a correction value according to the present invention.

FIG. 10 is a schematic diagram of an imaging unit of a solid-state imaging device used for describing the present invention.

FIG. 11 is a configuration diagram of an amplification type solid-state imaging device according to a comparative example.

FIG. 12 is a sectional view of a pixel MOS transistor.

FIG. 13 is a drive timing chart and an output waveform diagram of an amplification type solid-state imaging device of a comparative example.

FIG. 14 is an equivalent circuit diagram of a signal path of the horizontal scanning circuit.

FIG. 15 is an equivalent circuit of a signal path of a horizontal scanning circuit in which A and B horizontal switches are described using a capacitance model.

[Explanation of symbols]

2 pixel MOS transistor, 3 vertical scanning circuit, 4
Vertical selection line, 5 vertical signal line, 7 pixel signal operation switch, 8 pixel signal load capacitance element, 9 pixel signal horizontal switch, 10 horizontal signal line, 11 horizontal shift register, 15 charge detection circuit, 16 correction signal Horizontal switch, 17 correction signal capacitance element, 18 correction signal operation switch, 19, 21 correction signal memory, 20 correction signal write switch, 55 floating electrode, 57 control electrode, 71 control electrode, 72, 73 write electrode, 41,
61 Amplification type solid-state imaging device, 42, 62 Horizontal scanning circuit 81 Effective screen, 82 Optical black area, 82
H horizontal optical black area, 82V vertical optical black area, 84 imaging inspection apparatus, 97, 99
Correction value writing circuit

Claims (14)

[Claims] 1. An amplifying solid-state imaging device having a horizontal scanning circuit for outputting a pixel signal from a light receiving element to an output terminal for each row, wherein a correction signal corresponding to a variation of a switch in the horizontal scanning circuit is stored. An amplification type solid-state imaging device comprising a storage element, wherein a correction signal stored in the storage element at the same time as the pixel signal is read out to the horizontal output circuit. 2. The light receiving elements are arranged in a matrix, control electrodes of the light receiving elements in the same row are commonly connected to a vertical selection line from a vertical scanning circuit, and main electrodes of the light receiving elements in the same column are connected to a vertical signal. 2. The amplifying solid-state imaging device according to claim 1, wherein the storage devices are commonly connected to a line, and the storage elements are arranged corresponding to each column of light receiving elements. 3. A floating gate M is connected to the storage element.
2. The amplification type solid-state imaging device according to claim 1, wherein the amplification type solid-state imaging device is formed using an OS transistor or a transistor having a MONOS structure. 4. The amplification type solid-state imaging device according to claim 1, wherein hot electrons are injected into a floating gate of the storage element, and a changed threshold voltage is used as the correction signal. 5. An electron is injected or extracted from a floating gate of the storage element by a tunnel current between a write electrode and a floating gate via a tunnel oxide film, and a changed threshold voltage is used as the correction signal. The amplification type solid-state imaging device according to claim 1, wherein: 6. The pixel signal and the correction signal of the storage element are held in separate capacitance elements, and are mixed and output on the same horizontal signal line via the switch means. 2. The amplification type solid-state imaging device according to item 1. 7. The pixel signal and the correction signal of the storage element are respectively held in different capacitance elements, and are mixed and output on the same horizontal signal line via the switch means. 2. The amplification type solid-state imaging device according to item 1. 8. The amplification type solid-state imaging device according to claim 4, wherein the capacitance of the capacitance element holding the correction signal of the storage element is smaller than the capacitance of the capacitance element holding the pixel signal. element. 9. The amplification type solid-state imaging device according to claim 5, wherein the capacitance of the capacitance element holding the correction signal of the storage element is smaller than the capacitance of the capacitance element holding the pixel signal. element. 10. The amplifying solid-state imaging device according to claim 1, wherein the correction signal is obtained using a vertical optical black signal as a reference signal. 11. An amplifying solid-state imaging device which stores a correction value of fixed pattern noise in a storage element, mixes and outputs a pixel signal and the correction value by a horizontal scanning pulse, and corrects fixed pattern noise. An element fixed pattern noise correction method. 12. The method according to claim 11, wherein a vertical optical black signal is used as a reference signal for obtaining the correction value. 13. A switching element is connected to one main electrode of a storage element comprising a memory transistor, and a correction value is selectively written to the storage element by an on / off operation of the switching element. Correction value writing method. 14. The method according to claim 13, wherein a vertical optical black signal is used as a reference signal for obtaining the correction value.