CN107302005A - A kind of flash memories and preparation method, electronic installation with camera function - Google Patents
A kind of flash memories and preparation method, electronic installation with camera function Download PDFInfo
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- CN107302005A CN107302005A CN201610208297.XA CN201610208297A CN107302005A CN 107302005 A CN107302005 A CN 107302005A CN 201610208297 A CN201610208297 A CN 201610208297A CN 107302005 A CN107302005 A CN 107302005A
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
Abstract
The present invention provides a kind of flash memories and preparation method and electronic installation with camera function.The flash memories include some memory cells, and the memory cell includes：Substrate；Gate stack, above the substrate, including tunnel oxide layer, floating gate layer, separation layer and the control grid layer stacked gradually；Interconnection structure, is electrically connected positioned at the top of the gate stack and with the gate stack；Filter coating, positioned at the top of interconnection structure；On prism, the surface for being arranged at the filter coating.Flash memories of the present invention are flash memory (flash) storage chips first with ultraviolet image shoot function, have the advantages that non-volatile, image information will not lose after power-off, and be combined well with flash memory (flash) technique.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of with camera function
Flash memories and preparation method, electronic installation.
Background technology
Generally, imaging sensor is the semiconductor devices that optical imagery is converted into electric signal.Figure
As sensor includes charge coupling device (CCD) and complementary metal oxide semiconductor
(CMOS) imaging sensor.
Because cmos image sensor (CMOS image sensor, CIS) has improved system
Technology and characteristic are made, therefore semiconductor fabrication everyway concentrates on exploitation CMOS figures
As sensor.Cmos image sensor is manufactured using CMOS technology, and with relatively low
Power consumption, it is easier to realize highly integrated, produces smaller device, therefore, CMOS
Imaging sensor is widely used in various products, such as digital camera and digital camera
Deng.
Cmos image sensor (CMOS image sensor, CIS) is in daily life
Widely apply.It is the diode using reverse biased, and electronics is produced in the case of illumination,
And moved along built in field, in PN junction two-stage formation electrical potential difference, then by peripheral circuit electricity
Lotus information is exported according to certain way, forms certain image.
The current cmos image sensor has the following disadvantages：If inside diode
Electric charge is exported not in time, is waited after light source removes, electricity can gradually decay, and final electric charge disappears
Lose, the retention time was not over one second.Shortcoming is exactly that electric charge preserves impermanent.
Therefore, it is necessary to propose a kind of new cmos image sensor (CMOS image
Sensor, CIS), to solve existing technical problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be specific real
Apply in mode part and be further described.The Summary of the present invention is not meant to
Attempt to limit the key feature and essential features of technical scheme claimed, less
Mean the protection domain for attempting to determine technical scheme claimed.
In order to overcome the problem of presently, there are, one aspect of the present invention provides a kind of with photograph work(
The flash memories of energy, the flash memories include some memory cells, the memory
Unit includes：
Substrate；
Gate stack, above the substrate, including stack gradually tunnel oxide layer,
Floating gate layer, separation layer and control grid layer；
Interconnection structure, is electrically connected positioned at the top of the gate stack and with the gate stack；
Filter coating, positioned at the top of interconnection structure；
On prism, the surface for being arranged at the filter coating.
Alternatively, passivation is also formed with above the interconnection structure, below the filter coating
Layer, the passivation layer has flat surface.
Alternatively, the filter coating is ultraviolet filter film.
Alternatively, the interconnection structure includes some through holes and metal level being arranged alternately, described
The length of some through holes and wide critical size are less than the length and wide critical size of the prism；Institute
The length and wide critical size for stating metal level are less than the length and wide critical size of the prism.
Alternatively, the square structure of the prism.
Alternatively, some row wordline of flash memories including setting intersected with each other and some
Row bit line, above-mentioned memory cell is provided with the infall of the wordline and bit line.
Alternatively, the distance between the memory cell is equal.
The invention provides a kind of preparation method of the flash memories with uv photography function,
Methods described includes：
Substrate is provided, gate stack is formed on the substrate, wherein the gate stack includes
Tunnel oxide layer, floating gate layer, separation layer and the control grid layer stacked gradually；
Interconnection structure is formed on the gate stack to electrically connect with gate stack formation；
Filter coating and prism are sequentially formed above the interconnection structure, to form imager
Part.
Alternatively, it be may further include before the prism is formed above the interconnection structure
The step of forming passivation layer and planarize the passivation layer.
Alternatively, the interconnection structure includes some through holes and metal level being arranged alternately, described
The length of some through holes and wide critical size are less than the length and wide critical size of the prism；Institute
The length and wide critical size for stating metal level are less than the length and wide critical size of the prism.
Alternatively, the filter coating is ultraviolet filter film.
The invention provides a kind of electronic installation, including above-mentioned flash memories.
The problem of present invention in solving in order to presently, there are is there is provided a kind of with camera function
Flash memories and preparation method, the flash memories with camera function include substrate,
Gate stack, interconnection structure and prism, the gate stack include the tunnel oxide stacked gradually
Nitride layer, floating gate layer, separation layer and control grid layer.Flash memory (flash) memory of the present invention
Usually front shutter is closed, it is unglazed to enter, with general memory and indistinction.Need to make
Used time, first flash memory (flash) data are exported, then all storage positions (bit) are all placed in compiling
The state of journey (program), carries out ultraviolet image shooting, and the flash memories can only enter
Row is once shot, after data are exported, and could be shot second.
Flash memories of the present invention are the flash memories (flash) first with ultraviolet image shoot function
Storage chip, has the advantages that non-volatile, and image information will not lose after power-off, and very
Good is combined with flash memory (flash) technique.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 shows the structural profile of the flash memories of the present invention with camera function
Schematic diagram；
Fig. 2 shows that the flash memories of the present invention with camera function are flat in passivation layer
Structural profile schematic diagram before smoothization；
Fig. 3 shows the domain structure of the flash memories of the present invention with camera function
Schematic diagram；
Fig. 4 shows the preparation technology of the flash memories of the present invention with camera function
Flow chart；
Fig. 5 shows the schematic diagram of electronic installation according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
It can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, and it will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from beginning to end
Icon note represents identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, with
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then in the absence of element or layer between two parties.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term is limited.These terms be used merely to distinguish element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience herein and by using from
And an element shown in figure or feature and other elements or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of and operation
In device different orientation.If for example, the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
For other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.Herein in use, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " comprising ", when in this specification in use, determine the feature,
Integer, step, operation, the presence of element and/or part, but be not excluded for it is one or more its
Its feature, integer, step, operation, element, the presence or addition of part and/or group.
Herein in use, term "and/or" includes any and all combination of related Listed Items.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description
Suddenly, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail
It is as follows, but in addition to these detailed descriptions, the present invention can also have other embodiment.
In view of the problem of presently, there are, the present invention provides a kind of flash memory storage with camera function
Device, Fig. 1 shows that the structural profile of the flash memories of the present invention with camera function shows
It is intended to.
As shown in figure 1, the flash memories with camera function, the flash memories include
Some memory cells, the memory cell includes：
Substrate；
Gate stack, above the substrate, including the tunnel oxide layer stacked gradually
101st, floating gate layer 102, separation layer 103 and control grid layer 104；
Interconnection structure, is electrically connected positioned at the top of the gate stack and with the gate stack,
Including some through holes being arranged alternately and metal level；
Filter coating, positioned at the top of interconnection structure；
On prism, the surface for being arranged at the filter coating.
Wherein, the flash memories include some row wordline and several columns of setting intersected with each other
Bit line, above-mentioned memory cell is provided with the infall of the wordline and bit line.
Wherein, the distance between the memory cell is equal, prevents anamorphose.
The length of some through holes described in the interconnection structure and wide critical size are less than the rib
The length of mirror and wide critical size, the length of the metal level and wide critical size are less than the rib
The length of mirror and wide critical size, such as described interconnection structure include the first metal from the bottom up
Three layers of layer M1, second metal layer M2 and metal layer at top (top metal), its CD is not
Can be too wide, hide as far as possible below prism, prevent from being in the light.
Alternatively, the poly- ultraviolet light prism design is into square, to absorb more light as far as possible.
Passivation (passivation) layer after metal layer at top (top metal) needs cmp planarization
Change, to prevent ultraviolet light prism incidence light path difference from leading to not focus on floating boom (Floating
Gate poly) above.
Alternatively, it is furnished with the color filter (ultraviolet filters of ultraviolet below last prism
Film), only retain ultraviolet.
There is provided a kind of flash memory with camera function for problem present in solving by the present invention
Memory and preparation method, the flash memories with camera function include：Substrate and grid
Pole lamination, the gate stack includes the tunnel oxide layer, floating gate layer, isolation stacked gradually
Layer and control grid layer, interconnection structure and prism.Flash memory (flash) memory of the present invention is put down
When front shutter is closed, it is unglazed to enter, with general memory and indistinction.Need to use
When, first flash memory (flash) data are exported, then all storage position positions (bit) are all placed in compiling
The state of journey (program), carries out ultraviolet image shooting, and the flash memories can only enter
Row is once shot, after data are exported, and could be shot second.
Flash memories of the present invention are the flash memories (flash) first with ultraviolet image shoot function
Storage chip, has the advantages that non-volatile, and image information will not lose after power-off, and very
Good is combined with flash memory (flash) technique.
Embodiment one
The flash memories with camera function of the present invention are carried out below with reference to Fig. 1 and Fig. 2
Describe in detail, Fig. 1 shows the flash memory with camera function according to an embodiment of the present invention
The diagrammatic cross-section of memory；Fig. 2 shows that the flash memory of the present invention with camera function is deposited
Structural profile schematic diagram of the reservoir before passivation layer planarization.
Specifically, the flash memories with camera function, the flash memories include some
Memory cell, the memory cell includes：
Substrate；
Gate stack, above the substrate, including the tunnel oxide layer stacked gradually
101st, floating gate layer 102, separation layer 103 and control grid layer 104；
Interconnection structure, is electrically connected positioned at the top of the gate stack and with the gate stack,
Including some through holes being arranged alternately and metal level；
Filter coating, positioned at the top of interconnection structure；
On prism, the surface for being arranged at the filter coating.
The flash memories with camera function of the present invention include substrate, and the substrate can be wrapped
Include peripheral region and core space.
Specifically, the substrate can be at least one of following material being previously mentioned：Silicon,
Silicon (SSOI) is laminated on silicon-on-insulator (SOI), insulator, SiGe is laminated on insulator
(S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI)
Etc..Fleet plough groove isolation structure (not shown) can also be formed with the substrate.
Wherein, the substrate can be divided into core space and peripheral region, wherein the core space has
There is higher integrated level, wherein the number of the gate stack is not limited to a certain numerical value model
Enclose, the peripheral region has several gate stacks, gate stack is sparse, in order to simplify centre
Eliminate some gate stacks.
Exemplarily, deposition tunnel oxide layer 101, the tunnelling oxygen are formed with substrate
Compound layer 101 is oxide, in the present invention optional SiO2Layer as tunnel oxide layer 101,
The thickness of the tunnel oxide layer 101 can be 1-20nm, but be not limited solely to the thickness
Degree, those skilled in the art can be adjusted as needed, to obtain more preferable effect.
Wherein, the material of floating gate layer 102 can select semi-conducting material, such as silicon, polysilicon
Or Ge etc., it is not limited to the material of a certain material, in this embodiment floating gate layer 102
Material selects polysilicon.
Separation layer 103 is formed with floating gate layer 102, wherein the material of the separation layer can be selected
With insulating materials commonly used in the art, such as the one or more in oxide, nitride.
For example the separation layer selects ONO (oxidenitride oxides in this embodiment
Structural insulation separation layer).
Control grid layer 104 is formed on the separation layer 103, wherein, the control grid layer 104
Material can select semi-conducting material, such as silicon, polysilicon or Ge, do not limit to
In the material selection polysilicon of a certain material, the in this embodiment control gate.
In one example, oxide has also been can be selectively formed on the surface of the substrate
Layer, is used as gate dielectric.
As an example, the clearance wall on the gate stack sidewall.Wherein, clearance wall can be with
Including at least one layer of oxide skin(coating) and/or at least one layer of nitride layer.Clearance wall can be individual layer
Structure or sandwich construction.It should be noted that clearance wall is optional rather than required, it is led
Be used for be subsequently etched or during ion implanting protection gate stack side wall it is injury-free.
In this implementation, the material of clearance wall is preferably with TEOS lower temperature depositions (TP-TEOS) shape
Into silica.
As alternate embodiment, the control grid layer can be formed before patterning, for example
The control grid layer is formed before etching forms lamination, then to the control grid layer, isolation
Layer, floating gate layer and the tunnel oxide layer are patterned, to form gate stack.
Or patterned to the separation layer, floating gate layer and the tunnel oxide layer
Form control gate afterwards, the elongated structure of control gate, to cover the separation layer, such as
In Fig. 3 302 shown in.
Source and drain is formed with the substrate of the gate stack both sides, wherein source and drain injection
Ionic type and the concentration of doping can select scope commonly used in the art.Select in the present invention
Implant energy is 1000ev-30kev, preferably 1000-10kev, to ensure that it adulterates
Concentration can reach 5E17~1E25 atoms/cm3。
The domain structures of the flash memories is as shown in figure 3, wherein, the flash memories
Including active area 302, control gate 303, prism 304 and contact hole 301, wherein, institute
Some row wordline and several columns bit line of the flash memories including setting intersected with each other are stated, described
The infall of wordline and bit line is provided with above-mentioned memory cell.
Alternatively, the distance between the memory cell is equal.
Form interconnection structure on the gate stack to electrically connect with gate stack formation, institute
State some through holes and metal level that interconnection structure includes being arranged alternately.
Specifically, the interconnection structure includes the first metal layer M1, the second gold medal from the bottom up
Belong to three layers of layer M2 and metal layer at top (top metal), its CD can not be too wide, hides as far as possible
Keep away below prism, prevent from being in the light.
Alternatively, the length of some through holes described in the interconnection structure and wide critical size are less than
The length of the prism and wide critical size, the length of the metal level and wide critical size are less than
The length of the prism and wide critical size, to hide below prism as far as possible, prevent from being in the light.
Passivation layer is formed with above the interconnection structure.Wherein, the passivation layer can be two
Silica or silicon nitride layer etc., if the passivation film structure it is fine and close, stably, be not easily susceptible to
Destroy, the erosion of various ions and hydrone can be stopped, it is not limited to above-mentioned example.
As a kind of embodiment, the passivation layer 209 includes plasma enhanced silicon nitride layer
PESIN layers, PETEOS layers of tetraethyl orthosilicate of plasma enhancing, SiN layer and positive silicic acid second
One or more combinations in ester TEOS, layer.
In the present invention, the passivation layer is the combination of above-mentioned various materials, first passivation
Layer includes PESIN layers, PETEOS layers, SiN layer and TEOS layers stacked gradually, for example
Described PESIN layers thickness is 650-850 angstroms, and described PETEOS layers thickness is
3800-4200 angstroms, the thickness of the SiN layer is 650-850 angstroms, described TEOS layers thickness
Spend for 2400-2600 angstroms
The passivation layer need to simultaneously be planarized, and with the surface planarized, prevent ultraviolet light
Prism incidence light path difference leads to not focus on floating boom (Floating gate poly) above.
Prism 105 is formed with above the interconnection structure, the lower section of prism 105 is also extremely
Filter coating is formed with less.
Alternatively, the lower section of prism 105 is provided with ultraviolet filter film.Institute in the present invention
If stating flash memory without electrically erasable, the information of the inside can also be wiped by ultraviolet light (UV).
Electronics inside floating boom (Floating gate), can be with transition after the energy of ultraviolet light is obtained
Cross tunnel oxide layer (tunnel oxide) or separation layer ONO potential barrier.
The operation principle of flash memories of the present invention：It is first that flash memory (flash) is all
Storage position (bit) all injects electronics and becomes to program (program) state.According to the UV light time,
Intensity is bigger, and corresponding flash memory position threshold voltage (flash bit VT) reduces more, flash memory
(flash) there is decoding (decoder) region, it can be determined that go out this storage position (bit) and exist
Position in array, and threshold voltage (VT) power, you can draw ultraviolet light image.
Because flash memory (flash) is non-volatility memorizer, therefore this figure can be retained for a long time
Picture.This is flash memory (flash) storage chip first with image camera function.
Flash memory (flash) memory of the present invention usually closes front shutter, unglazed to enter,
With general memory and indistinction.When needing to use, first flash memory (flash) data are exported,
Then all storage positions (bit) are all placed in programming the state of (program), carry out ultraviolet figure
As shooting, the flash memories can only once be shot, after data are exported, and could be clapped
Take the photograph second.
Flash memories of the present invention are the flash memories (flash) first with ultraviolet image shoot function
Storage chip, has the advantages that non-volatile, and image information will not lose after power-off, and very
Good is combined with flash memory (flash) technique.
Embodiment two
Below with reference to systems of the Fig. 2 to Fig. 4 to the flash memories with camera function of the present invention
Preparation Method is described in detail, and Fig. 2 shows the flash memory storage of the present invention with camera function
Structural profile schematic diagram of the device before passivation layer planarization；Fig. 3 shows tool of the present invention
There is the domain structure schematic diagram of the flash memories of camera function；Fig. 4 shows of the present invention
The preparation technology flow chart of flash memories with camera function.
The present invention provides a kind of preparation method of the flash memories with camera function, such as Fig. 4
Shown, the key step of the preparation method includes：
Step S1：Substrate is provided, gate stack is formed on the substrate, wherein the grid
Pole lamination includes tunnel oxide layer, floating gate layer, separation layer and the control grid layer stacked gradually；
Step S2：Interconnection structure is formed on the gate stack to be formed with the gate stack
Electrical connection；
Step S3：Filter coating and prism are sequentially formed above the interconnection structure, with shape
Into image device.
The method of the invention segment process before and after flash memory (Flash) totally keeps constant, if
Domain (layout) is counted it is noted that equidistantly to prevent image from becoming between storage position (bit)
Shape.Back segment is usually the first metal layer M1, second metal layer M2 and metal layer at top (top
Metal) three layers, CD can not be too wide, hides as far as possible below prism, prevents from being in the light.Last
Poly- ultraviolet light prism design is into square, to absorb more light as far as possible.The flash memories
Have the advantages that non-volatile, image information will not lose after power-off, and well and flash
Technique is combined.
Below, the embodiment to the preparation method of the semiconductor devices of the present invention is done in detail
Explanation.
First, step one is performed there is provided substrate, forms flash memory cell on the substrate,
The flash memory cell includes being arranged at the gate stack above the substrate, and the grid is folded
Layer includes tunnel oxide layer 201, floating gate layer 202, separation layer 203 and the control stacked gradually
Gate layer 204 processed.
Specifically, as shown in Fig. 2 providing Semiconductor substrate first in this step.Wherein institute
It can be at least one of following material being previously mentioned to state Semiconductor substrate：On silicon, insulator
Be laminated on silicon (SOI), insulator silicon (SSOI), stacking SiGe (S-SiGeOI) on insulator,
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..In addition, half
Active area can be defined on conductor substrate.Others can also be included on the active region to be had
Source device, for convenience, is not indicated in shown figure.
The Semiconductor substrate can select p-type, form tunnelling oxygen on the semiconductor substrate
Compound layer 201, wherein, the tunnel oxide layer 201 is oxide, excellent in the present invention
Select SiO2Layer is as tunnel oxide, and the thickness of the tunnel oxide layer 201 can be
1-20nm, but the thickness is not limited solely to, those skilled in the art can be carried out as needed
Adjustment, to obtain more preferable effect.
In this step as a kind of embodiment, the SiO is deposited2It can be selected during layer
With thermal oxide, ald, chemical vapor deposition, electron beam evaporation or magnetically controlled sputter method.
Alternatively, it can also be formed on the substrate before the tunnel oxide layer 201
Dielectric layer, the dielectric layer can be not limited to a certain from the conventional dielectric layer in this area
Kind.
Then floating gate layer 202 is formed on the tunnel oxide 201, wherein the floating gate layer
202 select semi-conducting material, such as silicon, polysilicon or Ge, it is not limited to a certain
Material is planted, the deposition process of the floating gate layer 202 can select molecular beam epitaxy (MBE), gold
Belong to organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), laser
One kind in ablation deposition (LAD) and selective epitaxy growth (SEG).
In this embodiment, the floating gate layer 202 of polysilicon is preferably formed as, the polysilicon is selected
Epitaxy method is formed, specifically, is described further in a preferred embodiment by taking silicon as an example, instead
Gas is answered to include hydrogen (H2) carry silicon tetrachloride (SiCl4) or trichlorosilane
(SiHCl3), silane (SiH4) and dichloro hydrogen silicon (SiH2Cl2) etc. at least one of enter
Enter to be placed with the reative cell of silicon substrate, high-temperature chemical reaction is carried out in reative cell, make to contain pasc reaction
Gas reduction or thermal decomposition, produced silicon atom extension life on the surface of tunnel oxide 201
It is long.
Methods described may further include the step of forming separation layer 203 on the floating gate layer,
Wherein described separation layer selects ONO (the structure separation layer of oxidenitride oxide),
A certain kind is not limited to, can be selected according to specific needs.
Further, mask layer is formed on the separation layer 203, preferably hard mask is described
Hard mask layer can be nitride or oxide, preferably, selecting Si in this embodiment3N4
As the mask layer, its thickness is 400-2000 angstroms.
Preferably, the deposition process of the mask layer can select chemical vapor deposition (CVD)
The low pressure of the formation such as method, physical vapour deposition (PVD) (PVD) method or ald (ALD) method
Chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG)
In one kind.Preferred chemical vapor deposition (CVD) method in the present invention.
Pattern the mask layer, separation layer 203, floating gate layer 202 and the tunnel oxide
Layer 201 and the Semiconductor substrate, partly the leading in lamination both sides while lamination is formed
Shallow trench is formed in body substrate.
Organic distribution layer (Organic distribution are formed on the mask layer in this step
Layer, ODL), siliceous bottom antireflective coating (Si-BARC), at the siliceous bottom
The photoresist layer of deposit patterned on portion's ARC (Si-BARC), or cover described
Pattern definition that film layer is only formed on the photoresist layer patterned, the photoresist is wanted
The figure of floating boom is formed, then using the photoresist layer as mask layer or to have described in the etching
Machine distribution layer, bottom antireflective coating, the lamination of photoresist layer formation are mask etch mask layer.
Then organic distribution layer (Organic distribution layer, ODL) is removed, is contained
The bottom antireflective coating (Si-BARC) of silicon, photoresist layer, then using the mask layer as
Separation layer 203, floating gate layer 202 and the tunnel oxide 201 described in mask etch are to portion
Divide the Semiconductor substrate, in the semiconductor of the lamination both sides while lamination is formed
Shallow trench is formed in substrate.
In this step, from dry etching, reactive ion etching (RIE), ion beam milling,
Plasma etching.Dry etching is carried out preferably by one or more RIE step, at this
Reactive ion etching described in step (RIE) can be by controlling reacting gas, air pressure, stream
Amount and radio-frequency power, obtain faster etch-rate and good anisotropy, can realize
The condition of the purpose may be incorporated for the present invention.
N can be for example selected in the present invention2In conduct etching atmosphere, can also add simultaneously
Enter other a small amount of gas such as CF4、CO2、O2, the etching pressure can be
50-200mTorr, preferably 100-150mTorr, power are 200-600W, in the present invention
The etching period is 5-80s, more preferably 10-60s, while in the present invention from larger
Gas flow, alternatively, in N of the present invention2Flow be 30-300sccm, be, for example,
50-100sccm。
Alternatively, the shallow trench is filled from isolated material, and is planarized to form shallow trench
Isolation structure.Specifically, in groove fill shallow trench isolated material, with formed shallow trench every
From structure.Specifically, deposit shallow trench isolated material in the enough grooves of money, the shallow trench every
Can be silica, silicon oxynitride and/or other existing advanced low-k materials from material；
Then perform and planarize and stop on the mask layer, there is shallow trench isolation junction to be formed
Structure.
The planarisation step, can use flattening method conventional in field of semiconductor manufacture
To realize the planarization on surface.The non-limiting examples of the flattening method include machinery planarization
Method and chemically mechanical polishing flattening method.Chemically mechanical polishing flattening method is more often used.
The mask layer is removed, is gone in this step from the larger engraving method of etching selectivity
Except the mask layer, so that ensure will not be to the floating gate layer during the mask layer is removed
Impact.
Preferably, in this step, from dry etching, reactive ion etching (RIE),
Ion beam milling, plasma etching.Done preferably by one or more RIE step
Method is etched, and the reactive ion etching (RIE) can be by controlling reaction gas in this step
Body, air pressure, flow and radio-frequency power, obtain faster etch-rate and well each to different
Property, it can realize that the condition of the purpose may be incorporated for the present invention.
Further, on the separation layer 203 formed control grid layer 204, wherein, it is described every
Control grid layer 204 can select with the floating gate layer identical material, such as silicon, polysilicon or
Person Ge etc., it is not limited to a certain material, the deposition process of the control grid layer 204 can
To select molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), low pressure
Chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG)
In one kind.
As alternate embodiment, the control grid layer can be formed before patterning, for example
The control grid layer is formed before etching forms lamination, then to the control grid layer, isolation
Layer, floating gate layer and the tunnel oxide layer are patterned, to form gate stack.
Or patterned to the separation layer, floating gate layer and the tunnel oxide layer
Form control gate afterwards, the elongated structure of control gate, to cover the separation layer, such as
In Fig. 3 302 shown in.
Then clearance wall is formed on the side wall of the gate stack, and performs source and drain injection step
Suddenly, with the both sides of gate stack formation source-drain area.
Wherein, the clearance wall can use silicon nitride, carborundum, silicon oxynitride or its combination
Material.The first silicon oxide layer, the first silicon nitride layer and the second oxygen can be deposited on substrate
SiClx layer, then using engraving method formation clearance wall, the clearance wall can have
10-30NM thickness.
Then source and drain injection is carried out on the semiconductor material layer of the gate stack both sides, wherein
The ionic type of the source and drain injection and the concentration of doping can select model commonly used in the art
Enclose.The implant energy selected in the present invention be 1000ev-30kev, preferably 1000-10k ev,
To ensure that its doping concentration can reach 5E17~1E25 atoms/cm3.Preferably, in source and drain
Annealing steps can also be carried out after injection, specifically, are performed after the thermal anneal step, can be with
Infringement on silicon chip is eliminated, minority carrier lifetime and mobility can obtain different degrees of
Recover, impurity can also obtain a certain proportion of activation, therefore can improve device efficiency.
The domain structures of the flash memories is as shown in figure 3, wherein, the flash memories
Including active area 302, control gate 303, prism 304 and contact hole 301, wherein, institute
Some row wordline and several columns bit line of the flash memories including setting intersected with each other are stated, described
The infall of wordline and bit line is provided with above-mentioned memory cell.
Alternatively, the distance between described some memory cells are equal, and the imaging sensing is single
The distance between member is equal.
Step 2 is performed, interconnection structure and the gate stack shape are formed on the gate stack
Into electrical connection, the interconnection structure includes some through holes and metal level being arranged alternately.
Specifically, the interconnection structure includes the first metal layer M1 206 from the bottom up, the
208 3 layers of two metal level M2 207 and metal layer at top (top metal), its CD can not be too
Width, hides below prism, prevents from being in the light as far as possible.
The forming method of the interconnection architecture includes the deposit dielectric first on the gate stack
Layer and the first patterned mask layer (not shown), using first patterned mask layer as
Dielectric layer described in mask etch, to open the dielectric layer, forms opening in the dielectric layer,
The etching process selects dry etching or wet etching, in an embodiment, institute
Wet etching is stated from hydrofluoric acid and ammonium fluoride (HF/NH4F the cushioning liquid that) is formed is etched
The hard mask layer of silica, or select CF4Or CHF3Etchant gas described in
Dielectric layer, above-mentioned example is only schematical, it is not limited to methods described.
Conductive material, such as metal material are filled in said opening, to form first through hole
205, then proceed to dielectric layer and pattern, to form the first metal layer M1 206, according to
It is secondary to analogize, to form second metal layer M2 207 and metal layer at top (top metal) 208
Three layers.
Alternatively, the length of some through holes described in the interconnection structure and wide critical size are less than
The length of the prism and wide critical size, the length of the metal level and wide critical size are less than
The length of the prism and wide critical size, to hide below prism as far as possible, prevent from being in the light.
Step 3 is performed, passivation layer 209 is formed above the interconnection structure and institute is planarized
The step of stating passivation layer.
Wherein, the passivation layer 209 can be silica or silicon nitride layer etc., as long as institute
State passivation film structure it is fine and close, stably, be not easily susceptible to destruction, various ions and moisture can be stopped
The erosion of son, it is not limited to above-mentioned example.
As a kind of embodiment, the passivation layer 209 includes plasma enhanced silicon nitride layer
PESIN layers, PETEOS layers of tetraethyl orthosilicate of plasma enhancing, SiN layer and positive silicic acid second
One or more combinations in ester TEOS, layer.
In the present invention, the passivation layer is the combination of above-mentioned various materials, first passivation
Layer includes PESIN layers, PETEOS layers, SiN layer and TEOS layers stacked gradually, for example
Described PESIN layers thickness is 650-850 angstroms, and described PETEOS layers thickness is
3800-4200 angstroms, the thickness of the SiN layer is 650-850 angstroms, described TEOS layers thickness
Spend for 2400-2600 angstroms.
Alternatively, the deposition process of the passivation layer can select chemical vapor deposition (CVD)
The low pressure of the formation such as method, physical vapour deposition (PVD) (PVD) method or ald (ALD) method
Chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG)
In one kind.Preferred chemical vapor deposition (CVD) method in the present invention.
Then the passivation layer is planarized, with the surface planarized, prevents ultraviolet
Light prism incidence light path difference leads to not focus on floating boom (Floating gate poly) above.
Step 4 is performed, prism 105, the prism 105 are formed in the top of the interconnection structure
Lower section also includes filter coating.
Alternatively, the lower section of prism 105 is also formed with ultraviolet filter film.In the present invention
If the flash memory can also wipe the letter of the inside without electrically erasable by ultraviolet light (UV)
Breath.Electronics inside floating boom (Floating gate), can be with after the energy of ultraviolet light is obtained
Tunneling oxide (tunnel oxide) or ONO potential barrier are crossed in transition.
Alternatively, it is used as ultraviolet light using flash memory (Flash) or EEPROM
Imaging sensor, FEOL is constant, the upper microprism technique of last part technology collocation, you can realize
Function.Operation principle：All storage positions (bit) of flash memory (flash) are all injected electricity first
Son becomes to program (program) state.According to the UV light time, intensity is bigger, corresponding sudden strain of a muscle
Depositing a threshold voltage (flash bit VT) reduces more, and flash memory (flash) has decoding (decoder)
Region, it can be determined that go out this position of storage position (bit) in an array, and threshold value electricity
Press the power of (VT), you can draw ultraviolet light image.Because flash memory (flash) is non-waves
Hair property memory, therefore this image can be retained for a long time.This is that have image taking first
Flash memory (flash) storage chip of function.
Segment process totally keeps constant, design layout before and after flash memory (flash) in the present invention
(layout) it is noted that equidistantly to prevent anamorphose between storage bit.Back segment is general
It is three layers of the first metal layer M1, second metal layer M2 and metal layer at top (top metal),
CD can not be too wide, hides as far as possible below prism, backstop light.Last poly- ultraviolet light prism is set
Square is counted into, to absorb more light as far as possible.After metal layer at top (Top metal)
Passivation layer (passivation) layer needs to planarize (CMP), to prevent ultraviolet light prism incidence
Light path difference leads to not focus on floating boom (Floating gate poly) above.Last rib
Technique used in mirror is with traditional CIS imaging sensors.It is furnished with ultraviolet below prism
Ultraviolet filter film (color filter), only retains ultraviolet.With ultraviolet image sensing function
Storage chip just carry out, be fitted on inside camera lens i.e. usable.
So far the key step of the preparation method of the present invention is completed, for the system of complete device
Other intermediate steps or subsequent step are also needed, is repeated no more herein.
Flash memory (flash) memory of the present invention usually closes front shutter, unglazed to enter,
With general memory and indistinction.When needing to use, first flash memory (flash) data are exported,
Then all storage positions (bit) are all placed in programming the state of (program), carry out ultraviolet figure
As shooting, the flash memories can only once be shot, after data are exported, and could be clapped
Take the photograph second.
Flash memories of the present invention are the flash memories (flash) first with ultraviolet image shoot function
Storage chip, has the advantages that non-volatile, and image information will not lose after power-off, and very
Good is combined with flash memory (flash) technique.
Embodiment three
An alternative embodiment of the invention provides a kind of electronic installation, and it includes flash memories,
The flash memories are the flash memories in previous embodiment one, or according to embodiment two
Flash memories preparation method obtained by flash memories.
The electronic installation, can be mobile phone, tablet personal computer, notebook computer, net book, trip
Gaming machine, television set, VCD, DVD, navigator, camera, video camera, recording pen,
Any electronic product such as MP3, MP4, PSP or equipment or with above-mentioned semiconductor
The intermediate products of device, for example：Cell phone mainboard with the integrated circuit etc..
Due to including flash storage device there is higher performance, the electronic installation equally has
Above-mentioned advantage.
Wherein, Fig. 5 shows the example of mobile phone handsets.Mobile phone handsets 500 are set
It is equipped with the display portion 502 being included in shell 501, operation button 503, external connection terminal
Mouth 504, loudspeaker 505, microphone 506 etc..
Wherein described mobile phone handsets include foregoing flash memories, or according to embodiment one
Flash memories obtained by the preparation method of described flash memories, the flash memories
All storage positions (bit) of flash memory (flash) electronics is all injected first to become to program (program)
State.According to the UV light time, intensity is bigger, corresponding flash memory position threshold voltage (flash bit VT)
Reduction is more, and flash memory (flash) has decoding (decoder) region, it can be determined that go out this
Store position (bit) position in an array, and threshold voltage (VT) power, you can
Draw ultraviolet light image.Because flash memory (flash) is non-volatility memorizer, therefore can be with
Retain this image for a long time.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
The purpose that embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that not office of the invention
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repaiied
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (12)
1. a kind of flash memories with camera function, it is characterised in that the flash memory is deposited
Reservoir includes some memory cells, and the memory cell includes：
Substrate；
Gate stack, above the substrate, including stack gradually tunnel oxide layer,
Floating gate layer, separation layer and control grid layer；
Interconnection structure, is electrically connected positioned at the top of the gate stack and with the gate stack；
Filter coating, positioned at the top of interconnection structure；
On prism, the surface for being arranged at the filter coating.
2. flash memories according to claim 1, it is characterised in that described mutual
Passivation layer is also formed with below company's superstructure, the filter coating, the passivation layer has flat
Smooth surface.
3. flash memories according to claim 1, it is characterised in that the optical filtering
Film is ultraviolet filter film.
4. flash memories according to claim 1, it is characterised in that the interconnection
Structure includes some through holes and some metal levels being arranged alternately, the length and width of some through holes
Critical size be less than the prism length and wide critical size；The length and width of the metal level
Critical size be less than the prism length and wide critical size.
5. flash memories according to claim 1, it is characterised in that the prism
Square structure.
6. flash memories according to claim 1, it is characterised in that the flash memory
Some row wordline and several columns bit line of memory including setting intersected with each other, in the wordline and
The infall of bit line is provided with above-mentioned memory cell.
7. flash memories according to claim 6, it is characterised in that the storage
Distance between device unit is equal.
8. a kind of preparation method of the flash memories with uv photography function, its feature exists
In methods described includes：
Substrate is provided, gate stack is formed on the substrate, wherein the gate stack includes
Tunnel oxide layer, floating gate layer, separation layer and the control grid layer stacked gradually；
Interconnection structure is formed on the gate stack to electrically connect with gate stack formation；
Filter coating and prism are sequentially formed above the interconnection structure, to form imager
Part.
9. preparation method according to claim 8, it is characterised in that described being formed
It may further include before prism and passivation layer formed above the interconnection structure and is planarized
The step of passivation layer.
10. preparation method according to claim 8, it is characterised in that the mutual link
Structure includes some through holes and some metal levels that are arranged alternately, the length of some through holes and wide
Critical size is less than the length and wide critical size of the prism；The length of the metal level and wide
Critical size is less than the length and wide critical size of the prism.
11. preparation method according to claim 8, it is characterised in that the filter coating
For ultraviolet filter film.
12. a kind of electronic installation, it is characterised in that including such as one of claim 1 to 7 institute
The flash memories stated.
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| CN201610208297.XA CN107302005A (en) | 2016-04-05 | 2016-04-05 | A kind of flash memories and preparation method, electronic installation with camera function |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6784933B1 (en) * | 1999-09-10 | 2004-08-31 | Kabushiki Kaisha Toshiba | Solid-state imaging device and method for controlling same |
| CN1992231A (en) * | 2005-12-28 | 2007-07-04 | 海力士半导体有限公司 | Method of manufacturing flash memory device |
| WO2016038986A1 (en) * | 2014-09-11 | 2016-03-17 | 株式会社 東芝 | Image pickup device |
-
2016
- 2016-04-05 CN CN201610208297.XA patent/CN107302005A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6784933B1 (en) * | 1999-09-10 | 2004-08-31 | Kabushiki Kaisha Toshiba | Solid-state imaging device and method for controlling same |
| CN1992231A (en) * | 2005-12-28 | 2007-07-04 | 海力士半导体有限公司 | Method of manufacturing flash memory device |
| WO2016038986A1 (en) * | 2014-09-11 | 2016-03-17 | 株式会社 東芝 | Image pickup device |
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Application publication date: 20171027 |