WO2016019561A1 - 一种数据处理装置及飞行器 - Google Patents

一种数据处理装置及飞行器 Download PDF

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WO2016019561A1
WO2016019561A1 PCT/CN2014/083946 CN2014083946W WO2016019561A1 WO 2016019561 A1 WO2016019561 A1 WO 2016019561A1 CN 2014083946 W CN2014083946 W CN 2014083946W WO 2016019561 A1 WO2016019561 A1 WO 2016019561A1
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Prior art keywords
clock
detector
processor
data
signal
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PCT/CN2014/083946
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English (en)
French (fr)
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杨康
周谷越
余雷
高欣
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深圳市大疆创新科技有限公司
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Priority to CN201480005208.0A priority Critical patent/CN105518639B/zh
Priority to JP2016528176A priority patent/JP6289633B2/ja
Priority to PCT/CN2014/083946 priority patent/WO2016019561A1/zh
Publication of WO2016019561A1 publication Critical patent/WO2016019561A1/zh
Priority to US15/426,087 priority patent/US10108188B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05D—SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
    • G05D1/00—Control of position, course, altitude or attitude of land, water, air or space vehicles, e.g. using automatic pilots
    • G05D1/0011—Control of position, course, altitude or attitude of land, water, air or space vehicles, e.g. using automatic pilots associated with a remote control arrangement
    • G05D1/0038—Control of position, course, altitude or attitude of land, water, air or space vehicles, e.g. using automatic pilots associated with a remote control arrangement by providing the operator with simple or augmented images from one or more cameras located onboard the vehicle, e.g. tele-operation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B64—AIRCRAFT; AVIATION; COSMONAUTICS
    • B64C—AEROPLANES; HELICOPTERS
    • B64C39/00—Aircraft not otherwise provided for
    • B64C39/02—Aircraft not otherwise provided for characterised by special use
    • B64C39/024—Aircraft not otherwise provided for characterised by special use of the remote controlled vehicle type, i.e. RPV
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/1774—Structural details of routing resources for global signals, e.g. clock, reset
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/745—Circuitry for generating timing or clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B64—AIRCRAFT; AVIATION; COSMONAUTICS
    • B64U—UNMANNED AERIAL VEHICLES [UAV]; EQUIPMENT THEREFOR
    • B64U10/00—Type of UAV
    • B64U10/10—Rotorcrafts
    • B64U10/13—Flying platforms
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B64—AIRCRAFT; AVIATION; COSMONAUTICS
    • B64U—UNMANNED AERIAL VEHICLES [UAV]; EQUIPMENT THEREFOR
    • B64U2101/00—UAVs specially adapted for particular uses or applications
    • B64U2101/30—UAVs specially adapted for particular uses or applications for imaging, photography or videography
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B64—AIRCRAFT; AVIATION; COSMONAUTICS
    • B64U—UNMANNED AERIAL VEHICLES [UAV]; EQUIPMENT THEREFOR
    • B64U2201/00—UAVs characterised by their flight controls
    • B64U2201/20—Remote controls
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/40—Bus coupling

Definitions

  • the present invention relates to the field of electronic technologies, and in particular, to a data processing device and an aircraft.
  • FPGA Field-Programmable Gate Array
  • FPGA Semi-custom integrated circuit
  • the data transmission mode based on LVDS (Low Voltage Differential Signaling) interface has been widely used in devices including image sensors because of its high rate of data transmission, low noise, low power consumption and the like.
  • the clock output channel of the LVDS includes two, and the related pins are the differential clock signal positive terminal and the differential clock signal negative terminal.
  • FIG. 1 shows an existing connection method in which only one image sensor can be connected in an FPGA with only one pair of dedicated clock pins. After the differential clock signals of the two LVDSs are respectively input, the FPGA performs fusion calculation to obtain a clock signal for sampling the input data signal, and samples the data signal based on the clock signal.
  • the PLL and the dedicated clock pin are both scarce resources.
  • the current method of connecting the link with the dual clock signal to the FPGA clock pin limits the dual clock signal that the single FPGA can access.
  • the embodiment of the invention provides a data processing device and an aircraft, which can increase the number of corresponding detectors on the basis of the original FPGA.
  • Embodiments of the present invention provide a data processing apparatus including: a detector for sensing a data signal, a processor for processing the data signal based on a clock signal, and a clock converter,
  • a data signal output pin of the detector is connected to a data signal input pin of the processor
  • the detector includes at least two clock output pins, and each clock output pin of the detector is connected to an input pin of the clock converter;
  • An output pin of the clock converter is coupled to a clock input pin of the processor
  • the clock converter is configured to convert a clock signal input from each input pin into a single-ended clock signal, and output the single-ended clock signal to the processor through the output pin.
  • the detector is a detector based on a differential clock signal
  • a positive clock signal of the detector is connected to a first input pin of the clock converter
  • the negative terminal of the differential clock signal of the detector is connected to the second input pin of the clock converter
  • the clock converter is specifically configured to convert the differential clock signal output by the detector into a single-ended clock signal and output the signal to the processor.
  • a distance between a positive clock signal of the detector and a first input pin of the clock converter is greater than an output pin of the clock converter to an input pin of the processor
  • a distance between the negative terminal of the differential clock signal of the detector and the second input pin of the clock converter is greater than an output pin of the clock converter to the processor Enter the distance between the pins.
  • the detector comprises an image sensor using a low voltage differential signal interface
  • the processor comprises a processor formed by a programmable logic gate array FPGA.
  • the device further includes: a data executor
  • the data executor is configured to respond to data processed by the processor input from the data input pin.
  • an embodiment of the present invention further provides an aircraft, including: a detector, a processor, and a clock converter, wherein:
  • the detector is configured to sense a related data signal during flight
  • the processor is configured to process the data signal based on a clock signal
  • a data signal output pin of the detector is connected to a data signal input pin of the processor
  • the detector includes at least two clock output pins, and each clock output pin of the detector is connected to an input pin of the clock converter;
  • An output pin of the clock converter is coupled to a clock input pin of the processor
  • the clock converter is configured to convert a clock signal input from each input pin into a single-ended clock signal, and output the single-ended clock signal to the processor through the output pin.
  • the detector is a detector based on a differential clock signal
  • a positive clock signal of the detector is connected to a first input pin of the clock converter
  • the negative terminal of the differential clock signal of the detector is connected to the second input pin of the clock converter
  • the clock converter is specifically configured to convert the differential clock signal output by the detector into a single-ended clock signal and output the signal to the processor.
  • a distance between a positive clock signal of the detector and a first input pin of the clock converter is greater than an output pin of the clock converter to an input pin of the processor
  • a distance between the negative terminal of the differential clock signal of the detector and the second input pin of the clock converter is greater than an output pin of the clock converter to the processor Enter the distance between the pins.
  • the detector comprises an image sensor using a low voltage differential signal interface
  • the processor comprises a processor formed by a programmable logic gate array FPGA.
  • the aircraft further includes: a data executor
  • the data executor is configured to respond to data processed by the processor input from the data input pin.
  • the data executor is a flight controller or a communication module for transmitting visual data.
  • the embodiment of the invention can enable the processor composed of a single FPGA to access more detectors with two clock signals or other multi-channels on the basis of the original processor composed of a single FPGA.
  • the detector of the clock signal extends the access of the detector at low cost.
  • FIG. 1 is a schematic diagram of a connection between a conventional camera and a processor composed of an FPGA;
  • FIG. 2 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present invention.
  • the embodiment of the invention adopts a clock converter, and can directly process two clock signals according to requirements before the clock signal is connected to the processor formed by the FPGA, and becomes one signal input into the processor formed by the FPGA.
  • the clock converter directly converts the positive terminal LVDS_CLK_P signal of the differential clock signal and the negative terminal LVDS_CLK_N signal of the differential clock signal to obtain a path for indicating data signal sampling.
  • the clock signal is input to the FPGA.
  • FIG. 2 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present invention.
  • the apparatus can be applied to a scene such as image acquisition processing, and can be specifically set in a drone to complete an acquisition and processing function such as an aerial image. Of course, it can also be in equipment such as remote control cars and robots.
  • the apparatus includes: a detector 1 for sensing a data signal, a processor 2 for processing the data signal based on a clock signal, and a clock converter 3, wherein the data signal of the detector 1 An output pin is coupled to the data signal input pin of the processor 2; a first clock output pin of the detector 1 is coupled to a first input pin of the clock converter 3, the detector 1 a second clock output pin is coupled to the second input pin of the clock converter 3;
  • An output pin of the clock converter 3 is connected to a clock input pin of the processor 2;
  • the clock converter 3 is configured to convert a clock signal input from the first input pin and the second input pin into a single-ended clock signal, and output the single-ended clock signal to the processor 2.
  • the detector 1 may be an image sensor such as a camera, and is connected to the processor 2 by using an LVDS interface.
  • the processor 2 is based on an FPGA.
  • the processor 2 composed of an FPGA includes at least a pair of clock interfaces.
  • the detector 1 is a detector 1 based on a differential clock signal; a positive clock signal of the detector 1 is connected to a first input pin of the clock converter 3 The negative terminal of the differential clock signal of the detector 1 is connected to the second input pin of the clock converter 3;
  • the clock converter 3 is specifically configured to convert the differential clock signal output by the detector 1 into a single-ended clock signal and output the signal to the processor 2.
  • LVDS_data_P/N is a data output interface of the detector 1. After acquiring the original data signal such as an image, the detector 1 outputs the data signal to the processor 2 through the LVDS_data_P/N output pin.
  • the positive terminal interface of the LVDS_CLK_P differential clock signal and the negative terminal interface of the LVDS_CLK_N differential clock signal respectively transmit a differential clock signal to the clock converter 3.
  • the clock converter 3 may specifically be a differential signal to a single-ended signal converter. After combining the two signals, a clock signal is obtained and connected to a clock pin of the processor 2, and the processing is performed.
  • the device 2 directly samples the data signal received from the LVDS_data_P/N pin according to a clock signal converted by the clock converter 3, and obtains a corresponding digital signal such as a digital image signal.
  • the clock converter 3 can also be a comparator for comparing the input two clock signals. When the comparison result is greater than 0, the output level value is 1 signal, and when the comparison result is less than or equal to 0, the output is output. A signal with a flat value of zero.
  • the processor 2 which is composed of an FPGA, can process the digital data of the original data by performing processing such as sampling, and can also configure other functions, such as image pixel compensation, as needed, and is not specifically described herein.
  • a distance between a positive clock signal of the detector 1 and a first input pin of the clock converter 3 is greater than an input of the clock converter 3 to an input of the processor 2 a distance between the pins; and/or a distance between a negative terminal of the differential clock signal of the detector 1 and a second input pin of the clock converter 3 is greater than an output pin of the clock converter 3 The distance between the input pins of the processor 2.
  • the length of the signal transmission line between the detector 1 and the clock converter 3 can be made larger than that of the clock converter 3 to the processor 2. The length of the signal transmission line to reduce signal interference.
  • the apparatus of the embodiment of the present invention may further include a data executor, a data input pin of the data executor and a data output pin of the processor 2; and the data executor Responsive to data processed by the processor 2 input from the data input pin.
  • the data executor may specifically be a controller, a display, a communication module, or the like.
  • the processor 2 After the processor 2 obtains the desired digital signal, it sends it to the controller, so that the controller performs corresponding control processing according to the digital signal. For example, in flight control, the controller can detect an obstacle based on the camera. Controlling the completion of the obstacle-avoiding flight operation; or after the processor 2 obtains the desired digital signal, transmitting it to the display, directly analyzing and displaying the image corresponding to the digital signal by the display; or obtaining the desired image in the processor 2 After the digital signal is sent to the communication module, it is sent by the communication module to the corresponding user terminal.
  • the embodiment of the present invention can enable the processor 2 composed of a single FPGA to access more LVDS or the like with two channels or the like without increasing the size, weight and cost of the processor 2 composed of a single FPGA.
  • the detector 1 with multiple clock signals extends the access of the detector 1 at low cost.
  • An embodiment of the present invention further provides an aircraft, including a fixed wing aircraft, a rotorcraft, and the like.
  • the aircraft includes: a detector, a processor, and a clock converter, wherein:
  • the detector is configured to sense a related data signal during flight
  • the processor is configured to process the data signal based on a clock signal
  • a data signal output pin of the detector is connected to a data signal input pin of the processor
  • the detector includes at least two clock output pins, and each clock output pin of the detector is connected to an input pin of the clock converter;
  • An output pin of the clock converter is coupled to a clock input pin of the processor
  • the clock converter is configured to convert a clock signal input from each input pin into a single-ended clock signal, and output the single-ended clock signal to the processor through the output pin.
  • the detector is a detector based on a differential clock signal
  • a positive clock signal of the detector is connected to a first input pin of the clock converter
  • the negative terminal of the differential clock signal of the detector is connected to the second input pin of the clock converter
  • the clock converter is specifically configured to convert the differential clock signal output by the detector into a single-ended clock signal and output the signal to the processor.
  • a distance between a positive clock signal of the detector and a first input pin of the clock converter is greater than an output pin of the clock converter to an input pin of the processor
  • a distance between the negative terminal of the differential clock signal of the detector and the second input pin of the clock converter is greater than an output pin of the clock converter to the processor Enter the distance between the pins.
  • the detector comprises an image sensor employing a low voltage differential signal interface
  • the processor comprises a processor comprised of a programmable logic gate array FPGA.
  • the aircraft may further include: a data executor
  • the data executor is configured to respond to data processed by the processor input from the data input pin.
  • the data executor is a flight controller or a communication module for transmitting visual data.
  • a specific implementation of the various components in the aircraft may correspond to the description of the related structure in the data processing device embodiment corresponding to FIG.
  • the embodiment of the invention can enable a processor composed of a single FPGA to access more LVDS or the like with two paths or other bands without increasing the size, weight and cost of the processor composed of a single FPGA.
  • the detector of the road clock signal expands the access amount of the detector at a low cost, and also expands the function of the aircraft at low cost.

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Abstract

一种数据处理装置及飞行器，装置包括：探测器（1），处理器（2），以及时钟转换器，探测器（1）的数据信号输出引脚与处理器（2）的数据信号输入引脚相连；探测器（1）包括至少两个时钟输出引脚，探测器（1）的每一个时钟输出引脚与时钟转换器的一输入引脚相连；时钟转换器的输出引脚与处理器（2）的时钟输入引脚相连；时钟转换器，用于将从各输入引脚输入的时钟信号转换为单端时钟信号，并将单端时钟信号通过输出引脚输出至处理器（2）。在不增加单片ＦＰＧＡ构成的处理器的尺寸、重量及成本的情况下，扩展了探测器（1）的接入量，也低成本地扩展了飞行器的功能。

Description

一种数据处理装置及飞行器 技术领域
本发明涉及电子技术领域，尤其涉及一种数据处理装置及飞行器。
背景技术
FPGA（Field-Programmable Gate Array，可编程逻辑门阵列）是FPGA（Field-Programmable Gate Array，可编程逻辑门阵列）是一种半定制的集成电路，用户通过编程可以把FPGA设计成任意的数字集成电路芯片， 因为其灵活性，FPGA是数字信号接口的最佳选择。
基于LVDS（Low Voltage Differential Signaling，低压差分信号）接口的数据传输方式以其可高速率传输数据，低噪声、低功耗等优点，已在包括图像传感器等装置中得到广泛的应用。LVDS的时钟输出通道包括两个，相关引脚为差分时钟信号正端和差分时钟信号负端。
LVDS在与FPGA配合进行数据处理时，一个LVDS 链路就需要占用FPGA上的一个PLL和一对专用时钟管脚。图1示出了一种现有的连接方式，在只有一对专用时钟管脚的FPGA中，就只能接入一个图像传感器。在两路LVDS的差分时钟信号分别输入后，FPGA会对其进行融合计算，得到用于对输入的数据信号进行采样的时钟信号，并基于该时钟信号对数据信号进行采样。
在FPGA中，PLL和专用时钟管脚都是紧缺的资源，目前采用的将具有双时钟信号的链路接入FPGA时钟管脚的方式，限制了单片FPGA可以接入的具有双时钟信号的摄像头等探测器的数量。
发明内容
本发明实施例提供了一种数据处理装置及飞行器，能够在原有FPGA的基础上增加接入相应探测器的数量。
本发明实施例提供了一种数据处理装置，包括：用于感测数据信号的探测器，用于基于时钟信号处理所述数据信号的处理器，以及时钟转换器，
所述探测器的数据信号输出引脚与所述处理器的数据信号输入引脚相连；
所述探测器包括至少两个时钟输出引脚，所述探测器的每一个时钟输出引脚与所述时钟转换器的一输入引脚相连；
所述时钟转换器的输出引脚与所述处理器的时钟输入引脚相连；
所述时钟转换器，用于将从各输入引脚输入的时钟信号转换为单端时钟信号，并将所述单端时钟信号通过所述输出引脚输出至所述处理器。
其中可选地，所述探测器为基于差分时钟信号的探测器；
所述探测器的差分时钟信号正端与所述时钟转换器的第一输入引脚相连；
所述探测器的差分时钟信号负端与所述时钟转换器的第二输入引脚相连；
所述时钟转换器，具体用于将所述探测器输出的差分时钟信号转换为单端时钟信号，并输出至所述处理器。
其中可选地，所述探测器的差分时钟信号正端到所述时钟转换器的第一输入引脚之间的距离大于所述时钟转换器的输出引脚到所述处理器的输入引脚之间的距离；和/或所述探测器的差分时钟信号负端到所述时钟转换器的第二输入引脚之间的距离大于所述时钟转换器的输出引脚到所述处理器的输入引脚之间的距离。
其中可选地，所述探测器包括采用低压差分信号接口的图像传感器；所述处理器包括可编程逻辑门阵列FPGA构成的处理器。
其中可选地，所述装置还包括：数据执行器；
所述数据执行器的数据输入引脚与所述处理器的数据输出引脚；
所述数据执行器，用于响应从所述数据输入引脚输入的由所述处理器处理后的数据。
相应地，本发明实施例还提供了一种飞行器，包括：探测器、处理器及时钟转换器，其中：
所述探测器，用于在飞行过程中，感测相关的数据信号；
所述处理器，用于基于时钟信号处理所述数据信号；
所述探测器的数据信号输出引脚与所述处理器的数据信号输入引脚相连；
所述探测器包括至少两个时钟输出引脚，所述探测器的每一个时钟输出引脚与所述时钟转换器的一输入引脚相连；
所述时钟转换器的输出引脚与所述处理器的时钟输入引脚相连；
所述时钟转换器，用于将从各输入引脚输入的时钟信号转换为单端时钟信号，并将所述单端时钟信号通过所述输出引脚输出至所述处理器。
其中可选地，所述探测器为基于差分时钟信号的探测器；
所述探测器的差分时钟信号正端与所述时钟转换器的第一输入引脚相连；
所述探测器的差分时钟信号负端与所述时钟转换器的第二输入引脚相连；
所述时钟转换器，具体用于将所述探测器输出的差分时钟信号转换为单端时钟信号，并输出至所述处理器。
其中可选地，所述探测器的差分时钟信号正端到所述时钟转换器的第一输入引脚之间的距离大于所述时钟转换器的输出引脚到所述处理器的输入引脚之间的距离；和/或所述探测器的差分时钟信号负端到所述时钟转换器的第二输入引脚之间的距离大于所述时钟转换器的输出引脚到所述处理器的输入引脚之间的距离。
其中可选地，所述探测器包括采用低压差分信号接口的图像传感器；所述处理器包括可编程逻辑门阵列FPGA构成的处理器。
其中可选地，所述飞行器还包括：数据执行器；
所述数据执行器的数据输入引脚与所述处理器的数据输出引脚；
所述数据执行器，用于响应从所述数据输入引脚输入的由所述处理器处理后的数据。
其中可选地，所述数据执行器为飞行控制器，或者为用于传输视觉数据的通信模块。
本发明实施例能够在原有的由单片FPGA构成的处理器的基础上，使该由单片FPGA构成的处理器能够接入更多的带两路时钟信号的探测器或者其他的带多路时钟信号的探测器，低成本地扩展了探测器的接入量。
 附图说明
图1是现有的摄像头和FPGA构成的处理器的连接示意图；
图2是本发明实施例的一种数据处理装置的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例采用时钟转换器，可以直接在时钟信号接入到FPGA构成的处理器之前，将两路时钟信号按照需要进行处理，变为一路信号输入到FPGA构成的处理器中。例如，对于上述涉及的LVDS对应的两路差分时钟信号，所述时钟转换器对差分时钟信号的正端LVDS_CLK_P信号和差分时钟信号的负端LVDS_CLK_N信号直接融合转换，得到一路用于指示数据信号采样的时钟信号输入给FPGA。
请参见图2，是本发明实施例的一种数据处理装置的结构示意图，该装置可以应用在图像采集处理等场景中，具体可设置在无人机中，完成如航拍图像的采集与处理功能，当然也可以是诸如遥控汽车、机器人等设备中。
具体的，所述装置包括：用于感测数据信号的探测器1，用于基于时钟信号处理所述数据信号的处理器2，以及时钟转换器3，其中，所述探测器1的数据信号输出引脚与所述处理器2的数据信号输入引脚相连；所述探测器1的第一时钟输出引脚与所述时钟转换器3的第一输入引脚相连，所述探测器1的第二时钟输出引脚与所述时钟转换器3的第二输入引脚相连；
所述时钟转换器3的输出引脚与所述处理器2的时钟输入引脚相连；
所述时钟转换器3，用于将从第一输入引脚和第二输入引脚输入的时钟信号转换为单端时钟信号，并将所述单端时钟信号输出至所述处理器2。
具体如图2所示，所述探测器1具体可以为摄像头等图像传感器，其采用LVDS接口与所述处理器2相连。所述处理器2基于FPGA构成，在本发明实施例中，该由FPGA构成的处理器2至少包括一对时钟接口。
具体的，在本发明实施例中，所述探测器1为基于差分时钟信号的探测器1；所述探测器1的差分时钟信号正端与所述时钟转换器3的第一输入引脚相连；所述探测器1的差分时钟信号负端与所述时钟转换器3的第二输入引脚相连；
所述时钟转换器3，具体用于将所述探测器1输出的差分时钟信号转换为单端时钟信号，并输出至所述处理器2。所述图2中，LVDS_data_P/N为探测器1的数据输出接口，探测器1在采集到图像等原始数据信号后，将数据信号通过LVDS_data_P/N输出引脚输出至所述处理器2中。LVDS_CLK_P差分时钟信号的正端接口，LVDS_CLK_N差分时钟信号的负端接口，分别传输一路差分时钟信号至时钟转换器3。
时钟转换器3具体可以是差分信号到单端信号的转换器，其在对两路信号进行融合后，得到一路时钟信号，接入到所述处理器2的一时钟引脚上，所述处理器2直接根据时钟转换器3转换得到的一路时钟信号，对从LVDS_data_P/N引脚接收到的数据信号进行采样，得到相应的如数字图像信号等数字信号。具体的，该时钟转换器3也可以为一个比较器，对于输入的两路时钟信号进行比较，当比较结果大于0时，输出电平值为1的信号，而小于等于0时，则输出电平值为0的信号。
当然，由FPGA构成的所述处理器2除了可以进行采样等处理得到原始数据的数字数据的处理外，还可以根据需要配置其他的功能，例如图片像素补偿等处理功能，在此不具体描述。
进一步地，所述探测器1的差分时钟信号正端到所述时钟转换器3的第一输入引脚之间的距离大于所述时钟转换器3的输出引脚到所述处理器2的输入引脚之间的距离；和/或所述探测器1的差分时钟信号负端到所述时钟转换器3的第二输入引脚之间的距离大于所述时钟转换器3的输出引脚到所述处理器2的输入引脚之间的距离。
由于LVDS的两路差分时钟信号的摆幅较小，产生的干扰也比较小，所以可以让探测器1到时钟转换器3之间信号传输线的长度大于时钟转换器3到所述处理器2之间信号传输线的长度，以降低信号干扰。
进一步可选地，本发明实施例的所述装置还可以包括一数据执行器，所述数据执行器的数据输入引脚与所述处理器2的数据输出引脚；所述数据执行器，用于响应从所述数据输入引脚输入的由所述处理器2处理后的数据。
该数据执行器具体可以为控制器，显示器，通信模块等。在所述处理器2得到想要的数字信号后，发送给控制器，以使控制器根据该数字信号执行相应的控制处理，例如，在飞行控制中，控制器可以基于摄像头探测到的障碍物，控制完成避障飞行操作；或者在所述处理器2得到想要的数字信号后，发送给显示器，由显示器直接解析并显示数字信号对应的图像；或者在所述处理器2得到想要的数字信号后，发送给通信模块，由通信模块发送给对应的用户终端。
本发明实施例能够在不增加单片FPGA构成的处理器2的尺寸、重量以及成本的情况下，使由单片FPGA构成的处理器2能够接入更多的LVDS等带两路或者其他的带多路时钟信号的探测器1，低成本地扩展了探测器1的接入量。
本发明实施例还提供了一种飞行器，包括固定翼飞行器、旋翼飞行器等，具体的，所述飞行器包括：探测器、处理器及时钟转换器，其中：
所述探测器，用于在飞行过程中，感测相关的数据信号；
所述处理器，用于基于时钟信号处理所述数据信号；
所述探测器的数据信号输出引脚与所述处理器的数据信号输入引脚相连；
所述探测器包括至少两个时钟输出引脚，所述探测器的每一个时钟输出引脚与所述时钟转换器的一输入引脚相连；
所述时钟转换器的输出引脚与所述处理器的时钟输入引脚相连；
所述时钟转换器，用于将从各输入引脚输入的时钟信号转换为单端时钟信号，并将所述单端时钟信号通过所述输出引脚输出至所述处理器。
进一步可选地，所述探测器为基于差分时钟信号的探测器；
所述探测器的差分时钟信号正端与所述时钟转换器的第一输入引脚相连；
所述探测器的差分时钟信号负端与所述时钟转换器的第二输入引脚相连；
所述时钟转换器，具体用于将所述探测器输出的差分时钟信号转换为单端时钟信号，并输出至所述处理器。
进一步可选地，所述探测器的差分时钟信号正端到所述时钟转换器的第一输入引脚之间的距离大于所述时钟转换器的输出引脚到所述处理器的输入引脚之间的距离；和/或所述探测器的差分时钟信号负端到所述时钟转换器的第二输入引脚之间的距离大于所述时钟转换器的输出引脚到所述处理器的输入引脚之间的距离。
进一步可选地，所述探测器包括采用低压差分信号接口的图像传感器；所述处理器包括可编程逻辑门阵列FPGA构成的处理器。
进一步可选地，所述飞行器还可以包括：数据执行器；
所述数据执行器的数据输入引脚与所述处理器的数据输出引脚；
所述数据执行器，用于响应从所述数据输入引脚输入的由所述处理器处理后的数据。
进一步可选地，所述数据执行器为飞行控制器，或者为用于传输视觉数据的通信模块。
飞行器中各个组件的具体实现可对应地在参考图2对应的数据处理装置实施例中相关结构的描述。
本发明实施例能够在不增加单片FPGA构成的处理器的尺寸、重量以及成本的情况下，使由单片FPGA构成的处理器能够接入更多的LVDS等带两路或者其他的带多路时钟信号的探测器，低成本地扩展了探测器的接入量，也低成本地扩展了飞行器的功能。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (11)

  1. 一种数据处理装置，其特征在于，包括：用于感测数据信号的探测器，用于基于时钟信号处理所述数据信号的处理器，以及时钟转换器，
    所述探测器的数据信号输出引脚与所述处理器的数据信号输入引脚相连；
    所述探测器包括至少两个时钟输出引脚，所述探测器的每一个时钟输出引脚与所述时钟转换器的一输入引脚相连；
    所述时钟转换器的输出引脚与所述处理器的时钟输入引脚相连；
    所述时钟转换器，用于将从各输入引脚输入的时钟信号转换为单端时钟信号，并将所述单端时钟信号通过所述输出引脚输出至所述处理器。
  2. 如权利要求1所述的装置，其特征在于，所述探测器为基于差分时钟信号的探测器；
    所述探测器的差分时钟信号正端与所述时钟转换器的第一输入引脚相连；
    所述探测器的差分时钟信号负端与所述时钟转换器的第二输入引脚相连；
    所述时钟转换器，具体用于将所述探测器输出的差分时钟信号转换为单端时钟信号，并输出至所述处理器。
  3. 如权利要求2所述的装置，其特征在于，
    所述探测器的差分时钟信号正端到所述时钟转换器的第一输入引脚之间的距离大于所述时钟转换器的输出引脚到所述处理器的输入引脚之间的距离；
    和/或
    所述探测器的差分时钟信号负端到所述时钟转换器的第二输入引脚之间的距离大于所述时钟转换器的输出引脚到所述处理器的输入引脚之间的距离。
  4. 如权利要求1所述的装置，其特征在于，
    所述探测器包括采用低压差分信号接口的图像传感器；
    所述处理器包括可编程逻辑门阵列FPGA构成的处理器。
  5. 如权利要求3所述的装置，其特征在于，还包括：数据执行器；
    所述数据执行器的数据输入引脚与所述处理器的数据输出引脚；
    所述数据执行器，用于响应从所述数据输入引脚输入的由所述处理器处理后的数据。
  6. 一种飞行器，其特征在于，包括：探测器、处理器及时钟转换器，其中：
    所述探测器，用于在飞行过程中，感测相关的数据信号；
    所述处理器，用于基于时钟信号处理所述数据信号；
    所述探测器的数据信号输出引脚与所述处理器的数据信号输入引脚相连；
    所述探测器包括至少两个时钟输出引脚，所述探测器的每一个时钟输出引脚与所述时钟转换器的一输入引脚相连；
    所述时钟转换器的输出引脚与所述处理器的时钟输入引脚相连；
    所述时钟转换器，用于将从各输入引脚输入的时钟信号转换为单端时钟信号，并将所述单端时钟信号通过所述输出引脚输出至所述处理器。
  7. 如权利要求6所述的飞行器，其特征在于，所述探测器为基于差分时钟信号的探测器；
    所述探测器的差分时钟信号正端与所述时钟转换器的第一输入引脚相连；
    所述探测器的差分时钟信号负端与所述时钟转换器的第二输入引脚相连；
    所述时钟转换器，具体用于将所述探测器输出的差分时钟信号转换为单端时钟信号，并输出至所述处理器。
  8. 如权利要求7所述的飞行器，其特征在于，所述探测器的差分时钟信号正端到所述时钟转换器的第一输入引脚之间的距离大于所述时钟转换器的输出引脚到所述处理器的输入引脚之间的距离；
    和/或
    所述探测器的差分时钟信号负端到所述时钟转换器的第二输入引脚之间的距离大于所述时钟转换器的输出引脚到所述处理器的输入引脚之间的距离。
  9. 如权利要求8所述的飞行器，其特征在于，
    所述探测器包括采用低压差分信号接口的图像传感器；
    所述处理器包括可编程逻辑门阵列FPGA构成的处理器。
  10. 如权利要求8所述的飞行器，其特征在于，还包括：数据执行器；
    所述数据执行器的数据输入引脚与所述处理器的数据输出引脚；
    所述数据执行器，用于响应从所述数据输入引脚输入的由所述处理器处理后的数据。
  11. 如权利要求8所述的飞行器，其特征在于，所述数据执行器为飞行控制器，或者为用于传输视觉数据的通信模块。
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