WO2016014166A1 - Système et procédé pour inhiber l'effacement d'une partie de secteur de cellules de mémoire flash à grille divisée - Google Patents

Système et procédé pour inhiber l'effacement d'une partie de secteur de cellules de mémoire flash à grille divisée Download PDF

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Publication number
WO2016014166A1
WO2016014166A1 PCT/US2015/035360 US2015035360W WO2016014166A1 WO 2016014166 A1 WO2016014166 A1 WO 2016014166A1 US 2015035360 W US2015035360 W US 2015035360W WO 2016014166 A1 WO2016014166 A1 WO 2016014166A1
Authority
WO
WIPO (PCT)
Prior art keywords
flash memory
memory cells
row
gate
rows
Prior art date
Application number
PCT/US2015/035360
Other languages
English (en)
Inventor
Jinho Kim
Nhan Do
Yuri Tkachev
Kai Man Yue
Xiaozhou QIAN
Ning BAI
Original Assignee
Silicon Storage Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201410447574.3A external-priority patent/CN105609131A/zh
Application filed by Silicon Storage Technology, Inc. filed Critical Silicon Storage Technology, Inc.
Priority to KR1020177004734A priority Critical patent/KR20170037996A/ko
Priority to EP15731210.9A priority patent/EP3172733B1/fr
Priority to JP2017503134A priority patent/JP6532522B2/ja
Priority to TW104120307A priority patent/TWI592935B/zh
Publication of WO2016014166A1 publication Critical patent/WO2016014166A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)

Abstract

L'invention concerne un système et un procédé pour inhiber l'effacement d'une partie d'un secteur de cellules de mémoire flash à grille divisée tout en permettant au reste du secteur d'être effacé. L'inhibition est commandée par une logique de commande qui applique une ou plusieurs tensions de polarisation à la partie du secteur dont l'effacement doit être inhibé.
PCT/US2015/035360 2014-07-22 2015-06-11 Système et procédé pour inhiber l'effacement d'une partie de secteur de cellules de mémoire flash à grille divisée WO2016014166A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020177004734A KR20170037996A (ko) 2014-07-22 2015-06-11 분리형 게이트 플래시 메모리 셀들의 섹터의 일부분의 소거를 억제하는 시스템 및 방법
EP15731210.9A EP3172733B1 (fr) 2014-07-22 2015-06-11 Système et procédé pour inhiber l'effacement d'une partie de secteur de cellules de mémoire flash à grille divisée
JP2017503134A JP6532522B2 (ja) 2014-07-22 2015-06-11 スプリットゲートフラッシュメモリセルのセクタの一部分の消去を禁止するシステム及び方法
TW104120307A TWI592935B (zh) 2014-07-22 2015-06-24 用以抑制抹除分離閘快閃記憶體單元之部分磁區之系統與方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201410447574.3A CN105609131A (zh) 2014-07-22 2014-07-22 抑制擦除分裂栅闪存存储器单元扇区的部分的系统和方法
CN201410447574.3 2014-07-22
US14/486,687 2014-09-15
US14/486,687 US9633735B2 (en) 2014-07-22 2014-09-15 System and method to inhibit erasing of portion of sector of split gate flash memory cells

Publications (1)

Publication Number Publication Date
WO2016014166A1 true WO2016014166A1 (fr) 2016-01-28

Family

ID=53484184

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2015/035360 WO2016014166A1 (fr) 2014-07-22 2015-06-11 Système et procédé pour inhiber l'effacement d'une partie de secteur de cellules de mémoire flash à grille divisée

Country Status (1)

Country Link
WO (1) WO2016014166A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11973167B2 (en) 2018-12-21 2024-04-30 Lumileds Llc Photoresist patterning process supporting two step phosphor-deposition to form an LED matrix array

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5579259A (en) * 1995-05-31 1996-11-26 Sandisk Corporation Low voltage erase of a flash EEPROM system having a common erase electrode for two individually erasable sectors
US5748538A (en) * 1996-06-17 1998-05-05 Aplus Integrated Circuits, Inc. OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array
US20130223148A1 (en) * 2012-02-28 2013-08-29 Samsung Electronics Co., Ltd. Nonvolatile memory device and embedded memory system including the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5579259A (en) * 1995-05-31 1996-11-26 Sandisk Corporation Low voltage erase of a flash EEPROM system having a common erase electrode for two individually erasable sectors
US5748538A (en) * 1996-06-17 1998-05-05 Aplus Integrated Circuits, Inc. OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array
US20130223148A1 (en) * 2012-02-28 2013-08-29 Samsung Electronics Co., Ltd. Nonvolatile memory device and embedded memory system including the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11973167B2 (en) 2018-12-21 2024-04-30 Lumileds Llc Photoresist patterning process supporting two step phosphor-deposition to form an LED matrix array

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