WO2016009484A1

WO2016009484A1 - Electron emitting element array, image pickup device, and method for manufacturing electron emitting element array

Info

Publication number: WO2016009484A1
Application number: PCT/JP2014/068733
Authority: WO
Inventors: 智成中田; 一到酒村; 一智小幡
Original assignee: パイオニア株式会社
Priority date: 2014-07-14
Filing date: 2014-07-14
Publication date: 2016-01-21

Abstract

The present invention addresses the problem of providing an electron emitting element array or the like whereby film peeling of a semiconductor layer and reduction of a current path due to a step between a lower electrode layer and base portions of insulating barrier ribs can be eliminated. An electron emitting element array (1) of the present invention is provided with a semiconductor layer (3) between a lower electrode layer (2) and an upper electrode layer (5), and is characterized in that the semiconductor layer (3) has a first semiconductor layer (21) on the lower electrode layer (2) side, and a second semiconductor layer (22) on the upper electrode layer (5) side.

Description

ELECTRON EMITTING ELEMENT ARRAY, IMAGING DEVICE, AND ELECTRON EMITTING ELEMENT ARRAY MANUFACTURING METHOD

The present invention relates to a surface emission type electron-emitting device array having a cold cathode type electron source, an imaging apparatus, and a method for manufacturing the electron-emitting device array.

Conventionally, as this type of electron-emitting device array, a HEED cold cathode array incorporated in a HEED cold cathode HARP imaging device is known (see Patent Document 1).
This HEED cold cathode array is provided on a driving circuit layer of a MOS transistor and has a laminated structure including a lower electrode, a silicon layer (semiconductor layer), a silicon oxide layer (insulator layer), an upper electrode, and a carbon layer. ing. The upper electrode is common to all the pixels, and the lower electrode and the silicon layer are electrically separated through an insulating partition wall to constitute a plurality of pixels in a matrix form. Further, an opening is formed in the silicon oxide layer and the upper electrode for each pixel, and an emission site is formed on the surface of the silicon layer exposed through the opening.

JP 2010-28267 A

By the way, when a silicon layer is directly formed on the lower electrode, a contact failure occurs due to mutual diffusion of metal and silicon (semiconductor). For this reason, in a real thing, the barrier layer for protecting a lower electrode is formed between the lower electrode and the silicon layer. However, in the process, it is almost difficult to form a barrier layer on the end face of the lower electrode.
For this reason, in a conventional HEED cold cathode array, a base of an insulating partition is formed on the lower electrode, and then a contact hole is formed in the base for conducting the lower electrode and the silicon layer (semiconductor layer). In some cases, the size of the contact hole must be under the size of the lower electrode so that the end face of the lower electrode is not exposed. That is, in order to protect the end face of the lower electrode from the silicon layer, the base of the insulating partition wall is formed to overhang the peripheral edge of the lower electrode.

As a result, a step is generated between the lower electrode a and the base ba of the insulating partition b, and a seam S is generated in the deposited silicon layer c due to the step (see FIG. 7A).
In addition, in the polishing step of the pixel separation process for polishing the upper end surface of the insulating partition wall b, when the polishing chemical or cleaning chemical enters the generated seam S, the seam S expands due to the erosion (see FIG. 7B). .
As a result, not only the physical rigidity of the silicon layer c is lowered, but there is a problem that partial film peeling occurs in the silicon layer c in a later process. In addition, as the pixel becomes higher in definition, there is a problem that the current path in the silicon layer c becomes extremely narrow, the effective electron emission region is reduced, and the electron emission efficiency is lowered (see FIG. 7C).

The present invention relates to an electron-emitting device array, an imaging device, and an electron-emitting device array manufacturing method capable of preventing film peeling of a semiconductor layer and current path reduction based on a step between a lower electrode layer and a base of an insulating partition. It is an issue to provide.

The electron-emitting device array of the present invention is an electron-emitting device array including a semiconductor layer between a lower electrode layer and an upper electrode layer, the semiconductor layer including a first semiconductor layer on the lower electrode layer side and an upper electrode. And a second semiconductor layer on the layer side.

In this case, it is preferable that the lower electrode layer and the semiconductor layer are separated into a plurality of pixels via an insulating partition.

In this case, the semiconductor layer preferably further includes a protective resistance layer interposed between the first semiconductor layer and the second semiconductor layer and serving as a protective resistance against overcurrent.

In this case, the first semiconductor layer and the second semiconductor layer are preferably made of a semiconductor containing silicon as a main component, and the protective resistance layer is preferably made of an oxide of silicon.

Further, it is preferable that the surface of the first semiconductor layer on the second semiconductor layer side is subjected to planarization treatment.

On the other hand, the first semiconductor layer preferably has a higher film density than the second semiconductor layer.

Similarly, the first semiconductor layer is preferably formed by a film forming method having a higher film density than the second semiconductor layer.

Similarly, the first semiconductor layer and the second semiconductor layer are made of a semiconductor containing silicon as a main component, and the first semiconductor layer is formed under film forming conditions having a higher step coverage than the second semiconductor layer. It is preferred that

Similarly, the first semiconductor layer and the second semiconductor layer are made of a semiconductor containing silicon as a main component, and the first semiconductor layer is formed by a film formation method having a higher step coverage than the second semiconductor layer. It is preferred that

An imaging apparatus according to the present invention has an electron emission substrate section having the above-described electron emission element array and a drive circuit for driving the electron emission element array, and faces the electron emission substrate section in a vacuum space, and includes a photoelectric conversion layer. And a light receiving substrate portion.

The manufacturing method of the electron-emitting device array according to the present invention is the above-described manufacturing method of the electron-emitting device array, wherein the first semiconductor layer and the second semiconductor layer are each made of a semiconductor containing silicon as a main component, and the first insulation is used. A first semiconductor layer forming step of forming a first semiconductor layer on the lower electrode layer separated by pixels by the partition; a flattening step of flattening an upper surface of the first semiconductor layer; A second semiconductor layer forming step of forming a second semiconductor layer on the first insulating layer; and an insulating wall forming step of forming a second insulating partition on the first insulating partition and separating the first semiconductor layer and the second semiconductor layer from each other. And an electrode forming step of forming an upper electrode layer on the second semiconductor layer and the second insulating partition via the insulator layer.

In this case, it is preferable to further include an oxidation step of oxidizing the surface of the first semiconductor layer between the planarization step and the second semiconductor layer formation step.

In addition, it is preferable to perform the first semiconductor layer forming step under film forming conditions having a step coverage higher than that of the second semiconductor layer forming step instead of the planarization step.

Similarly, it is preferable to perform the first semiconductor layer forming step by a film forming method having a step coverage higher than that of the second semiconductor layer forming step instead of the planarization step.

It is a cross-sectional schematic diagram of the imaging device according to the embodiment. It is a cross-sectional schematic diagram of the electron-emitting device array which concerns on 1st Embodiment. It is a cross-sectional schematic diagram showing the manufacturing method (a), (b), (c), (d) of the electron-emitting device array which concerns on 1st Embodiment. It is a cross-sectional schematic diagram showing the manufacturing method (e), (f), (g) of the electron-emitting device array which concerns on 1st Embodiment. It is a cross-sectional schematic diagram of the electron-emitting device array which concerns on 2nd Embodiment. It is a cross-sectional schematic diagram of the electron-emitting device array which concerns on 3rd Embodiment. It is a cross-sectional schematic diagram for demonstrating the problem of the conventional electron emission element array.

Hereinafter, an electron-emitting device array according to an embodiment of the present invention, an imaging apparatus including the same, and a method for manufacturing the electron-emitting device array will be described with reference to the accompanying drawings.
This electron-emitting device array is a so-called HEED (High-efficiency Electron Emission Device) cold cathode array that constitutes an electron-emitting source, and is combined with an HARP (High-gain Avalanche Rushing amorphous Photoconductor) film that is a photoelectric conversion film. (Imaging device). Hereinafter, the description will proceed in the order of the imaging device, the electron-emitting device array, and the method for manufacturing the electron-emitting device array.

FIG. 1 is a schematic cross-sectional view of an imaging apparatus according to an embodiment. As shown in FIG. 1, the imaging apparatus 100 includes an electron emission substrate portion 101 in which the electron emission element array 1 is incorporated, and a light receiving substrate portion 103 that is opposed to the electron emission substrate portion 101 with a vacuum space 102 therebetween. And a mesh electrode 104 disposed in a vacuum space 102 between the electron emission substrate portion 101 and the light receiving substrate portion 103. The electron emission substrate 101 emits electrons as a surface electron emission source, and the mesh electrode 104 controls the trajectory of electrons (electron beams) emitted from the electron emission substrate 101 and accelerates the electrons. The light receiving substrate unit 103 receives light to be imaged and serves as a target for electrons emitted from the electron emission substrate unit 101.

The electron-emitting substrate unit 101 includes a rear substrate 111 made of silicon or the like, a driving circuit layer 112 formed on the rear substrate 111, and an electron-emitting device array 1 formed on the driving circuit layer 112. is doing. In the drive circuit layer 112, an active matrix drive circuit (switching circuit) is formed. Further, although not shown, a horizontal scanning circuit (driver) and a vertical scanning circuit (driver) for controlling driving of the active matrix driving circuit are disposed in the peripheral portion of the back substrate 111. The horizontal scanning circuit and the vertical scanning circuit drive the plurality of electron-emitting devices 1a of the electron-emitting device array 1 dot-sequentially via the active matrix driving circuit.

The light receiving substrate unit 103 includes a light transmitting side light transmitting substrate 121, a transparent electrode layer 122 formed on the back surface (lower surface) of the light transmitting substrate 121, and a photoelectric conversion layer 123 formed on the back surface of the transparent electrode layer 122. And have. Although not shown in the drawing, the light receiving substrate 103 includes a circuit for supplying signals and voltages necessary for driving, a circuit for outputting the detected video signal, and the like. The translucent substrate 121 is made of glass or the like that is transparent to visible light when the object to be imaged is visible light, sapphire or quartz glass or the like when it is ultraviolet light, and beryllium or the like when it is X-ray. Is formed. The photoelectric conversion layer 123 is formed of a semiconductor layer containing amorphous selenium (a-Se) as a main component.

Light incident from the surface of the translucent substrate 121 generates electron / hole pairs corresponding to the amount of light in the photoelectric conversion layer 123. The generated holes are accelerated by a strong electric field applied to the transparent electrode layer 122 and continuously collide with atoms constituting the photoelectric conversion layer 123 to generate new electron / hole pairs (avalanche multiplication). . The avalanche-multiplied holes are accumulated near the back surface of the photoelectric conversion layer 123 to form a hole pattern corresponding to the incident light image. And the electric current at the time of this hole pattern and the electron discharge | released from the electron emission element 1a (electron emission element array 1) couple | bonding is detected as a video signal according to an incident light image.

The mesh electrode 104 is formed of a metal plate or the like having a plurality of openings, and controls the trajectory of electrons emitted from the electron-emitting device array 1 and accelerates the electrons toward the photoelectric conversion layer 123. The mesh electrode 104 absorbs surplus electrons. For this reason, a voltage that is significantly higher than the drive voltage of the drive circuit layer 112 is applied to the mesh electrode 104.

Electrons emitted from the electron emission substrate 101 are extracted to the photoelectric conversion layer 123 side by the voltage applied to the mesh electrode 104, and also due to the electric field generated between the electron emission element array 1 and the photoelectric conversion layer 123. And converged on the back surface of the photoelectric conversion layer 123. Then, the emitted electrons are combined with the hole pattern of the photoelectric conversion layer 123. A color filter may be formed on the surface of the light receiving substrate portion 103. In this case, it is possible to perform color imaging by individually capturing R, G, and B images (videos).

[First Embodiment]
Next, the electron-emitting device array 1 of the embodiment will be described in detail with reference to FIG. As shown in FIG. 2, the electron-emitting device array 1 is formed on the lower electrode layer 2 formed on the drive circuit layer 112, the semiconductor layer 3 formed on the lower electrode layer 2, and the semiconductor layer 3. And the upper electrode layer 5 formed on the insulator layer 4. The insulator layer 4 and the upper electrode layer 5 are formed with a plurality of emission recesses 6 (circular shape) extending through them to the surface of the semiconductor layer 3. The plurality of emission recesses 6 are formed in a matrix, and an emission site 7 is formed in an exposed portion of the semiconductor layer 3 corresponding to the bottom of the emission recess 6. A carbon layer 8 is formed on the upper electrode layer 5 and over the inner peripheral surfaces of the plurality of discharge recesses 6.

On the other hand, the electron-emitting device array 1 is composed of a plurality of electron-emitting devices 1 a arranged in a matrix, and each electron-emitting device 1 a constitutes one pixel that is a drive unit of the drive circuit layer 112. In order to configure each pixel, the lower electrode layer 2 and the semiconductor layer 3 are separated by an insulating partition wall 9. The insulating partition 9 includes an insulating wall base 11 (first insulating partition) formed so as to overhang the adjacent lower electrode layer 2, and a standing wall 12 (second insulating partition) formed on the insulating wall base 11. have.

The lower electrode layer 2 is formed of a layer mainly composed of a metal such as Al, W, or Cu. The semiconductor layer 3 is made of, for example, amorphous silicon (a-Si). The insulator layer 4 and the insulating wall base 11 are made of, for example, silicon oxide formed by a CVD method. The upper electrode layer 5 is formed of a layer containing a metal such as tungsten (W) as a main component. The standing wall 12 is made of, for example, silicon oxide formed by a CVD method. The lower electrode layer 2 and the upper electrode layer 5 may be other electrode materials or nitride / oxide electrode materials, and the insulator layer 4 and the insulating wall base 11 may be oxide-based or nitride-based. Insulating material may be used.

When the lower electrode layer 2 is set to the ground potential and a predetermined voltage is applied to the upper electrode layer 5, a strong electric field is generated at each emission site 7 of the semiconductor layer 3. By this electric field, electrons inside the semiconductor layer 3 are accelerated, and electrons are emitted from the emission site 7 by the tunnel effect. The carbon layer 8 conducts the upper electrode layer 5 and the emission site 7 and excites the emission of electrons. A focusing electrode layer or the like for focusing the emitted electrons (electron beam) may be provided on the upper electrode layer 5.

By the way, in the electron-emitting device array 1 of the present embodiment, the insulating wall base 11 is formed so as to overhang at the edge of the lower electrode layer 2, and a step is generated in this portion. Although not shown in the drawing, a barrier layer that protects the lower electrode layer 2 from the semiconductor layer 3 is provided between the metal lower electrode layer 2 and the silicon semiconductor layer 3. However, the end face of the lower electrode layer 2 where the barrier layer cannot be formed is protected by overhanging the insulating wall base 11.

On the other hand, a seam S is generated in the semiconductor layer 3 formed on the step between the insulating wall base 11 and the lower electrode layer 2 due to this step. Then, when the seam S is enlarged in the subsequent process, a defect such as partial film peeling in the semiconductor layer 3 or an extremely narrow current path in the semiconductor layer 3 occurs (see FIG. 7C). Therefore, in the electron-emitting device array 1 of the present embodiment, the semiconductor layer 3 has a two-layer structure.

Specifically, the semiconductor layer 3 includes a first semiconductor layer 21 on the lower electrode layer 2 side, a second semiconductor layer 22 on the upper electrode layer 5 side, and between the first semiconductor layer 21 and the second semiconductor layer 22. And a protective resistance layer 23 interposed therebetween. Although details will be described later, after the first semiconductor layer 21 is formed, a planarization process is performed on the surface of the first semiconductor layer 21 that is uneven due to the step. Further, the surface of the planarized first semiconductor layer 21 is oxidized to form the protective resistance layer 23. Then, the second semiconductor layer 22 is formed on the protective resistance layer 23.

In this case, even if the seam S is generated in the first semiconductor layer 21, the generation of the seam S is prevented in the second semiconductor layer 22 formed on the flat surface. That is, the seam S does not occur in the second semiconductor layer 22 so as to be continuous with the seam S of the first semiconductor layer 21 by planarizing the surface of the first semiconductor layer 21. The first semiconductor layer 21 and the second semiconductor layer 22 constituting the semiconductor layer 3 are formed of amorphous silicon (a-Si) as described above, and the protective resistance layer 23 is an oxide layer of the first semiconductor layer 21. It is made of silicon oxide (SiO ₂ ). The protective resistance layer 23 protects the electron-emitting device 1a from failure and deterioration of each part due to a sudden current (overcurrent).

Next, a method for manufacturing the electron-emitting device array 1 will be described with reference to FIGS. In this manufacturing method, a first semiconductor layer forming step (FIG. 3A) for forming the first semiconductor layer 21 on the lower electrode layer 2 separated by the insulating wall base 11 is performed. A planarization step (FIG. 3B) for planarizing the upper surface, an oxidation step for oxidizing the surface of the first semiconductor layer 21, and a second semiconductor layer 22 are formed on the first semiconductor layer 21. A second semiconductor layer forming step (FIG. 3C) and an insulating wall forming step in which the standing wall 12 is formed on the insulating wall base 11 and the first semiconductor layer 21 and the second semiconductor layer 22 are separated from each other by pixels. And an embedded polishing step (FIG. 3 (d)) for polishing the upper end of the standing wall 12, and the upper electrode layer 5 is formed on the second semiconductor layer 22 and the standing wall 12 via the insulator layer 4. And an electrode forming step (FIG. 4E) to be formed. Further, this manufacturing method includes a recess forming step (FIG. 4 (f)) for forming the discharge recess 6 and a carbon layer forming step (FIG. 4 (g)) for forming the carbon layer 8.

In the first semiconductor layer forming step, the first semiconductor layer 21 is formed by sputtering (see FIG. 3A). The film thickness of the first semiconductor layer 21 is about 2 μm. Note that a CVD method may be used instead of the sputtering method. In the first semiconductor layer forming step, the generation of the seam S is allowed.
In the planarization step, the surface of the first semiconductor layer 21 is polished and planarized by a CMP (Chemical Mechanical Polishing) method (see FIG. 3B). The polishing amount of the first semiconductor layer 21 is about 1 μm. Note that planarization may be performed by an etch-back method using a dry etcher instead of the CMP method.
In the oxidation step, the surface of the polished first semiconductor layer 21 is exposed to air to oxidize it. The protective resistance layer 23 formed by the oxidation treatment has a thickness of about 2.5 nm.

In the second semiconductor layer forming step, the second semiconductor layer 22 is formed on the protective resistance layer 23 by sputtering as in the first semiconductor layer forming step (FIG. 3C). Also in this case, the film thickness of the second semiconductor layer 22 is about 2 μm. Note that a CVD method may be used instead of the sputtering method.
In the insulating wall forming step, first, trenches for the standing walls 12 are formed in the first semiconductor layer 21, the protective resistance layer 23, and the second semiconductor layer 22 by RIE (reactive ion etching). Next, a silicon oxide film for embedding the standing wall 12 in the formed trench is formed by CVD. The wall thickness is about 1 μm.

In the embedded polishing step, as in the planarization step, the surface of the formed silicon oxide is polished by CMP to expose the surface of the second semiconductor layer 22 (see FIG. 3D). This polishing amount is sufficient if the surface of the second semiconductor layer 22 can be formed (approximately 1 μm or more).
In the electrode forming step, first, the insulator layer 4 is formed on the second semiconductor layer 22 and the standing wall 12 by the CVD method (FIG. 4E). The thickness of the insulator layer 4 is about 300 nm. Next, the upper electrode layer 5 is formed on the insulator layer 4 by sputtering. The film thickness of the upper electrode layer 5 is about 50 nm.

In the recess forming step, as in the insulating wall forming step, a plurality of circular discharge recesses 6 are formed in a matrix in the insulating layer 4 and the upper electrode layer 5 by the RIE method (FIG. 4F). reference).
In the carbon layer forming step, the carbon layer 8 is formed on the surface of the upper electrode layer 5 and the inner peripheral surface of each emission recess 6 by sputtering (see FIG. 4G). The film thickness of the carbon layer 8 is about 50 nm. Thus, the electron-emitting device array 1 is manufactured through a plurality of manufacturing processes.

As described above, according to the electron-emitting device array 1 of the first embodiment, the semiconductor layer 3 has a two-layer structure of the first semiconductor layer 21 and the second semiconductor layer 22 and is planarized. The second semiconductor layer 22 is formed on the substrate. For this reason, even if the seam S occurs in the first semiconductor layer 21, the seam S does not occur in the second semiconductor layer 22. Accordingly, it is possible to effectively prevent the rigidity of the semiconductor layer 3 from being lowered, the semiconductor layer 3 from being partially peeled off, and the electron emission efficiency from being reduced due to the semiconductor layer 3 and the current path being reduced.

Further, since the protective resistance layer 23 is formed by oxidizing the surface of the first semiconductor layer 21, the electron-emitting device 1a is protected from failure and deterioration of each part due to sudden current (overcurrent). Can do.

[Second Embodiment]
Next, an electron-emitting device array 1A according to the second embodiment will be described with reference to FIG. In this embodiment, parts different from the first embodiment will be mainly described.
As shown in FIG. 5, in the electron-emitting device array 1 </ b> A of the second embodiment, the first semiconductor layer 21 of the semiconductor layer 3 is formed under film forming conditions having a higher step coverage than the second semiconductor layer 22. It is filmed.

Specifically, in the first semiconductor layer forming step of the manufacturing method, sputtering is controlled so that silicon particles reach the target with high energy in order to improve the step coverage of the first semiconductor layer 21. As a result, the first semiconductor layer 21 is a film having a dense particle density. On the other hand, in the second semiconductor layer forming step, it is necessary to relax the film stress for obtaining a film thickness necessary for stable electron emission, and sputtering is controlled so that silicon particles reach the target with low energy. As a result, the second semiconductor layer 22 is a film having a coarse particle density. Thereby, in the first semiconductor layer forming step, the first semiconductor layer 21 having good step coverage is formed, while in the second semiconductor layer forming step, the second semiconductor having a stable film thickness necessary for electron emission. Layer 22 is deposited.

Thus, in this embodiment, since the first semiconductor layer 21 with good step coverage is formed, the planarization step in the manufacturing method can be omitted. In this case as well, it is preferable to form the protective resistance layer 23 on the first semiconductor layer 21.

Thus, also in the electron-emitting device array 1A of the second embodiment, since the semiconductor layer 3 has a two-layer structure of the first semiconductor layer 21 and the second semiconductor layer 22, a seam S is formed on the first semiconductor layer 21. Even if this occurs, the seam S does not occur in the second semiconductor layer 22. Accordingly, it is possible to effectively prevent the rigidity of the semiconductor layer 3 from being lowered, the semiconductor layer 3 from being partially peeled off, and the electron emission efficiency from being reduced due to the semiconductor layer 3 and the current path being reduced.

[Third Embodiment]
Next, the electron-emitting device array 1B of the embodiment will be described in detail with reference to FIG. In this embodiment, parts different from the first embodiment will be mainly described.
As shown in FIG. 6, in the electron-emitting device array 1B of the third embodiment, the first semiconductor layer 21 of the semiconductor layer 3 is formed by a film forming method having a higher step coverage than the second semiconductor layer 22. It is filmed.

Specifically, in the first semiconductor layer forming step of the above manufacturing method, the first semiconductor layer 21 is formed (controlled) by the CVD method to form, for example, a microcrystalline film structure. On the other hand, in the second semiconductor layer forming step, the second semiconductor layer 22 is formed by a normal sputtering method. Thereby, in the first semiconductor layer forming step, the first semiconductor layer 21 having good step coverage is formed, while in the second semiconductor layer forming step, the second semiconductor having a stable film thickness necessary for electron emission. Layer 22 is deposited. Note that the first semiconductor layer forming step may be performed by an oblique sputtering method.

Thus, also in the electron-emitting device array 1B of the third embodiment, since the semiconductor layer 3 has a two-layer structure of the first semiconductor layer 21 and the second semiconductor layer 22, the seam S is formed on the first semiconductor layer 21. Even if this occurs, the seam S does not occur in the second semiconductor layer 22. Accordingly, it is possible to effectively prevent the rigidity of the semiconductor layer 3 from being lowered, the semiconductor layer 3 from being partially peeled off, and the electron emission efficiency from being reduced due to the semiconductor layer 3 and the current path being reduced.

In these embodiments, the HEED type electron-emitting

device arrays

1, 1A, and 1B have been described. However, the present invention also applies to a BSD (ballistic electron conduction electron source) or a Spindt-type electron source that is a surface electron emission source. Applicable.

1, 1A, 1B electron-emitting device array, 1a electron-emitting device, 2 lower electrode layer, 3 semiconductor layer, 4 insulator layer, 5 upper electrode layer, 9 insulating partition, 11 insulating wall base, 12 standing wall, 21st 1 semiconductor layer, 22 second semiconductor layer, 23 protective resistance layer, 100 imaging device, 101 electron emission substrate, 102 vacuum space, 103 light receiving substrate, 123 photoelectric conversion layer, S seam

Claims

An electron-emitting device array including a semiconductor layer between a lower electrode layer and an upper electrode layer,
The semiconductor layer is
An electron-emitting device array, comprising: a first semiconductor layer on the lower electrode layer side; and a second semiconductor layer on the upper electrode layer side.
2. The electron-emitting device array according to claim 1, wherein the lower electrode layer and the semiconductor layer are separated into a plurality of pixels via an insulating partition.
The semiconductor layer is
3. The electron according to claim 1, further comprising a protective resistance layer interposed between the first semiconductor layer and the second semiconductor layer and serving as a protective resistance against overcurrent. Emitting element array.
The first semiconductor layer and the second semiconductor layer are made of a semiconductor containing silicon as a main component,
4. The electron-emitting device array according to claim 3, wherein the protective resistance layer is made of silicon oxide.
5. The electron-emitting device array according to claim 1, wherein the surface of the first semiconductor layer on the second semiconductor layer side is flattened.
5. The electron-emitting device array according to claim 1, wherein the first semiconductor layer has a higher film density than the second semiconductor layer.
5. The electron-emitting device array according to claim 1, wherein the first semiconductor layer is formed by a film forming method having a higher film density than the second semiconductor layer.
The first semiconductor layer and the second semiconductor layer are made of a semiconductor containing silicon as a main component,
5. The electron emission according to claim 1, wherein the first semiconductor layer is formed under a film forming condition having a step coverage higher than that of the second semiconductor layer. Element array.
The first semiconductor layer and the second semiconductor layer are made of a semiconductor containing silicon as a main component,
5. The electron-emitting device according to claim 1, wherein the first semiconductor layer is formed by a film forming method having a higher step coverage than the second semiconductor layer. array.
An electron-emitting substrate unit having an electron-emitting device array according to any one of claims 1 to 9, and a drive circuit that drives the electron-emitting device array,
An image pickup apparatus comprising: a light receiving substrate portion having a photoelectric conversion layer facing the electron emission substrate portion in a vacuum space.
A method for manufacturing an electron-emitting device array according to claim 2,
For each of the first semiconductor layer and the second semiconductor layer, a semiconductor containing silicon as a main component is used.
A first semiconductor layer forming step of forming the first semiconductor layer on the lower electrode layer separated by pixels by a first insulating partition;
A planarization step of planarizing the upper surface of the first semiconductor layer;
A second semiconductor layer forming step of forming the second semiconductor layer on the first semiconductor layer;
Forming an insulating wall on the first insulating partition, and forming an insulating wall for pixel separation of the first semiconductor layer and the second semiconductor layer;
And an electrode forming step of forming the upper electrode layer on the second semiconductor layer and the second insulating partition via an insulator layer.
Between the planarization step and the second semiconductor layer formation step,
The method of manufacturing an electron-emitting device array according to claim 11, further comprising an oxidation step of oxidizing the surface of the first semiconductor layer.
Instead of the planarization step,
12. The method of manufacturing an electron-emitting device array according to claim 11, wherein the first semiconductor layer forming step is performed under a film forming condition having a step coverage higher than that of the second semiconductor layer forming step.
Instead of the planarization step,
12. The method of manufacturing an electron-emitting device array according to claim 11, wherein the first semiconductor layer forming step is performed by a film forming method having a step coverage higher than that of the second semiconductor layer forming step.