WO2016002846A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2016002846A1
WO2016002846A1 PCT/JP2015/069017 JP2015069017W WO2016002846A1 WO 2016002846 A1 WO2016002846 A1 WO 2016002846A1 JP 2015069017 W JP2015069017 W JP 2015069017W WO 2016002846 A1 WO2016002846 A1 WO 2016002846A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
metal plate
semiconductor device
insulating resin
resin layer
Prior art date
Application number
PCT/JP2015/069017
Other languages
French (fr)
Japanese (ja)
Inventor
俊佑 望月
和哉 北川
洋次 白土
啓太 長橋
美香 津田
憲也 平沢
素美 黒川
Original Assignee
住友ベークライト株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 住友ベークライト株式会社 filed Critical 住友ベークライト株式会社
Priority to JP2016531422A priority Critical patent/JP6635034B2/en
Publication of WO2016002846A1 publication Critical patent/WO2016002846A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Definitions

  • the present invention relates to a semiconductor device.
  • a type in which the semiconductor chip is mounted on one surface of the metal plate and an insulating resin layer is provided on the other surface of the metal plate There are things.
  • Patent Document 1 a semiconductor chip is mounted on one surface of a metal plate (the lead frame of the same document), an insulating resin layer is provided on the other surface of the metal plate, and the metal plate side in the insulating resin layer is A semiconductor device in which a metal layer (a heat sink of the same document) is provided on the opposite surface is described.
  • the insulating resin layer of the same literature is comprised including the secondary aggregation particle
  • the film thickness of the insulating resin layer when the average particle diameter of the flaky boron nitride secondary agglomerated particles contained in the insulating resin layer is too large compared to the film thickness of the insulating resin layer, the film thickness of the insulating resin layer.
  • the electric field is most concentrated in the plane of the insulating resin layer as the package of the semiconductor device becomes larger, even if such deterioration in insulation does not become a problem. The electric field at the location becomes stronger.
  • the present invention has been made in view of the above-described problems, and a semiconductor device having an insulating resin layer in which the film thickness is uniformly made uniform, the generation of voids is suppressed, and the thermal conductivity is good
  • the purpose is to provide.
  • the present invention A metal plate, A semiconductor chip provided on the first surface side of the metal plate; An insulating resin layer bonded to a second surface opposite to the first surface of the metal plate; Mold resin sealing the semiconductor chip and the metal plate; With The insulating resin layer includes secondary aggregated particles formed by isotropic aggregation of primary particles of flaky boron nitride, When the thickness of the insulating resin layer is D and the average particle diameter of the secondary aggregated particles is d, A semiconductor device having d / D of 0.05 or more and 0.8 or less is provided.
  • the insulating resin layer can have a structure with good thermal conductivity. Furthermore, since d / D is 0.8 or less, the insulating resin layer can be made to have a structure in which the film thickness is made uniform and has good insulating properties and the generation of voids is suppressed. .
  • the present invention it is possible to provide a semiconductor device having an insulating resin layer in which the film thickness is made uniform and the generation of voids is suppressed and the thermal conductivity is good.
  • 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. It is typical sectional drawing of the insulating resin layer of the semiconductor device which concerns on 1st Embodiment. It is typical sectional drawing of the semiconductor device which concerns on 2nd Embodiment. It is typical sectional drawing of the semiconductor device which concerns on 3rd Embodiment. It is typical sectional drawing of the semiconductor device which concerns on 4th Embodiment. It is typical sectional drawing of the semiconductor device which concerns on 5th Embodiment. It is typical sectional drawing of the semiconductor device which concerns on 6th Embodiment.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 according to the first embodiment.
  • FIG. 2 is a schematic cross-sectional view of the insulating resin layer 140 of the semiconductor device 100 according to the first embodiment.
  • the positional relationship (vertical relationship, etc.) of each component of the semiconductor device 100 may be described as the relationship shown in each drawing.
  • the positional relationship in this description is independent of the positional relationship when the semiconductor device 100 is used or manufactured.
  • the semiconductor device 100 is bonded to the heat sink 130, the semiconductor chip 110 provided on the first surface 131 side of the heat sink 130, and the second surface 132 opposite to the first surface 131 of the heat sink 130. And an insulating resin layer 140 and a mold resin 180 sealing the semiconductor chip 110 and the heat sink 130.
  • the insulating resin layer 140 includes secondary agglomerated particles 144 formed by isotropic aggregation of the scaly boron nitride primary particles 143. When the thickness of the insulating resin layer 140 is D and the average particle diameter of the secondary aggregated particles 144 is d, d / D is 0.05 or more and 0.8 or less. Details will be described below.
  • the semiconductor device 100 includes, for example, a conductive layer 120, an electrode terminal portion 135, a metal layer 150, a lead 160, and a wire (metal wiring) 170 in addition to the above configuration.
  • An electrode pattern (not shown) is formed on the upper surface 111 of the semiconductor chip 110, and a conductive pattern (not shown) is formed on the lower surface 112 of the semiconductor chip 110.
  • the lower surface 112 of the semiconductor chip 110 is bonded to the first surface 131 of the heat sink 130 via a conductive layer 120 such as silver paste.
  • the electrode pattern on the upper surface 111 of the semiconductor chip 110 is electrically connected to the electrode 161 of the lead 160 via the wire 170.
  • the mold resin 180 constitutes a housing by sealing the wires 170, the conductive layer 120, and portions of the leads 160 in addition to the semiconductor chip 110 and the heat sink 130 inside. Another part of each lead 160 protrudes from the side surface of the mold resin 180 to the outside of the mold resin 180.
  • the lower surface 182 of the mold resin 180 and the second surface 132 of the heat sink 130 are located on the same plane.
  • One end portion of the electrode terminal portion 135 is located in the mold resin 180 and is electrically connected to the heat sink 130, and the other end portion protrudes outside the mold resin 180. For this reason, the heat sink 130 plays a role as an electrode that receives external power supply.
  • the heat sink 130 is made of metal.
  • the electrode terminal portion 135 is formed integrally with the heat sink 130. That is, the electrode terminal portion 135 is a part of the heat sink 130. In this case, the electrode terminal portion 135 is in a state of being electrically connected to the heat sink 130 by itself. However, the electrode terminal portion 135 may be formed separately from the heat sink 130. In this case, one end portion of the electrode terminal portion 135 is electrically connected to, for example, the first surface 131 of the heat sink 130 via a conductive layer (not shown).
  • the insulating resin layer 140 is a heat conducting material having heat dissipation.
  • a heat conductive sheet heat radiating resin sheet
  • a heat conductive filler filler
  • the upper surface 141 of the insulating resin layer 140 is bonded to the second surface 132 of the heat sink 130 and the lower surface 182 of the mold resin 180. That is, the mold resin 180 is in contact with the surface (upper surface 141) of the insulating resin layer 140 on the heat sink 130 side around the heat sink 130.
  • the upper surface 151 of the metal layer 150 is joined to the lower surface 142 of the insulating resin layer 140. That is, one surface (upper surface 151) of the metal layer 150 is bonded to a surface (lower surface 142) on the opposite side of the heat sink 130 side of the insulating resin layer 140.
  • the outline of the upper surface 151 of the metal layer 150 and the outline of the surface of the insulating resin layer 140 opposite to the heat sink 130 (the lower surface 142) preferably overlap.
  • the entire surface of the metal layer 150 opposite to the one surface (upper surface 151) (lower surface 152) is exposed from the mold resin 180.
  • the insulating resin layer 140 is bonded to the second surface 132 of the heat sink 130 and the lower surface 182 of the mold resin 180, the insulating resin layer 140 is , Except for the upper surface 141, it is exposed to the outside of the mold resin 180. The entire metal layer 150 is exposed to the outside of the mold resin 180.
  • the second surface 132 and the first surface 131 of the heat sink 130 are each formed flat, for example.
  • the mounting floor area of the semiconductor device 100 is not particularly limited, but can be 10 ⁇ 10 mm or more and 100 ⁇ 100 mm or less as an example.
  • the mounting floor area of the semiconductor device 100 is the area of the lower surface 152 of the metal layer 150. That is, the planar shape of the metal layer 150 can be a rectangular shape with a side length of 10 mm or more and 100 mm or less, and the lower surface 152 thereof has a rectangular shape with a side length of 10 mm or more and 100 mm or less. Can do.
  • the number of semiconductor chips 110 mounted on one heat sink 130 is not particularly limited. There may be one or more. For example, it may be 3 or more (6 etc.). That is, as an example, three or more semiconductor chips 110 are provided on the first surface 131 side of one heat sink 130, and the mold resin 180 collectively seals these three or more semiconductor chips 110.
  • the semiconductor device 100 is, for example, a power semiconductor device. That is, the semiconductor chip 110 is, for example, a power semiconductor chip.
  • the semiconductor device 100 for example, 2 in 1 in which two semiconductor chips 110 are sealed in a mold resin 180, 6 in 1 in which six semiconductor chips 110 are sealed in a mold resin 180, or 7 in 7 in a mold resin 180.
  • a 7-in-1 configuration in which individual semiconductor chips 110 are sealed can be employed.
  • the insulating resin layer 140 includes a filler in the thermosetting resin 145.
  • the film thickness of the insulating resin layer 140 is, for example, 50 ⁇ m or more and 500 ⁇ m or less.
  • thermosetting resin 145 examples include an epoxy resin, a polyimide resin, a benzoxazine resin, an unsaturated polyester resin, a phenol resin, a melamine resin, a silicone resin, a bismaleimide resin, and an acrylic resin. Examples thereof include resins and cyanate resins. As the thermosetting resin 145, one of these may be used alone, or two or more may be used in combination. As the thermosetting resin 145, an epoxy resin is preferable. By using an epoxy resin, the glass transition temperature can be increased and the thermal conductivity of the insulating resin layer 140 can be improved. Moreover, since glass transition temperature can be raised by using cyanate resin, the heat resistance of the insulating resin layer 140 can be improved.
  • epoxy resin examples include bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol E type epoxy resin, bisphenol S type epoxy resin, bisphenol M type epoxy resin (4,4 ′-(1,3-phenylenediiso Pridiene) bisphenol type epoxy resin), bisphenol P type epoxy resin (4,4 ′-(1,4-phenylenediisopridiene) bisphenol type epoxy resin), bisphenol Z type epoxy resin (4,4′-cyclohexyl) Diene bisphenol type epoxy resin), etc .; phenol novolac type epoxy resin, cresol novolac type epoxy resin, tetraphenol group ethane type novolac type epoxy resin, novo having condensed ring aromatic hydrocarbon structure Novolak epoxy resins such as epoxy resins; biphenyl epoxy resins; arylalkylene epoxy resins such as xylylene epoxy resins and biphenyl aralkyl epoxy resins; naphthylene ether epoxy resins, naphthol epoxy resins, naphthal
  • epoxy resin one of these may be used alone, or two or more may be used in combination.
  • epoxy resins bisphenol type epoxy resin, novolac type epoxy resin, biphenyl type epoxy resin, arylalkylene type epoxy resin, naphthalene type epoxy from the viewpoint of further improving the heat resistance and insulation reliability of the obtained insulating resin layer 140
  • epoxy resins bisphenol type epoxy resin, novolac type epoxy resin, biphenyl type epoxy resin, arylalkylene type epoxy resin, naphthalene type epoxy from the viewpoint of further improving the heat resistance and insulation reliability of the obtained insulating resin layer 140
  • One or more selected from the group consisting of resins, anthracene type epoxy resins, and dicyclopentadiene type epoxy resins are preferred.
  • the cyanate resin is not particularly limited.
  • the cyanate resin is a compound having an —OCN group in the molecule, and forms a three-dimensional network structure by the reaction of the —OCN group by heating, and is cured. Resin.
  • Specific examples include 1,3-dicyanatobenzene, 1,4-dicyanatobenzene, 1,3,5-tricyanatobenzene, 1,3-dicyanatonaphthalene, 1,4-dicyanatonaphthalene, 1, 6-dicyanatonaphthalene, 1,8-dicyanatonaphthalene, 2,6-dicyanatonaphthalene, 2,7-dicyanatonaphthalene, 1,3,6-tricyanatonaphthalene, 4,4'-dicyanatobiphenyl, bis (4-cyanatophenyl) methane, bis (3,5-dimethyl-4-cyanatophenyl) methane, 2,2-bis (4-cyanatophenyl) propane, 2,2-bis (3,5-dibromo -4-Cyanatophenyl) propane, bis (4-cyanatophenyl) ether, bis (4-cyanatophenyl) thioether, bis (4-cyanatophenyl) s And ruthenes, tris (4-cyan
  • a prepolymer having a triazine ring formed by trimerizing a cyanate group can also be used.
  • This prepolymer is obtained by polymerizing the above-mentioned polyfunctional cyanate resin monomer using, for example, an acid such as mineral acid or Lewis acid, a base such as sodium alcoholate or tertiary amine, or a salt such as sodium carbonate as a catalyst. It is done.
  • an acid such as mineral acid or Lewis acid
  • a base such as sodium alcoholate or tertiary amine
  • a salt such as sodium carbonate as a catalyst. It is done.
  • cyanate resin especially novolak-type cyanate resin
  • the content of the thermosetting resin 145 contained in the insulating resin layer 140 is not particularly limited as long as it is appropriately adjusted according to the purpose, but it is 1% by mass or more and 30% by mass with respect to 100% by mass of the insulating resin layer. The following is preferable, and 5 mass% or more and 20 mass% or less are more preferable.
  • the content of the thermosetting resin 145 is equal to or more than the lower limit value, handling properties are improved, and the insulating resin layer 140 can be easily formed.
  • the content of the thermosetting resin 145 is not more than the above upper limit value, the strength and flame retardancy of the insulating resin layer 140 are further improved, and the thermal conductivity of the insulating resin layer 140 is further improved.
  • the insulating resin layer 140 preferably further includes a curing agent.
  • a curing agent one or more selected from a curing catalyst and a phenol-based curing agent can be used.
  • the curing catalyst include organic metal salts such as zinc naphthenate, cobalt naphthenate, tin octylate, cobalt octylate, bisacetylacetonate cobalt (II), and trisacetylacetonate cobalt (III); triethylamine, tributylamine, Tertiary amines such as 1,4-diazabicyclo [2.2.2] octane; 2-phenyl-4-methylimidazole, 2-ethyl-4-methylimidazole, 2,4-diethylimidazole, 2-phenyl-4 -Imidazoles such as methyl-5-hydroxyimidazole and 2-phenyl-4,5-dihydroxymethylimi
  • the curing catalyst (C-1) one kind including these derivatives can be used alone, or two or more kinds including these derivatives can be used in combination.
  • the content of the curing catalyst contained in the insulating resin layer 140 is not particularly limited, but is preferably 0.001% by mass or more and 1% by mass or less with respect to 100% by mass of the insulating resin layer.
  • phenolic curing agents include phenol novolak resins, cresol novolak resins, naphthol novolak resins, aminotriazine novolak resins, novolak resins and other novolak type phenol resins; terpene modified phenol resins, dicyclopentadiene modified phenol resins and the like.
  • Resin Aralkyl type resin such as phenol aralkyl resin having phenylene skeleton and / or biphenylene skeleton, naphthol aralkyl resin having phenylene skeleton and / or biphenylene skeleton; Bisphenol compound such as bisphenol A and bisphenol F; Resol type phenol resin and the like These may be used alone or in combination of two or more.
  • the phenolic curing agent is preferably a novolac type phenol resin or a resol type phenol resin.
  • curing agent is not specifically limited, 1 to 30 mass% is preferable with respect to 100 mass% of insulating resin layers, and 5 to 15 mass% is more preferable.
  • secondary aggregated particles 144 formed by agglomerating primary particles 143 of flaky boron nitride isotropically (that is, in a state of being oriented in a random direction).
  • the insulating resin layer 140 includes, for example, secondary aggregated particles 144 formed by isotropic aggregation of the scaly boron nitride primary particles 143.
  • the primary particles 143 mean individual particles that are not aggregated.
  • the shape of the secondary agglomerated particles 144 is, for example, spherical.
  • the insulating resin layer 140 may include primary particles 143 arranged isotropically (that is, in a random direction) in the thermosetting resin 145 in addition to the secondary aggregated particles 144 as a filler. , It does not have to be included. Further, as the filler, for example, one or more of silica, alumina, aluminum nitride, silicon carbide and the like may be included.
  • Secondary agglomerated particles 144 can be formed, for example, by agglomerating scaly boron nitride using a spray drying method or the like and then firing the agglomerated particles.
  • the firing temperature is, for example, 1200 to 2500 ° C.
  • dicyclohexane is used as the thermosetting resin. It is particularly preferable to use a pentadiene type epoxy resin or a novolac type epoxy resin.
  • the average particle size of the secondary agglomerated particles 144 is preferably 5 ⁇ m or more and 180 ⁇ m or less, for example. Thereby, the insulating resin layer 140 excellent in the balance between thermal conductivity and electrical insulation can be realized.
  • the content of the filler with respect to the entire insulating resin layer 140 is, for example, preferably 65% by mass or more and 90% by mass or less, and more preferably 70% by mass or more and 85% by mass or less.
  • the content of the filler is, for example, preferably 65% by mass or more and 90% by mass or less, and more preferably 70% by mass or more and 85% by mass or less.
  • the thickness of the insulating resin layer 140 is D and the average particle diameter of the secondary aggregated particles 144 is d, d / D is 0.05 or more and 0.8 or less.
  • the thickness D of the insulating resin layer 140 can be, for example, an average value of thicknesses at a plurality of locations (5 locations, 10 locations, etc.).
  • the average particle diameter d of the secondary aggregated particles 144 can be an average value of the particle diameters of a plurality of (5, 10, etc.) secondary aggregated particles 144 in the insulating resin layer 140.
  • the average particle diameter d is the particle diameter d1 to d10. It can be an average value.
  • d / D is preferably less than 0.5.
  • the thermal conductivity in the thickness direction of the insulating resin layer 140 is preferably 6 W / m ⁇ K or more and 50 W / m ⁇ K or less, more preferably 7 W / m ⁇ K or more and 50 W / m ⁇ K or less, and more preferably 8 W / m ⁇ K or more. 50 W / m ⁇ K or less is more preferable, and 9 W / m ⁇ K or more and 50 W / m ⁇ K or less is more preferable. By doing so, it is possible to obtain the insulating resin layer 140 exhibiting better characteristics in terms of thermal resistance.
  • the thermal conductivity in the thickness direction of the insulating resin layer 140 can be measured by, for example, a laser flash method.
  • the heat sink 130 and the semiconductor chip 110 are prepared, and the lower surface 112 of the semiconductor chip 110 is bonded to the first surface 131 of the heat sink 130 via the conductive layer 120 such as silver paste.
  • a lead frame (not shown) including the lead 160 is prepared, and the electrode pattern on the upper surface of the semiconductor chip 110 and the electrode 161 of the lead 160 are electrically connected to each other through the wire 170.
  • the semiconductor chip 110, the conductive layer 120, the heat sink 130, the wire 170, and a part of the lead 160 are collectively sealed with the mold resin 180.
  • thermosetting resin constituting the thermally conductive sheet is a B stage. Furthermore, one surface (upper surface 151) of the metal layer 150 is attached to the surface (lower surface 142) on the side opposite to the heat sink 130 side of the insulating resin layer 140. Then, by thermosetting the thermosetting resin constituting the heat conductive sheet to form a C stage, the heat conductive sheet becomes the insulating resin layer 140, the second surface 132 of the heat sink 130, and the mold resin 180. The upper surface 151 of the metal layer 150 is bonded to the lower surface 182 with the insulating resin layer 140 interposed therebetween.
  • each lead 160 is cut from the frame (not shown) of the lead frame.
  • the semiconductor device 100 having the structure as shown in FIG. 1 is obtained.
  • the semiconductor device 100 includes the heat sink 130, the semiconductor chip 110 provided on the first surface 131 side of the heat sink 130, and the opposite side of the first surface 131 of the heat sink 130.
  • the insulating resin layer 140 bonded to the second surface 132 and the mold resin 180 that seals the semiconductor chip 110 and the heat sink 130 are provided.
  • the insulating resin layer 140 includes secondary agglomerated particles 144 formed by isotropic aggregation of the scaly boron nitride primary particles 143. When the thickness of the insulating resin layer 140 is D and the average particle diameter of the secondary aggregated particles 144 is d, d / D is 0.05 or more and 0.8 or less.
  • the insulating resin layer 140 can have a structure with good thermal conductivity. Furthermore, since d / D is 0.8 or less, the insulating resin layer 140 should have a structure in which the film thickness is made uniform and has good insulation and the generation of voids is suppressed. it can. Moreover, it can suppress that the thermal resistance of the insulating resin layer 140 increases locally because the film thickness of the insulating resin layer 140 is made uniform uniformly.
  • the insulating resin layer 140 containing the secondary aggregated particles 144 can be easily and stably produced.
  • the electric field at the location where the electric field is most concentrated becomes stronger. For this reason, it is thought that the deterioration of the insulation property by the slight fluctuation
  • the semiconductor device 100 includes the insulating resin layer 140 having the above structure even when the mounting floor area is a large package having a mounting floor area of 10 ⁇ 10 mm to 100 ⁇ 100 mm. Therefore, it can be expected to obtain a sufficient withstand voltage.
  • the semiconductor device 100 for example, three or more semiconductor chips 110 are provided on the first surface 131 side of one heat sink 130, and the mold resin 180 bundles these three or more semiconductor chips together. Even if the semiconductor device 100 has a large sealing package, that is, even if the semiconductor device 100 is a large package, by providing the insulating resin layer 140 having the above structure, sufficient withstand voltage can be obtained. Can be expected.
  • the semiconductor device 100 further includes a metal layer 150 having one surface (upper surface 151) bonded to the surface (lower surface 142) opposite to the heat sink 130 side of the insulating resin layer 140, the metal layer 150 is provided. Therefore, the heat dissipation of the semiconductor device 100 is improved.
  • the upper surface 151 of the metal layer 150 is smaller than the lower surface 142 of the insulating resin layer 140, the lower surface 142 of the insulating resin layer 140 is exposed to the outside, and a crack may occur in the insulating resin layer 140 due to protrusions such as foreign matters. Occurs.
  • the upper surface 151 of the metal layer 150 is larger than the lower surface 142 of the insulating resin layer 140, the end portion of the metal layer 150 floats in the air, and the metal layer 150 is handled during the manufacturing process. May come off.
  • the entire lower surface 152 of the metal layer 150 is exposed from the mold resin 180, heat can be radiated on the entire lower surface 152 of the metal layer 150, and high heat dissipation of the semiconductor device 100 can be obtained.
  • FIG. 3 is a schematic cross-sectional view of the semiconductor device 100 according to the second embodiment.
  • the semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment in the points described below, and otherwise the semiconductor device 100 according to the first embodiment described above. It is configured in the same way.
  • the semiconductor device 100 according to the present embodiment includes a second heat sink 230 and a second insulating resin layer 240 in addition to the configuration of the semiconductor device 100 according to the first embodiment.
  • the second insulating resin layer 240 is the same as the insulating resin layer 140.
  • the second heat sink 230 is made of metal.
  • the second heat sink 230 is disposed to face the heat sink 130 with the semiconductor chip 110 interposed therebetween.
  • the semiconductor chip 110 is provided on one surface (lower surface 232) side of the second heat sink 230, and the semiconductor chip 110 is sandwiched between the heat sink 130 and the second heat sink 230.
  • the second insulating resin layer 240 is bonded to the surface (upper surface 231) of the second heat sink 230 opposite to the semiconductor chip 110 side.
  • the mold resin 180 seals the second heat sink 230 and is in contact with the second heat sink 230 side surface (lower surface 242) of the second insulating resin layer 240 around the second heat sink 230.
  • the upper surface 181 of the mold resin 180 and the upper surface 231 of the second heat sink 230 are located on the same plane.
  • the second insulating resin layer 240 further includes a second surface (lower surface 252) bonded to a surface (upper surface 241) opposite to the second heat sink 230 side.
  • a metal layer 250 is further provided. The entire surface of the surface (upper surface 251) opposite to the one surface (lower surface 252) of the second metal layer 250 is exposed from the mold resin 180. Moreover, it is preferable that the outline of the lower surface 252 of the second metal layer 250 and the outline of the upper surface 241 of the second insulating resin layer 240 overlap in plan view.
  • the semiconductor device 100 further includes, for example, a metal block 220 disposed between the semiconductor chip 110 and the second heat sink 230.
  • the lower surface 222 of the metal block 220 is bonded to a partial region of the upper surface 111 of the semiconductor chip 110 via a conductive layer 211 such as silver paste.
  • a conductive pattern (not shown) is formed in the partial region of the semiconductor chip 110.
  • the lower surface 232 of the second heat sink 230 is joined to the upper surface 221 of the metal block 220 via a conductive layer 212 such as silver paste.
  • the semiconductor device 100 further includes a second heat sink 230 disposed opposite the heat sink 130 with the semiconductor chip 110 interposed therebetween, and a second insulating resin layer 240.
  • the semiconductor chip 110 is provided on one surface (lower surface 232) side of the second heat sink 230, and the semiconductor chip 110 is sandwiched between the heat sink 130 and the second heat sink 230.
  • the second insulating resin layer 240 is bonded to the surface (upper surface 231) of the second heat sink 230 opposite to the semiconductor chip 110 side.
  • the mold resin 180 seals the second heat sink 230.
  • heat sinks heat sink 130 and second heat sink 230
  • heat sink 130 and second heat sink 230 are provided on both surfaces of the semiconductor chip 110, heat can be radiated from both surfaces of the semiconductor chip 110, and the semiconductor device 100 has excellent heat dissipation. be able to.
  • the semiconductor device 100 further includes a second metal layer 250 in which one surface (lower surface 252) is bonded to a surface (upper surface 241) opposite to the second heat sink 230 side in the second insulating resin layer 240.
  • the second metal layer 250 can radiate heat suitably, so that the heat dissipation of the semiconductor device 100 is improved.
  • the lower surface 252 of the second metal layer 250 is smaller than the upper surface 241 of the second insulating resin layer 240, the upper surface 241 of the second insulating resin layer 240 is exposed to the outside, and projections such as foreign matter cause the second insulating resin. There is a concern that cracks may occur in the layer 240.
  • the lower surface 252 of the second metal layer 150 is larger than the upper surface 241 of the second insulating resin layer 240, the end of the second metal layer 150 is in a suspended structure, and is handled during the manufacturing process. In such a case, the second metal layer 250 may be peeled off.
  • the second insulating resin layer has a structure in which the outline of the lower surface 252 of the second metal layer 250 and the outline of the upper surface 241 of the second insulating resin layer 240 overlap in plan view. Generation of cracks in 240 and peeling of the second metal layer 250 can be suppressed.
  • FIG. 4 is a schematic cross-sectional view of a semiconductor device 100 according to the third embodiment.
  • the semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment in the points described below, and otherwise the semiconductor device 100 according to the first embodiment described above. It is configured in the same way.
  • the semiconductor device 100 includes a heat dissipating grease layer 310 formed on the lower surface 152 of the metal layer 150 and a cooling fin 320 fixed to the lower surface 152 of the metal layer 150 via the heat dissipating grease layer 310.
  • a heat dissipating grease layer 310 formed on the lower surface 152 of the metal layer 150 and a cooling fin 320 fixed to the lower surface 152 of the metal layer 150 via the heat dissipating grease layer 310.
  • the cooling fins 320 are made of metal, for example.
  • the cooling fin 320 includes, for example, a flat plate-like main body portion and a large number of protrusions that protrude downward from the lower surface side of the main body portion.
  • the semiconductor device 100 includes a heat dissipating grease layer 310 formed on a surface (lower surface 152) opposite to one surface (upper surface 151) of the metal layer 150, and a metal layer via the heat dissipating grease layer 310. 150, and a cooling fin 320 fixed to the opposite surface (lower surface 152) of 150. Therefore, heat can be radiated with high heat radiating efficiency by the cooling fins 320, so that the heat radiating property of the semiconductor device 100 is improved.
  • FIG. 5 is a schematic cross-sectional view of a semiconductor device 100 according to the fourth embodiment.
  • the semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the second embodiment in the points described below, and otherwise the semiconductor device 100 according to the second embodiment described above. It is configured in the same way.
  • the semiconductor device 100 includes a heat dissipating grease layer 310 formed on the lower surface 152 of the metal layer 150, a cooling fin 320 fixed to the lower surface 152 of the metal layer 150 via the heat dissipating grease layer 310, A second heat dissipating grease layer 410 formed on the upper surface 251 of the second metal layer 250; and a second cooling fin 420 fixed to the upper surface 251 of the second metal layer 250 via the second heat dissipating grease layer 410. ing.
  • the second cooling fin 420 is the same as the cooling fin 320 described in the third embodiment, and is arranged upside down with respect to the cooling fin 320.
  • the metal layer 150, the second metal layer 250, the cooling fins 320, and the second cooling fins 420 are made of the same kind of metal, for example. More specifically, for example, the metal layer 150, the second metal layer 250, the cooling fin 320, and the second cooling fin 420 are each made of aluminum.
  • the semiconductor device 100 includes a heat dissipating grease layer 310 formed on a surface (lower surface 152) opposite to one surface (upper surface 151) of the metal layer 150, and a metal layer via the heat dissipating grease layer 310. And a cooling fin 320 fixed to the opposite surface (lower surface 152) of 150. Therefore, heat can be radiated with high heat radiating efficiency by the cooling fins 320, so that the heat radiating property of the semiconductor device 100 is improved.
  • a second heat dissipating grease layer 410 formed on a surface (upper surface 251) opposite to one surface (lower surface 252) of the second metal layer 250, and the second metal through the second heat dissipating grease layer 410.
  • a second cooling fin 420 fixed to the opposite surface (upper surface 251) of the layer 250. Therefore, since heat can be radiated with high heat radiation efficiency by the second cooling fins 420, the heat radiation performance of the semiconductor device 100 is improved.
  • the metal layer 150, the second metal layer 250, the cooling fin 320, and the second cooling fin 420 are made of the same kind of metal, the potential difference between the metal layer 150 and the cooling fin 320, and the second metal layer 250. And corrosion degradation due to the potential difference between the second cooling fin 420 and the second cooling fin 420 can be suppressed.
  • the metal layer 150, the second metal layer 250, the cooling fins 320, and the second cooling fins 420 may be made of aluminum so that these structures are inexpensive and have excellent workability and heat dissipation. it can.
  • FIG. 6 is a schematic cross-sectional view of a semiconductor device 100 according to the fifth embodiment.
  • the semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the second embodiment in the points described below, and otherwise the semiconductor device 100 according to the second embodiment described above. It is configured in the same way.
  • the peripheral edge of the metal layer 150 and the peripheral edge of the second metal layer 250 are each curved toward the mold resin 180 side. Note that a fillet or the like protruding from the resin may be formed around the metal layer 150. Similarly, a fillet or the like may be formed around the second metal layer 250.
  • the semiconductor device 100 according to the present embodiment can be obtained, for example, by pressing the semiconductor device 100 according to the second embodiment (FIG. 3) evenly from above and below.
  • the peripheral portion of the metal layer 150 and the peripheral portion of the second metal layer 250 are curved toward the mold resin 180, respectively.
  • the peeling of the layer 150 and the second metal layer 250 can be suppressed.
  • the insulating resin layer 140 and the second insulating resin layer 240 are less likely to come into direct contact with outside air or moisture, and the long-term reliability of the semiconductor device 100 is stabilized.
  • the peripheral portion of the metal layer 150 and the peripheral portion of the second metal layer 250 of the semiconductor device 100 according to the second embodiment are curved toward the mold resin 180 side, respectively.
  • the peripheral portion of the metal layer 150 of the semiconductor device 100 according to the first embodiment may be curved toward the mold resin 180 side.
  • FIG. 7 is a schematic cross-sectional view of a semiconductor device 100 according to the sixth embodiment.
  • the semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment in the points described below, and otherwise the semiconductor device 100 according to the first embodiment described above. It is configured in the same way.
  • the insulating resin layer 140 is sealed in the mold resin 180.
  • the metal layer 150 is also sealed in the mold resin 180 except for the lower surface 152 thereof.
  • the lower surface 152 of the metal layer 150 and the lower surface 182 of the mold resin 180 are located on the same plane.
  • FIG. 7 shows an example in which at least two or more semiconductor chips 110 are mounted on the first surface 131 of the heat sink 130.
  • the electrode patterns on the upper surface 111 of the semiconductor chip 110 are electrically connected to each other through a wire 610.
  • a total of six semiconductor chips 110 are mounted on the first surface 131. That is, for example, two semiconductor chips 110 are arranged in three rows in the depth direction of FIG.
  • a power module including the substrate and the semiconductor device 100 can be obtained by mounting the semiconductor device 100 according to each of the above embodiments on a substrate (not shown).
  • the metal plate is a heat sink
  • the metal plate may be a depressed lead or a heat dissipation plate.
  • each thickness is represented by an average film thickness.
  • Example 1> Preparation of secondary agglomerated particles composed of primary particles of scaly boron nitride
  • this slurry was supplied to a spray granulator and sprayed under the conditions of an atomizer rotation speed of 15000 rpm, a temperature of 200 ° C., and a slurry supply amount of 5 ml / min, thereby producing composite particles.
  • the obtained composite particles were fired under a nitrogen atmosphere at 2000 ° C. for 10 hours to obtain aggregated boron nitride (filler 1) having an average particle diameter d of 70 ⁇ m.
  • the average particle size of the agglomerated boron nitride was determined by measuring the particle size distribution of the particles on a volume basis with a laser diffraction particle size distribution analyzer (LA-500, manufactured by HORIBA), and the median diameter (D 50 ). .
  • thermosetting resin and a curing agent were added to methyl ethyl ketone as a solvent, and this was stirred to obtain a solution of a thermosetting resin composition.
  • an inorganic filler was put into this solution and premixed, and then kneaded with a three roll to obtain a resin composition in which the inorganic filler was uniformly dispersed.
  • aging was performed on the obtained resin composition under conditions of 60 ° C. and 15 hours. Subsequently, after apply
  • a semiconductor device shown in FIG. 1 was fabricated using the obtained insulating resin layer.
  • the mounting floor area of the semiconductor device was 30 ⁇ 40 mm.
  • Example 2 A semiconductor device was produced in the same manner as in Example 1 except that a B-stage insulating resin layer was produced so that the film thickness D was 80 ⁇ m.
  • Epoxy resin 1 biphenyl type epoxy resin (YL6121, manufactured by Mitsubishi Chemical Corporation)
  • Epoxy resin 2 bisphenol A type epoxy resin (JER828, manufactured by Mitsubishi Chemical Corporation)
  • Curing agent Trisphenol methane type novolak resin (MEH-7500, manufactured by Meiwa Kasei Co., Ltd.)
  • Curing catalyst 2-phenyl-4,5-dihydroxymethylimidazole (2PHZ-PW, manufactured by Shikoku Chemicals)
  • Example 1 and Comparative Examples 1 and 2 For each of the insulating resin layers obtained in Example 1 and Comparative Examples 1 and 2, whether or not voids were present in the insulating resin layer was observed with a scanning electron microscope. Specifically, it measured by the following procedures. First, the insulating resin layer was cut with a microtome to produce a cross section. Next, a cross-sectional photograph of the insulating resin layer magnified several thousand times was taken with a scanning electron microscope, and the presence or absence of voids was evaluated. ⁇ : No void ⁇ : Void present
  • the film thickness of each insulating resin layer obtained in Example 1 and Comparative Examples 1 and 2 was observed with a scanning electron microscope. Specifically, it measured by the following procedures. First, the insulating resin layer was cut with a microtome to produce a cross section. Next, a cross-sectional photograph of the insulating resin layer magnified several thousand times was taken with a scanning electron microscope to evaluate whether the film thickness of the insulating resin layer was uniform. ⁇ : The film thickness is uniformly made uniform. X: The film thickness varies.

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Abstract

This semiconductor device (100) is provided with: a metal plate (for example, a heatsink (130)); a semiconductor chip (110) provided at the first surface (131) side of the metal plate; an insulating resin layer (140) joined to a second surface (132) at the reverse side from the first surface (131) of the metal plate; and a molded resin (180) sealing the semiconductor chip (110) and the metal plate. The insulating resin layer (140) includes secondary aggregated particles (144) resulting from the isotropic aggregation of primary particles (143) of scaly boron nitride. When the thickness of the insulating resin layer (140) is D and the average particle size of the secondary aggregated particles (144) is d, d/D is 0.05-0.8 inclusive.

Description

半導体装置Semiconductor device
　本発明は、半導体装置に関する。 The present invention relates to a semiconductor device.
　半導体チップと、半導体チップを封止したモールド樹脂と、を有する半導体装置としては、半導体チップを金属板の一方の面に搭載し、且つ、金属板の他方の面に絶縁樹脂層を設けたタイプのものがある。 As a semiconductor device having a semiconductor chip and a mold resin encapsulating the semiconductor chip, a type in which the semiconductor chip is mounted on one surface of the metal plate and an insulating resin layer is provided on the other surface of the metal plate There are things.
　例えば、特許文献１には、半導体チップを金属板（同文献のリードフレーム）の一方の面に搭載し、金属板の他方の面に絶縁樹脂層を設け、絶縁樹脂層における金属板側とは反対側の面に金属層（同文献のヒートシンク）を設けた半導体装置が記載されている。そして、同文献の絶縁樹脂層は、鱗片状窒化ホウ素の一次粒子が等方的に凝集してなる二次凝集粒子を含んで構成されている。 For example, in Patent Document 1, a semiconductor chip is mounted on one surface of a metal plate (the lead frame of the same document), an insulating resin layer is provided on the other surface of the metal plate, and the metal plate side in the insulating resin layer is A semiconductor device in which a metal layer (a heat sink of the same document) is provided on the opposite surface is described. And the insulating resin layer of the same literature is comprised including the secondary aggregation particle | grains which the primary particle of scale-like boron nitride aggregates isotropically.
特開２０１０－１５７５６３号公報JP 2010-157563 A
　本発明者の検討によれば、絶縁樹脂層が含有する鱗片状窒化ホウ素の二次凝集粒子の平均粒子径が、絶縁樹脂層の膜厚に比して大きすぎる場合、絶縁樹脂層の膜厚が面内で安定せず、絶縁樹脂層の絶縁性が悪化する可能性がある。半導体装置のパッケージがある程度よりも小さい場合にはそのような絶縁性の悪化が問題として顕在化しなくても、半導体装置のパッケージが大面積となるほど、絶縁樹脂層の面内で電界が最も集中する箇所での電界が強くなる。このため、絶縁樹脂層の僅かな膜厚の変動による絶縁性の悪化も、問題として顕在化する可能性があると考えられる。
　また、二次凝集粒子の平均粒子径が絶縁樹脂層の膜厚に比して大きすぎる場合には、絶縁樹脂層内にボイドが存在する可能性も高まる。
　一方、二次凝集粒子の平均粒子径が絶縁樹脂層の膜厚に比して小さすぎる場合、絶縁樹脂層の熱抵抗が悪化（熱伝導率が悪化）する。 According to the study of the present inventor, when the average particle diameter of the flaky boron nitride secondary agglomerated particles contained in the insulating resin layer is too large compared to the film thickness of the insulating resin layer, the film thickness of the insulating resin layer However, there is a possibility that the insulating property of the insulating resin layer is deteriorated. If the package of the semiconductor device is smaller than a certain level, the electric field is most concentrated in the plane of the insulating resin layer as the package of the semiconductor device becomes larger, even if such deterioration in insulation does not become a problem. The electric field at the location becomes stronger. For this reason, it is thought that the deterioration of the insulation property by the slight fluctuation | variation of the film thickness of an insulating resin layer may also become apparent as a problem.
In addition, when the average particle diameter of the secondary agglomerated particles is too large compared to the film thickness of the insulating resin layer, the possibility that voids are present in the insulating resin layer is also increased.
On the other hand, when the average particle diameter of the secondary agglomerated particles is too small as compared with the film thickness of the insulating resin layer, the thermal resistance of the insulating resin layer is deteriorated (thermal conductivity is deteriorated).
　本発明は、以上の点に課題に鑑みなされたものであり、膜厚が良好に均一化されているとともにボイドの発生が抑制され、且つ、熱伝導率が良好な絶縁樹脂層を有する半導体装置を提供することを目的とする。 The present invention has been made in view of the above-described problems, and a semiconductor device having an insulating resin layer in which the film thickness is uniformly made uniform, the generation of voids is suppressed, and the thermal conductivity is good The purpose is to provide.
　本発明は、
　金属板と、
　前記金属板の第１面側に設けられた半導体チップと、
　前記金属板の前記第１面とは反対側の第２面に接合された絶縁樹脂層と、
　前記半導体チップおよび前記金属板を封止しているモールド樹脂と、
　を備え、
　前記絶縁樹脂層は、鱗片状窒化ホウ素の一次粒子が等方的に凝集してなる二次凝集粒子を含み、
　前記絶縁樹脂層の厚みをＤ、前記二次凝集粒子の平均粒子径をｄとすると、
　ｄ／Ｄが、０．０５以上０．８以下である半導体装置を提供する。 The present invention
A metal plate,
A semiconductor chip provided on the first surface side of the metal plate;
An insulating resin layer bonded to a second surface opposite to the first surface of the metal plate;
Mold resin sealing the semiconductor chip and the metal plate;
With
The insulating resin layer includes secondary aggregated particles formed by isotropic aggregation of primary particles of flaky boron nitride,
When the thickness of the insulating resin layer is D and the average particle diameter of the secondary aggregated particles is d,
A semiconductor device having d / D of 0.05 or more and 0.8 or less is provided.
　本発明によれば、ｄ／Ｄが０．０５以上であるので、絶縁樹脂層を、熱伝導率が良好な構造のものとすることができる。さらに、ｄ／Ｄが０．８以下であるので、絶縁樹脂層を、膜厚が良好に均一化されて良好な絶縁性を有するとともにボイドの発生が抑制された構造のものとすることができる。 According to the present invention, since d / D is 0.05 or more, the insulating resin layer can have a structure with good thermal conductivity. Furthermore, since d / D is 0.8 or less, the insulating resin layer can be made to have a structure in which the film thickness is made uniform and has good insulating properties and the generation of voids is suppressed. .
　本発明によれば、膜厚が良好に均一化されているとともにボイドの発生が抑制され、且つ、熱伝導率が良好な絶縁樹脂層を有する半導体装置を提供することができる。 According to the present invention, it is possible to provide a semiconductor device having an insulating resin layer in which the film thickness is made uniform and the generation of voids is suppressed and the thermal conductivity is good.
　上述した目的、およびその他の目的、特徴および利点は、以下に述べる好適な実施の形態、およびそれに付随する以下の図面によってさらに明らかになる。 The above-described object and other objects, features, and advantages will be further clarified by a preferred embodiment described below and the following drawings attached thereto.
第１の実施形態に係る半導体装置の模式的な断面図である。1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. 第１の実施形態に係る半導体装置の絶縁樹脂層の模式的な断面図である。It is typical sectional drawing of the insulating resin layer of the semiconductor device which concerns on 1st Embodiment. 第２の実施形態に係る半導体装置の模式的な断面図である。It is typical sectional drawing of the semiconductor device which concerns on 2nd Embodiment. 第３の実施形態に係る半導体装置の模式的な断面図である。It is typical sectional drawing of the semiconductor device which concerns on 3rd Embodiment. 第４の実施形態に係る半導体装置の模式的な断面図である。It is typical sectional drawing of the semiconductor device which concerns on 4th Embodiment. 第５の実施形態に係る半導体装置の模式的な断面図である。It is typical sectional drawing of the semiconductor device which concerns on 5th Embodiment. 第６の実施形態に係る半導体装置の模式的な断面図である。It is typical sectional drawing of the semiconductor device which concerns on 6th Embodiment.
　以下、本発明の実施形態について、図面を用いて説明する。なお、すべての図面において、同様の構成要素には同一の符号を付し、適宜に説明を省略する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
　（第１の実施形態）
　図１は第１の実施形態に係る半導体装置１００の模式的な断面図である。図２は第１の実施形態に係る半導体装置１００の絶縁樹脂層１４０の模式的な断面図である。 (First embodiment)
FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 according to the first embodiment. FIG. 2 is a schematic cross-sectional view of the insulating resin layer 140 of the semiconductor device 100 according to the first embodiment.
　以下においては、説明を簡単にするため、半導体装置１００の各構成要素の位置関係（上下関係等）が各図に示す関係であるものとして説明を行う場合がある。ただし、この説明における位置関係は、半導体装置１００の使用時や製造時の位置関係とは無関係である。 Hereinafter, in order to simplify the description, the positional relationship (vertical relationship, etc.) of each component of the semiconductor device 100 may be described as the relationship shown in each drawing. However, the positional relationship in this description is independent of the positional relationship when the semiconductor device 100 is used or manufactured.
　本実施形態では、金属板がヒートシンクである例を説明する。本実施形態に係る半導体装置１００は、ヒートシンク１３０と、ヒートシンク１３０の第１面１３１側に設けられた半導体チップ１１０と、ヒートシンク１３０の第１面１３１とは反対側の第２面１３２に接合された絶縁樹脂層１４０と、半導体チップ１１０およびヒートシンク１３０を封止しているモールド樹脂１８０と、を備えている。絶縁樹脂層１４０は、鱗片状窒化ホウ素の一次粒子１４３が等方的に凝集してなる二次凝集粒子１４４を含んでいる。絶縁樹脂層１４０の厚みをＤ、二次凝集粒子１４４の平均粒子径をｄとすると、ｄ／Ｄが、０．０５以上０．８以下である。
　以下、詳細に説明する。 In this embodiment, an example in which the metal plate is a heat sink will be described. The semiconductor device 100 according to the present embodiment is bonded to the heat sink 130, the semiconductor chip 110 provided on the first surface 131 side of the heat sink 130, and the second surface 132 opposite to the first surface 131 of the heat sink 130. And an insulating resin layer 140 and a mold resin 180 sealing the semiconductor chip 110 and the heat sink 130. The insulating resin layer 140 includes secondary agglomerated particles 144 formed by isotropic aggregation of the scaly boron nitride primary particles 143. When the thickness of the insulating resin layer 140 is D and the average particle diameter of the secondary aggregated particles 144 is d, d / D is 0.05 or more and 0.8 or less.
Details will be described below.
　半導体装置１００は、例えば、上記の構成の他に、導電層１２０、電極端子部１３５、金属層１５０、リード１６０およびワイヤ（金属配線）１７０を有する。 The semiconductor device 100 includes, for example, a conductive layer 120, an electrode terminal portion 135, a metal layer 150, a lead 160, and a wire (metal wiring) 170 in addition to the above configuration.
　半導体チップ１１０の上面１１１には図示しない電極パターンが形成され、半導体チップ１１０の下面１１２には図示しない導電パターンが形成されている。半導体チップ１１０の下面１１２は、銀ペースト等の導電層１２０を介してヒートシンク１３０の第１面１３１に接合されている。半導体チップ１１０の上面１１１の電極パターンは、ワイヤ１７０を介してリード１６０の電極１６１に対して電気的に接続されている。 An electrode pattern (not shown) is formed on the upper surface 111 of the semiconductor chip 110, and a conductive pattern (not shown) is formed on the lower surface 112 of the semiconductor chip 110. The lower surface 112 of the semiconductor chip 110 is bonded to the first surface 131 of the heat sink 130 via a conductive layer 120 such as silver paste. The electrode pattern on the upper surface 111 of the semiconductor chip 110 is electrically connected to the electrode 161 of the lead 160 via the wire 170.
　モールド樹脂１８０は、半導体チップ１１０およびヒートシンク１３０の他に、ワイヤ１７０と、導電層１２０と、リード１６０の一部分ずつと、を内部に封止して筐体を構成している。各リード１６０の他の一部分ずつは、モールド樹脂１８０の側面より、該モールド樹脂１８０の外部に突出している。本実施形態の場合、例えば、モールド樹脂１８０の下面１８２とヒートシンク１３０の第２面１３２とが互いに同一平面上に位置している。 The mold resin 180 constitutes a housing by sealing the wires 170, the conductive layer 120, and portions of the leads 160 in addition to the semiconductor chip 110 and the heat sink 130 inside. Another part of each lead 160 protrudes from the side surface of the mold resin 180 to the outside of the mold resin 180. In the present embodiment, for example, the lower surface 182 of the mold resin 180 and the second surface 132 of the heat sink 130 are located on the same plane.
　電極端子部１３５の一端部はモールド樹脂１８０内に位置しているとともにヒートシンク１３０に電気的に接続され、他端部はモールド樹脂１８０の外部に突出している。このため、ヒートシンク１３０は、外部からの電力供給を受ける電極としての役割を担う。 One end portion of the electrode terminal portion 135 is located in the mold resin 180 and is electrically connected to the heat sink 130, and the other end portion protrudes outside the mold resin 180. For this reason, the heat sink 130 plays a role as an electrode that receives external power supply.
　ヒートシンク１３０は、金属により構成されている。本実施形態の場合、電極端子部１３５は、ヒートシンク１３０と一体に形成されている。すなわち、電極端子部１３５はヒートシンク１３０の一部分である。この場合、電極端子部１３５は、自ずとヒートシンク１３０に電気的に接続された状態となっている。
　ただし、電極端子部１３５はヒートシンク１３０とは別体に形成されていても良い。この場合、電極端子部１３５の一端部は、図示しない導電層を介して、例えばヒートシンク１３０の第１面１３１に対して電気的に接続されている。 The heat sink 130 is made of metal. In the present embodiment, the electrode terminal portion 135 is formed integrally with the heat sink 130. That is, the electrode terminal portion 135 is a part of the heat sink 130. In this case, the electrode terminal portion 135 is in a state of being electrically connected to the heat sink 130 by itself.
However, the electrode terminal portion 135 may be formed separately from the heat sink 130. In this case, one end portion of the electrode terminal portion 135 is electrically connected to, for example, the first surface 131 of the heat sink 130 via a conductive layer (not shown).
　絶縁樹脂層１４０は、放熱性を有する熱伝導材である。このような熱伝導材を形成する材料として、窒化ホウ素やアルミナ等の熱伝導性フィラー（充填材）を含む熱伝導性シート（放熱樹脂シート）が挙げられる。 The insulating resin layer 140 is a heat conducting material having heat dissipation. As a material for forming such a heat conductive material, a heat conductive sheet (heat radiating resin sheet) containing a heat conductive filler (filler) such as boron nitride or alumina can be cited.
　絶縁樹脂層１４０の上面１４１は、ヒートシンク１３０の第２面１３２と、モールド樹脂１８０の下面１８２と、に対して接合されている。つまり、モールド樹脂１８０は、ヒートシンク１３０の周囲において絶縁樹脂層１４０のヒートシンク１３０側の面（上面１４１）に接している。 The upper surface 141 of the insulating resin layer 140 is bonded to the second surface 132 of the heat sink 130 and the lower surface 182 of the mold resin 180. That is, the mold resin 180 is in contact with the surface (upper surface 141) of the insulating resin layer 140 on the heat sink 130 side around the heat sink 130.
　絶縁樹脂層１４０の下面１４２には、金属層１５０の上面１５１が接合されている。すなわち、金属層１５０の一方の面（上面１５１）は、絶縁樹脂層１４０におけるヒートシンク１３０側とは反対側の面（下面１４２）に対して接合されている。 The upper surface 151 of the metal layer 150 is joined to the lower surface 142 of the insulating resin layer 140. That is, one surface (upper surface 151) of the metal layer 150 is bonded to a surface (lower surface 142) on the opposite side of the heat sink 130 side of the insulating resin layer 140.
　平面視において、金属層１５０の上面１５１の外形線と、絶縁樹脂層１４０におけるヒートシンク１３０側とは反対側の面（下面１４２）の外形線と、が重なっていることが好ましい。 In plan view, the outline of the upper surface 151 of the metal layer 150 and the outline of the surface of the insulating resin layer 140 opposite to the heat sink 130 (the lower surface 142) preferably overlap.
　また、金属層１５０は、その一方の面（上面１５１）に対する反対側の面（下面１５２）の全面がモールド樹脂１８０から露出している。なお、本実施形態の場合、上記のように、絶縁樹脂層１４０は、その上面１４１が、ヒートシンク１３０の第２面１３２およびモールド樹脂１８０の下面１８２に接合されているため、絶縁樹脂層１４０は、その上面１４１を除き、モールド樹脂１８０の外部に露出している。そして、金属層１５０は、その全体がモールド樹脂１８０の外部に露出している。 Further, the entire surface of the metal layer 150 opposite to the one surface (upper surface 151) (lower surface 152) is exposed from the mold resin 180. In the present embodiment, as described above, since the upper surface 141 of the insulating resin layer 140 is bonded to the second surface 132 of the heat sink 130 and the lower surface 182 of the mold resin 180, the insulating resin layer 140 is , Except for the upper surface 141, it is exposed to the outside of the mold resin 180. The entire metal layer 150 is exposed to the outside of the mold resin 180.
　なお、ヒートシンク１３０の第２面１３２および第１面１３１は、例えば、それぞれ平坦に形成されている。 Note that the second surface 132 and the first surface 131 of the heat sink 130 are each formed flat, for example.
　半導体装置１００の実装床面積は、特に限定されないが、一例として、１０×１０ｍｍ以上１００×１００ｍｍ以下とすることができる。ここで、半導体装置１００の実装床面積とは、金属層１５０の下面１５２の面積である。すなわち、金属層１５０の平面形状は、一辺の長さが１０ｍｍ以上、１００ｍｍ以下の矩形状とすることができ、その下面１５２は、一辺の長さが１０ｍｍ以上、１００ｍｍ以下の矩形状とすることができる。 The mounting floor area of the semiconductor device 100 is not particularly limited, but can be 10 × 10 mm or more and 100 × 100 mm or less as an example. Here, the mounting floor area of the semiconductor device 100 is the area of the lower surface 152 of the metal layer 150. That is, the planar shape of the metal layer 150 can be a rectangular shape with a side length of 10 mm or more and 100 mm or less, and the lower surface 152 thereof has a rectangular shape with a side length of 10 mm or more and 100 mm or less. Can do.
　また、一のヒートシンク１３０に搭載された半導体チップ１１０の数は、特に限定されない。１つであっても良いし、複数であっても良い。例えば、３個以上（６個等）とすることもできる。すなわち、一例として、一のヒートシンク１３０の第１面１３１側に３個以上の半導体チップ１１０が設けられ、モールド樹脂１８０はこれら３個以上の半導体チップ１１０を一括して封止している。 Further, the number of semiconductor chips 110 mounted on one heat sink 130 is not particularly limited. There may be one or more. For example, it may be 3 or more (6 etc.). That is, as an example, three or more semiconductor chips 110 are provided on the first surface 131 side of one heat sink 130, and the mold resin 180 collectively seals these three or more semiconductor chips 110.
　半導体装置１００は、例えば、パワー半導体装置である。すなわち、半導体チップ１１０は、例えばパワー半導体チップである。 The semiconductor device 100 is, for example, a power semiconductor device. That is, the semiconductor chip 110 is, for example, a power semiconductor chip.
　この半導体装置１００は、例えば、モールド樹脂１８０内に２個の半導体チップ１１０が封止された２ｉｎ１、モールド樹脂１８０内に６個の半導体チップ１１０が封止された６ｉｎ１またはモールド樹脂１８０内に７個の半導体チップ１１０が封止された７ｉｎ１の構成とすることができる。 In the semiconductor device 100, for example, 2 in 1 in which two semiconductor chips 110 are sealed in a mold resin 180, 6 in 1 in which six semiconductor chips 110 are sealed in a mold resin 180, or 7 in 7 in a mold resin 180. A 7-in-1 configuration in which individual semiconductor chips 110 are sealed can be employed.
　図２に示すように、絶縁樹脂層１４０は、熱硬化性樹脂１４５中に充填材を含んでなる。 As shown in FIG. 2, the insulating resin layer 140 includes a filler in the thermosetting resin 145.
　絶縁樹脂層１４０の膜厚は、例えば５０μｍ以上５００μｍ以下である。 The film thickness of the insulating resin layer 140 is, for example, 50 μm or more and 500 μm or less.
　絶縁樹脂層１４０を構成する材料のうち、熱硬化性樹脂１４５としては、たとえば、エポキシ樹脂、ポリイミド樹脂、ベンゾオキサジン樹脂、不飽和ポリエステル樹脂、フェノール樹脂、メラミン樹脂、シリコーン樹脂、ビスマレイミド樹脂、アクリル樹脂、シアネート樹脂等が挙げられる。熱硬化性樹脂１４５として、これらの中の１種類を単独で用いてもよいし、２種類以上を併用してもよい。熱硬化性樹脂１４５としては、エポキシ樹脂が好ましい。エポキシ樹脂を使用することで、ガラス転移温度を高くするとともに、絶縁樹脂層１４０の熱伝導性を向上させることができる。また、シアネート樹脂を使用することにより、ガラス転移温度を高めることができるので、絶縁樹脂層１４０の耐熱性を向上させることができる。 Among the materials constituting the insulating resin layer 140, examples of the thermosetting resin 145 include an epoxy resin, a polyimide resin, a benzoxazine resin, an unsaturated polyester resin, a phenol resin, a melamine resin, a silicone resin, a bismaleimide resin, and an acrylic resin. Examples thereof include resins and cyanate resins. As the thermosetting resin 145, one of these may be used alone, or two or more may be used in combination. As the thermosetting resin 145, an epoxy resin is preferable. By using an epoxy resin, the glass transition temperature can be increased and the thermal conductivity of the insulating resin layer 140 can be improved. Moreover, since glass transition temperature can be raised by using cyanate resin, the heat resistance of the insulating resin layer 140 can be improved.
　エポキシ樹脂としては、たとえば、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、ビスフェノールＥ型エポキシ樹脂、ビスフェノールＳ型エポキシ樹脂、ビスフェノールＭ型エポキシ樹脂（４，４'－（１，３－フェニレンジイソプリジエン）ビスフェノール型エポキシ樹脂）、ビスフェノールＰ型エポキシ樹脂（４，４'－（１，４－フェニレンジイソプリジエン）ビスフェノール型エポキシ樹脂）、ビスフェノールＺ型エポキシ樹脂（４，４'－シクロヘキシジエンビスフェノール型エポキシ樹脂）等のビスフェノール型エポキシ樹脂；フェノールノボラック型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂、テトラフェノール基エタン型ノボラック型エポキシ樹脂，縮合環芳香族炭化水素構造を有するノボラック型エポキシ樹脂等のノボラック型エポキシ樹脂；ビフェニル型エポキシ樹脂；キシリレン型エポキシ樹脂、ビフェニルアラルキル型エポキシ樹脂等のアリールアルキレン型エポキシ樹脂；ナフチレンエーテル型エポキシ樹脂、ナフトール型エポキシ樹脂、ナフタレンジオール型エポキシ樹脂、２官能ないし４官能エポキシ型ナフタレン樹脂、ビナフチル型エポキシ樹脂、ナフタレンアラルキル型エポキシ樹脂等のナフタレン型エポキシ樹脂；アントラセン型エポキシ樹脂；フェノキシ型エポキシ樹脂；ジシクロペンタジエン型エポキシ樹脂；ノルボルネン型エポキシ樹脂；アダマンタン型エポキシ樹脂；フルオレン型エポキシ樹脂等が挙げられる。 Examples of the epoxy resin include bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol E type epoxy resin, bisphenol S type epoxy resin, bisphenol M type epoxy resin (4,4 ′-(1,3-phenylenediiso Pridiene) bisphenol type epoxy resin), bisphenol P type epoxy resin (4,4 ′-(1,4-phenylenediisopridiene) bisphenol type epoxy resin), bisphenol Z type epoxy resin (4,4′-cyclohexyl) Diene bisphenol type epoxy resin), etc .; phenol novolac type epoxy resin, cresol novolac type epoxy resin, tetraphenol group ethane type novolac type epoxy resin, novo having condensed ring aromatic hydrocarbon structure Novolak epoxy resins such as epoxy resins; biphenyl epoxy resins; arylalkylene epoxy resins such as xylylene epoxy resins and biphenyl aralkyl epoxy resins; naphthylene ether epoxy resins, naphthol epoxy resins, naphthalenediol types Epoxy resin, bifunctional or tetrafunctional epoxy type naphthalene resin, binaphthyl type epoxy resin, naphthalene type aralkyl type epoxy resin, etc .; anthracene type epoxy resin; phenoxy type epoxy resin; dicyclopentadiene type epoxy resin; norbornene type epoxy resin Resins; adamantane type epoxy resins; fluorene type epoxy resins and the like.
　エポキシ樹脂として、これらの中の１種類を単独で用いてもよいし、２種類以上を併用してもよい。 As the epoxy resin, one of these may be used alone, or two or more may be used in combination.
　エポキシ樹脂の中でも、得られる絶縁樹脂層１４０の耐熱性および絶縁信頼性をより一層向上できる観点から、ビスフェノール型エポキシ樹脂、ノボラック型エポキシ樹脂、ビフェニル型エポキシ樹脂、アリールアルキレン型エポキシ樹脂、ナフタレン型エポキシ樹脂、アントラセン型エポキシ樹脂、ジシクロペンタジエン型エポキシ樹脂からなる群から選択される一種または二種以上が好ましい。 Among epoxy resins, bisphenol type epoxy resin, novolac type epoxy resin, biphenyl type epoxy resin, arylalkylene type epoxy resin, naphthalene type epoxy from the viewpoint of further improving the heat resistance and insulation reliability of the obtained insulating resin layer 140 One or more selected from the group consisting of resins, anthracene type epoxy resins, and dicyclopentadiene type epoxy resins are preferred.
　本実施形態において、シアネート樹脂としては、特に限定されないが、例えば、分子内に－ＯＣＮ基を有する化合物であり、加熱により－ＯＣＮ基が反応することで３次元的網目構造を形成し、硬化する樹脂である。具体的に例示すると、１，３－ジシアナトベンゼン、１，４－ジシアナトベンゼン、１，３，５－トリシアナトベンゼン、１，３－ジシアナトナフタレン、１，４－ジシアナトナフタレン、１，６－ジシアナトナフタレン、１，８－ジシアナトナフタレン、２，６－ジシアナトナフタレン、２，７－ジシアナトナフタレン、１，３，６－トリシアナトナフタレン、４，４'－ジシアナトビフェニル、ビス（４－シアナトフェニル）メタン、ビス（３，５－ジメチル－４－シアナトフェニル）メタン、２，２－ビス（４－シアナトフェニル）プロパン、２，２－ビス（３，５－ジブロモ－４－シアナトフェニル）プロパン、ビス（４－シアナトフェニル）エーテル、ビス（４－シアナトフェニル）チオエーテル、ビス（４－シアナトフェニル）スルホン、トリス（４－シアナトフェニル）ホスファイト、トリス（４－シアナトフェニル）ホスフェート、及びノボラック樹脂とハロゲン化シアンとの反応により得られるシアネート類などが挙げられ、これらの多官能シアネート樹脂のシアネート基を三量化することによって形成されるトリアジン環を有するプレポリマーも使用できる。このプレポリマーは、上記の多官能シアネート樹脂モノマーを、例えば、鉱酸、ルイス酸などの酸、ナトリウムアルコラート、第三級アミン類などの塩基、炭酸ナトリウムなどの塩類を触媒として重合させることにより得られる。
　本実施形態において、熱硬化性樹脂としてシアネート樹脂（特にノボラック型シアネート樹脂）を用いる場合、エポキシ樹脂を併用してもよい。 In this embodiment, the cyanate resin is not particularly limited. For example, the cyanate resin is a compound having an —OCN group in the molecule, and forms a three-dimensional network structure by the reaction of the —OCN group by heating, and is cured. Resin. Specific examples include 1,3-dicyanatobenzene, 1,4-dicyanatobenzene, 1,3,5-tricyanatobenzene, 1,3-dicyanatonaphthalene, 1,4-dicyanatonaphthalene, 1, 6-dicyanatonaphthalene, 1,8-dicyanatonaphthalene, 2,6-dicyanatonaphthalene, 2,7-dicyanatonaphthalene, 1,3,6-tricyanatonaphthalene, 4,4'-dicyanatobiphenyl, bis (4-cyanatophenyl) methane, bis (3,5-dimethyl-4-cyanatophenyl) methane, 2,2-bis (4-cyanatophenyl) propane, 2,2-bis (3,5-dibromo -4-Cyanatophenyl) propane, bis (4-cyanatophenyl) ether, bis (4-cyanatophenyl) thioether, bis (4-cyanatophenyl) s And ruthenes, tris (4-cyanatophenyl) phosphite, tris (4-cyanatophenyl) phosphate, and cyanates obtained by reacting novolak resins with cyanogen halides. A prepolymer having a triazine ring formed by trimerizing a cyanate group can also be used. This prepolymer is obtained by polymerizing the above-mentioned polyfunctional cyanate resin monomer using, for example, an acid such as mineral acid or Lewis acid, a base such as sodium alcoholate or tertiary amine, or a salt such as sodium carbonate as a catalyst. It is done.
In this embodiment, when using cyanate resin (especially novolak-type cyanate resin) as a thermosetting resin, you may use an epoxy resin together.
　絶縁樹脂層１４０に含まれる熱硬化性樹脂１４５の含有量は、その目的に応じて適宜調整されればよく特に限定されないが、当該絶縁樹脂層１００質量％に対し、１質量％以上３０質量％以下が好ましく、５質量％以上２０質量％以下がより好ましい。熱硬化性樹脂１４５の含有量が上記下限値以上であると、ハンドリング性が向上し、絶縁樹脂層１４０を形成するのが容易となる。熱硬化性樹脂１４５の含有量が上記上限値以下であると、絶縁樹脂層１４０の強度や難燃性がより一層向上したり、絶縁樹脂層１４０の熱伝導性がより一層向上したりする。 The content of the thermosetting resin 145 contained in the insulating resin layer 140 is not particularly limited as long as it is appropriately adjusted according to the purpose, but it is 1% by mass or more and 30% by mass with respect to 100% by mass of the insulating resin layer. The following is preferable, and 5 mass% or more and 20 mass% or less are more preferable. When the content of the thermosetting resin 145 is equal to or more than the lower limit value, handling properties are improved, and the insulating resin layer 140 can be easily formed. When the content of the thermosetting resin 145 is not more than the above upper limit value, the strength and flame retardancy of the insulating resin layer 140 are further improved, and the thermal conductivity of the insulating resin layer 140 is further improved.
　絶縁樹脂層１４０は、熱硬化性樹脂１４５としてエポキシ樹脂を用いる場合、さらに硬化剤を含むのが好ましい。
　硬化剤としては、硬化触媒およびフェノール系硬化剤から選択される１種以上を用いることができる。
　硬化触媒としては、たとえばナフテン酸亜鉛、ナフテン酸コバルト、オクチル酸スズ、オクチル酸コバルト、ビスアセチルアセトナートコバルト（ＩＩ）、トリスアセチルアセトナートコバルト（ＩＩＩ）等の有機金属塩；トリエチルアミン、トリブチルアミン、１，４－ジアザビシクロ［２．２．２］オクタン等の３級アミン類；２－フェニル－４－メチルイミダゾール、２－エチル－４－メチルイミダゾール、２，４－ジエチルイミダゾール、２－フェニル－４－メチル－５－ヒドロキシイミダゾール、２－フェニル－４，５－ジヒドロキシメチルイミダゾール等のイミダゾール類；トリフェニルホスフィン、トリ－ｐ－トリルホスフィン、テトラフェニルホスホニウム・テトラフェニルボレート、トリフェニルホスフィン・トリフェニルボラン、１，２－ビス－（ジフェニルホスフィノ）エタン等の有機リン化合物；フェノール、ビスフェノールＡ、ノニルフェノール等のフェノール化合物；酢酸、安息香酸、サリチル酸、ｐ－トルエンスルホン酸等の有機酸；等、またはこの混合物が挙げられる。硬化触媒（Ｃ－１）として、これらの中の誘導体も含めて１種類を単独で用いることもできるし、これらの誘導体も含めて２種類以上を併用したりすることもできる。
　絶縁樹脂層１４０中に含まれる硬化触媒の含有量は、特に限定されないが、絶縁樹脂層１００質量％に対し、０．００１質量％以上１質量％以下が好ましい。 When using an epoxy resin as the thermosetting resin 145, the insulating resin layer 140 preferably further includes a curing agent.
As the curing agent, one or more selected from a curing catalyst and a phenol-based curing agent can be used.
Examples of the curing catalyst include organic metal salts such as zinc naphthenate, cobalt naphthenate, tin octylate, cobalt octylate, bisacetylacetonate cobalt (II), and trisacetylacetonate cobalt (III); triethylamine, tributylamine, Tertiary amines such as 1,4-diazabicyclo [2.2.2] octane; 2-phenyl-4-methylimidazole, 2-ethyl-4-methylimidazole, 2,4-diethylimidazole, 2-phenyl-4 -Imidazoles such as methyl-5-hydroxyimidazole and 2-phenyl-4,5-dihydroxymethylimidazole; triphenylphosphine, tri-p-tolylphosphine, tetraphenylphosphonium tetraphenylborate, triphenylphosphine triphenyl Organic phosphorus compounds such as borane and 1,2-bis- (diphenylphosphino) ethane; phenol compounds such as phenol, bisphenol A and nonylphenol; organic acids such as acetic acid, benzoic acid, salicylic acid and p-toluenesulfonic acid; Or this mixture is mentioned. As the curing catalyst (C-1), one kind including these derivatives can be used alone, or two or more kinds including these derivatives can be used in combination.
The content of the curing catalyst contained in the insulating resin layer 140 is not particularly limited, but is preferably 0.001% by mass or more and 1% by mass or less with respect to 100% by mass of the insulating resin layer.
　また、フェノール系硬化剤としては、フェノールノボラック樹脂、クレゾールノボラック樹脂、ナフトールノボラック樹脂、アミノトリアジンノボラック樹脂、ノボラック樹脂等のノボラック型フェノール樹脂；テルペン変性フェノール樹脂、ジシクロペンタジエン変性フェノール樹脂等の変性フェノール樹脂；フェニレン骨格及び／又はビフェニレン骨格を有するフェノールアラルキル樹脂、フェニレン骨格及び／又はビフェニレン骨格を有するナフトールアラルキル樹脂等のアラルキル型樹脂；ビスフェノールＡ、ビスフェノールＦ等のビスフェノール化合物；レゾール型フェノール樹脂等が挙げられ、これらは１種類を単独で用いても２種類以上を併用してもよい。
　これらの中でも、ガラス転移温度の向上及び線膨張係数の低減の観点から、フェノール系硬化剤がノボラック型フェノール樹脂またはレゾール型フェノール樹脂が好ましい。
　フェノール系硬化剤の含有量は、特に限定されないが、絶縁樹脂層１００質量％に対し、１質量％以上３０質量％以下が好ましく、５質量％以上１５質量％以下がより好ましい。 Examples of phenolic curing agents include phenol novolak resins, cresol novolak resins, naphthol novolak resins, aminotriazine novolak resins, novolak resins and other novolak type phenol resins; terpene modified phenol resins, dicyclopentadiene modified phenol resins and the like. Resin; Aralkyl type resin such as phenol aralkyl resin having phenylene skeleton and / or biphenylene skeleton, naphthol aralkyl resin having phenylene skeleton and / or biphenylene skeleton; Bisphenol compound such as bisphenol A and bisphenol F; Resol type phenol resin and the like These may be used alone or in combination of two or more.
Among these, from the viewpoint of improving the glass transition temperature and reducing the linear expansion coefficient, the phenolic curing agent is preferably a novolac type phenol resin or a resol type phenol resin.
Although content of a phenol type hardening | curing agent is not specifically limited, 1 to 30 mass% is preferable with respect to 100 mass% of insulating resin layers, and 5 to 15 mass% is more preferable.
　絶縁樹脂層１４０を構成する材料のうち、充填材としては、鱗片状窒化ホウ素の一次粒子１４３が等方的に（つまりランダムな向きに配向された状態で）凝集してなる二次凝集粒子１４４が含まれる。すなわち、絶縁樹脂層１４０は、例えば、鱗片状窒化ホウ素の一次粒子１４３が等方的に凝集してなる二次凝集粒子１４４を含んでいる。一次粒子１４３とは、凝集していない個々の粒子を意味する。二次凝集粒子１４４の形状は、例えば、球状などである。
　絶縁樹脂層１４０は、充填材として、二次凝集粒子１４４の他に、等方的に（すなわちランダムな向きに）配置された一次粒子１４３を熱硬化性樹脂１４５中に含んでいても良いし、含んでいなくても良い。
　また、充填材としては、たとえばシリカ、アルミナ、窒化アルミニウム、炭化ケイ素等のうちの１種以上を含んでいても良い。 Among the materials constituting the insulating resin layer 140, as a filler, secondary aggregated particles 144 formed by agglomerating primary particles 143 of flaky boron nitride isotropically (that is, in a state of being oriented in a random direction). Is included. That is, the insulating resin layer 140 includes, for example, secondary aggregated particles 144 formed by isotropic aggregation of the scaly boron nitride primary particles 143. The primary particles 143 mean individual particles that are not aggregated. The shape of the secondary agglomerated particles 144 is, for example, spherical.
The insulating resin layer 140 may include primary particles 143 arranged isotropically (that is, in a random direction) in the thermosetting resin 145 in addition to the secondary aggregated particles 144 as a filler. , It does not have to be included.
Further, as the filler, for example, one or more of silica, alumina, aluminum nitride, silicon carbide and the like may be included.
　二次凝集粒子１４４は、たとえば鱗片状窒化ホウ素をスプレードライ法等を用いて凝集させたあと、これを焼成することにより形成することができる。焼成温度は、たとえば１２００～２５００℃である。
　このように、鱗片状窒化ホウ素を焼結させて得られる二次凝集粒子１４４を用いる場合には、熱硬化性樹脂中における充填材の分散性を向上させる観点から、熱硬化性樹脂としてジシクロペンタジエン型エポキシ樹脂またはノボラック型エポキシ樹脂を用いることがとくに好ましい。 Secondary agglomerated particles 144 can be formed, for example, by agglomerating scaly boron nitride using a spray drying method or the like and then firing the agglomerated particles. The firing temperature is, for example, 1200 to 2500 ° C.
Thus, when using the secondary agglomerated particles 144 obtained by sintering the scaly boron nitride, from the viewpoint of improving the dispersibility of the filler in the thermosetting resin, dicyclohexane is used as the thermosetting resin. It is particularly preferable to use a pentadiene type epoxy resin or a novolac type epoxy resin.
　二次凝集粒子１４４の平均粒径は、たとえば５μｍ以上１８０μｍ以下であることが好ましい。これにより、熱伝導性と電気絶縁性のバランスに優れた絶縁樹脂層１４０を実現することができる。 The average particle size of the secondary agglomerated particles 144 is preferably 5 μm or more and 180 μm or less, for example. Thereby, the insulating resin layer 140 excellent in the balance between thermal conductivity and electrical insulation can be realized.
　絶縁樹脂層１４０全体に対する充填材の含有量は、たとえば６５質量％以上９０質量％以下であることが好ましく、７０質量％以上８５質量％以下であることがより好ましい。充填材の含有量を上記下限値以上とすることにより、絶縁樹脂層１４０における熱伝導性や機械的強度の向上をより効果的に図ることができる。一方で、充填材の含有量を上記上限値以下とすることにより、樹脂組成物の成膜性や作業性を向上させ、絶縁樹脂層１４０の膜厚における均一性を良好なものとすることができる。 The content of the filler with respect to the entire insulating resin layer 140 is, for example, preferably 65% by mass or more and 90% by mass or less, and more preferably 70% by mass or more and 85% by mass or less. By setting the content of the filler to the above lower limit value or more, the thermal conductivity and mechanical strength in the insulating resin layer 140 can be improved more effectively. On the other hand, by making the content of the filler not more than the above upper limit value, the film formability and workability of the resin composition can be improved, and the uniformity in the thickness of the insulating resin layer 140 can be improved. it can.
　上記のように、絶縁樹脂層１４０の厚みをＤ、二次凝集粒子１４４の平均粒子径をｄとすると、ｄ／Ｄが、０．０５以上０．８以下である。ここで、絶縁樹脂層１４０の厚みＤは、例えば、複数箇所（５箇所、１０箇所等）の厚みの平均値とすることができる。また、二次凝集粒子１４４の平均粒子径ｄは、絶縁樹脂層１４０内の複数個（５個、１０個等）の二次凝集粒子１４４の粒子径の平均値とすることができる。例えば、１０個の二次凝集粒子１４４の粒子径がそれぞれｄ１、ｄ２、ｄ３、ｄ４、ｄ５、ｄ６、ｄ７、ｄ８、ｄ９およびｄ１０である場合、平均粒子径ｄは、粒子径ｄ１～ｄ１０の平均値とすることができる。ｄ／Ｄは、０．５未満であることが好ましい。 As described above, when the thickness of the insulating resin layer 140 is D and the average particle diameter of the secondary aggregated particles 144 is d, d / D is 0.05 or more and 0.8 or less. Here, the thickness D of the insulating resin layer 140 can be, for example, an average value of thicknesses at a plurality of locations (5 locations, 10 locations, etc.). Further, the average particle diameter d of the secondary aggregated particles 144 can be an average value of the particle diameters of a plurality of (5, 10, etc.) secondary aggregated particles 144 in the insulating resin layer 140. For example, when the particle diameters of the ten secondary aggregated particles 144 are d1, d2, d3, d4, d5, d6, d7, d8, d9 and d10, the average particle diameter d is the particle diameter d1 to d10. It can be an average value. d / D is preferably less than 0.5.
　絶縁樹脂層１４０の厚み方向における熱伝導率は、６Ｗ／ｍ・Ｋ以上５０Ｗ／ｍ・Ｋ以下が好ましく、７Ｗ／ｍ・Ｋ以上５０Ｗ／ｍ・Ｋ以下がより好ましく、８Ｗ／ｍ・Ｋ以上５０Ｗ／ｍ・Ｋ以下がさらに好ましく、９Ｗ／ｍ・Ｋ以上５０Ｗ／ｍ・Ｋ以下が一層好ましい。こうすることで、より一層熱抵抗という観点において良好な特性を示す絶縁樹脂層１４０とすることができる。なお、絶縁樹脂層１４０の厚み方向における熱伝導率は、たとえばレーザーフラッシュ法により測定することが可能である。 The thermal conductivity in the thickness direction of the insulating resin layer 140 is preferably 6 W / m · K or more and 50 W / m · K or less, more preferably 7 W / m · K or more and 50 W / m · K or less, and more preferably 8 W / m · K or more. 50 W / m · K or less is more preferable, and 9 W / m · K or more and 50 W / m · K or less is more preferable. By doing so, it is possible to obtain the insulating resin layer 140 exhibiting better characteristics in terms of thermal resistance. The thermal conductivity in the thickness direction of the insulating resin layer 140 can be measured by, for example, a laser flash method.
　次に、本実施形態に係る半導体装置１００を製造する方法の一例を説明する。 Next, an example of a method for manufacturing the semiconductor device 100 according to the present embodiment will be described.
　先ず、ヒートシンク１３０および半導体チップ１１０を準備し、銀ペースト等の導電層１２０を介して、半導体チップ１１０の下面１１２をヒートシンク１３０の第１面１３１に接合する。 First, the heat sink 130 and the semiconductor chip 110 are prepared, and the lower surface 112 of the semiconductor chip 110 is bonded to the first surface 131 of the heat sink 130 via the conductive layer 120 such as silver paste.
　次に、リード１６０を含むリードフレーム（全体図示略）を準備し、半導体チップ１１０の上面の電極パターンとリード１６０の電極１６１とをワイヤ１７０を介して相互に電気的に接続する。 Next, a lead frame (not shown) including the lead 160 is prepared, and the electrode pattern on the upper surface of the semiconductor chip 110 and the electrode 161 of the lead 160 are electrically connected to each other through the wire 170.
　次に、半導体チップ１１０と、導電層１２０と、ヒートシンク１３０と、ワイヤ１７０と、リード１６０の一部分ずつと、をモールド樹脂１８０により一括して封止する。 Next, the semiconductor chip 110, the conductive layer 120, the heat sink 130, the wire 170, and a part of the lead 160 are collectively sealed with the mold resin 180.
　次に、絶縁樹脂層１４０の材料となる熱伝導性シートを準備し、この熱伝導性シートの一方の面を、ヒートシンク１３０の第２面１３２と、モールド樹脂１８０の下面１８２と、に対して貼り付ける。この段階で、熱伝導性シートを構成する熱硬化性樹脂はＢステージである。更に、金属層１５０の一方の面（上面１５１）を、絶縁樹脂層１４０におけるヒートシンク１３０側とは反対側の面（下面１４２）に対して貼り付ける。そして、熱伝導性シートを構成する熱硬化性樹脂を熱硬化させてＣステージとすることにより、熱伝導性シートが絶縁樹脂層１４０となるとともに、ヒートシンク１３０の第２面１３２と、モールド樹脂１８０の下面１８２と、に対して、絶縁樹脂層１４０を介して金属層１５０の上面１５１が接合された状態となる。 Next, a heat conductive sheet as a material of the insulating resin layer 140 is prepared, and one surface of the heat conductive sheet is placed on the second surface 132 of the heat sink 130 and the lower surface 182 of the mold resin 180. paste. At this stage, the thermosetting resin constituting the thermally conductive sheet is a B stage. Furthermore, one surface (upper surface 151) of the metal layer 150 is attached to the surface (lower surface 142) on the side opposite to the heat sink 130 side of the insulating resin layer 140. Then, by thermosetting the thermosetting resin constituting the heat conductive sheet to form a C stage, the heat conductive sheet becomes the insulating resin layer 140, the second surface 132 of the heat sink 130, and the mold resin 180. The upper surface 151 of the metal layer 150 is bonded to the lower surface 182 with the insulating resin layer 140 interposed therebetween.
　次に、各リード１６０をリードフレームの枠体（図示略）から切断する。こうして、図１に示すような構造の半導体装置１００が得られる。 Next, each lead 160 is cut from the frame (not shown) of the lead frame. Thus, the semiconductor device 100 having the structure as shown in FIG. 1 is obtained.
　以上のような第１の実施形態によれば、半導体装置１００は、ヒートシンク１３０と、ヒートシンク１３０の第１面１３１側に設けられた半導体チップ１１０と、ヒートシンク１３０の第１面１３１とは反対側の第２面１３２に接合された絶縁樹脂層１４０と、半導体チップ１１０およびヒートシンク１３０を封止しているモールド樹脂１８０と、を備えている。絶縁樹脂層１４０は、鱗片状窒化ホウ素の一次粒子１４３が等方的に凝集してなる二次凝集粒子１４４を含んでいる。そして、絶縁樹脂層１４０の厚みをＤ、二次凝集粒子１４４の平均粒子径をｄとすると、ｄ／Ｄが、０．０５以上０．８以下である。
　ｄ／Ｄが０．０５以上であるので、絶縁樹脂層１４０を、熱伝導率が良好な構造のものとすることができる。さらに、ｄ／Ｄが０．８以下であるので、絶縁樹脂層１４０を、膜厚が良好に均一化されて良好な絶縁性を有するとともにボイドの発生が抑制された構造のものとすることができる。また、絶縁樹脂層１４０の膜厚が良好に均一化されることにより、絶縁樹脂層１４０の熱抵抗が局所的に増大してしまうことを抑制することができる。 According to the first embodiment as described above, the semiconductor device 100 includes the heat sink 130, the semiconductor chip 110 provided on the first surface 131 side of the heat sink 130, and the opposite side of the first surface 131 of the heat sink 130. The insulating resin layer 140 bonded to the second surface 132 and the mold resin 180 that seals the semiconductor chip 110 and the heat sink 130 are provided. The insulating resin layer 140 includes secondary agglomerated particles 144 formed by isotropic aggregation of the scaly boron nitride primary particles 143. When the thickness of the insulating resin layer 140 is D and the average particle diameter of the secondary aggregated particles 144 is d, d / D is 0.05 or more and 0.8 or less.
Since d / D is 0.05 or more, the insulating resin layer 140 can have a structure with good thermal conductivity. Furthermore, since d / D is 0.8 or less, the insulating resin layer 140 should have a structure in which the film thickness is made uniform and has good insulation and the generation of voids is suppressed. it can. Moreover, it can suppress that the thermal resistance of the insulating resin layer 140 increases locally because the film thickness of the insulating resin layer 140 is made uniform uniformly.
　また、ｄ／Ｄを０．５未満とすることによって、二次凝集粒子１４４を含有する絶縁樹脂層１４０を容易且つ安定的に作製することができる。 Further, by setting d / D to less than 0.5, the insulating resin layer 140 containing the secondary aggregated particles 144 can be easily and stably produced.
　上述のように、半導体装置のパッケージがある程度よりも小さい場合には絶縁樹脂層の絶縁性の悪化が問題として顕在化しなくても、半導体装置のパッケージが大面積となるほど、絶縁樹脂層の面内で電界が最も集中する箇所での電界が強くなる。このため、絶縁樹脂層の僅かな膜厚の変動による絶縁性の悪化も、問題として顕在化する可能性があると考えられる。
　これに対し、本実施形態に係る半導体装置１００は、例えば、その実装床面積が１０×１０ｍｍ以上１００×１００ｍｍ以下の大型のパッケージであったとしても、上記の構造の絶縁樹脂層１４０を備えることにより、十分な絶縁耐圧を得ることが期待できる。 As described above, in the case where the package of the semiconductor device is smaller than a certain level, the larger the area of the package of the semiconductor device is, the more the surface of the insulating resin layer becomes, even if the deterioration of the insulating property of the insulating resin layer does not become a problem. As a result, the electric field at the location where the electric field is most concentrated becomes stronger. For this reason, it is thought that the deterioration of the insulation property by the slight fluctuation | variation of the film thickness of an insulating resin layer may also become apparent as a problem.
On the other hand, the semiconductor device 100 according to the present embodiment includes the insulating resin layer 140 having the above structure even when the mounting floor area is a large package having a mounting floor area of 10 × 10 mm to 100 × 100 mm. Therefore, it can be expected to obtain a sufficient withstand voltage.
　また、本実施形態に係る半導体装置１００は、例えば、一のヒートシンク１３０の第１面１３１側に３個以上の半導体チップ１１０が設けられ、これら３個以上の半導体チップをモールド樹脂１８０が一括して封止している構造のものであったとしても、すなわち、半導体装置１００が大型のパッケージであったとしても、上記の構造の絶縁樹脂層１４０を備えることにより、十分な絶縁耐圧を得ることが期待できる。 Further, in the semiconductor device 100 according to the present embodiment, for example, three or more semiconductor chips 110 are provided on the first surface 131 side of one heat sink 130, and the mold resin 180 bundles these three or more semiconductor chips together. Even if the semiconductor device 100 has a large sealing package, that is, even if the semiconductor device 100 is a large package, by providing the insulating resin layer 140 having the above structure, sufficient withstand voltage can be obtained. Can be expected.
　また、絶縁樹脂層１４０におけるヒートシンク１３０側とは反対側の面（下面１４２）に対して一方の面（上面１５１）が接合された金属層１５０を半導体装置１００が更に備える場合、この金属層１５０によって好適に放熱することができるため、半導体装置１００の放熱性が向上する。 When the semiconductor device 100 further includes a metal layer 150 having one surface (upper surface 151) bonded to the surface (lower surface 142) opposite to the heat sink 130 side of the insulating resin layer 140, the metal layer 150 is provided. Therefore, the heat dissipation of the semiconductor device 100 is improved.
　また、金属層１５０の上面１５１が絶縁樹脂層１４０の下面１４２よりも小さいと、絶縁樹脂層１４０の下面１４２が外部に露出し、異物などの突起物により絶縁樹脂層１４０にクラックが発生する懸念が生じる。一方、金属層１５０の上面１５１が絶縁樹脂層１４０の下面１４２よりも大きいと金属層１５０の端部が宙に浮いたような構造になり、製造工程での取り扱いの際などにおいて、金属層１５０が剥がれてしまう可能性がある。
　これに対し、平面視において、金属層１５０の上面１５１の外形線と、絶縁樹脂層１４０の下面１４２の外形線と、が重なっている構造とすることにより、絶縁樹脂層１４０におけるクラックの発生および金属層１５０の剥離を抑制することができる。 Further, if the upper surface 151 of the metal layer 150 is smaller than the lower surface 142 of the insulating resin layer 140, the lower surface 142 of the insulating resin layer 140 is exposed to the outside, and a crack may occur in the insulating resin layer 140 due to protrusions such as foreign matters. Occurs. On the other hand, when the upper surface 151 of the metal layer 150 is larger than the lower surface 142 of the insulating resin layer 140, the end portion of the metal layer 150 floats in the air, and the metal layer 150 is handled during the manufacturing process. May come off.
On the other hand, in the plan view, by forming a structure in which the outline of the upper surface 151 of the metal layer 150 and the outline of the lower surface 142 of the insulating resin layer 140 overlap, generation of cracks in the insulating resin layer 140 and The peeling of the metal layer 150 can be suppressed.
　また、金属層１５０の下面１５２の全面がモールド樹脂１８０から露出しているので、金属層１５０の下面１５２の全面での放熱が可能となり、半導体装置１００の高い放熱性が得られる。 Further, since the entire lower surface 152 of the metal layer 150 is exposed from the mold resin 180, heat can be radiated on the entire lower surface 152 of the metal layer 150, and high heat dissipation of the semiconductor device 100 can be obtained.
　（第２の実施形態）
　図３は第２の実施形態に係る半導体装置１００の模式的な断面図である。本実施形態に係る半導体装置１００は、以下に説明する点で、上記の第１の実施形態に係る半導体装置１００と相違し、その他の点では、上記の第１の実施形態に係る半導体装置１００と同様に構成されている。 (Second Embodiment)
FIG. 3 is a schematic cross-sectional view of the semiconductor device 100 according to the second embodiment. The semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment in the points described below, and otherwise the semiconductor device 100 according to the first embodiment described above. It is configured in the same way.
　本実施形態に係る半導体装置１００は、上記の第１の実施形態に係る半導体装置１００の構成に加えて、第２ヒートシンク２３０と、第２絶縁樹脂層２４０と、を備えている。第２絶縁樹脂層２４０は絶縁樹脂層１４０と同様のものである。 The semiconductor device 100 according to the present embodiment includes a second heat sink 230 and a second insulating resin layer 240 in addition to the configuration of the semiconductor device 100 according to the first embodiment. The second insulating resin layer 240 is the same as the insulating resin layer 140.
　第２ヒートシンク２３０は、金属により構成されている。第２ヒートシンク２３０は、半導体チップ１１０を間に挟んでヒートシンク１３０と対向して配置されている。半導体チップ１１０が第２ヒートシンク２３０の一方の面（下面２３２）側に設けられて、ヒートシンク１３０と第２ヒートシンク２３０とにより半導体チップ１１０が挟持されている。また、第２絶縁樹脂層２４０は、第２ヒートシンク２３０における半導体チップ１１０側とは反対側の面（上面２３１）に接合されている。モールド樹脂１８０は、第２ヒートシンク２３０を封止しているとともに、第２ヒートシンク２３０の周囲において第２絶縁樹脂層２４０の第２ヒートシンク２３０側の面（下面２４２）に接している。本実施形態の場合、例えば、モールド樹脂１８０の上面１８１と第２ヒートシンク２３０の上面２３１とが互いに同一平面上に位置している。 The second heat sink 230 is made of metal. The second heat sink 230 is disposed to face the heat sink 130 with the semiconductor chip 110 interposed therebetween. The semiconductor chip 110 is provided on one surface (lower surface 232) side of the second heat sink 230, and the semiconductor chip 110 is sandwiched between the heat sink 130 and the second heat sink 230. The second insulating resin layer 240 is bonded to the surface (upper surface 231) of the second heat sink 230 opposite to the semiconductor chip 110 side. The mold resin 180 seals the second heat sink 230 and is in contact with the second heat sink 230 side surface (lower surface 242) of the second insulating resin layer 240 around the second heat sink 230. In the present embodiment, for example, the upper surface 181 of the mold resin 180 and the upper surface 231 of the second heat sink 230 are located on the same plane.
　本実施形態に係る半導体装置１００は、更に、第２絶縁樹脂層２４０における第２ヒートシンク２３０側とは反対側の面（上面２４１）に対して一方の面（下面２５２）が接合された第２金属層２５０を更に備えている。そして、第２金属層２５０の一方の面（下面２５２）に対する反対側の面（上面２５１）の全面がモールド樹脂１８０から露出している。
　また、平面視において、第２金属層２５０の下面２５２の外形線と、第２絶縁樹脂層２４０の上面２４１の外形線と、が重なっていることが好ましい。 In the semiconductor device 100 according to the present embodiment, the second insulating resin layer 240 further includes a second surface (lower surface 252) bonded to a surface (upper surface 241) opposite to the second heat sink 230 side. A metal layer 250 is further provided. The entire surface of the surface (upper surface 251) opposite to the one surface (lower surface 252) of the second metal layer 250 is exposed from the mold resin 180.
Moreover, it is preferable that the outline of the lower surface 252 of the second metal layer 250 and the outline of the upper surface 241 of the second insulating resin layer 240 overlap in plan view.
　より具体的には、半導体装置１００は、例えば、半導体チップ１１０と第２ヒートシンク２３０との間に配置された金属ブロック２２０を更に備えている。金属ブロック２２０の下面２２２は、銀ペーストなどの導電層２１１を介して、半導体チップ１１０の上面１１１の一部領域に対して接合されている。半導体チップ１１０の当該一部領域には、図示しない導電パターンが形成されている。金属ブロック２２０の上面２２１には、銀ペーストなどの導電層２１２を介して、第２ヒートシンク２３０の下面２３２が接合されている。 More specifically, the semiconductor device 100 further includes, for example, a metal block 220 disposed between the semiconductor chip 110 and the second heat sink 230. The lower surface 222 of the metal block 220 is bonded to a partial region of the upper surface 111 of the semiconductor chip 110 via a conductive layer 211 such as silver paste. A conductive pattern (not shown) is formed in the partial region of the semiconductor chip 110. The lower surface 232 of the second heat sink 230 is joined to the upper surface 221 of the metal block 220 via a conductive layer 212 such as silver paste.
　以上のような第２の実施形態によれば、上記の第１の実施形態と同様の効果が得られる他に、以下の効果が得られる。 According to the second embodiment as described above, the following effects can be obtained in addition to the same effects as the first embodiment.
　本実施形態に係る半導体装置１００は、半導体チップ１１０を間に挟んでヒートシンク１３０と対向して配置された第２ヒートシンク２３０と、第２絶縁樹脂層２４０と、を更に備えている。そして、半導体チップ１１０が第２ヒートシンク２３０の一方の面（下面２３２）側に設けられて、ヒートシンク１３０と第２ヒートシンク２３０とにより半導体チップ１１０が挟持されている。また、第２絶縁樹脂層２４０は、第２ヒートシンク２３０における半導体チップ１１０側とは反対側の面（上面２３１）に接合されている。モールド樹脂１８０は、第２ヒートシンク２３０を封止している。
　よって、半導体チップ１１０の両面にヒートシンク（ヒートシンク１３０および第２ヒートシンク２３０）が設けられているので、半導体チップ１１０の両面から放熱を行うことができ、半導体装置１００を優れた放熱性のものとすることができる。 The semiconductor device 100 according to the present embodiment further includes a second heat sink 230 disposed opposite the heat sink 130 with the semiconductor chip 110 interposed therebetween, and a second insulating resin layer 240. The semiconductor chip 110 is provided on one surface (lower surface 232) side of the second heat sink 230, and the semiconductor chip 110 is sandwiched between the heat sink 130 and the second heat sink 230. The second insulating resin layer 240 is bonded to the surface (upper surface 231) of the second heat sink 230 opposite to the semiconductor chip 110 side. The mold resin 180 seals the second heat sink 230.
Therefore, since the heat sinks (heat sink 130 and second heat sink 230) are provided on both surfaces of the semiconductor chip 110, heat can be radiated from both surfaces of the semiconductor chip 110, and the semiconductor device 100 has excellent heat dissipation. be able to.
　また、第２絶縁樹脂層２４０における第２ヒートシンク２３０側とは反対側の面（上面２４１）に対して一方の面（下面２５２）が接合された第２金属層２５０を半導体装置１００が更に備える場合、この第２金属層２５０によって好適に放熱することができるため、半導体装置１００の放熱性が向上する。 In addition, the semiconductor device 100 further includes a second metal layer 250 in which one surface (lower surface 252) is bonded to a surface (upper surface 241) opposite to the second heat sink 230 side in the second insulating resin layer 240. In this case, the second metal layer 250 can radiate heat suitably, so that the heat dissipation of the semiconductor device 100 is improved.
　また、第２金属層２５０の下面２５２が第２絶縁樹脂層２４０の上面２４１よりも小さいと、第２絶縁樹脂層２４０の上面２４１が外部に露出し、異物などの突起物により第２絶縁樹脂層２４０にクラックが発生する懸念が生じる。一方、第２金属層１５０の下面２５２が第２絶縁樹脂層２４０の上面２４１よりも大きいと第２金属層１５０の端部が宙に浮いたような構造になり、製造工程での取り扱いの際などにおいて、第２金属層２５０が剥がれてしまう可能性がある。
　これに対し、平面視において、第２金属層２５０の下面２５２の外形線と、第２絶縁樹脂層２４０の上面２４１の外形線と、が重なっている構造とすることにより、第２絶縁樹脂層２４０におけるクラックの発生および第２金属層２５０の剥離を抑制することができる。 In addition, when the lower surface 252 of the second metal layer 250 is smaller than the upper surface 241 of the second insulating resin layer 240, the upper surface 241 of the second insulating resin layer 240 is exposed to the outside, and projections such as foreign matter cause the second insulating resin. There is a concern that cracks may occur in the layer 240. On the other hand, when the lower surface 252 of the second metal layer 150 is larger than the upper surface 241 of the second insulating resin layer 240, the end of the second metal layer 150 is in a suspended structure, and is handled during the manufacturing process. In such a case, the second metal layer 250 may be peeled off.
On the other hand, the second insulating resin layer has a structure in which the outline of the lower surface 252 of the second metal layer 250 and the outline of the upper surface 241 of the second insulating resin layer 240 overlap in plan view. Generation of cracks in 240 and peeling of the second metal layer 250 can be suppressed.
　また、第２金属層２５０の上面２５１の全面がモールド樹脂１８０から露出しているので、第２金属層２５０の上面２５１の全面での放熱が可能となり、半導体装置１００の高い放熱性が得られる。 Further, since the entire upper surface 251 of the second metal layer 250 is exposed from the mold resin 180, heat can be radiated over the entire upper surface 251 of the second metal layer 250, and high heat dissipation of the semiconductor device 100 can be obtained. .
　（第３の実施形態）
　図４は第３の実施形態に係る半導体装置１００の模式的な断面図である。本実施形態に係る半導体装置１００は、以下に説明する点で、上記の第１の実施形態に係る半導体装置１００と相違し、その他の点では、上記の第１の実施形態に係る半導体装置１００と同様に構成されている。 (Third embodiment)
FIG. 4 is a schematic cross-sectional view of a semiconductor device 100 according to the third embodiment. The semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment in the points described below, and otherwise the semiconductor device 100 according to the first embodiment described above. It is configured in the same way.
　本実施形態の場合、半導体装置１００は、金属層１５０の下面１５２に形成された放熱グリース層３１０と、放熱グリース層３１０を介して金属層１５０の下面１５２に固定された冷却フィン３２０と、を更に備えている。 In the case of this embodiment, the semiconductor device 100 includes a heat dissipating grease layer 310 formed on the lower surface 152 of the metal layer 150 and a cooling fin 320 fixed to the lower surface 152 of the metal layer 150 via the heat dissipating grease layer 310. In addition.
　冷却フィン３２０は、例えば金属により構成されている。冷却フィン３２０は、例えば平板状の本体部と、この本体部の下面側より下方に向けて突出する多数の突起と、を備えて構成されている。 The cooling fins 320 are made of metal, for example. The cooling fin 320 includes, for example, a flat plate-like main body portion and a large number of protrusions that protrude downward from the lower surface side of the main body portion.
　以上のような第３の実施形態によれば、上記の第１の実施形態と同様の効果が得られる他に、以下の効果が得られる。 According to the third embodiment as described above, the following effects can be obtained in addition to the same effects as the first embodiment.
　本実施形態に係る半導体装置１００は、金属層１５０の一方の面（上面１５１）とは反対側の面（下面１５２）に形成された放熱グリース層３１０と、放熱グリース層３１０を介して金属層１５０の反対側の面（下面１５２）に固定された冷却フィン３２０と、を備えている。よって、冷却フィン３２０によって高い放熱効率で放熱を行うことができるので、半導体装置１００の放熱性が向上する。 The semiconductor device 100 according to this embodiment includes a heat dissipating grease layer 310 formed on a surface (lower surface 152) opposite to one surface (upper surface 151) of the metal layer 150, and a metal layer via the heat dissipating grease layer 310. 150, and a cooling fin 320 fixed to the opposite surface (lower surface 152) of 150. Therefore, heat can be radiated with high heat radiating efficiency by the cooling fins 320, so that the heat radiating property of the semiconductor device 100 is improved.
　（第４の実施形態）
　図５は第４の実施形態に係る半導体装置１００の模式的な断面図である。本実施形態に係る半導体装置１００は、以下に説明する点で、上記の第２の実施形態に係る半導体装置１００と相違し、その他の点では、上記の第２の実施形態に係る半導体装置１００と同様に構成されている。 (Fourth embodiment)
FIG. 5 is a schematic cross-sectional view of a semiconductor device 100 according to the fourth embodiment. The semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the second embodiment in the points described below, and otherwise the semiconductor device 100 according to the second embodiment described above. It is configured in the same way.
　本実施形態の場合、半導体装置１００は、金属層１５０の下面１５２に形成された放熱グリース層３１０と、放熱グリース層３１０を介して金属層１５０の下面１５２に固定された冷却フィン３２０と、第２金属層２５０の上面２５１に形成された第２放熱グリース層４１０と、第２放熱グリース層４１０を介して第２金属層２５０の上面２５１に固定された第２冷却フィン４２０と、を更に備えている。 In the case of this embodiment, the semiconductor device 100 includes a heat dissipating grease layer 310 formed on the lower surface 152 of the metal layer 150, a cooling fin 320 fixed to the lower surface 152 of the metal layer 150 via the heat dissipating grease layer 310, A second heat dissipating grease layer 410 formed on the upper surface 251 of the second metal layer 250; and a second cooling fin 420 fixed to the upper surface 251 of the second metal layer 250 via the second heat dissipating grease layer 410. ing.
　第２冷却フィン４２０は、上記の第３の実施形態で説明した冷却フィン３２０と同様のものであり、冷却フィン３２０とは上下反転して配置されている。 The second cooling fin 420 is the same as the cooling fin 320 described in the third embodiment, and is arranged upside down with respect to the cooling fin 320.
　ここで、金属層１５０、第２金属層２５０、冷却フィン３２０および第２冷却フィン４２０は、例えば互いに同種の金属により構成されている。より具体的には、例えば、金属層１５０、第２金属層２５０、冷却フィン３２０および第２冷却フィン４２０は、それぞれアルミニウムにより構成されている。 Here, the metal layer 150, the second metal layer 250, the cooling fins 320, and the second cooling fins 420 are made of the same kind of metal, for example. More specifically, for example, the metal layer 150, the second metal layer 250, the cooling fin 320, and the second cooling fin 420 are each made of aluminum.
　以上のような第４の実施形態によれば、上記の第２の実施形態と同様の効果が得られる他に、以下の効果が得られる。 According to the fourth embodiment as described above, in addition to the same effects as those of the second embodiment, the following effects can be obtained.
　本実施形態に係る半導体装置１００は、金属層１５０の一方の面（上面１５１）とは反対側の面（下面１５２）に形成された放熱グリース層３１０と、放熱グリース層３１０を介して金属層１５０の反対側の面（下面１５２）に固定された冷却フィン３２０と、を更に備えている。よって、冷却フィン３２０によって高い放熱効率で放熱を行うことができるので、半導体装置１００の放熱性が向上する。
　同様に、第２金属層２５０の一方の面（下面２５２）とは反対側の面（上面２５１）に形成された第２放熱グリース層４１０と、第２放熱グリース層４１０を介して第２金属層２５０の反対側の面（上面２５１）に固定された第２冷却フィン４２０と、を更に備えている。よって、第２冷却フィン４２０によって高い放熱効率で放熱を行うことができるので、半導体装置１００の放熱性が向上する。 The semiconductor device 100 according to this embodiment includes a heat dissipating grease layer 310 formed on a surface (lower surface 152) opposite to one surface (upper surface 151) of the metal layer 150, and a metal layer via the heat dissipating grease layer 310. And a cooling fin 320 fixed to the opposite surface (lower surface 152) of 150. Therefore, heat can be radiated with high heat radiating efficiency by the cooling fins 320, so that the heat radiating property of the semiconductor device 100 is improved.
Similarly, a second heat dissipating grease layer 410 formed on a surface (upper surface 251) opposite to one surface (lower surface 252) of the second metal layer 250, and the second metal through the second heat dissipating grease layer 410. And a second cooling fin 420 fixed to the opposite surface (upper surface 251) of the layer 250. Therefore, since heat can be radiated with high heat radiation efficiency by the second cooling fins 420, the heat radiation performance of the semiconductor device 100 is improved.
　また、金属層１５０、第２金属層２５０、冷却フィン３２０および第２冷却フィン４２０が同種の金属により構成されているので、金属層１５０と冷却フィン３２０との電位差、ならびに、第２金属層２５０と第２冷却フィン４２０との電位差に起因する腐食劣化を抑制することができる。 In addition, since the metal layer 150, the second metal layer 250, the cooling fin 320, and the second cooling fin 420 are made of the same kind of metal, the potential difference between the metal layer 150 and the cooling fin 320, and the second metal layer 250. And corrosion degradation due to the potential difference between the second cooling fin 420 and the second cooling fin 420 can be suppressed.
　特に、金属層１５０、第２金属層２５０、冷却フィン３２０および第２冷却フィン４２０をアルミニウムにより構成することによって、これらの構成を、安価で、加工性および放熱性に優れたものとすることができる。 In particular, the metal layer 150, the second metal layer 250, the cooling fins 320, and the second cooling fins 420 may be made of aluminum so that these structures are inexpensive and have excellent workability and heat dissipation. it can.
　（第５の実施形態）
　図６は第５の実施形態に係る半導体装置１００の模式的な断面図である。本実施形態に係る半導体装置１００は、以下に説明する点で、上記の第２の実施形態に係る半導体装置１００と相違し、その他の点では、上記の第２の実施形態に係る半導体装置１００と同様に構成されている。 (Fifth embodiment)
FIG. 6 is a schematic cross-sectional view of a semiconductor device 100 according to the fifth embodiment. The semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the second embodiment in the points described below, and otherwise the semiconductor device 100 according to the second embodiment described above. It is configured in the same way.
　本実施形態の場合、金属層１５０の周縁部および第２金属層２５０の周縁部が、それぞれモールド樹脂１８０側へ向けて湾曲している。なお、金属層１５０の周囲には、樹脂がはみ出したフィレットなどが形成されていても良い。同様に、第２金属層２５０の周囲にもフィレットなどが形成されていても良い。 In the present embodiment, the peripheral edge of the metal layer 150 and the peripheral edge of the second metal layer 250 are each curved toward the mold resin 180 side. Note that a fillet or the like protruding from the resin may be formed around the metal layer 150. Similarly, a fillet or the like may be formed around the second metal layer 250.
　本実施形態に係る半導体装置１００は、例えば、上記の第２の実施形態に係る半導体装置１００（図３）を上下方向から均等に加圧プレスすることによって得ることができる。 The semiconductor device 100 according to the present embodiment can be obtained, for example, by pressing the semiconductor device 100 according to the second embodiment (FIG. 3) evenly from above and below.
　以上のような第５の実施形態によれば、金属層１５０の周縁部および第２金属層２５０の周縁部が、それぞれモールド樹脂１８０側へ向けて湾曲しているので、物が引っ掛かることによる金属層１５０および第２金属層２５０の剥離を抑制することができる。その結果、絶縁樹脂層１４０および第２絶縁樹脂層２４０が直接外気や水分と触れにくくなり、半導体装置１００の長期信頼性が安定する。 According to the fifth embodiment as described above, the peripheral portion of the metal layer 150 and the peripheral portion of the second metal layer 250 are curved toward the mold resin 180, respectively. The peeling of the layer 150 and the second metal layer 250 can be suppressed. As a result, the insulating resin layer 140 and the second insulating resin layer 240 are less likely to come into direct contact with outside air or moisture, and the long-term reliability of the semiconductor device 100 is stabilized.
　なお、上記の第５の実施形態では、上記の第２の実施形態に係る半導体装置１００の金属層１５０の周縁部および第２金属層２５０の周縁部が、それぞれモールド樹脂１８０側へ向けて湾曲している例を説明したが、上記の第１の実施形態に係る半導体装置１００の金属層１５０の周縁部がモールド樹脂１８０側へ向けて湾曲していても良い。 In the fifth embodiment, the peripheral portion of the metal layer 150 and the peripheral portion of the second metal layer 250 of the semiconductor device 100 according to the second embodiment are curved toward the mold resin 180 side, respectively. However, the peripheral portion of the metal layer 150 of the semiconductor device 100 according to the first embodiment may be curved toward the mold resin 180 side.
　（第６の実施形態）
　図７は第６の実施形態に係る半導体装置１００の模式的な断面図である。本実施形態に係る半導体装置１００は、以下に説明する点で、上記の第１の実施形態に係る半導体装置１００と相違し、その他の点では、上記の第１の実施形態に係る半導体装置１００と同様に構成されている。 (Sixth embodiment)
FIG. 7 is a schematic cross-sectional view of a semiconductor device 100 according to the sixth embodiment. The semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment in the points described below, and otherwise the semiconductor device 100 according to the first embodiment described above. It is configured in the same way.
　本実施形態の場合、絶縁樹脂層１４０は、モールド樹脂１８０内に封止されている。また、金属層１５０も、その下面１５２を除き、モールド樹脂１８０内に封止されている。そして、金属層１５０の下面１５２と、モールド樹脂１８０の下面１８２とが互いに同一平面上に位置している。 In the case of this embodiment, the insulating resin layer 140 is sealed in the mold resin 180. The metal layer 150 is also sealed in the mold resin 180 except for the lower surface 152 thereof. The lower surface 152 of the metal layer 150 and the lower surface 182 of the mold resin 180 are located on the same plane.
　なお、図７には、ヒートシンク１３０の第１面１３１に少なくとも２個以上の半導体チップ１１０が搭載されている例が示されている。これら半導体チップ１１０の上面１１１の電極パターンどうしが、ワイヤ６１０を介して相互に電気的に接続されている。第１面１３１には、例えば、合計６個の半導体チップ１１０が搭載されている。すなわち、例えば、２個ずつの半導体チップ１１０が、図７の奥行き方向において３列に配置されている。 FIG. 7 shows an example in which at least two or more semiconductor chips 110 are mounted on the first surface 131 of the heat sink 130. The electrode patterns on the upper surface 111 of the semiconductor chip 110 are electrically connected to each other through a wire 610. For example, a total of six semiconductor chips 110 are mounted on the first surface 131. That is, for example, two semiconductor chips 110 are arranged in three rows in the depth direction of FIG.
　以上のような第６の実施形態によっても、上記の第１の実施形態と同様の効果が得られる。 According to the sixth embodiment as described above, the same effect as in the first embodiment can be obtained.
　なお、上記の各実施形態に係る半導体装置１００を基板（図示略）上に搭載することにより、基板と、半導体装置１００と、を備えるパワーモジュールが得られる。 In addition, a power module including the substrate and the semiconductor device 100 can be obtained by mounting the semiconductor device 100 according to each of the above embodiments on a substrate (not shown).
　本発明は上記の実施形態に限定されるものではなく、本発明を逸脱しない範囲において種々の態様で実施しうることはいうまでもない。 The present invention is not limited to the above-described embodiment, and it goes without saying that the present invention can be implemented in various modes without departing from the present invention.
　例えば、上記においては、金属板がヒートシンクである例を説明したが、金属板は、ディプレスされたリード、または放熱板であっても良い。
　また、上記の第２、第４および第５の実施形態では、筐体の上面１８１が第２ヒートシンク２３０の上面２３１と同一平面上に配置されている例を説明したが、筐体の上面１８１は、第２金属層２５０の上面２５１と同一平面上に配置されていても良い。 For example, in the above description, an example in which the metal plate is a heat sink has been described. However, the metal plate may be a depressed lead or a heat dissipation plate.
In the second, fourth, and fifth embodiments, the example in which the upper surface 181 of the casing is disposed on the same plane as the upper surface 231 of the second heat sink 230 has been described. May be disposed on the same plane as the upper surface 251 of the second metal layer 250.
　以下、本発明を実施例および比較例により説明するが、本発明はこれらに限定されるものではない。なお、実施例では、それぞれの厚みは平均膜厚で表わされている。 Hereinafter, although an example and a comparative example explain the present invention, the present invention is not limited to these. In the examples, each thickness is represented by an average film thickness.
＜実施例１＞
（鱗片状窒化ホウ素の一次粒子により構成された二次凝集粒子の作製）
　ホウ酸メラミン（ホウ酸：メラミン＝２：１（モル比））と鱗片状窒化ホウ素粉末（平均長径：８μｍ）を混合して得られた混合物（ホウ酸メラミン：鱗片状窒化ホウ素粉末＝１０：１（質量比））を、３．０質量％のポリアクリル酸アンモニウム水溶液へ添加し、２時間混合して噴霧用スラリーを調製した（ポリアクリル酸アンモニウム水溶液：混合物＝１００：３０（質量比））。次いで、このスラリーを噴霧造粒機に供給し、アトマイザーの回転数１５０００ｒｐｍ、温度２００℃、スラリー供給量５ｍｌ／ｍｉｎの条件で噴霧することにより、複合粒子を作製した。次いで、得られた複合粒子を、窒素雰囲気下、２０００℃、１０時間の条件で焼成することにより、平均粒径ｄが７０μｍの凝集窒化ホウ素（充填材１）を得た。
　ここで、凝集窒化ホウ素の平均粒径は、レーザー回折式粒度分布測定装置（ＨＯＲＩＢＡ社製、ＬＡ－５００）により、粒子の粒度分布を体積基準で測定し、そのメディアン径（Ｄ５０）とした。 <Example 1>
(Preparation of secondary agglomerated particles composed of primary particles of scaly boron nitride)
A mixture obtained by mixing melamine borate (boric acid: melamine = 2: 1 (molar ratio)) and scaly boron nitride powder (average major axis: 8 μm) (melamine borate: scaly boron nitride powder = 10: 1 (mass ratio)) was added to a 3.0 mass% ammonium polyacrylate aqueous solution and mixed for 2 hours to prepare a slurry for spraying (ammonium polyacrylate aqueous solution: mixture = 100: 30 (mass ratio)). ). Subsequently, this slurry was supplied to a spray granulator and sprayed under the conditions of an atomizer rotation speed of 15000 rpm, a temperature of 200 ° C., and a slurry supply amount of 5 ml / min, thereby producing composite particles. Next, the obtained composite particles were fired under a nitrogen atmosphere at 2000 ° C. for 10 hours to obtain aggregated boron nitride (filler 1) having an average particle diameter d of 70 μm.
Here, the average particle size of the agglomerated boron nitride was determined by measuring the particle size distribution of the particles on a volume basis with a laser diffraction particle size distribution analyzer (LA-500, manufactured by HORIBA), and the median diameter (D 50 ). .
（絶縁樹脂層の作製）
　まず、表１に示す配合に従い、熱硬化性樹脂と、硬化剤とを溶媒であるメチルエチルケトンに添加し、これを撹拌して熱硬化性樹脂組成物の溶液を得た。次いで、この溶液に無機充填材を入れて予備混合した後、三本ロールにて混練し、無機充填材を均一に分散させた樹脂組成物を得た。次いで、得られた樹脂組成物に対し、６０℃、１５時間の条件によりエージングを行った。次いで、樹脂組成物を、銅箔上にドクターブレード法を用いて塗布した後、これを１００℃、３０分間の熱処理により乾燥して、樹脂シートを作製した。次いで、上記樹脂シートを二本のロール間に通して圧縮することにより、樹脂シート内の気泡を除去し、膜厚Ｄが１７５μｍであるＢステージ状の絶縁樹脂層を得た。 (Preparation of insulating resin layer)
First, according to the composition shown in Table 1, a thermosetting resin and a curing agent were added to methyl ethyl ketone as a solvent, and this was stirred to obtain a solution of a thermosetting resin composition. Next, an inorganic filler was put into this solution and premixed, and then kneaded with a three roll to obtain a resin composition in which the inorganic filler was uniformly dispersed. Next, aging was performed on the obtained resin composition under conditions of 60 ° C. and 15 hours. Subsequently, after apply | coating the resin composition on copper foil using the doctor blade method, this was dried by heat processing for 30 minutes at 100 degreeC, and the resin sheet was produced. Next, the resin sheet was compressed by passing between two rolls to remove bubbles in the resin sheet, and a B-stage insulating resin layer having a film thickness D of 175 μm was obtained.
（半導体装置の作製）
　得られた絶縁樹脂層を用いて図１に示す半導体装置を作製した。なお、半導体装置の実装床面積は３０×４０ｍｍとした。 (Fabrication of semiconductor devices)
A semiconductor device shown in FIG. 1 was fabricated using the obtained insulating resin layer. The mounting floor area of the semiconductor device was 30 × 40 mm.
＜比較例１＞
　ポリアクリル酸アンモニウム水溶液の濃度を２．０質量％、アトマイザーの回転数１００００ｒｐｍに変更した以外は実施例１と同様の方法により作製された平均粒径ｄが２０μｍの凝集窒化ホウ素（充填材２）を用いた点、膜厚Ｄが５００μｍとなるようにＢステージ状の絶縁樹脂層を作製した点以外は、実施例１と同様の方法で半導体装置を作製した。 <Comparative Example 1>
Aggregated boron nitride having an average particle diameter d of 20 μm produced by the same method as in Example 1 except that the concentration of the ammonium polyacrylate aqueous solution was changed to 2.0 mass% and the atomizer rotation speed was 10,000 rpm (filler 2) A semiconductor device was fabricated in the same manner as in Example 1, except that a B-stage insulating resin layer was fabricated so that the film thickness D was 500 μm.
＜比較例２＞
　膜厚Ｄが８０μｍとなるようにＢステージ状の絶縁樹脂層を作製した点以外は、実施例１と同様の方法で半導体装置を作製した。 <Comparative example 2>
A semiconductor device was produced in the same manner as in Example 1 except that a B-stage insulating resin layer was produced so that the film thickness D was 80 μm.
　なお、表１中における各成分の詳細は下記のとおりである。 The details of each component in Table 1 are as follows.
（熱硬化性樹脂）
エポキシ樹脂１：ビフェニル型エポキシ樹脂（ＹＬ６１２１、三菱化学（株）製）
エポキシ樹脂２：ビスフェノールＡ型エポキシ樹脂（ＪＥＲ８２８、三菱化学（株）製） (Thermosetting resin)
Epoxy resin 1: biphenyl type epoxy resin (YL6121, manufactured by Mitsubishi Chemical Corporation)
Epoxy resin 2: bisphenol A type epoxy resin (JER828, manufactured by Mitsubishi Chemical Corporation)
（硬化剤および硬化触媒）
硬化剤：トリスフェノールメタン型ノボラック樹脂（ＭＥＨ－７５００、明和化成（株）製）
硬化触媒：２－フェニル－４，５－ジヒドロキシメチルイミダゾール（２ＰＨＺ－ＰＷ、四国化成社製） (Curing agent and curing catalyst)
Curing agent: Trisphenol methane type novolak resin (MEH-7500, manufactured by Meiwa Kasei Co., Ltd.)
Curing catalyst: 2-phenyl-4,5-dihydroxymethylimidazole (2PHZ-PW, manufactured by Shikoku Chemicals)
（充填材）
上記作製例により作製された凝集窒化ホウ素 (Filler)
Agglomerated boron nitride produced by the above production example
（絶縁樹脂層の硬化体の熱伝導率）
　実施例１および比較例１～２のそれぞれについて、半導体装置とは別に絶縁樹脂層の硬化体を作製し、その熱伝導率を次のように測定した。まず、得られた絶縁樹脂層を１８０℃、１時間の条件により硬化することにより、絶縁樹脂層の硬化体を得た。この絶縁樹脂層の硬化体について、密度を水中置換法により測定し、比熱をＤＳＣ（示差走査熱量測定）により測定し、さらに、レーザーフラッシュ法により熱拡散率を測定した。
　そして、実施例１および比較例１～２で得られた絶縁樹脂層の各々について、厚み方向における熱伝導率を以下の式から算出した。
　熱伝導率（Ｗ／ｍ・Ｋ）＝密度（ｋｇ／ｍ３）×比熱（ｋＪ／ｋｇ・Ｋ）×熱拡散率（ｍ２／Ｓ）×１０００ (Thermal conductivity of the cured body of the insulating resin layer)
For each of Example 1 and Comparative Examples 1 and 2, a cured body of an insulating resin layer was prepared separately from the semiconductor device, and its thermal conductivity was measured as follows. First, the obtained insulating resin layer was cured at 180 ° C. for 1 hour to obtain a cured body of the insulating resin layer. About the hardening body of this insulating resin layer, the density was measured by the underwater substitution method, the specific heat was measured by DSC (differential scanning calorimetry), and the thermal diffusivity was further measured by the laser flash method.
For each of the insulating resin layers obtained in Example 1 and Comparative Examples 1 and 2, the thermal conductivity in the thickness direction was calculated from the following equation.
Thermal conductivity (W / m · K) = density (kg / m 3 ) × specific heat (kJ / kg · K) × thermal diffusivity (m 2 / S) × 1000
（ボイドの有無）
　実施例１および比較例１～２で得られた絶縁樹脂層の各々について、当該絶縁樹脂層内にボイドが存在しているか否かについては、走査型電子顕微鏡により観察した。具体的には、以下の手順で測定した。まず、絶縁樹脂層をミクロトームで切断し、断面を作製した。次いで、走査型電子顕微鏡により、数千倍に拡大した絶縁樹脂層の断面写真を撮影して、ボイドの有無を評価した。
○：ボイドなし
×：ボイドあり (With or without voids)
For each of the insulating resin layers obtained in Example 1 and Comparative Examples 1 and 2, whether or not voids were present in the insulating resin layer was observed with a scanning electron microscope. Specifically, it measured by the following procedures. First, the insulating resin layer was cut with a microtome to produce a cross section. Next, a cross-sectional photograph of the insulating resin layer magnified several thousand times was taken with a scanning electron microscope, and the presence or absence of voids was evaluated.
○: No void ×: Void present
（膜厚の均一さ）
　実施例１および比較例１～２で得られた各絶縁樹脂層について、膜厚を走査型電子顕微鏡により観察した。具体的には、以下の手順で測定した。まず、絶縁樹脂層をミクロトームで切断し、断面を作製した。次いで、走査型電子顕微鏡により、数千倍に拡大した絶縁樹脂層の断面写真を撮影して、絶縁樹脂層の膜厚が均一であるか否かを評価した。
○：膜厚が良好に均一化されている。
×：膜厚にバラつきが生じている。 (Uniformity of film thickness)
The film thickness of each insulating resin layer obtained in Example 1 and Comparative Examples 1 and 2 was observed with a scanning electron microscope. Specifically, it measured by the following procedures. First, the insulating resin layer was cut with a microtome to produce a cross section. Next, a cross-sectional photograph of the insulating resin layer magnified several thousand times was taken with a scanning electron microscope to evaluate whether the film thickness of the insulating resin layer was uniform.
○: The film thickness is uniformly made uniform.
X: The film thickness varies.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　実施例１の半導体装置を用いて温度８５℃、湿度８５％、交流印加電圧１．５ｋＶの条件で連続湿中絶縁抵抗を評価した場合、抵抗値が１０６Ω以下となり故障するまでに、３００時間以上かかった。一方、比較例１および２の半導体装置を用いて上記連続湿中絶縁抵抗を評価した場合、実施例１の半導体装置と比べて大幅に短い時間で故障してしまった。つまり、実施例１の半導体装置は、絶縁信頼性という観点において優れたものであったのに対し、比較例１および２の半導体装置は、いずれも、絶縁信頼性という観点において要求水準を満たすものではなかった。 When the insulation resistance in continuous humidity was evaluated using the semiconductor device of Example 1 under the conditions of a temperature of 85 ° C., a humidity of 85%, and an AC applied voltage of 1.5 kV, the resistance value was 10 6 Ω or less before the failure occurred. It took more than an hour. On the other hand, when the continuous humidity insulation resistance was evaluated using the semiconductor devices of Comparative Examples 1 and 2, the device failed in a significantly shorter time than the semiconductor device of Example 1. That is, the semiconductor device of Example 1 was excellent in terms of insulation reliability, whereas the semiconductor devices of Comparative Examples 1 and 2 both satisfy the required level in terms of insulation reliability. It wasn't.
　この出願は、２０１４年７月２日に出願された日本出願特願２０１４－１３７２３４号を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2014-137234 filed on July 2, 2014, the entire disclosure of which is incorporated herein.

Claims (14)

  1. 　金属板と、
    　前記金属板の第１面側に設けられた半導体チップと、
    　前記金属板の前記第１面とは反対側の第２面に接合された絶縁樹脂層と、
    　前記半導体チップおよび前記金属板を封止しているモールド樹脂と、
    　を備え、
    　前記絶縁樹脂層は、鱗片状窒化ホウ素の一次粒子が等方的に凝集してなる二次凝集粒子を含み、
    　前記絶縁樹脂層の厚みをＤ、前記二次凝集粒子の平均粒子径をｄとすると、
    　ｄ／Ｄが、０．０５以上０．８以下である半導体装置。     A metal plate,
    A semiconductor chip provided on the first surface side of the metal plate;
    An insulating resin layer bonded to a second surface opposite to the first surface of the metal plate;
    Mold resin sealing the semiconductor chip and the metal plate;
    With
    The insulating resin layer includes secondary aggregated particles formed by isotropic aggregation of primary particles of flaky boron nitride,
    When the thickness of the insulating resin layer is D and the average particle diameter of the secondary aggregated particles is d,
    A semiconductor device having d / D of 0.05 or more and 0.8 or less.
  2. 　ｄ／Ｄが、０．５未満である請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein d / D is less than 0.5.
  3. 　当該半導体装置の実装床面積が１０×１０ｍｍ以上１００×１００ｍｍ以下である請求項１又は２に記載の半導体装置。 The semiconductor device according to claim 1, wherein a mounting floor area of the semiconductor device is 10 × 10 mm or more and 100 × 100 mm or less.
  4. 　一の前記金属板の前記第１面側に３個以上の半導体チップが設けられ、
    　前記モールド樹脂は前記３個以上の半導体チップを一括して封止している請求項１乃至３の何れか一項に記載の半導体装置。     Three or more semiconductor chips are provided on the first surface side of the one metal plate,
    The semiconductor device according to claim 1, wherein the mold resin seals the three or more semiconductor chips together.
  5. 　前記絶縁樹脂層における前記金属板側とは反対側の面に対して、一方の面が接合された金属層を更に備える請求項１乃至４の何れか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 4, further comprising a metal layer in which one surface is bonded to a surface opposite to the metal plate side in the insulating resin layer.
  6. 　平面視において、前記金属層の前記一方の面の外形線と、前記絶縁樹脂層における前記金属板側とは反対側の面の外形線と、が重なっている請求項５に記載の半導体装置。 The semiconductor device according to claim 5, wherein an outline of the one surface of the metal layer overlaps an outline of the surface of the insulating resin layer opposite to the metal plate in a plan view.
  7. 　前記金属層の前記一方の面に対する反対側の面の全面が前記モールド樹脂から露出している請求項５または６に記載の半導体装置。 The semiconductor device according to claim 5 or 6, wherein an entire surface of the metal layer opposite to the one surface is exposed from the mold resin.
  8. 　前記金属層の前記一方の面とは反対側の面に形成された放熱グリース層と、
    　前記放熱グリース層を介して前記金属層の前記反対側の面に固定された冷却フィンと、
    　を更に備える請求項５または６に記載の半導体装置。     A heat dissipating grease layer formed on a surface opposite to the one surface of the metal layer;
    A cooling fin fixed to the opposite surface of the metal layer via the heat dissipating grease layer;
    The semiconductor device according to claim 5, further comprising:
  9. 　前記半導体チップを間に挟んで前記金属板と対向して配置された第２金属板と、
    　第２絶縁樹脂層と、
    　を更に備え、
    　前記半導体チップが前記第２金属板の一方の面側に設けられて、前記金属板と前記第２金属板とにより前記半導体チップが挟持されており、
    　前記第２絶縁樹脂層は、前記第２金属板における前記半導体チップ側とは反対側の面に接合されており、
    　前記モールド樹脂は、前記第２金属板を封止している、請求項１乃至８の何れか一項に記載の半導体装置。     A second metal plate disposed opposite to the metal plate with the semiconductor chip interposed therebetween,
    A second insulating resin layer;
    Further comprising
    The semiconductor chip is provided on one surface side of the second metal plate, and the semiconductor chip is sandwiched between the metal plate and the second metal plate;
    The second insulating resin layer is bonded to a surface of the second metal plate opposite to the semiconductor chip side,
    The semiconductor device according to claim 1, wherein the mold resin seals the second metal plate.
  10. 　前記第２絶縁樹脂層における前記第２金属板側とは反対側の面に対して一方の面が接合された第２金属層を更に備える請求項９に記載の半導体装置。 10. The semiconductor device according to claim 9, further comprising a second metal layer in which one surface is bonded to a surface opposite to the second metal plate side in the second insulating resin layer.
  11. 　前記第２金属層の前記一方の面に対する反対側の面の全面が前記モールド樹脂から露出している請求項１０に記載の半導体装置。 The semiconductor device according to claim 10, wherein an entire surface of the second metal layer opposite to the one surface is exposed from the mold resin.
  12. 　前記第２金属層の前記一方の面とは反対側の面に形成された第２放熱グリース層と、
    　前記第２放熱グリース層を介して前記第２金属層の前記反対側の面に固定された第２冷却フィンと、
    　を更に備える請求項１０または１１に記載の半導体装置。     A second heat dissipating grease layer formed on a surface opposite to the one surface of the second metal layer;
    A second cooling fin fixed to the opposite surface of the second metal layer via the second heat dissipating grease layer;
    The semiconductor device according to claim 10 or 11, further comprising:
  13. 　前記半導体チップを間に挟んで前記金属板と対向して配置された第２金属板と、
    　第２絶縁樹脂層と、
    　を更に備え、
    　前記半導体チップが前記第２金属板の一方の面側に設けられて、前記金属板と前記第２金属板とにより前記半導体チップが挟持されており、
    　前記第２絶縁樹脂層は、前記第２金属板における前記半導体チップ側とは反対側の面に接合されており、
    　前記モールド樹脂は、前記第２金属板を封止しており、
    　当該半導体装置は、
    　前記第２絶縁樹脂層における前記第２金属板側とは反対側の面に対して、一方の面が接合された第２金属層と、
    　前記第２金属層の前記一方の面とは反対側の面に形成された第２放熱グリース層と、
    　前記第２放熱グリース層を介して前記第２金属層の前記反対側の面に固定された第２冷却フィンと、
    　を更に備え、
    　前記金属層、前記第２金属層、前記冷却フィンおよび前記第２冷却フィンが同種の金属により構成されている請求項８に記載の半導体装置。     A second metal plate disposed opposite to the metal plate with the semiconductor chip interposed therebetween,
    A second insulating resin layer;
    Further comprising
    The semiconductor chip is provided on one surface side of the second metal plate, and the semiconductor chip is sandwiched between the metal plate and the second metal plate;
    The second insulating resin layer is bonded to a surface of the second metal plate opposite to the semiconductor chip side,
    The mold resin seals the second metal plate;
    The semiconductor device is
    A second metal layer having one surface bonded to a surface opposite to the second metal plate in the second insulating resin layer;
    A second heat dissipating grease layer formed on a surface opposite to the one surface of the second metal layer;
    A second cooling fin fixed to the opposite surface of the second metal layer via the second heat dissipating grease layer;
    Further comprising
    The semiconductor device according to claim 8, wherein the metal layer, the second metal layer, the cooling fin, and the second cooling fin are made of the same kind of metal.
  14. 　前記半導体チップを間に挟んで前記金属板と対向して配置された第２金属板と、
    　第２絶縁樹脂層と、
    　を更に備え、
    　前記半導体チップが前記第２金属板の一方の面側に設けられて、前記金属板と前記第２金属板とにより前記半導体チップが挟持されており、
    　前記第２絶縁樹脂層は、前記第２金属板における前記半導体チップ側とは反対側の面に接合されており、
    　前記モールド樹脂は、前記第２金属板を封止しており、
    　当該半導体装置は、
    　前記第２絶縁樹脂層における前記第２金属板側とは反対側の面に対して、一方の面が接合された第２金属層と、
    　前記第２金属層の前記一方の面とは反対側の面に形成された第２放熱グリース層と、
    　前記第２放熱グリース層を介して前記第２金属層の前記反対側の面に固定された第２冷却フィンと、
    　を更に備え、
    　前記金属層、前記第２金属層、前記冷却フィンおよび前記第２冷却フィンがアルミニウムにより構成されている請求項８に記載の半導体装置。     A second metal plate disposed opposite to the metal plate with the semiconductor chip interposed therebetween,
    A second insulating resin layer;
    Further comprising
    The semiconductor chip is provided on one surface side of the second metal plate, and the semiconductor chip is sandwiched between the metal plate and the second metal plate;
    The second insulating resin layer is bonded to a surface of the second metal plate opposite to the semiconductor chip side,
    The mold resin seals the second metal plate;
    The semiconductor device is
    A second metal layer having one surface bonded to a surface opposite to the second metal plate in the second insulating resin layer;
    A second heat dissipating grease layer formed on a surface opposite to the one surface of the second metal layer;
    A second cooling fin fixed to the opposite surface of the second metal layer via the second heat dissipating grease layer;
    Further comprising
    The semiconductor device according to claim 8, wherein the metal layer, the second metal layer, the cooling fin, and the second cooling fin are made of aluminum.
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