JP6635034B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  As a semiconductor device having a semiconductor chip and a mold resin encapsulating the semiconductor chip, a type in which the semiconductor chip is mounted on one surface of a metal plate and an insulating resin layer is provided on the other surface of the metal plate There are things.

  For example, in Patent Literature 1, a semiconductor chip is mounted on one surface of a metal plate (lead frame of the same document), an insulating resin layer is provided on the other surface of the metal plate, A semiconductor device in which a metal layer (a heat sink in the same document) is provided on the opposite surface is described. And the insulating resin layer of the said document is comprised including the secondary aggregated particle which the primary particle of flaky boron nitride aggregates isotropically.

JP 2010-157563 A

According to the study of the present inventors, if the average particle diameter of the secondary aggregated particles of flaky boron nitride contained in the insulating resin layer is too large compared to the thickness of the insulating resin layer, the thickness of the insulating resin layer May not be stable in the plane, and the insulating property of the insulating resin layer may be deteriorated. When the package of the semiconductor device is smaller than a certain degree, the electric field concentrates most in the plane of the insulating resin layer as the package of the semiconductor device becomes larger, even if such deterioration of the insulating property does not appear as a problem. The electric field at the location becomes stronger. For this reason, it is considered that the deterioration of the insulating property due to a slight change in the thickness of the insulating resin layer may become a problem as a problem.
If the average particle diameter of the secondary aggregated particles is too large compared to the thickness of the insulating resin layer, the possibility that voids exist in the insulating resin layer also increases.
On the other hand, when the average particle diameter of the secondary aggregated particles is too small compared to the thickness of the insulating resin layer, the thermal resistance of the insulating resin layer deteriorates (thermal conductivity deteriorates).

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a semiconductor device having an insulating resin layer which has a uniform film thickness, suppresses generation of voids, and has a good thermal conductivity. The purpose is to provide.

A metal plate,
A semiconductor chip provided on the first surface side of the metal plate;
An insulating resin layer joined to a second surface of the metal plate opposite to the first surface;
A mold resin sealing the semiconductor chip and the metal plate,
With
The insulating resin layer includes secondary agglomerated particles in which primary particles of flaky boron nitride are isotropically agglomerated,
The content of the secondary aggregated particles is 65% by mass or more and 90% by mass or less based on the entire insulating resin layer,
When the thickness of the insulating resin layer is D and the average particle diameter of the secondary aggregated particles is d,
Provided is a semiconductor device having d / D of 0.05 or more and 0.8 or less.

  According to the present invention, since d / D is 0.05 or more, the insulating resin layer can have a structure having good thermal conductivity. Furthermore, since d / D is 0.8 or less, the insulating resin layer can have a structure in which the film thickness is excellently uniform, has good insulating properties, and suppresses generation of voids. .

  According to the present invention, it is possible to provide a semiconductor device having an insulating resin layer whose film thickness is satisfactorily uniform, generation of voids is suppressed, and thermal conductivity is good.

  The above and other objects, features and advantages will become more apparent from the preferred embodiments described below and the accompanying drawings.

FIG. 2 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. FIG. 2 is a schematic sectional view of an insulating resin layer of the semiconductor device according to the first embodiment. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. FIG. 9 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. FIG. 14 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. It is a typical sectional view of the semiconductor device concerning a 5th embodiment. It is a typical sectional view of the semiconductor device concerning a 6th embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and description thereof will not be repeated.

(First embodiment)
FIG. 1 is a schematic sectional view of a semiconductor device 100 according to the first embodiment. FIG. 2 is a schematic cross-sectional view of the insulating resin layer 140 of the semiconductor device 100 according to the first embodiment.

  In the following, for the sake of simplicity, the description may be made on the assumption that the positional relationship (such as the vertical relationship) of each component of the semiconductor device 100 is the relationship shown in each drawing. However, the positional relationship in this description is irrelevant to the positional relationship when the semiconductor device 100 is used or manufactured.

In the present embodiment, an example in which the metal plate is a heat sink will be described. The semiconductor device 100 according to the present embodiment is joined to the heat sink 130, the semiconductor chip 110 provided on the first surface 131 side of the heat sink 130, and the second surface 132 of the heat sink 130 opposite to the first surface 131. And a molding resin 180 that seals the semiconductor chip 110 and the heat sink 130. The insulating resin layer 140 includes secondary aggregated particles 144 in which the primary particles 143 of flaky boron nitride are isotropically aggregated. Assuming that the thickness of the insulating resin layer 140 is D and the average particle diameter of the secondary aggregated particles 144 is d, d / D is 0.05 or more and 0.8 or less.
The details will be described below.

  The semiconductor device 100 includes, for example, a conductive layer 120, an electrode terminal portion 135, a metal layer 150, a lead 160, and a wire (metal wiring) 170 in addition to the above-described configuration.

  An electrode pattern (not shown) is formed on the upper surface 111 of the semiconductor chip 110, and a conductive pattern (not shown) is formed on the lower surface 112 of the semiconductor chip 110. The lower surface 112 of the semiconductor chip 110 is joined to the first surface 131 of the heat sink 130 via a conductive layer 120 such as a silver paste. The electrode pattern on the upper surface 111 of the semiconductor chip 110 is electrically connected to the electrode 161 of the lead 160 via the wire 170.

  The mold resin 180 seals the wires 170, the conductive layer 120, and a part of each of the leads 160 in addition to the semiconductor chip 110 and the heat sink 130 to form a housing. The other part of each lead 160 projects outside the mold resin 180 from the side surface of the mold resin 180. In the case of the present embodiment, for example, the lower surface 182 of the mold resin 180 and the second surface 132 of the heat sink 130 are located on the same plane.

  One end of the electrode terminal 135 is located inside the mold resin 180 and is electrically connected to the heat sink 130, and the other end protrudes outside the mold resin 180. For this reason, the heat sink 130 plays a role as an electrode that receives power supply from the outside.

The heat sink 130 is made of metal. In the case of the present embodiment, the electrode terminal portion 135 is formed integrally with the heat sink 130. That is, the electrode terminal 135 is a part of the heat sink 130. In this case, the electrode terminal 135 is naturally electrically connected to the heat sink 130.
However, the electrode terminal 135 may be formed separately from the heat sink 130. In this case, one end of the electrode terminal portion 135 is electrically connected to, for example, the first surface 131 of the heat sink 130 via a conductive layer (not shown).

  The insulating resin layer 140 is a heat conductive material having heat dissipation. As a material for forming such a heat conductive material, a heat conductive sheet (heat radiating resin sheet) containing a heat conductive filler (filler) such as boron nitride or alumina is exemplified.

  Upper surface 141 of insulating resin layer 140 is joined to second surface 132 of heat sink 130 and lower surface 182 of mold resin 180. That is, the mold resin 180 is in contact with the surface (the upper surface 141) of the insulating resin layer 140 on the heat sink 130 side around the heat sink 130.

  The lower surface 142 of the insulating resin layer 140 is joined to the upper surface 151 of the metal layer 150. That is, one surface (upper surface 151) of the metal layer 150 is joined to the surface (lower surface 142) of the insulating resin layer 140 opposite to the heat sink 130 side.

  In plan view, it is preferable that the outline of the upper surface 151 of the metal layer 150 and the outline of the surface (the lower surface 142) of the insulating resin layer 140 opposite to the heat sink 130 be overlapped.

  Further, the entire surface of the metal layer 150 on the opposite side (lower surface 152) to one surface (upper surface 151) is exposed from the mold resin 180. In the present embodiment, as described above, since the upper surface 141 of the insulating resin layer 140 is joined to the second surface 132 of the heat sink 130 and the lower surface 182 of the mold resin 180, the insulating resin layer 140 , Except for its upper surface 141, is exposed outside the mold resin 180. The entire metal layer 150 is exposed outside the mold resin 180.

  The second surface 132 and the first surface 131 of the heat sink 130 are formed, for example, flat, respectively.

  The mounting floor area of the semiconductor device 100 is not particularly limited, but may be, for example, 10 × 10 mm or more and 100 × 100 mm or less. Here, the mounting floor area of the semiconductor device 100 is the area of the lower surface 152 of the metal layer 150. That is, the planar shape of the metal layer 150 can be a rectangular shape having a side length of 10 mm or more and 100 mm or less, and the lower surface 152 thereof can be a rectangular shape having a side length of 10 mm or more and 100 mm or less. Can be.

  Further, the number of semiconductor chips 110 mounted on one heat sink 130 is not particularly limited. It may be one or a plurality. For example, the number may be three or more (six or the like). That is, as an example, three or more semiconductor chips 110 are provided on the first surface 131 side of one heat sink 130, and the mold resin 180 collectively seals the three or more semiconductor chips 110.

  The semiconductor device 100 is, for example, a power semiconductor device. That is, the semiconductor chip 110 is, for example, a power semiconductor chip.

  The semiconductor device 100 is, for example, a 2in1 in which two semiconductor chips 110 are sealed in a mold resin 180, a 6in1 in which six semiconductor chips 110 are sealed in a mold resin 180, or a 7in1 in a mold resin 180. A 7in1 configuration in which the semiconductor chips 110 are sealed can be employed.

  As shown in FIG. 2, the insulating resin layer 140 includes a filler in the thermosetting resin 145.

  The thickness of the insulating resin layer 140 is, for example, not less than 50 μm and not more than 500 μm.

  Among the materials constituting the insulating resin layer 140, examples of the thermosetting resin 145 include an epoxy resin, a polyimide resin, a benzoxazine resin, an unsaturated polyester resin, a phenol resin, a melamine resin, a silicone resin, a bismaleimide resin, and an acrylic resin. Resins and cyanate resins. As the thermosetting resin 145, one of these may be used alone, or two or more thereof may be used in combination. As the thermosetting resin 145, an epoxy resin is preferable. By using an epoxy resin, the glass transition temperature can be increased, and the thermal conductivity of the insulating resin layer 140 can be improved. Further, by using a cyanate resin, the glass transition temperature can be increased, so that the heat resistance of the insulating resin layer 140 can be improved.

  Examples of the epoxy resin include bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol E type epoxy resin, bisphenol S type epoxy resin, and bisphenol M type epoxy resin (4,4 ′-(1,3-phenylene diisopropane). (Pridiene) bisphenol type epoxy resin), bisphenol P type epoxy resin (4,4 '-(1,4-phenylenediisopridiene) bisphenol type epoxy resin), bisphenol Z type epoxy resin (4,4'-cyclohexyl) Bisphenol type epoxy resins such as diene bisphenol type epoxy resin); phenol novolak type epoxy resin, cresol novolak type epoxy resin, tetraphenol group ethane type novolak type epoxy resin, and novola having a condensed ring aromatic hydrocarbon structure Novolak epoxy resins such as epoxy resins; biphenyl epoxy resins; arylalkylene epoxy resins such as xylylene epoxy resins and biphenylaralkyl epoxy resins; naphthylene ether epoxy resins, naphthol epoxy resins, and naphthalene diol epoxy resins Resins, naphthalene epoxy resins such as bifunctional to tetrafunctional epoxy naphthalene resins, binaphthyl epoxy resins, naphthalene aralkyl epoxy resins; anthracene epoxy resins; phenoxy epoxy resins; dicyclopentadiene epoxy resins; norbornene epoxy resins An adamantane type epoxy resin; a fluorene type epoxy resin;

  One of these may be used alone as the epoxy resin, or two or more thereof may be used in combination.

  Among the epoxy resins, from the viewpoint of further improving the heat resistance and insulation reliability of the obtained insulating resin layer 140, bisphenol type epoxy resin, novolak type epoxy resin, biphenyl type epoxy resin, arylalkylene type epoxy resin, naphthalene type epoxy resin One or two or more selected from the group consisting of resin, anthracene-type epoxy resin, and dicyclopentadiene-type epoxy resin are preferable.

In the present embodiment, the cyanate resin is not particularly limited, but is, for example, a compound having an -OCN group in a molecule, and the -OCN group reacts by heating to form a three-dimensional network structure and cure. Resin. Specific examples include 1,3-dicyanatobenzene, 1,4-dicyanatobenzene, 1,3,5-tricyanatobenzene, 1,3-dicyanatonaphthalene, 1,4-dicyanatonaphthalene, 6-dicyanatonaphthalene, 1,8-dicyanatonaphthalene, 2,6-dicyanatonaphthalene, 2,7-dicyanatonaphthalene, 1,3,6-tricyanatonaphthalene, 4,4′-dicyanatobiphenyl, bis (4-cyanatophenyl) methane, bis (3,5-dimethyl-4-cyanatophenyl) methane, 2,2-bis (4-cyanatophenyl) propane, 2,2-bis (3,5-dibromo -4-cyanatophenyl) propane, bis (4-cyanatophenyl) ether, bis (4-cyanatophenyl) thioether, bis (4-cyanatophenyl) s Examples thereof include rufone, tris (4-cyanatophenyl) phosphite, tris (4-cyanatophenyl) phosphate, and cyanates obtained by reacting a novolak resin with a cyanogen halide. Prepolymers having triazine rings formed by trimerizing cyanate groups can also be used. This prepolymer is obtained by polymerizing the above polyfunctional cyanate resin monomer with, for example, a mineral acid, an acid such as a Lewis acid, a base such as sodium alcoholate or a tertiary amine, or a salt such as sodium carbonate as a catalyst. Can be
In the present embodiment, when a cyanate resin (particularly a novolak type cyanate resin) is used as the thermosetting resin, an epoxy resin may be used in combination.

  The content of the thermosetting resin 145 contained in the insulating resin layer 140 is not particularly limited as long as it is appropriately adjusted according to the purpose, and is 1% by mass to 30% by mass with respect to 100% by mass of the insulating resin layer. Is preferably 5% by mass or more and 20% by mass or less. When the content of the thermosetting resin 145 is equal to or more than the above lower limit, the handleability is improved and the insulating resin layer 140 can be easily formed. When the content of the thermosetting resin 145 is equal to or less than the above upper limit, the strength and the flame retardancy of the insulating resin layer 140 are further improved, and the thermal conductivity of the insulating resin layer 140 is further improved.

When an epoxy resin is used as the thermosetting resin 145, the insulating resin layer 140 preferably further contains a curing agent.
As the curing agent, one or more selected from a curing catalyst and a phenolic curing agent can be used.
Examples of the curing catalyst include organic metal salts such as zinc naphthenate, cobalt naphthenate, tin octylate, cobalt octylate, bisacetylacetonatocobalt (II), and trisacetylacetonatocobalt (III); triethylamine, tributylamine, and the like. Tertiary amines such as 1,4-diazabicyclo [2.2.2] octane; 2-phenyl-4-methylimidazole, 2-ethyl-4-methylimidazole, 2,4-diethylimidazole, 2-phenyl-4 Imidazoles such as -methyl-5-hydroxyimidazole and 2-phenyl-4,5-dihydroxymethylimidazole; triphenylphosphine, tri-p-tolylphosphine, tetraphenylphosphonium tetraphenylborate, triphenylphosphine triphenyl Organic phosphorus compounds such as borane and 1,2-bis- (diphenylphosphino) ethane; phenol compounds such as phenol, bisphenol A and nonylphenol; organic acids such as acetic acid, benzoic acid, salicylic acid and p-toluenesulfonic acid; Or a mixture thereof. As the curing catalyst (C-1), one kind including these derivatives may be used alone, or two or more kinds including these derivatives may be used in combination.
The content of the curing catalyst contained in the insulating resin layer 140 is not particularly limited, but is preferably 0.001% by mass or more and 1% by mass or less based on 100% by mass of the insulating resin layer.

Examples of the phenolic curing agent include novolak-type phenol resins such as phenol novolak resin, cresol novolak resin, naphthol novolak resin, aminotriazine novolak resin, and novolak resin; and modified phenols such as terpene-modified phenol resin and dicyclopentadiene-modified phenol resin. Resins; phenol aralkyl resins having a phenylene skeleton and / or a biphenylene skeleton; aralkyl resins such as a naphthol aralkyl resin having a phenylene skeleton and / or a biphenylene skeleton; bisphenol compounds such as bisphenol A and bisphenol F; These may be used alone or in combination of two or more.
Among them, a phenolic curing agent is preferably a novolak-type phenol resin or a resol-type phenol resin from the viewpoint of improving the glass transition temperature and reducing the linear expansion coefficient.
The content of the phenolic curing agent is not particularly limited, but is preferably 1% by mass or more and 30% by mass or less, more preferably 5% by mass or more and 15% by mass or less based on 100% by mass of the insulating resin layer.

Among the materials constituting the insulating resin layer 140, as the filler, the secondary aggregated particles 144 formed by isotropically aggregating the primary particles 143 of flaky boron nitride (that is, in a state oriented in a random direction) are used. Is included. That is, the insulating resin layer 140 includes, for example, the secondary aggregated particles 144 in which the primary particles 143 of the flaky boron nitride are isotropically aggregated. The primary particles 143 mean individual particles that are not aggregated. The shape of the secondary aggregated particles 144 is, for example, spherical.
The insulating resin layer 140 may include, as a filler, the thermosetting resin 145, in addition to the secondary aggregated particles 144, primary particles 143 arranged isotropically (that is, in a random direction). , May not be included.
The filler may include, for example, one or more of silica, alumina, aluminum nitride, silicon carbide, and the like.

The secondary aggregated particles 144 can be formed, for example, by aggregating flaky boron nitride using a spray dry method or the like, and then firing the aggregated particles. The firing temperature is, for example, 1200 to 2500 ° C.
As described above, when the secondary aggregated particles 144 obtained by sintering the flaky boron nitride are used, from the viewpoint of improving the dispersibility of the filler in the thermosetting resin, dicyclohexane is used as the thermosetting resin. It is particularly preferable to use a pentadiene type epoxy resin or a novolak type epoxy resin.

  The average particle diameter of the secondary aggregated particles 144 is preferably, for example, 5 μm or more and 180 μm or less. Thereby, the insulating resin layer 140 having an excellent balance between the thermal conductivity and the electrical insulation can be realized.

  The content of the filler with respect to the entire insulating resin layer 140 is, for example, preferably from 65% by mass to 90% by mass, and more preferably from 70% by mass to 85% by mass. By setting the content of the filler to be equal to or more than the lower limit, the thermal conductivity and mechanical strength of the insulating resin layer 140 can be more effectively improved. On the other hand, when the content of the filler is equal to or less than the upper limit, the film forming property and workability of the resin composition are improved, and the uniformity in the thickness of the insulating resin layer 140 can be improved. it can.

  As described above, when the thickness of the insulating resin layer 140 is D and the average particle diameter of the secondary aggregated particles 144 is d, d / D is 0.05 or more and 0.8 or less. Here, the thickness D of the insulating resin layer 140 can be, for example, an average value of the thickness at a plurality of locations (5 locations, 10 locations, and the like). Further, the average particle diameter d of the secondary aggregated particles 144 can be an average value of the particle diameters of a plurality (5, 10, etc.) of the secondary aggregated particles 144 in the insulating resin layer 140. For example, when the particle diameters of the ten secondary aggregated particles 144 are d1, d2, d3, d4, d5, d6, d7, d8, d9, and d10, respectively, the average particle diameter d is the particle diameter d1 to d10. It can be an average value. d / D is preferably less than 0.5.

  The thermal conductivity in the thickness direction of the insulating resin layer 140 is preferably 6 W / m · K or more and 50 W / m · K or less, more preferably 7 W / m · K or more and 50 W / m · K or less, and 8 W / m · K or more. 50 W / m · K or less is more preferable, and 9 W / m · K or more and 50 W / m · K or less is more preferable. By doing so, it is possible to obtain the insulating resin layer 140 that exhibits better characteristics in terms of thermal resistance. The thermal conductivity in the thickness direction of the insulating resin layer 140 can be measured by, for example, a laser flash method.

  Next, an example of a method for manufacturing the semiconductor device 100 according to the embodiment will be described.

  First, the heat sink 130 and the semiconductor chip 110 are prepared, and the lower surface 112 of the semiconductor chip 110 is joined to the first surface 131 of the heat sink 130 via the conductive layer 120 such as a silver paste.

  Next, a lead frame (not shown) including the leads 160 is prepared, and the electrode patterns on the upper surface of the semiconductor chip 110 and the electrodes 161 of the leads 160 are electrically connected to each other via the wires 170.

  Next, the semiconductor chip 110, the conductive layer 120, the heat sink 130, the wires 170, and a part of each of the leads 160 are collectively sealed with a mold resin 180.

  Next, a heat conductive sheet to be a material of the insulating resin layer 140 is prepared, and one surface of the heat conductive sheet is held against the second surface 132 of the heat sink 130 and the lower surface 182 of the mold resin 180. paste. At this stage, the thermosetting resin constituting the heat conductive sheet is at the B stage. Further, one surface (upper surface 151) of the metal layer 150 is attached to a surface (lower surface 142) of the insulating resin layer 140 opposite to the heat sink 130 side. Then, the thermosetting resin constituting the heat conductive sheet is heat-cured to form a C stage, so that the heat conductive sheet becomes the insulating resin layer 140 and the second surface 132 of the heat sink 130 and the mold resin 180. The upper surface 151 of the metal layer 150 is joined to the lower surface 182 of the metal layer 150 via the insulating resin layer 140.

  Next, each lead 160 is cut from a frame (not shown) of the lead frame. Thus, the semiconductor device 100 having the structure as shown in FIG. 1 is obtained.

According to the above-described first embodiment, the semiconductor device 100 includes the heat sink 130, the semiconductor chip 110 provided on the first surface 131 side of the heat sink 130, and the opposite side of the heat sink 130 from the first surface 131. An insulating resin layer 140 bonded to the second surface 132 of the semiconductor chip 110 and a mold resin 180 sealing the semiconductor chip 110 and the heat sink 130 are provided. The insulating resin layer 140 includes secondary aggregated particles 144 in which the primary particles 143 of flaky boron nitride are isotropically aggregated. When the thickness of the insulating resin layer 140 is D and the average particle diameter of the secondary aggregated particles 144 is d, d / D is 0.05 or more and 0.8 or less.
Since d / D is 0.05 or more, the insulating resin layer 140 can have a structure with good thermal conductivity. Further, since d / D is 0.8 or less, the insulating resin layer 140 may have a structure in which the film thickness is excellently uniform, has good insulating properties, and suppresses generation of voids. it can. In addition, since the thickness of the insulating resin layer 140 is favorably made uniform, it is possible to suppress the thermal resistance of the insulating resin layer 140 from locally increasing.

  When d / D is less than 0.5, the insulating resin layer 140 containing the secondary aggregated particles 144 can be easily and stably formed.

As described above, when the package of the semiconductor device is smaller than a certain degree, the deterioration of the insulating property of the insulating resin layer does not appear as a problem, but the larger the package of the semiconductor device, the larger the surface area of the insulating resin layer. The electric field at the location where the electric field is concentrated most becomes strong. For this reason, it is considered that the deterioration of the insulating property due to a slight change in the thickness of the insulating resin layer may become a problem as a problem.
On the other hand, the semiconductor device 100 according to the present embodiment includes the insulating resin layer 140 having the above structure, even if the mounting floor area is a large package having a size of 10 × 10 mm or more and 100 × 100 mm or less. Thereby, it is expected that a sufficient withstand voltage is obtained.

  Further, in the semiconductor device 100 according to the present embodiment, for example, three or more semiconductor chips 110 are provided on the first surface 131 side of one heat sink 130, and the three or more semiconductor chips are collectively formed by the molding resin 180. Even if the semiconductor device 100 has a structure in which the semiconductor device 100 is a large package, the insulating resin layer 140 having the above structure can provide a sufficient withstand voltage. Can be expected.

  When the semiconductor device 100 further includes a metal layer 150 in which one surface (upper surface 151) is joined to a surface (lower surface 142) of the insulating resin layer 140 opposite to the heat sink 130, the metal layer 150 Accordingly, heat can be appropriately dissipated, so that the heat dissipation of the semiconductor device 100 is improved.

If the upper surface 151 of the metal layer 150 is smaller than the lower surface 142 of the insulating resin layer 140, the lower surface 142 of the insulating resin layer 140 is exposed to the outside, and there is a concern that cracks may occur in the insulating resin layer 140 due to projections such as foreign matters. Occurs. On the other hand, when the upper surface 151 of the metal layer 150 is larger than the lower surface 142 of the insulating resin layer 140, the end of the metal layer 150 has a structure floating in the air. May be peeled off.
On the other hand, when the outline of the upper surface 151 of the metal layer 150 and the outline of the lower surface 142 of the insulating resin layer 140 overlap each other in a plan view, cracks in the insulating resin layer 140 can be prevented. Peeling of the metal layer 150 can be suppressed.

  Further, since the entire lower surface 152 of the metal layer 150 is exposed from the mold resin 180, heat can be radiated over the entire lower surface 152 of the metal layer 150, and high heat radiation of the semiconductor device 100 can be obtained.

(Second embodiment)
FIG. 3 is a schematic sectional view of the semiconductor device 100 according to the second embodiment. The semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the above-described first embodiment in the following points, and the semiconductor device 100 according to the above-described first embodiment is otherwise different. It is configured similarly to.

  The semiconductor device 100 according to the present embodiment includes a second heat sink 230 and a second insulating resin layer 240 in addition to the configuration of the semiconductor device 100 according to the first embodiment. The second insulating resin layer 240 is similar to the insulating resin layer 140.

  The second heat sink 230 is made of metal. The second heat sink 230 is arranged to face the heat sink 130 with the semiconductor chip 110 interposed therebetween. The semiconductor chip 110 is provided on one surface (lower surface 232) of the second heat sink 230, and the semiconductor chip 110 is sandwiched between the heat sink 130 and the second heat sink 230. Further, the second insulating resin layer 240 is joined to a surface (upper surface 231) of the second heat sink 230 on the side opposite to the semiconductor chip 110 side. The mold resin 180 seals the second heat sink 230 and is in contact with the surface (lower surface 242) of the second insulating resin layer 240 on the side of the second heat sink 230 around the second heat sink 230. In the case of the present embodiment, for example, the upper surface 181 of the mold resin 180 and the upper surface 231 of the second heat sink 230 are located on the same plane.

The semiconductor device 100 according to this embodiment further includes a second surface (lower surface 252) joined to a surface (upper surface 241) of the second insulating resin layer 240 opposite to the second heat sink 230 side. Further, a metal layer 250 is provided. Then, the entire surface of the surface (upper surface 251) opposite to one surface (lower surface 252) of second metal layer 250 is exposed from mold resin 180.
Further, it is preferable that the outline of the lower surface 252 of the second metal layer 250 and the outline of the upper surface 241 of the second insulating resin layer 240 overlap in a plan view.

  More specifically, the semiconductor device 100 further includes, for example, a metal block 220 disposed between the semiconductor chip 110 and the second heat sink 230. The lower surface 222 of the metal block 220 is joined to a partial region of the upper surface 111 of the semiconductor chip 110 via a conductive layer 211 such as a silver paste. A conductive pattern (not shown) is formed in the partial region of the semiconductor chip 110. The lower surface 232 of the second heat sink 230 is joined to the upper surface 221 of the metal block 220 via a conductive layer 212 such as a silver paste.

  According to the above-described second embodiment, the following effects can be obtained in addition to the same effects as those of the first embodiment.

The semiconductor device 100 according to the present embodiment further includes a second heat sink 230 disposed opposite to the heat sink 130 with the semiconductor chip 110 interposed therebetween, and a second insulating resin layer 240. The semiconductor chip 110 is provided on one surface (lower surface 232) of the second heat sink 230, and the semiconductor chip 110 is held between the heat sink 130 and the second heat sink 230. Further, the second insulating resin layer 240 is joined to a surface (upper surface 231) of the second heat sink 230 on the side opposite to the semiconductor chip 110 side. The mold resin 180 seals the second heat sink 230.
Therefore, since heat sinks (the heat sink 130 and the second heat sink 230) are provided on both surfaces of the semiconductor chip 110, heat can be radiated from both surfaces of the semiconductor chip 110, and the semiconductor device 100 has excellent heat radiation. be able to.

  The semiconductor device 100 further includes a second metal layer 250 in which one surface (lower surface 252) is joined to a surface (upper surface 241) of the second insulating resin layer 240 opposite to the second heat sink 230 side. In this case, since the second metal layer 250 can appropriately dissipate heat, the heat dissipation of the semiconductor device 100 is improved.

Also, when the lower surface 252 of the second metal layer 250 is smaller than the upper surface 241 of the second insulating resin layer 240, the upper surface 241 of the second insulating resin layer 240 is exposed to the outside, and the second insulating resin There is a concern that cracks may occur in the layer 240. On the other hand, if the lower surface 252 of the second metal layer 150 is larger than the upper surface 241 of the second insulating resin layer 240, the end of the second metal layer 150 will have a structure that floats in the air. In such cases, the second metal layer 250 may be peeled off.
On the other hand, when the outline of the lower surface 252 of the second metal layer 250 and the outline of the upper surface 241 of the second insulating resin layer 240 are overlapped in a plan view, the second insulating resin layer Generation of cracks at 240 and peeling of the second metal layer 250 can be suppressed.

  Further, since the entire upper surface 251 of the second metal layer 250 is exposed from the mold resin 180, heat can be radiated over the entire upper surface 251 of the second metal layer 250, and the high heat radiation of the semiconductor device 100 can be obtained. .

(Third embodiment)
FIG. 4 is a schematic sectional view of a semiconductor device 100 according to the third embodiment. The semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the above-described first embodiment in the following points, and the semiconductor device 100 according to the above-described first embodiment is otherwise different. It is configured similarly to.

  In the case of the present embodiment, the semiconductor device 100 includes a heat radiation grease layer 310 formed on the lower surface 152 of the metal layer 150, and a cooling fin 320 fixed to the lower surface 152 of the metal layer 150 via the heat radiation grease layer 310. It has more.

  The cooling fins 320 are made of, for example, metal. The cooling fin 320 includes, for example, a flat plate-shaped main body and a number of protrusions protruding downward from the lower surface side of the main body.

  According to the above-described third embodiment, the following effects can be obtained in addition to the same effects as those of the first embodiment.

  The semiconductor device 100 according to the present embodiment includes a heat radiation grease layer 310 formed on a surface (lower surface 152) opposite to one surface (upper surface 151) of the metal layer 150, and a metal layer with the heat radiation grease layer 310 interposed therebetween. And cooling fins 320 fixed to a surface (lower surface 152) opposite to 150. Therefore, heat can be radiated with high heat radiation efficiency by the cooling fins 320, so that the heat radiation of the semiconductor device 100 is improved.

(Fourth embodiment)
FIG. 5 is a schematic sectional view of a semiconductor device 100 according to the fourth embodiment. The semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the above-described second embodiment in the following points, and is otherwise different from the semiconductor device 100 according to the above-described second embodiment. It is configured similarly to.

  In the case of the present embodiment, the semiconductor device 100 includes a heat radiation grease layer 310 formed on the lower surface 152 of the metal layer 150, a cooling fin 320 fixed to the lower surface 152 of the metal layer 150 via the heat radiation grease layer 310, It further includes a second heat radiation grease layer 410 formed on the upper surface 251 of the second metal layer 250, and second cooling fins 420 fixed to the upper surface 251 of the second metal layer 250 via the second heat radiation grease layer 410. ing.

  The second cooling fins 420 are similar to the cooling fins 320 described in the third embodiment, and are arranged upside down with respect to the cooling fins 320.

  Here, the metal layer 150, the second metal layer 250, the cooling fins 320, and the second cooling fins 420 are made of, for example, the same kind of metal. More specifically, for example, the metal layer 150, the second metal layer 250, the cooling fins 320, and the second cooling fins 420 are each made of aluminum.

  According to the above-described fourth embodiment, the following effects can be obtained in addition to the same effects as those of the second embodiment.

The semiconductor device 100 according to the present embodiment includes a heat radiation grease layer 310 formed on a surface (lower surface 152) opposite to one surface (upper surface 151) of the metal layer 150, and a metal layer with the heat radiation grease layer 310 interposed therebetween. And cooling fins 320 fixed to a surface (lower surface 152) opposite to 150. Therefore, heat can be radiated with high heat radiation efficiency by the cooling fins 320, so that the heat radiation of the semiconductor device 100 is improved.
Similarly, a second heat radiation grease layer 410 formed on a surface (upper surface 251) opposite to one surface (lower surface 252) of second metal layer 250, and a second metal grease layer via second heat radiation grease layer 410. A second cooling fin 420 fixed to the opposite surface (upper surface 251) of the layer 250. Therefore, heat can be radiated with high heat radiation efficiency by the second cooling fins 420, and the heat radiation of the semiconductor device 100 is improved.

  In addition, since the metal layer 150, the second metal layer 250, the cooling fins 320, and the second cooling fins 420 are made of the same kind of metal, the potential difference between the metal layers 150 and the cooling fins 320 and the second metal layer 250 Corrosion deterioration caused by a potential difference between the second cooling fin 420 and the second cooling fin 420 can be suppressed.

  In particular, by forming the metal layer 150, the second metal layer 250, the cooling fins 320, and the second cooling fins 420 from aluminum, it is possible to make these configurations inexpensive and excellent in workability and heat dissipation. it can.

(Fifth embodiment)
FIG. 6 is a schematic sectional view of a semiconductor device 100 according to the fifth embodiment. The semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the above-described second embodiment in the following points, and is otherwise different from the semiconductor device 100 according to the above-described second embodiment. It is configured similarly to.

  In the case of the present embodiment, the periphery of the metal layer 150 and the periphery of the second metal layer 250 are each curved toward the mold resin 180. A fillet or the like from which the resin has protruded may be formed around the metal layer 150. Similarly, a fillet or the like may be formed around the second metal layer 250.

  The semiconductor device 100 according to the present embodiment can be obtained, for example, by uniformly pressing the semiconductor device 100 (FIG. 3) according to the above-described second embodiment from above and below.

  According to the fifth embodiment as described above, since the peripheral edge of the metal layer 150 and the peripheral edge of the second metal layer 250 are each curved toward the mold resin 180, the metal that is caught by the object can be used. Separation of the layer 150 and the second metal layer 250 can be suppressed. As a result, the insulating resin layer 140 and the second insulating resin layer 240 hardly come into direct contact with outside air and moisture, and the long-term reliability of the semiconductor device 100 is stabilized.

  In the fifth embodiment, the periphery of the metal layer 150 and the periphery of the second metal layer 250 of the semiconductor device 100 according to the second embodiment are curved toward the mold resin 180, respectively. Although the example in which the metal layer 150 is formed has been described, the peripheral portion of the metal layer 150 of the semiconductor device 100 according to the first embodiment may be curved toward the mold resin 180.

(Sixth embodiment)
FIG. 7 is a schematic sectional view of a semiconductor device 100 according to the sixth embodiment. The semiconductor device 100 according to the present embodiment is different from the semiconductor device 100 according to the above-described first embodiment in the following points, and the semiconductor device 100 according to the above-described first embodiment is otherwise different. It is configured similarly to.

  In the case of the present embodiment, the insulating resin layer 140 is sealed in the mold resin 180. The metal layer 150 is also sealed in the mold resin 180 except for the lower surface 152. The lower surface 152 of the metal layer 150 and the lower surface 182 of the mold resin 180 are located on the same plane.

  FIG. 7 shows an example in which at least two or more semiconductor chips 110 are mounted on the first surface 131 of the heat sink 130. The electrode patterns on the upper surface 111 of the semiconductor chip 110 are electrically connected to each other via wires 610. On the first surface 131, for example, a total of six semiconductor chips 110 are mounted. That is, for example, two semiconductor chips 110 are arranged in three rows in the depth direction of FIG.

  According to the sixth embodiment as described above, the same effects as those of the first embodiment can be obtained.

  By mounting the semiconductor device 100 according to each of the above embodiments on a substrate (not shown), a power module including the substrate and the semiconductor device 100 can be obtained.

  The present invention is not limited to the above embodiment, and it goes without saying that the present invention can be implemented in various modes without departing from the present invention.

For example, in the above description, an example in which the metal plate is a heat sink has been described, but the metal plate may be a depressed lead or a heat sink.
In the second, fourth, and fifth embodiments, the example in which the upper surface 181 of the housing is disposed on the same plane as the upper surface 231 of the second heat sink 230 has been described. May be arranged on the same plane as the upper surface 251 of the second metal layer 250.
Hereinafter, examples of the reference embodiment will be additionally described.
1. A metal plate,
A semiconductor chip provided on the first surface side of the metal plate;
An insulating resin layer joined to a second surface of the metal plate opposite to the first surface;
A mold resin sealing the semiconductor chip and the metal plate,
With
The insulating resin layer includes secondary agglomerated particles in which primary particles of flaky boron nitride are isotropically agglomerated,
When the thickness of the insulating resin layer is D and the average particle diameter of the secondary aggregated particles is d,
A semiconductor device having d / D of 0.05 or more and 0.8 or less.
2. d / D is less than 0.5 3. The semiconductor device according to claim 1.
3. The mounting floor area of the semiconductor device is 10 × 10 mm or more and 100 × 100 mm or less Or 2. 3. The semiconductor device according to claim 1.
4. Three or more semiconductor chips are provided on the first surface side of one of the metal plates;
The mold resin collectively seals the three or more semiconductor chips. To 3. The semiconductor device according to any one of the above.
5. The semiconductor device further includes a metal layer having one surface bonded to a surface of the insulating resin layer opposite to the metal plate. To 4. The semiconductor device according to any one of the above.
6. 4. In a plan view, the outline of the one surface of the metal layer and the outline of the surface of the insulating resin layer opposite to the metal plate side overlap. 3. The semiconductor device according to claim 1.
7. 4. the entire surface of the metal layer opposite to the one surface is exposed from the mold resin; Or 6. 3. The semiconductor device according to claim 1.
8. A heat radiation grease layer formed on a surface of the metal layer opposite to the one surface,
Cooling fins fixed to the opposite surface of the metal layer via the heat radiation grease layer,
4. further comprising Or 6. 3. The semiconductor device according to claim 1.
9. A second metal plate disposed opposite to the metal plate with the semiconductor chip interposed therebetween;
A second insulating resin layer,
Further comprising
The semiconductor chip is provided on one surface side of the second metal plate, and the semiconductor chip is sandwiched between the metal plate and the second metal plate,
The second insulating resin layer is bonded to a surface of the second metal plate opposite to the semiconductor chip,
The mold resin seals the second metal plate. To 8. The semiconductor device according to any one of the above.
10. 8. further comprising a second metal layer having one surface joined to a surface of the second insulating resin layer opposite to the second metal plate side; 3. The semiconductor device according to claim 1.
11. 9. the entire surface of the second metal layer opposite to the one surface is exposed from the mold resin; 3. The semiconductor device according to claim 1.
12. A second heat radiation grease layer formed on a surface of the second metal layer opposite to the one surface;
A second cooling fin fixed to the opposite surface of the second metal layer via the second heat radiation grease layer;
10. Or 11. 3. The semiconductor device according to claim 1.
13. A second metal plate disposed opposite to the metal plate with the semiconductor chip interposed therebetween;
A second insulating resin layer,
Further comprising
The semiconductor chip is provided on one surface side of the second metal plate, and the semiconductor chip is sandwiched between the metal plate and the second metal plate,
The second insulating resin layer is bonded to a surface of the second metal plate opposite to the semiconductor chip,
The mold resin seals the second metal plate,
The semiconductor device is
A second metal layer having one surface joined to a surface of the second insulating resin layer opposite to the second metal plate;
A second heat radiation grease layer formed on a surface of the second metal layer opposite to the one surface;
A second cooling fin fixed to the opposite surface of the second metal layer via the second heat radiation grease layer;
Further comprising
7. The metal layer, the second metal layer, the cooling fin, and the second cooling fin are made of the same metal. 3. The semiconductor device according to claim 1.
14． A second metal plate disposed opposite to the metal plate with the semiconductor chip interposed therebetween;
A second insulating resin layer,
Further comprising
The semiconductor chip is provided on one surface side of the second metal plate, and the semiconductor chip is sandwiched between the metal plate and the second metal plate,
The second insulating resin layer is bonded to a surface of the second metal plate opposite to the semiconductor chip,
The mold resin seals the second metal plate,
The semiconductor device is
A second metal layer having one surface joined to a surface of the second insulating resin layer opposite to the second metal plate;
A second heat radiation grease layer formed on a surface of the second metal layer opposite to the one surface;
A second cooling fin fixed to the opposite surface of the second metal layer via the second heat radiation grease layer;
Further comprising
7. The metal layer, the second metal layer, the cooling fin, and the second cooling fin are made of aluminum. 3. The semiconductor device according to claim 1.

  Hereinafter, the present invention will be described with reference to Examples and Comparative Examples, but the present invention is not limited thereto. In the examples, each thickness is represented by an average film thickness.

<Example 1>
(Preparation of secondary aggregated particles composed of primary particles of flaky boron nitride)
A mixture (melamine borate: flaky boron nitride powder = 10 :) obtained by mixing melamine borate (boric acid: melamine = 2: 1 (molar ratio)) and flaky boron nitride powder (average major axis: 8 μm) 1 (mass ratio)) was added to a 3.0 mass% aqueous solution of ammonium polyacrylate and mixed for 2 hours to prepare a slurry for spraying (aqueous solution of ammonium polyacrylate: mixture = 100: 30 (mass ratio)). ). Next, the slurry was supplied to a spray granulator, and sprayed under the conditions of an atomizer rotation speed of 15000 rpm, a temperature of 200 ° C., and a slurry supply amount of 5 ml / min, to produce composite particles. Next, the obtained composite particles were fired under a nitrogen atmosphere at 2000 ° C. for 10 hours to obtain an aggregated boron nitride (filler 1) having an average particle diameter d of 70 μm.
Here, the average particle size of the aggregated boron nitride was determined by measuring the particle size distribution of the particles on a volume basis with a laser diffraction type particle size distribution measuring device (LA-500, manufactured by HORIBA), and defined as the median diameter (D ₅₀ ). .

(Preparation of insulating resin layer)
First, according to the composition shown in Table 1, a thermosetting resin and a curing agent were added to methyl ethyl ketone as a solvent, and this was stirred to obtain a solution of a thermosetting resin composition. Next, the inorganic filler was put into this solution and preliminarily mixed, followed by kneading with a three-roll mill to obtain a resin composition in which the inorganic filler was uniformly dispersed. Next, the obtained resin composition was aged at 60 ° C. for 15 hours. Next, the resin composition was applied on a copper foil by using a doctor blade method, and then dried by heat treatment at 100 ° C. for 30 minutes to prepare a resin sheet. Next, the resin sheet was passed between two rolls and compressed to remove bubbles in the resin sheet, thereby obtaining a B-stage insulating resin layer having a film thickness D of 175 μm.

(Production of semiconductor device)
The semiconductor device shown in FIG. 1 was manufactured using the obtained insulating resin layer. Note that the mounting floor area of the semiconductor device was 30 × 40 mm.

<Comparative Example 1>
Aggregated boron nitride having an average particle diameter d of 20 μm (filler 2) prepared by the same method as in Example 1 except that the concentration of the aqueous solution of ammonium polyacrylate was changed to 2.0% by mass and the number of revolutions of the atomizer was changed to 10,000 rpm. A semiconductor device was fabricated in the same manner as in Example 1 except that the B-staged insulating resin layer was fabricated so that the film thickness D became 500 μm.

<Comparative Example 2>
A semiconductor device was manufactured in the same manner as in Example 1, except that a B-stage-shaped insulating resin layer was formed so that the film thickness D became 80 μm.

  The details of each component in Table 1 are as follows.

(Thermosetting resin)
Epoxy resin 1: biphenyl type epoxy resin (YL6121, manufactured by Mitsubishi Chemical Corporation)
Epoxy resin 2: bisphenol A type epoxy resin (JER828, manufactured by Mitsubishi Chemical Corporation)

(Curing agent and curing catalyst)
Curing agent: Trisphenol methane type novolak resin (MEH-7500, manufactured by Meiwa Kasei Co., Ltd.)
Curing catalyst: 2-phenyl-4,5-dihydroxymethylimidazole (2PHZ-PW, manufactured by Shikoku Chemicals)

(Filling material)
Aggregated boron nitride produced by the above production example

(Thermal conductivity of cured body of insulating resin layer)
For each of Example 1 and Comparative Examples 1 and 2, a cured body of an insulating resin layer was prepared separately from the semiconductor device, and its thermal conductivity was measured as follows. First, the obtained insulating resin layer was cured at 180 ° C. for one hour to obtain a cured body of the insulating resin layer. With respect to the cured body of the insulating resin layer, the density was measured by an underwater substitution method, the specific heat was measured by DSC (differential scanning calorimetry), and the thermal diffusivity was measured by a laser flash method.
Then, for each of the insulating resin layers obtained in Example 1 and Comparative Examples 1 and 2, the thermal conductivity in the thickness direction was calculated from the following equation.
Thermal conductivity (W / m · K) = density (kg / m ³ ) × specific heat (kJ / kg · K) × thermal diffusivity (m ² / S) × 1000

(With or without void)
For each of the insulating resin layers obtained in Example 1 and Comparative Examples 1 and 2, whether or not voids were present in the insulating resin layers was observed with a scanning electron microscope. Specifically, it measured by the following procedures. First, the insulating resin layer was cut with a microtome to prepare a cross section. Next, a cross-sectional photograph of the insulating resin layer magnified several thousand times was taken with a scanning electron microscope to evaluate the presence or absence of voids.
○: No void ×: With void

(Uniformity of film thickness)
The film thickness of each of the insulating resin layers obtained in Example 1 and Comparative Examples 1 and 2 was observed with a scanning electron microscope. Specifically, it measured by the following procedures. First, the insulating resin layer was cut with a microtome to prepare a cross section. Next, a cross-sectional photograph of the insulating resin layer, which was enlarged several thousand times, was taken with a scanning electron microscope to evaluate whether or not the film thickness of the insulating resin layer was uniform.
：: The film thickness is satisfactorily uniform.
X: The film thickness varies.

When the insulation resistance under continuous humidity was evaluated using the semiconductor device of Example 1 under the conditions of a temperature of 85 ° C., a humidity of 85%, and an AC applied voltage of 1.5 kV, it was 300 Ω or less before the resistance value became 10 ⁶ Ω or less. It took more than an hour. On the other hand, when the above-described continuous wet insulation resistance was evaluated using the semiconductor devices of Comparative Examples 1 and 2, the failure occurred in a much shorter time than the semiconductor device of Example 1. In other words, the semiconductor device of Example 1 was excellent in terms of insulation reliability, while the semiconductor devices of Comparative Examples 1 and 2 each satisfied the required level in terms of insulation reliability. Was not.

  This application claims priority based on Japanese Patent Application No. 2014-137234 filed on Jul. 2, 2014, and incorporates the entire disclosure thereof.

Claims (14)

A metal plate,
A semiconductor chip provided on the first surface side of the metal plate;
An insulating resin layer joined to a second surface of the metal plate opposite to the first surface;
A mold resin sealing the semiconductor chip and the metal plate,
With
The insulating resin layer includes secondary agglomerated particles in which primary particles of flaky boron nitride are isotropically agglomerated,
The content of the secondary aggregated particles is 65% by mass or more and 90% by mass or less based on the entire insulating resin layer,
When the thickness of the insulating resin layer is D and the average particle diameter of the secondary aggregated particles is d,
A semiconductor device having d / D of 0.05 or more and 0.8 or less.   2. The semiconductor device according to claim 1, wherein d / D is less than 0.5.   The semiconductor device according to claim 1, wherein a mounting floor area of the semiconductor device is 10 × 10 mm or more and 100 × 100 mm or less. Three or more semiconductor chips are provided on the first surface side of one of the metal plates;
4. The semiconductor device according to claim 1, wherein the mold resin collectively seals the three or more semiconductor chips. 5.   The semiconductor device according to claim 1, further comprising a metal layer having one surface bonded to a surface of the insulating resin layer opposite to the metal plate.   6. The semiconductor device according to claim 5, wherein in a plan view, an outline of the one surface of the metal layer and an outline of a surface of the insulating resin layer opposite to the metal plate overlap with each other. 7.   7. The semiconductor device according to claim 5, wherein the entire surface of the metal layer on the side opposite to the one surface is exposed from the mold resin. A heat radiation grease layer formed on a surface of the metal layer opposite to the one surface,
Cooling fins fixed to the opposite surface of the metal layer via the heat radiation grease layer,
The semiconductor device according to claim 5, further comprising: A second metal plate disposed opposite to the metal plate with the semiconductor chip interposed therebetween;
A second insulating resin layer,
Further comprising
The semiconductor chip is provided on one surface side of the second metal plate, and the semiconductor chip is sandwiched between the metal plate and the second metal plate,
The second insulating resin layer is bonded to a surface of the second metal plate opposite to the semiconductor chip,
The semiconductor device according to claim 1, wherein the mold resin seals the second metal plate.   The semiconductor device according to claim 9, further comprising a second metal layer having one surface joined to a surface of the second insulating resin layer opposite to the second metal plate.   The semiconductor device according to claim 10, wherein an entire surface of the second metal layer on a surface opposite to the one surface is exposed from the mold resin. A second heat radiation grease layer formed on a surface of the second metal layer opposite to the one surface;
A second cooling fin fixed to the opposite surface of the second metal layer via the second heat radiation grease layer;
The semiconductor device according to claim 10, further comprising: A second metal plate disposed opposite to the metal plate with the semiconductor chip interposed therebetween;
A second insulating resin layer,
Further comprising
The semiconductor chip is provided on one surface side of the second metal plate, and the semiconductor chip is sandwiched between the metal plate and the second metal plate,
The second insulating resin layer is bonded to a surface of the second metal plate opposite to the semiconductor chip,
The mold resin seals the second metal plate,
The semiconductor device is
A second metal layer having one surface joined to a surface of the second insulating resin layer opposite to the second metal plate;
A second heat radiation grease layer formed on a surface of the second metal layer opposite to the one surface;
A second cooling fin fixed to the opposite surface of the second metal layer via the second heat radiation grease layer;
Further comprising
The semiconductor device according to claim 8, wherein the metal layer, the second metal layer, the cooling fin, and the second cooling fin are made of the same metal. A second metal plate disposed opposite to the metal plate with the semiconductor chip interposed therebetween;
A second insulating resin layer,
Further comprising
The semiconductor chip is provided on one surface side of the second metal plate, and the semiconductor chip is sandwiched between the metal plate and the second metal plate,
The second insulating resin layer is bonded to a surface of the second metal plate opposite to the semiconductor chip,
The mold resin seals the second metal plate,
The semiconductor device is
A second metal layer having one surface joined to a surface of the second insulating resin layer opposite to the second metal plate;
A second heat radiation grease layer formed on a surface of the second metal layer opposite to the one surface;
A second cooling fin fixed to the opposite surface of the second metal layer via the second heat radiation grease layer;
Further comprising
9. The semiconductor device according to claim 8, wherein the metal layer, the second metal layer, the cooling fin, and the second cooling fin are made of aluminum.

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