WO2015196772A1 - 一种基于自定时振荡环的工艺角检测电路 - Google Patents

一种基于自定时振荡环的工艺角检测电路 Download PDF

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WO2015196772A1
WO2015196772A1 PCT/CN2014/095074 CN2014095074W WO2015196772A1 WO 2015196772 A1 WO2015196772 A1 WO 2015196772A1 CN 2014095074 W CN2014095074 W CN 2014095074W WO 2015196772 A1 WO2015196772 A1 WO 2015196772A1
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input
reset
self
output
stage
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单伟伟
时龙兴
田朝轩
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Southeast University
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2882—Testing timing characteristics
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G01R31/2837—Characterising or performance testing, e.g. of frequency response
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators

Definitions

  • the invention relates to a process angle detecting circuit based on a self-timed oscillating ring. All circuit components can be composed of MOS transistors for detecting the process angle of the manufactured integrated circuit chip, and belong to the field of integrated circuit design.
  • Global bias describes the difference in device parameters in different chips, while device parameters within the same chip are considered identical. Simulations at different process angles are often used to assess the effects of global bias. Each process corner is in an extreme case, and its device parameters are essentially offset from their typical values. For the Fast Corner, all process fluctuations increase the drive current of the transistor and therefore the fastest. But for the slowest corner, the device speed is slowed by process variations.
  • the effect of process variation on the timing of different chips is generally normally distributed (average ⁇ global , variance is ⁇ global ), and the fastest and slowest process angles are generally in multiples of ⁇ global (eg 3 or 6 times ⁇ ) or Performance statistics derived from the segmentation test are defined.
  • process parameters doping concentration, oxide thickness, etc.
  • p-FET p-channel transistor
  • n-FET n-channel transistor
  • the general process library provides five process angles: FF, FNSP, TT, SNFP, and SS.
  • FF indicates that the circuit consists of the fastest p-FET and the fastest n-FET;
  • TT indicates that the circuit consists of a typical p-FET and a typical n-FET;
  • SS indicates that the circuit consists of the slowest p-FET and the slowest n-FET;
  • FNSP And SNFP belong to the cross-process angle, FNSP means that the circuit consists of the slowest p-FET and the fastest n-FET;
  • SNFP means that the circuit consists of the fastest p-FET and the slowest n-FET;
  • Cross-cutting angles are generally critical in analog circuits, but are secondary in digital circuits.
  • the effect of local deviation on the path delay can be characterized by the same logic gate with n flip times (rise or fall time) as t gate and corresponding standard deviation ⁇ t,gate .
  • the path delay t d n ⁇ t gate increases linearly with n, but the standard deviation ⁇ t,d is proportional to the square root of n, so the relative deviation of the path delay ⁇ t,d /t d and the reciprocal of the square root of n In direct proportion. Therefore, the absolute deviation of the path delay increases with the path growth, but the relative deviation decreases with the path growth.
  • each chip may be at a different process angle, and there is no corresponding process angle detection means to know the process angle of the chip.
  • the ring oscillator is the most common structure for detecting the process angle. The principle is to count the number of oscillations of the ring oscillator in a certain period of time. When the process angle of the chip is better, the delay of the device is smaller, and the ring oscillator is The number of oscillations in the same time is high; when the process angle of the chip is not good, the number of oscillations is low, so the counting result of the number of oscillations can reflect the process angle at which the chip is located.
  • the conventional ring oscillator generally adopts a logic structure in which an odd number of inverters are connected end to end in a loop, and an oscillation waveform is generated by using the delay of the inverter itself and its inversion function.
  • This kind of ring oscillator based on inverter chain the change of the process angle of the circuit will change the oscillation frequency, but the voltage and temperature changes will also affect the oscillation frequency.
  • the effect of voltage fluctuations can be eliminated by powering the circuit with an output voltage stable and accurate LDO, the effect of temperature fluctuations on the ring oscillator oscillation frequency cannot be eliminated.
  • the process variation in the integrated circuit manufacturing process has an increasing influence on the chip timing.
  • measures need to be taken to suppress the influence of the process deviation, which first needs to detect the chip is located.
  • Process angle The object of the present invention is to provide a process angle detecting circuit based on a self-timed oscillating ring, which can accurately detect the specific process angle after the chip is manufactured, and provides a reliable basis for suppressing the influence of process deviation.
  • the process angle detecting circuit based on the self-timed oscillating ring of the present invention comprises a reset circuit, a self-timed oscillating ring and a counting module.
  • the self-timed oscillation ring can reflect the good or bad process angle of the chip. When the process angle of the chip is better, the self-timed oscillation ring has higher oscillation times in the same time; when the chip process angle is not good, The number of oscillations is low, so the number of oscillations can reflect the process angle at which the chip is located.
  • the counting module is used to count the number of oscillations of the self-timed oscillation ring, and the counting result of the counting module reflects the quality of the process angle of the chip.
  • the reset circuit is used to reset the counting module after a detection is completed for re-detection; at the same time, the reset circuit can also set the initial state of the self-timed oscillation ring to ensure that it can start.
  • the reset circuit is composed of two flip-flops DR1, DR2, a two-input OR gate OR1, a two-input NOR gate NOR1 and a two-input NAND gate NAND1; the data input terminal D of the flip-flop DR1 is connected to the system clock eight
  • the frequency dividing signal CLK8 the clock terminal is connected to the system clock CLK, the data output terminal Q output signal is CLK8_1, the data input terminal D of the flip-flop DR2 is connected, the output signal of the inverted data output terminal Q is CLK8_1n;
  • the clock end of the flip-flop DR2 Connect the system clock CLK, the data output terminal Q output signal is CLK8_2, connect one input of the two input OR gate OR1; the other input of the two input OR gate OR1 connects the system clock eight-divided signal CLK8; two input OR gate OR1
  • the output signal is the reset signal RSTn of the counting module; the two input terminals of the two input NOR gate NOR1 are respectively
  • the self-timed oscillating ring is composed of m two-input Miller units and an inverter and a two-input AND gate AND1, where m is a positive integer greater than or equal to 3; the self-timed oscillating ring formed is m-level, each The stages are composed of a Miller unit and an inverter; the output of the inverter in each stage is connected to an input of the Miller unit of the stage The input end of the inverter is connected to the output of the lower-stage Miller unit, and the input of the inverter in the m-th stage is connected to the output of the first-stage Miller unit; The other input of the unit is connected to the output of the gate AND1; the other input of the remaining Miller unit is connected to the output of the previous stage Miller unit; the second input is connected to an input of the gate AND1 The output end of the Miller unit in the mth stage, and the other input end is connected to the output terminal Q of the flip-flop DR1; the output signal of the Miller unit in the first stage is used
  • the counting module is composed of n flip-flops with reset terminals, wherein n is a positive integer greater than or equal to 3; the counting module is composed of n levels, each stage is a flip-flop; all the clock ends of the flip-flops are connected To the output signal OSC_OUT of the self-timed oscillation loop, the reset terminal is connected to the reset signal RSTn outputted by the reset circuit; the data input terminal of the first-stage flip-flop is connected to the power supply VDD, and the data input terminal of each subsequent flip-flop is Connect to the data output of the previous stage trigger.
  • the number of 1s in the data output by the n-level flip-flop in the counting module indicates the number of times the self-timed oscillation ring oscillates.
  • the invention provides a process angle detecting circuit based on a self-timed oscillating ring, and adopts a self-timed oscillating ring composed of a Miller unit and an inverter as a ring oscillator reflecting the good or bad process angle. Due to the Charlie effect, the delay of the Miller unit compensates for temperature changes, so the self-timed oscillation ring is not sensitive to temperature changes. The so-called Charlie effect means that since the output of the Miller unit changes when the two inputs are the same, the flipping of the output requires one flip of the two inputs and the flipping of the two inputs of the Miller unit. The shorter the interval, the greater the propagation delay; conversely, the longer the interval between two input flips, the smaller the propagation delay.
  • the process angle detecting circuit based on the self-timed oscillating ring can accurately detect the process angle after the chip is manufactured, thereby providing a basis for suppressing the influence of the process deviation, thereby improving the stability of the chip operation.
  • the invention has the following beneficial effects:
  • the invention is all constructed by a digital CMOS circuit. Compared with the process angle detecting circuit using the analog device, the circuit structure of the invention is simple, the design process is friendly to the EDA tool, and the design difficulty is low.
  • the invention is insensitive to the influence of temperature fluctuations when the working voltage is stable, and is sensitive to the influence of process deviation. Compared with the process angle detecting circuit using the inverter chain as the oscillation ring, the present invention can more accurately distinguish the process angle at which the chip is located.
  • the present invention has a reset mechanism. After a test is completed, the self-timed oscillating ring and the counting module can be reset and re-detected.
  • the self-timed oscillation ring has an enable terminal, which can be configured when the process angle detection is not required, so that the self-timed oscillation ring stops oscillating and reduces the power consumption of the circuit.
  • FIG. 1 is a block diagram of a circuit structure of the present invention
  • Figure 3 is a circuit diagram of a Miller unit in the present invention.
  • FIG. 4 is a circuit diagram of a self-timed oscillation ring in the present invention.
  • FIG. 5 is a diagram showing the HSPICE simulation results of the circuit in the present invention under the conditions of SS process angle, 1.8V, and 125°C;
  • the self-timed oscillation ring based process angle detecting circuit of the present invention comprises a reset circuit, a self-timed oscillation ring and a counting module.
  • the self-timed oscillating ring includes at least a 3-stage Miller unit and an inverter
  • the counting module includes at least three flip-flops. Under different process angles, the number of oscillations of the self-timed oscillation ring is different in the same time, and the number of triggers in the counting module should be greater than the maximum number of oscillations of the self-timed oscillation ring during the oscillation.
  • the detailed implementation is as follows:
  • the reset circuit is as shown in FIG. 1 and is composed of two flip-flops DR1, DR2, a two-input OR gate OR1, a two-input NOR gate NOR1 and a two-input NAND gate NAND1;
  • the data input terminal D of the flip-flop DR1 Connect the system clock's eight-divide signal CLK8, the clock terminal is connected to the system clock CLK, the data output terminal Q output signal is CLK8_1, the data input terminal D of the flip-flop DR2 is connected, and the output signal of the inverted data output terminal Q is CLK8_1n;
  • the clock terminal of the device DR2 is connected to the system clock CLK, the output signal of the data output terminal Q is CLK8_2, and is connected to one input terminal of the two-input OR gate; the other input terminal of the two-input OR gate is connected to the eight-divided signal CLK8 of the system clock;
  • the output signal of the two input OR gate OR1 is the reset signal RSTn of the
  • the self-timed oscillating ring is composed of nine two-input Miller units and an inverter and a two-input AND gate AND1 as shown in Figure 4.
  • the self-timed oscillating ring is composed of 9 stages, each of which is composed of a Miller.
  • the output of the inverter in each stage is connected to one input of the Miller unit of the stage, and the input of the inverter is connected to the output of the Miller unit of the next stage, ninth
  • the input of the inverter in the stage is connected to the output of the first stage Miller unit; the input of the first stage Miller unit is connected to the output of the two input AND gate AND1, and the other of the remaining Miller units
  • the input end is connected to the output end of the previous stage Miller unit, one input end of the two input AND gate AND1 is connected to the output end of the Miller unit in the ninth stage, and the other input end is connected with the output end of the trigger DR1.
  • the output signal of the Miller unit in the first stage is used as the output signal OSC_OUT of the self-timed oscillation ring.
  • the counting module consists of 32 flip-flops with reset terminals connected in series; the counting module is composed of 32 stages, each stage is a flip-flop; the clock terminals of all the flip-flops are connected to the oscillation output signal OSC_OUT of the self-timed oscillation ring, reset The terminals are connected to the reset signal RSTn outputted by the reset circuit; the data input terminal of the first stage flip-flop is connected to the high level (power supply VDD), and the data input end of each subsequent flip-flop is connected to the previous stage trigger The data output of the device.
  • the Miller unit in each stage of the self-timed oscillating ring has a reset end reset and a set end set. As shown in FIG. 2, the reset end reset clears the output value of the Miller unit, and sets the set end pair. The output value of the Miller unit is set to set the initial state of the self-timed oscillation ring.
  • a Miller cell with a reset terminal reset and a set terminal set is composed of three NMOS transistors (MP1, MP2, MP3), three PMOS transistors (MN1, MN2, MN3), and two inverters (INV1, INV2). It has two input terminals A and B, one output terminal Z, as shown in FIG. 3; the source of MP1 is connected to the power supply VDD, the gate is connected to the input signal A, the drain is connected to the source of MP2, and the gate of the MP2 is connected to the input signal B.
  • the drain is connected to the drain of MN1; the gate of MN1 is connected to the input signal A, the source is connected to the drain of MN2; the gate of MN2 is connected to the input signal B, the source is grounded to GND; the source of MP3 is connected to the power supply VDD, and the gate is connected to the signal.
  • the drain is connected to the node Zn whose drain is connected to the drain of MN1; the drain of MN3 is also connected to Zn, the gate is connected to reset signal reset, the source is grounded to GND; the input terminal of inverter INV1 is connected to Zn, and its output is The terminal is the output terminal Z of the Miller unit; at the same time, Z is connected to the input terminal of the inverter INV2, and the output terminal of the INV2 is also connected to the Zn; the width and length ratio of the PMOS in the MP1, MP2, MP3 and INV1 are the same, MN1.
  • the width-to-length ratio of the NMOS in MN2, MN3, and INV1 is also the same, but the aspect ratio of the PMOS and the NMOS transistor in INV2 is at least twice as large as the width ratio of the PMOS and NMOS transistors in INV1, respectively.
  • the initial output state of the first eight-stage Miller unit in the self-timed oscillation ring before oscillation is set to 0, and the initial output state of the ninth-stage Miller unit before oscillation is set to 1; the placement of the first eight-stage Miller unit
  • the bit end set is connected to the output signal set0 of the NAND1, the reset end reset is connected to the ground; the set end set of the ninth and Miller unit is connected to the power supply VDD, and the reset end reset is connected to the output signal set1 of the NOR1.
  • the number of 1 in the data outputted by the 32-level flip-flop of the counting module indicates the number of times of self-timed oscillation ring oscillation; the counting result of the counting module reflects the quality of the process angle of the chip.
  • the HSPICE simulation results of the process angle detection module are shown in Figure 5.
  • the process used in this circuit is SMIC 0.18 ⁇ m CMOS process, and the corresponding PVT conditions are SS process angle, 1.8V, 125°C.
  • CLK is the system clock
  • OSC_out is the output of the self-timed oscillating ring
  • Rstn_osc is the counting module reset signal
  • Counter[31:0] is the output of the 32-level flip-flop in the counting module.
  • the oscillation ring has an oscillation output while the enable signal CLK8_1 of the self-timed oscillation ring is high, and does not oscillate when CLK8_1 is low; the reset signal Rstn_osc is the value of CLK8 and CLK8_2 phase or later. It is valid in the middle of two clock cycles when CLK8_1 is low; when the CLK8_1 is high, the oscillation ring oscillates 15 times in total, and the output value of the counting module Counter[31:0] is 7fff, including 15 ones. The number of oscillations is the same as that of the oscillation ring.
  • the process angle detection module is simulated at different process angles and different temperatures, and the ring oscillator count results are shown in Table 1. It can be seen from Table 1 that when the chip is at the SS process angle, the oscillation frequency of the ring oscillator ranges from 15 to 17; when the chip is at the TT process angle, the oscillation frequency of the ring oscillator ranges from 19 to 21; At the SS process angle, the ring oscillator oscillates in the range of 24 to 27. Under different process angles, the counting results do not overlap when the temperature changes.
  • the 125 °C in Table 1 corresponds to a very extreme case, and the process angle detection occurs after the chip is powered on and before starting to work. At this time, the temperature of the chip can be regarded as the same as the ambient temperature, and the extreme situation is not reached. Therefore, when judging the process angle based on the counting result of the oscillation ring, it is possible to consider only the counting result within the range of the normal ambient temperature variation, that is, between -25 ° C and 50 ° C. The specific judgment values are shown in Table 2.

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Abstract

一种基于自定时振荡环的工艺角检测电路，包括复位电路（1）、自定时振荡环（2）和计数模块（3），所述复位电路（1）由两个触发器和一个二输入或门构成；所述自定时振荡环（2）由m个二输入密勒单元和反相器以及一个二输入与门构成，其中m是大于等于3的正整数；所述计数模块（3）由n个带复位端的触发器串联构成，其中n是大于等于3的正整数。该电路可以用来检测制造完成的集成电路芯片所处的工艺角，通过自定时振荡环（2）的振荡次数来反映芯片所处的工艺角。在芯片流片前先通过仿真得出自定时振荡环（2）在不同工艺角下的振荡次数，在流片后就可以根据实测的振荡次数来判断芯片处于何工艺角。

Description

一种基于自定时振荡环的工艺角检测电路 技术领域
本发明涉及一种基于自定时振荡环的工艺角检测电路，所有电路元件都可由MOS晶体管构成，用于检测制造完成的集成电路芯片所处的工艺角，属于集成电路设计领域。
背景技术
保证电路的“时序安全”电路中时序路径的时延变化不引起同步失效是确保电路可靠工作的基本条件之一。然而，随着制造工艺持续向纳米尺度推进，工艺、电压、温度(Process-Voltage-Temperature,PVT)等因素的偏差对集成电路时序的影响越来越大，确保时序安全变得愈发困难和代价高昂，使其成为集成电路领域重要的研究课题。为了抑制PVT等因素的偏差对芯片时序的影响，需要对芯片工作时所处的PVT条件进行监测，根据监测到的PVT信息对芯片做相应的调节，从而保证芯片时序始终正确。
在所有影响芯片时序的因素中，工艺偏差是造成时序波动的主要原因之一。2011年国际半导体技术路线图(International Technology Roadmap for Semiconductors,ITRS)中说道：“由于特征尺寸的缩小，设计人员所面临的最关键问题之一是与设计相关的参数的波动性在持续增加，这是由于制造参数的偏差和原子的固有特性影响了沟道掺杂”。工艺偏差由制造工艺的不一致性引起，分为全局偏差和局部偏差。
对于全局偏差，氧化层厚度、掺杂浓度等器件参数的变化对同一芯片中的所有晶体管来说是相同的。不同晶圆或不同批次中的芯片间工艺偏差都属于这一类。相反的，对于局部偏差——也称失配或随机不相关偏差——同一芯片中的每个晶体管所受的影响都不同。
全局偏差描述不同芯片中的器件参数差异，而同一芯片内的器件参数视为相同。通常用不同工艺角下的仿真来评估全局偏差的影响。每个工艺角都处于一种极端的情况，其器件参数基本上都和它们的典型值有所偏差。对于最快工艺角(Fast Corner)，所有的工艺波动都是增加晶体管的驱动电流的，因此速度最快。但是对于最慢工艺角(Slow Corner)，器件速度都被工艺偏差放慢。
工艺偏差对不同芯片时序的影响一般是呈正态分布(均值为μglobal，方差为σglobal)，最快和最慢工艺角一般是按σglobal的倍数(如3倍或6倍σ)或分段测试得出的性能统 计数据进行定义的。对于分段测试，工艺参数(掺杂浓度、氧化层厚度等)被人为地设定为偏向于制造最慢或最快芯片。除了最快和最慢工艺角，还有一些交叉工艺角，如由最快p沟道晶体管(p-FET)和最慢n沟道晶体管(n-FET)组成，或反之。一般工艺库提供的有FF、FNSP、TT、SNFP、SS五种工艺角。FF表示电路由最快p-FET和最快n-FET组成；TT表示电路由典型p-FET和典型n-FET组成；SS表示电路由最慢p-FET和最慢n-FET组成；FNSP和SNFP属于交叉工艺角，FNSP表示电路由最慢p-FET和最快n-FET组成；SNFP表示电路由最快p-FET和最慢n-FET组成；。交叉工艺角一般在模拟电路中比较关键，但是在数字电路中则是次要的。
局部偏差正随着CMOS工艺尺寸的缩小而增加。晶体管尺寸的减小会使阈值电压的标准差σVT和电流因子σk/k(k＝μCoxW/L)增加，因为它们与有源区面积的平方根倒数成正比。
局部偏差对路径延时的影响可以用n个翻转时间(上升或下降时间)为tgate、对应标准方差为σt,gate的相同逻辑门来进行刻画。路径延时td＝n×tgate随着n线性增加，但是标准方差σt,d与n的平方根成正比，因此路径延时的相对偏差σt,d/td与n的平方根的倒数成正比。所以路径延时的绝对偏差随路径增长而增加，但是相对偏差则随路径增长减小。
随着工艺制程的演进，在先进工艺下工艺偏差对芯片时序的影响越来越严重。而在芯片制造完成后，每一块芯片可能都处于不同的工艺角，没有相应的工艺角检测手段无法获知芯片具体所处的工艺角。环形振荡器是检测工艺角的最常用结构，其原理是对环形振荡器在一定时间内的振荡次数进行计数，当芯片所处工艺角比较好时，器件的延时较小，环形振荡器在相同时间内的振荡次数较高；而当芯片工艺角情况不好时，振荡次数较低，所以振荡次数的计数结果可以反映芯片所处的工艺角。
传统的环形振荡器一般采用的逻辑结构为奇数个反相器首尾相连成环，利用反相器自身的延时和其反相功能产生振荡波形。这种基于反相器链的环形振荡器，其电路所处工艺角的变化会改变振荡频率，但是电压和温度的变化也会对振荡频率产生影响。虽然可以通过采用输出电压稳定精确的LDO对电路进行供电来消除电压波动的影响，但是温度波动对环形振荡器振荡频率的影响无法消除。通过HSPICE仿真可以发现在不同的工艺角下，环形振荡器的计数结果存在交叠的情况，即在两个工艺角下，当较差的工艺 角处于低温而较好的工艺角处于高温条件下时，计数范围发生重合，通过计数结果无法准确区分芯片所处的工艺角。
发明内容
发明目的：目前集成电路制造过程中工艺偏差对芯片时序的影响越来越大，为了降低工艺偏差对芯片时序的影响，需要采取措施抑制工艺偏差的影响，而这首先需要检测出芯片所处的工艺角。本发明的目的就在于提供一种基于自定时振荡环的工艺角检测电路，它可以较为准确的检测出芯片制造完成后具体所处的工艺角，为抑制工艺偏差影响提供可靠的依据。
技术方案：本发明所述的基于自定时振荡环的工艺角检测电路，包括复位电路、自定时振荡环和计数模块。自定时振荡环可以反映出芯片所处工艺角的好坏，当芯片所处工艺角比较好时，自定时振荡环在相同时间内的振荡次数较高；而当芯片工艺角情况不好时，振荡次数较低，所以振荡次数可以反映芯片所处的工艺角。计数模块就是用来对自定时振荡环的振荡次数进行计数，计数模块的计数结果反映了芯片所处工艺角情况的好坏。而复位电路则用来在一次检测完成后对计数模块进行复位，以便进行再次检测；同时复位电路还能设置自定时振荡环的初始状态，保证其能够起振。
所述复位电路由两个触发器DR1、DR2、一个二输入或门OR1、一个二输入或非门NOR1和一个二输入与非门NAND1构成；触发器DR1的数据输入端D连接系统时钟的八分频信号CLK8，时钟端连接系统时钟CLK，数据输出端Q输出信号为CLK8_1，连接触发器DR2的数据输入端D，其反相数据输出端Q的输出信号为CLK8_1n；触发器DR2的时钟端连接系统时钟CLK，数据输出端Q输出信号为CLK8_2，连接二输入或门OR1的一个输入端；二输入或门OR1的另一个输入端连接系统时钟的八分频信号CLK8；二输入或门OR1的输出信号就是计数模块的复位信号RSTn；二输入或非门NOR1的两个输入端分别连接至信号CLK8_1和地，其输出信号为set1；二输入与非门NAND1的两个输入端分别连接至电源VDD和信号CLK8_1n，其输出信号为set0；
所述自定时振荡环由m个二输入密勒单元和反相器以及一个二输入与门AND1构成，其中m是大于等于3的正整数；所构成的自定时振荡环为m级，每一级都由一个密勒单元和一个反相器组成；每一级中反相器的输出连接到该级密勒单元的一个输入 端，反相器的输入端则和下一级密勒单元的输出端相连，第m级中反相器的输入端则和第一级密勒单元的输出端相连；第一级中密勒单元的另一个输入端和二输入与门AND1的输出端相连；其余密勒单元的另一个输入端则和前一级密勒单元的输出端相连；二输入与门AND1的一个输入端连接到第m级中密勒单元的输出端，另一个输入端则和触发器DR1的输出端Q相连；第一级中密勒单元的输出信号作为自定时振荡环的输出信号OSC_OUT；
所述计数模块由n个带复位端的触发器串联构成，其中n是大于等于3的正整数；所构成的计数模块为n级，每一级为一个触发器；所有触发器的时钟端都连接到自定时振荡环的输出信号OSC_OUT，复位端都连接到复位电路输出的复位信号RSTn；第一级触发器的数据输入端连接到电源VDD，其后的每一级触发器的数据输入端都连接到前一级触发器的数据输出端。
计数模块中n级触发器输出的数据中1的个数就表示自定时振荡环振荡的次数。
本发明提供了一种基于自定时振荡环的工艺角检测电路，采用由密勒单元和反相器构成的自定时振荡环作为反映工艺角好坏的环形振荡器。由于受到Charlie效应的影响，密勒单元的延时对温度变化有补偿作用，所以自定时振荡环对温度变化不敏感。所谓Charlie效应是指，由于密勒单元的输出在两个输入相同时才会发生改变，所以输出端的翻转需要两个输入端分别发生一次翻转，而密勒单元的两个输入端发生翻转的时间间隔越短，其传播延时越大；反之，两个输入端发生翻转的时间间隔越长，则传播延时越小。在自定时振荡环中，当由于温度的升高使某一级密勒单元的延时增大，其输出端增加的延时导致后一级密勒单元的两个输入端翻转的时间间隔增大，所以后一级密勒单元的传播延时变小，因此前后两级的延时会相互补偿，整个振荡环的延时会相对维持稳定。所以基于自定时振荡环的工艺角检测电路可以较为准确的检测出芯片制造完成后所处的工艺角，从而为抑制工艺偏差的影响提供依据，进而提高芯片工作的稳定性。
本发明与现有技术相比，其有益效果是：
1、本发明全部采用数字CMOS电路构成，相比于采用模拟器件的工艺角检测电路，本发明的电路结构简单，设计过程对EDA工具友好，设计难度较低。
2、本发明在工作电压稳定时，对温度波动的影响不敏感，而对工艺偏差的影响很敏感， 相比于采用反相器链作为振荡环的工艺角检测电路，本发明能够较为准确的区分芯片所处的工艺角。
3、本发明具有复位机制，在一次检测完成后，可以对自定时振荡环和计数模块进行复位，重新进行检测。另外自定时振荡环具有使能端，可以在不需要进行工艺角检测时配置使能端，使自定时振荡环停止振荡，降低电路功耗。
附图说明
图1为本发明的电路结构框图；
图2为本发明中带有复位端和置位端的密勒单元的逻辑符号；
图3为本发明中密勒单元的电路图；
图4为本发明中自定时振荡环的电路图；
图5为本发明中的电路在SS工艺角、1.8V、125℃条件下的HSPICE仿真结果图；
具体实施方式
下面对本发明技术方案进行详细说明，但是本发明的保护范围不局限于所述实施例。
实施例1：如图1所示，本发明所述的基于自定时振荡环的工艺角检测电路，包括复位电路、自定时振荡环和计数模块。自定时振荡环至少包括3级密勒单元与反相器，计数模块至少包括3个触发器。在不同的工艺角下，相同时间内自定时振荡环的振荡次数是不同的，计数模块中触发器的个数应大于自定时振荡环在振荡期间的最大振荡次数。当自定时振荡环包括的密勒单元与反相器的级数为9，计数模块包括的触发器级数为32时，详细的实施方案如下：
复位电路如图1中所示，由两个触发器DR1、DR2、一个二输入或门OR1、一个二输入或非门NOR1和一个二输入与非门NAND1构成；触发器DR1的数据输入端D连接系统时钟的八分频信号CLK8，时钟端连接系统时钟CLK，数据输出端Q输出信号为CLK8_1，连接触发器DR2的数据输入端D，其反相数据输出端Q的输出信号为CLK8_1n；触发器DR2的时钟端连接系统时钟CLK，数据输出端Q输出信号为CLK8_2，连接二输入或门OR1的一个输入端；二输入或门OR1的另一个输入端连接系统时钟的八分频信号CLK8；二输入或门OR1的输出信号就是计数模块的复位信号RSTn；二输入或非门NOR1的两个输入端分别连接至CLK8_1和地，其输出信号为set1；二输入与 非门NAND1的两个输入端分别连接至电源VDD和CLK8_1n，其输出信号为set0。
自定时振荡环如图4所示，由9个二输入密勒单元和反相器以及一个二输入与门AND1构成；所构成的自定时振荡环为9级，每一级都由一个密勒单元和一个反相器组成；每一级中反相器的输出连接到该级密勒单元的一个输入端，反相器的输入端则和下一级密勒单元的输出端相连，第九级中反相器的输入端则和第一级密勒单元的输出端相连；第一级密勒单元的输入端则和二输入与门AND1的输出端相连，其余级密勒单元的另一个输入端则和前一级密勒单元的输出端相连，二输入与门AND1的一个输入端连接到第九级中密勒单元的输出端，另一个输入端则和触发器DR1的输出端Q相连；第一级中密勒单元的输出信号作为自定时振荡环的输出信号OSC_OUT。
计数模块由32个带复位端的触发器串联构成；所构成的计数模块为32级，每一级为一个触发器；所有触发器的时钟端都连接到自定时振荡环的振荡输出信号OSC_OUT，复位端都连接到复位电路输出的复位信号RSTn；第一级触发器的数据输入端连接到高电平(电源VDD)，其后的每一级触发器的数据输入端都连接到前一级触发器的数据输出端。
自定时振荡环的每一级中的密勒单元均带有复位端reset与置位端set，如图2所示，复位端reset对密勒单元的输出值进行清零，置位端set对密勒单元的输出值进行置位，从而设定自定时振荡环的初始状态。
带复位端reset与置位端set的密勒单元由三个NMOS管(MP1、MP2、MP3)、三个PMOS管(MN1、MN2、MN3)和两个反相器(INV1、INV2)构成，其具有两个输入端A和B，一个输出端Z，如图3所示；MP1的源极接电源VDD，栅极接输入信号A，漏极接MP2源极；MP2栅极接输入信号B，漏极接MN1漏极；MN1栅极接输入信号A，源极接MN2漏极；MN2栅极接输入信号B，源极接地GND；MP3的源极接电源VDD，栅极接置位信号set，漏极接MP2漏极与MN1漏极相连的节点Zn；MN3的漏极也连接到Zn，栅极接复位信号reset，源极接地GND；反相器INV1的输入端接Zn，其输出端就是密勒单元的输出端Z；同时Z连接到反相器INV2的输入端，INV2的输出端也连接到Zn；MP1、MP2、MP3与INV1中的PMOS的宽长比都相同，MN1、MN2、MN3与INV1中的NMOS的宽长比也相同，但是INV2中的PMOS与NMOS管的宽长比都分别至少比INV1中的PMOS、NMOS管宽长比小一倍。
自定时振荡环中的前八级密勒单元在振荡前的初始输出状态被设置成0，第九级密勒单元在振荡前的初始输出状态被设置成1；前八级密勒单元的置位端set都连接至NAND1的输出信号set0，复位端reset都连接至地；第九及密勒单元的置位端set与电源VDD相连，复位端reset与NOR1的输出信号set1相连。
计数模块的32级触发器输出的数据中1的个数就表示自定时振荡环振荡的次数；计数模块的计数结果反映了芯片所处工艺角情况的好坏。
基于自定时振荡环的工艺角检测电路设计完成后，利用HSPISE工具进行仿真。工艺角检测模块的HSPICE仿真结果如图5所示，该电路所采用的工艺为SMIC 0.18μm CMOS工艺，对应的PVT条件为SS工艺角、1.8V、125℃。图5中CLK为系统时钟，OSC_out为自定时振荡环的输出，Rstn_osc为计数模块复位信号，Counter[31:0]为计数模块中32级触发器的输出。从图中可以看出，在自定时振荡环的使能信号CLK8_1为高电平期间，振荡环有振荡输出，而CLK8_1为低电平时不振荡；复位信号Rstn_osc为CLK8和CLK8_2相或后的值，正好在CLK8_1为低电平的中间两个时钟周期有效；在CLK8_1为高电平期间振荡环共振荡了15次，计数模块的输出值Counter[31:0]为7fff，包含15个1，与振荡环的振荡次数相同。
对工艺角检测模块在不同工艺角、不同温度下仿真，得到的环形振荡器计数结果如表1所示。从表1中可以看出，当芯片处于SS工艺角时，环形振荡器的振荡次数范围为15到17；当芯片处于TT工艺角时，环形振荡器的振荡次数范围为19到21；当芯片处于SS工艺角时，环形振荡器的振荡次数范围为24到27。不同的工艺角下，温度变化时计数结果没有交叠的情况。
表1 自定时振荡环在1.8V时不同工艺角和温度下的振荡次数
Figure PCTCN2014095074-appb-000001
表1中125℃所对应的是非常极端的情况，而工艺角检测是发生在芯片上电之后、开始工作之前，此时芯片的温度可以看作和环境温度相同，并未达到极端情况。因此在根据振荡环的计数结果来判定工艺角时，可以只考虑正常的环境温度变化范围内的计数结果，即-25℃到50℃之间的情况。具体的判定值如表2所示。
表2 计数结果对应的工艺角判定方法
计数结果N 判定结果
16≤N≤17 SS工艺角
18≤N≤19 SS和TT之间的工艺角
20≤N≤21 TT工艺角
22≤N≤24 TT和FF之间的工艺角
25≤N≤27 FF工艺角
由表2可知，当计数结果为16或17时，可判定芯片处于SS工艺角；当计数结果为18或19时，可判定芯片处于SS和TT之间的工艺角；当计数结果处于20到21之间时，可判定芯片处于TT工艺角；当计数结果处于22到24之间时，可判定芯片处于TT和FF之间的工艺角；当计数结果处于25到27之间时，可判定芯片处于FF工艺角。
如上所述，尽管参照特定的优选实施例已经表示和表述了本发明，但其不得解释为对本发明自身的限制。在不脱离所附权利要求定义的本发明的精神和范围前提下，可对其在形式上和细节上做出各种变化。

Claims (4)

  1. 一种基于自定时振荡环的工艺角检测电路，包括复位电路(1)、自定时振荡环(2)和计数模块(3)，其特征在于：
    所述复位电路(1)由两个触发器DR1、DR2、一个二输入或门OR1、一个二输入或非门NOR1和一个二输入与非门NAND1构成；触发器DR1的数据输入端连接系统时钟的八分频信号CLK8，时钟端连接系统时钟CLK，数据输出端输出信号为CLK8_1，连接触发器DR2的数据输入端，其反相数据输出端的输出信号为CLK8_1n；触发器DR2的时钟端连接系统时钟CLK，数据输出端输出信号为CLK8_2，连接二输入或门OR1的一个输入端；二输入或门OR1的另一个输入端连接系统时钟的八分频信号CLK8；二输入或门OR1的输出信号就是计数模块的复位信号RSTn；二输入或非门NOR1的两个输入端分别连接至信号CLK8_1和地，其输出信号为set1；二输入与非门NAND1的两个输入端分别连接至电源VDD和信号CLK8_1n，其输出信号为set0；
    所述自定时振荡环(2)由m个二输入密勒单元和反相器以及一个二输入与门AND1构成，其中m是大于等于3的正整数；所构成的自定时振荡环为m级，每一级都由一个密勒单元和一个反相器组成；每一级中反相器的输出连接到该级密勒单元的一个输入端，反相器的输入端则和下一级密勒单元的输出端相连，第m级中反相器的输入端则和第一级密勒单元的输出端相连；第一级中密勒单元的另一个输入端和二输入与门AND1的输出端相连；其余密勒单元的另一个输入端则和前一级密勒单元的输出端相连；二输入与门AND1的一个输入端连接到第m级中密勒单元的输出端，另一个输入端则和触发器DR1的输出端Q相连；第一级中密勒单元的输出信号作为自定时振荡环的输出信号OSC_OUT；
    所述计数模块(3)由n个带复位端的触发器串联构成，其中n是大于等于3的正整数；所构成的计数模块为n级，每一级为一个触发器；所有触发器的时钟端都连接到自定时振荡环的输出信号OSC_OUT，复位端都连接到复位电路输出的复位信号RSTn；第一级触发器的数据输入端连接到电源VDD，其后的每一级触发器的数据输入端都连接到前一级触发器的数据输出端。
  2. 根据权利要求1所述的基于自定时振荡环的工艺角检测电路，其特征在于：所述自定时振荡环(2)其每一级中的密勒单元均带有复位端reset与置位端set，复位端reset对密勒单元的输出值进行清零，置位端set对密勒单元的输出值进行置位，用于设定自定时振荡环的初始状态。
  3. 根据权利要求2所述的基于自定时振荡环的工艺角检测电路，其特征在于：所述带复位端reset与置位端set的密勒单元由三个NMOS管MP1、MP2、MP3、三个PMOS管MN1、MN2、MN3和两个反相器INV1、INV2构成，其具有两个输入端A和B，一个输出端Z；NMOS管MP1的源极接电源VDD，栅极接输入信号A，漏极接NMOS管MP2源极；NMOS管MP2栅极接输入信号B，漏极接PMOS管MN1漏极；PMOS管MN1栅极接输入信号A，源极接PMOS管MN2漏极；PMOS管MN2栅极接输入信号B，源极接地GND；NMOS管MP3的源极接电源VDD，栅极接置位信号set，漏极接NMOS管MP2漏极与PMOS管MN1漏极相连的节点Zn；PMOS管MN3的漏极也连接到Zn，栅极接复位信号reset，源极接地GND；反相器INV1的输入端接Zn，其输出端就是密勒单元的输出端Z；同时Z连接到反相器INV2的输入端，反相器INV2的输出端也连接到Zn；NMOS管MP1、MP2、MP3与反相器INV1中的PMOS的宽长比都相同，PMOS管MN1、MN2、MN3与反相器INV1中的NMOS的宽长比也相同，但是反相器INV2中的PMOS与NMOS管的宽长比都分别至少比反相器INV1中的PMOS、NMOS管宽长比小一倍。
  4. 根据权利要求2所述的基于自定时振荡环的工艺角检测电路，其特征在于：所述的自定时振荡环(2)中的前m-1级密勒单元在振荡前的初始输出状态被设置成0，第m级密勒单元在振荡前的初始输出状态被设置成1；前m-1级密勒单元的置位端set都连接至二输入与非门NAND1的输出信号set0，复位端reset都连接至地；第m及密勒单元的置位端set与电源VDD相连，复位端reset与二输入或非门NOR1的输出信号set1相连。
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