WO2015196334A1 - Methods for signaling of sub-pu syntax element in multi-view and 3d video coding - Google Patents
Methods for signaling of sub-pu syntax element in multi-view and 3d video coding Download PDFInfo
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- WO2015196334A1 WO2015196334A1 PCT/CN2014/080516 CN2014080516W WO2015196334A1 WO 2015196334 A1 WO2015196334 A1 WO 2015196334A1 CN 2014080516 W CN2014080516 W CN 2014080516W WO 2015196334 A1 WO2015196334 A1 WO 2015196334A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/46—Embedding additional information in the video signal during the compression process
- H04N19/463—Embedding additional information in the video signal during the compression process by compressing encoding parameters before transmission
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/597—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding specially adapted for multi-view video sequence encoding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
- H04N13/10—Processing, recording or transmission of stereoscopic or multi-view image signals
- H04N13/106—Processing image signals
- H04N13/161—Encoding, multiplexing or demultiplexing different image signal components
Definitions
- the invention relates generally to Three-Dimensional (3D) video processing.
- the present invention relates to the signaling of sub-PU syntax element in multi-view and 3D video coding.
- 3D video coding is developed for encoding or decoding video data of multiple views simultaneously captured by several cameras. Since all cameras capture the same scene from different viewpoints, multi-view video data contains a large amount of inter-view redundancy.
- additional tools such as inter-view motion prediction (IVMP) and motion parameter inheritance (MPI) have been integrated to 3D- HEVC (High Efficiency Video Coding) or 3D-AVC (Advanced Video Coding) codec.
- IVMP inter-view motion prediction
- MPI motion parameter inheritance
- sub-PU level IVMP and sub-PU level MPI are used.
- a syntax element iv_mv_pred_flag is sent for each layer with layer ID larger than zero to indicate whether IVMP is used.
- the other syntax element log2_sub_pb_size_minus3 is sent to indicate the sub-PU size.
- a syntax element mpi_flag is sent for each layer with layer ID larger than zero to indicate whether MPI is used.
- the sub-PU size for MPI is shared by all layers and is indicated by another syntax element log2_mpi_sub_pb_size_minus3 at video parameter set (VPS).
- Fig. 1 shows the current syntax design in 3D-HEVC.
- Fig. 1 is a table showing the current syntax design in 3D-HEVC
- Fig. 2 is a table showing an example of the proposed syntax design method 1 ;
- Fig. 3 is a table showing an example of the proposed syntax design method 2;
- Fig. 4 is a table showing an example of the proposed syntax design method 3;
- Fig. 5 is a table showing an example of the proposed syntax design method 4.
- the proposed methods are the signaling of the sub-PU size syntax element, wherein the same syntax element is used for sub-PU level inter-view motion prediction (IVMP) and sub-PU level and motion parameter inheritance (MPI).
- IVMP sub-PU level inter-view motion prediction
- MPI sub-PU level and motion parameter inheritance
- the sub-PU size is shared by each layer and is indicated by log2_sub_pb_size_minus3 at VPS.
- log2_sub_pb_size_minus3 indicate the sub-PU size of IVMP; in depth coding, it indicates the sub-PU size of MPI.
- the sub-PU size is signaled at each layer with layer ID larger than 0 and is indicated by log2_sub_pb_size_minus3.
- log2_sub_pb_size_minus3[layerId ] indicate the sub-PU size of IVMP in texture coding; in depth coding, it indicates the sub-PU size of MPI.
- log2_sub_pb_size_niinus3 can also be conditioned by the usage of IVMP and MPI. If IVMP or MPI is used (e.g., iv mv pred flag equal to 1 or mpi flag equal to 1), then log2_sub_pb_size_minus3 is signaled; otherwise, log2_sub_pb_size_minus3 is not signaled.
- IVMP or MPI e.g., iv mv pred flag equal to 1 or mpi flag equal to 1
- the syntax element iv_mv_pred_flag and mpi_flag can also be shared by all layers, and only signaled once in VPS.
- the syntax element log2_sub_pb_size_minus3 is only sent in each texture coding layer with layer ID larger than zero to indicate the sub-PU size of IVMP.
- the syntax element log2_mpi_sub_pb_size_minus3 is also sent in each depth coding layer with layer ID larger than zero to indicate the sub-PU size of MPI.
- syntax element can also be signaled in the other high level syntax, for examples sequence parameter set (SPS), adaptive parameter set (APS), and slice header.
- SPS sequence parameter set
- APS adaptive parameter set
- slice header slice header
- sub-PU syntax signaling methods described above can be used in a video encoder as well as in a video decoder.
- Embodiments of sub-PU syntax signaling method according to the present invention as described above may be implemented in various hardware, software codes, or a combination of both.
- an embodiment of the present invention can be a circuit integrated into a video compression chip or program codes integrated into video compression software to perform the processing described herein.
- An embodiment of the present invention may also be program codes to be executed on a Digital Signal Processor (DSP) to perform the processing described herein.
- DSP Digital Signal Processor
- the invention may also involve a number of functions to be performed by a computer processor, a digital signal processor, a microprocessor, or field programmable gate array (FPGA).
- processors can be configured to perform particular tasks according to the invention, by executing machine-readable software code or firmware code that defines the particular methods embodied by the invention.
- the software code or firmware codes may be developed in different programming languages and different format or style.
- the software code may also be compiled for different target platform.
- different code formats, styles and languages of software codes and other means of configuring code to perform the tasks in accordance with the invention will not depart from the spirit and scope of the invention.
Abstract
Methods for signaling of sub-PU syntax in multi-view and 3D video coding are disclosed. The same syntax element for sub-PU size is used for techniques using sub-PU level processing.
Description
METHODS FOR SIGNALING OF SUB-PU SYNTAX ELEMENT IN
MULTI-VIEW AND 3D VIDEO CODING
FIELD OF INVENTION
The invention relates generally to Three-Dimensional (3D) video processing. In particular, the present invention relates to the signaling of sub-PU syntax element in multi-view and 3D video coding.
BACKGROUND OF THE INVENTION
3D video coding is developed for encoding or decoding video data of multiple views simultaneously captured by several cameras. Since all cameras capture the same scene from different viewpoints, multi-view video data contains a large amount of inter-view redundancy. To exploit the inter-view and inter-component redundancy, additional tools such as inter-view motion prediction (IVMP) and motion parameter inheritance (MPI) have been integrated to 3D- HEVC (High Efficiency Video Coding) or 3D-AVC (Advanced Video Coding) codec. To further improve the coding efficiency, sub-PU level IVMP and sub-PU level MPI are used.
In current 3D-HEVC, a syntax element iv_mv_pred_flag is sent for each layer with layer ID larger than zero to indicate whether IVMP is used. For each layer with layer ID larger than zero, the other syntax element log2_sub_pb_size_minus3 is sent to indicate the sub-PU size. For depth coding, a syntax element mpi_flag is sent for each layer with layer ID larger than zero to indicate whether MPI is used. However, the sub-PU size for MPI is shared by all layers and is indicated by another syntax element log2_mpi_sub_pb_size_minus3 at video parameter set (VPS). Fig. 1 shows the current syntax design in 3D-HEVC. SUMMARY OF THE INVENTION
In light of the previously described problems, methods for signaling of sub-PU syntax element are proposed.
Other aspects and features of the invention will become apparent to those with ordinary skill in the art upon review of the following descriptions of specific embodiments.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
Fig. 1 is a table showing the current syntax design in 3D-HEVC;
Fig. 2 is a table showing an example of the proposed syntax design method 1 ;
Fig. 3 is a table showing an example of the proposed syntax design method 2;
Fig. 4 is a table showing an example of the proposed syntax design method 3;
Fig. 5 is a table showing an example of the proposed syntax design method 4.
DETAILED DESCRIPTION
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
The proposed methods are the signaling of the sub-PU size syntax element, wherein the same syntax element is used for sub-PU level inter-view motion prediction (IVMP) and sub-PU level and motion parameter inheritance (MPI).
In method 1, as shown in Fig.2, the sub-PU size is shared by each layer and is indicated by log2_sub_pb_size_minus3 at VPS. In texture coding, log2_sub_pb_size_minus3 indicate the sub-PU size of IVMP; in depth coding, it indicates the sub-PU size of MPI.
In method 2, as shown in Fig.3, the sub-PU size is signaled at each layer with layer ID larger than 0 and is indicated by log2_sub_pb_size_minus3. For each layer with layer ID larger than 0, log2_sub_pb_size_minus3[layerId ] indicate the sub-PU size of IVMP in texture coding; in depth coding, it indicates the sub-PU size of MPI.
Signaling of log2_sub_pb_size_niinus3 can also be conditioned by the usage of IVMP and MPI. If IVMP or MPI is used (e.g., iv mv pred flag equal to 1 or mpi flag equal to 1), then log2_sub_pb_size_minus3 is signaled; otherwise, log2_sub_pb_size_minus3 is not signaled.
The syntax element iv_mv_pred_flag and mpi_flag can also be shared by all layers, and only signaled once in VPS.
For the other possible sub-PU level techniques, similar unification method for the sub-PU syntax element can be used.
In method 3, as shown in Fig. 4, the syntax element log2_sub_pb_size_minus3 is only sent in each texture coding layer with layer ID larger than zero to indicate the sub-PU size of IVMP.
In method 4, as shown in Fig. 5, the syntax element log2_mpi_sub_pb_size_minus3 is also sent in each depth coding layer with layer ID larger than zero to indicate the sub-PU size of
MPI.
All the syntax element can also be signaled in the other high level syntax, for examples sequence parameter set (SPS), adaptive parameter set (APS), and slice header. The above methods can be applied to other techniques that use sub-PU level processing.
The sub-PU syntax signaling methods described above can be used in a video encoder as well as in a video decoder. Embodiments of sub-PU syntax signaling method according to the present invention as described above may be implemented in various hardware, software codes, or a combination of both. For example, an embodiment of the present invention can be a circuit integrated into a video compression chip or program codes integrated into video compression software to perform the processing described herein. An embodiment of the present invention may also be program codes to be executed on a Digital Signal Processor (DSP) to perform the processing described herein. The invention may also involve a number of functions to be performed by a computer processor, a digital signal processor, a microprocessor, or field programmable gate array (FPGA). These processors can be configured to perform particular tasks according to the invention, by executing machine-readable software code or firmware code that defines the particular methods embodied by the invention. The software code or firmware codes may be developed in different programming languages and different format or style. The software code may also be compiled for different target platform. However, different code formats, styles and languages of software codes and other means of configuring code to perform the tasks in accordance with the invention will not depart from the spirit and scope of the invention.
The invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described examples are to be considered in all respects only as illustrative and not restrictive. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims
1. A method for signaling of sub-PU (sub-prediction unit) syntax element in multi-view or 3D video coding, comprising signaling a sub-PU syntax element in a video bitstream.
2. The method as claimed in claim 1, wherein the same sub-PU syntax element is used for sub-PU level inter- view motion prediction (IVMP) and motion parameter inheritance (MPI).
3. The method as claimed in claim 2, the syntax element log2_sub_pb_size_minus3 indicates a sub-PU size of IVMP in texture coding and also indicates a sub-PU size of MPI in depth coding.
4. The method as claimed in claim 3, the syntax element is shared by all layers with layer
ID larger than 0 and signaled in video parameter set (VPS).
5. The method as claimed in claim 3, the syntax element is signaled for each layer with layer ID larger than 0.
6. The method as claimed in claim 3, the syntax element is sent in other high level syntax, sequence parameter set (SPS), adaptive parameter set (APS), or slice header.
7. The method as claimed in claim 2, the syntax element log2_sub_pb_size_minus3 is signaled only if MPI or IVMP is used.
8. The method as claimed in claim 1, the syntax element log2_sub_pb_size_minus3 is only sent in each texture coding layer with layer ID larger than zero to indicate a sub-PU size of IVMP.
9. The method as claimed in claim 1, the syntax element log2_mpi_sub_pb_size_minus3 is only sent in each depth coding layer with layer ID larger than zero to indicate a sub-PU size ofMPI.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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PCT/CN2014/080516 WO2015196334A1 (en) | 2014-06-23 | 2014-06-23 | Methods for signaling of sub-pu syntax element in multi-view and 3d video coding |
JP2016571299A JP2017520994A (en) | 2014-06-20 | 2015-06-18 | Sub-PU syntax signaling and illumination compensation method for 3D and multi-view video coding |
PCT/CN2015/081753 WO2015192781A1 (en) | 2014-06-20 | 2015-06-18 | Method of sub-pu syntax signaling and illumination compensation for 3d and multi-view video coding |
US14/905,705 US10218957B2 (en) | 2014-06-20 | 2015-06-18 | Method of sub-PU syntax signaling and illumination compensation for 3D and multi-view video coding |
CN201580001621.4A CN105519120B (en) | 2014-06-20 | 2015-06-18 | For the three-dimensional of video data or the compartment model coding method of multi-view video coding |
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Citations (2)
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US20130156099A1 (en) * | 2010-09-30 | 2013-06-20 | Panasonic Corporation | Image decoding method, image coding method, image decoding apparatus, image coding apparatus, program, and integrated circuit |
US20140022343A1 (en) * | 2012-07-20 | 2014-01-23 | Qualcomm Incorporated | Parameter sets in video coding |
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US20130156099A1 (en) * | 2010-09-30 | 2013-06-20 | Panasonic Corporation | Image decoding method, image coding method, image decoding apparatus, image coding apparatus, program, and integrated circuit |
US20140022343A1 (en) * | 2012-07-20 | 2014-01-23 | Qualcomm Incorporated | Parameter sets in video coding |
Non-Patent Citations (2)
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TECH, GERHARD ET AL.: "3D-HEVC Draft Text 2", JOINT COLLABORATIVE TEAM ON 3D VIDEO CODING EXTENSION DEVELOPMENT OFITU-T SG 16 WP 3 AND ISO/IEC JTC 1/SC 29/WG 11, 6TH MEETING, 25 October 2013 (2013-10-25), Geneva, CH * |
TECH, GERHARD ET AL.: "3D-HEVC Draft Text 4", JOINT COLLABORATIVE TEAM ON 3D VIDEO CODING EXTENSIONS OF ITU-T SG 16 WP 3 AND ISO/IEC JTC 1/SC 29/WG 11, 8TH MEETING, 29 March 2014 (2014-03-29), Valencia, ES * |
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