WO2015100712A1 - The method to perform the deblocking on sub-pu edge - Google Patents

The method to perform the deblocking on sub-pu edge Download PDF

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Publication number
WO2015100712A1
WO2015100712A1 PCT/CN2014/070014 CN2014070014W WO2015100712A1 WO 2015100712 A1 WO2015100712 A1 WO 2015100712A1 CN 2014070014 W CN2014070014 W CN 2014070014W WO 2015100712 A1 WO2015100712 A1 WO 2015100712A1
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WO
WIPO (PCT)
Prior art keywords
sub
edge
deblocking
size
perform
Prior art date
Application number
PCT/CN2014/070014
Other languages
French (fr)
Inventor
Jicheng An
Kai Zhang
Jian-Liang Lin
Original Assignee
Mediatek Singapore Pte. Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mediatek Singapore Pte. Ltd. filed Critical Mediatek Singapore Pte. Ltd.
Priority to PCT/CN2014/070014 priority Critical patent/WO2015100712A1/en
Publication of WO2015100712A1 publication Critical patent/WO2015100712A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/85—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
    • H04N19/86—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving reduction of coding artifacts, e.g. of blockiness
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/597—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding specially adapted for multi-view video sequence encoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards

Definitions

  • the invention relates generally to Three-Dimensional (3D) video processing.
  • the present invention relates to methods for deblocking of the sub prediction unit (PU) edges.
  • 3D video coding is developed for encoding or decoding video data of multiple views simultaneously captured by several cameras. Since all cameras capture the same scene from different viewpoints, multi-view video data contains a large amount of inter- view redundancy.
  • additional tools such as sub-PU based inter-view motion prediction (SPIVMP), and view synthesized prediction (VSP) have been integrated to conventional 3D-HEVC (High Efficiency Video Coding) or 3D-AVC (Advanced Video Coding) codec.
  • SPIVMP sub-PU based inter-view motion prediction
  • VSP view synthesized prediction
  • 3D-HEVC High Efficiency Video Coding
  • 3D-AVC Advanced Video Coding
  • the sub-PU temporal inter-view motion vector candidate and VSP merge candidate are both processed in sub-PU level, i.e., the PU is divided into multiple sub- PUs and each sub-PU have its own motion parameter for motion compensation.
  • the deblocking process is still the same with HEVC, only PU and TU edges can be deblocked, the sub-PU edge is not considered.
  • Fig. 1 shows an example of sub-PU edges in one PU.
  • the sub-PU edge is proposed to be set as a TU edge for deblocking.
  • deblocking process it is needed to check the existence of non-zero transform coefficients of the two participating blocks of a TU edge to reduce the artifacts resulted from the block based transform.
  • the sub-PU edge is not TU edge and doesn't have the transform artifacts. Therefore, setting the sub-PU edge as TU edge is not reasonable.
  • Fig. 1 is a diagram illustrating the sub-PU edges in one PU.
  • sub-PU edge As a PU edge for deblocking, because the sub-PU edge and PU edge have the same feature for deblocking, i.e., the two participating blocks of one edge may have different motion vectors.
  • the method described above can be used in a video encoder as well as in a video decoder.
  • Embodiments of the method according to the present invention as described above may be implemented in various hardware, software codes, or a combination of both.
  • an embodiment of the present invention can be a circuit integrated into a video compression chip or program codes integrated into video compression software to perform the processing described herein.
  • An embodiment of the present invention may also be program codes to be executed on a Digital Signal Processor (DSP) to perform the processing described herein.
  • DSP Digital Signal Processor
  • the invention may also involve a number of functions to be performed by a computer processor, a digital signal processor, a microprocessor, or field programmable gate array (FPGA). These processors can be configured to perform particular tasks according to the invention, by executing machine-readable software code or firmware code that defines the particular methods embodied by the invention.
  • the software code or firmware codes may be developed in different programming languages and different format or style.
  • the software code may also be compiled for different target platform.
  • different code formats, styles and languages of software codes and other means of configuring code to perform the tasks in accordance with the invention will not depart from the spirit and scope of the invention.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

A method of deblocking the sub-PU edge in 3DVC is proposed to reduce the artifacts resulted from the sub-PU based process. It is proposed to set the sub-PU edge as PU edge instead of TU edge for deblocking because the sub-PU edge has the same feature with PU edge for deblocking, i.e., the two participating blocks of one edge may have different motion vectors.

Description

THE METHOD TO PERFORM THE DEBLOCKING ON SUB-PU EDGE
FIELD OF INVENTION
The invention relates generally to Three-Dimensional (3D) video processing. In particular, the present invention relates to methods for deblocking of the sub prediction unit (PU) edges.
BACKGROUND OF THE INVENTION
3D video coding is developed for encoding or decoding video data of multiple views simultaneously captured by several cameras. Since all cameras capture the same scene from different viewpoints, multi-view video data contains a large amount of inter- view redundancy. To exploit the inter-view redundancy, additional tools such as sub-PU based inter-view motion prediction (SPIVMP), and view synthesized prediction (VSP) have been integrated to conventional 3D-HEVC (High Efficiency Video Coding) or 3D-AVC (Advanced Video Coding) codec.
For the detailed information about such coding tools in 3D-HEVC, one can refer to the document JCT3V-F1001_v4 which can be found at http://phenix.it- sudparis.eu/jct2/doc_end_user/documents/6_Geneva/wgl l/JCT3 V-F1001-v4.zip. The description for SPIVMP (can also be called as the sub-PU temporal inter-view motion vector candidate) is in the section H.8.5.3.2.16 and H.8.5.3.2.11. The description for VSP is in the section H.8.5.3.2.13 and H.8.5.3.3.8.
In current 3D-HEVC, the sub-PU temporal inter-view motion vector candidate and VSP merge candidate are both processed in sub-PU level, i.e., the PU is divided into multiple sub- PUs and each sub-PU have its own motion parameter for motion compensation. However, the deblocking process is still the same with HEVC, only PU and TU edges can be deblocked, the sub-PU edge is not considered. Fig. 1 shows an example of sub-PU edges in one PU.
In the proposal JCT3V-F0135, which was proposed at the 6th JCT3V meeting on October 2013, the sub-PU edge is proposed to be set as a TU edge for deblocking. In deblocking process, it is needed to check the existence of non-zero transform coefficients of the two participating blocks of a TU edge to reduce the artifacts resulted from the block based transform. However, the sub-PU edge is not TU edge and doesn't have the transform artifacts. Therefore, setting the sub-PU edge as TU edge is not reasonable.
SUMMARY OF THE INVENTION In light of the previously described problems, it is proposed to set the sub-PU edge as a PU edge for deblocking, because the sub-PU edge and PU edge have the same feature for deblocking, i.e., the two participating blocks of one edge may have different motion vectors.
Other aspects and features of the invention will become apparent to those with ordinary skill in the art upon review of the following descriptions of specific embodiments.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
Fig. 1 is a diagram illustrating the sub-PU edges in one PU.
DETAILED DESCRIPTION
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
It is proposed to set the sub-PU edge as a PU edge for deblocking, because the sub-PU edge and PU edge have the same feature for deblocking, i.e., the two participating blocks of one edge may have different motion vectors.
The method described above can be used in a video encoder as well as in a video decoder.
Embodiments of the method according to the present invention as described above may be implemented in various hardware, software codes, or a combination of both. For example, an embodiment of the present invention can be a circuit integrated into a video compression chip or program codes integrated into video compression software to perform the processing described herein. An embodiment of the present invention may also be program codes to be executed on a Digital Signal Processor (DSP) to perform the processing described herein. The invention may also involve a number of functions to be performed by a computer processor, a digital signal processor, a microprocessor, or field programmable gate array (FPGA). These processors can be configured to perform particular tasks according to the invention, by executing machine-readable software code or firmware code that defines the particular methods embodied by the invention. The software code or firmware codes may be developed in different programming languages and different format or style. The software code may also be compiled for different target platform. However, different code formats, styles and languages of software codes and other means of configuring code to perform the tasks in accordance with the invention will not depart from the spirit and scope of the invention.
The invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described examples are to be considered in all respects only as illustrative and not restrictive. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

1. A method to perform the deblocking on the sub-PU edges.
2. The method as claimed in claim 1, wherein the sub-PU edge is set as PU edge for deblocking.
3. The method as claimed in claim 1, wherein the sub-PU is resulted from the 3DVC coding tools such as the sub prediction block temporal inter-view motion vector candidate and the VSP merge candidate.
4. The method as claimed in claim 1, wherein the existence of non-zero transform coefficients of two participating blocks of one sub-PU edge are no need to be checked in the deblocking process.
5. The method as claimed in claim 1, a flag is explicitly transmitted in the sequence, view, layer, picture, slice, CTU, CU or PU level to indicate whether the deblocking is perfomed on the sub-PU edge.
6. The method as claimed in claim 1, a flag is implicitly derived on the decoder to decide whether the deblocking is performed on the sub-PU edge.
7. The method as claimed in claim 1, the decoder decides whether to perform the deblocking process on the sub-PU edge according to the PU or sub-PU size. For example, the deblocking is performed on the sub-PU edge only when the size of PU or sub-PU is larger (or equal to) than a given size.
8. The method as claimed in claim 1, the decoder decides whether to perform the deblocking process on the sub-PU edge according to the PU or sub-PU size. For example, the deblocking is performed on the sub-PU edge only when the size of PU or sub-PU is smaller (or equal to) than a certain/given size.
PCT/CN2014/070014 2014-01-02 2014-01-02 The method to perform the deblocking on sub-pu edge WO2015100712A1 (en)

Priority Applications (1)

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PCT/CN2014/070014 WO2015100712A1 (en) 2014-01-02 2014-01-02 The method to perform the deblocking on sub-pu edge

Publications (1)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101494782A (en) * 2008-01-25 2009-07-29 三星电子株式会社 Video encoding method and apparatus, and video decoding method and apparatus
CN102447907A (en) * 2012-01-31 2012-05-09 北京工业大学 Video sequence coding method aiming at HEVC (High Efficiency Video Coding)
WO2013012479A1 (en) * 2011-07-19 2013-01-24 Qualcomm Incorporated Deblocking of non-square blocks for video coding

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101494782A (en) * 2008-01-25 2009-07-29 三星电子株式会社 Video encoding method and apparatus, and video decoding method and apparatus
WO2013012479A1 (en) * 2011-07-19 2013-01-24 Qualcomm Incorporated Deblocking of non-square blocks for video coding
CN102447907A (en) * 2012-01-31 2012-05-09 北京工业大学 Video sequence coding method aiming at HEVC (High Efficiency Video Coding)

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