WO2015192389A1 - 一种可编程伽玛校正缓冲电路芯片及产生伽马电压的方法 - Google Patents

一种可编程伽玛校正缓冲电路芯片及产生伽马电压的方法 Download PDF

Info

Publication number
WO2015192389A1
WO2015192389A1 PCT/CN2014/080830 CN2014080830W WO2015192389A1 WO 2015192389 A1 WO2015192389 A1 WO 2015192389A1 CN 2014080830 W CN2014080830 W CN 2014080830W WO 2015192389 A1 WO2015192389 A1 WO 2015192389A1
Authority
WO
WIPO (PCT)
Prior art keywords
resistor
circuit chip
buffer circuit
operational amplifier
gamma correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2014/080830
Other languages
English (en)
French (fr)
Inventor
曾德康
郭东胜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/379,845 priority Critical patent/US20160247482A1/en
Publication of WO2015192389A1 publication Critical patent/WO2015192389A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/10—Intensity circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve

Definitions

  • the present invention relates to the field of image display, and more particularly to a programmable gamma correction buffer circuit chip and a method for generating a gamma voltage.
  • the data driver circuit (Data Driver) generates gamma 2.2 correction by using a gamma voltage as a reference.
  • Programmable gamma correction buffer circuit chip
  • P Gamma IC is an integrated chip that generates gamma voltages after digital-to-analog conversion (DAC) through a digital logic circuit (Digital Logic Circuit).
  • the existing P-Gamma ICs subdivide the analog reference voltage Vref (reference voltage) into 2 s aliquots by digital logic circuits (S is the number of digital-to-analog conversion bits), and then pass through the FET in the DAC module.
  • MOS tube selects the corresponding channel, and finally obtains the corresponding analog voltage (Analog voltage) through the voltage follower (OP) to generate the gamma voltage required for the analog voltage.
  • OP voltage follower
  • a total of Sx2 s MOS transistors are required.
  • Figure 1 shows the 3-bit DAC module circuit. As you can see, there are a total of 24 (3x8) MOS transistors. For higher digits, such as 10-bit, 10240 (10x1024) MOS transistors are required. Since the number of MOS tubes will directly affect the size and cost of the IC, too many MOS tubes will undoubtedly increase the size and cost of the IC. Summary of the invention
  • the technical problem to be solved by the present invention is to provide a programmable gamma correction buffer circuit chip and a method for generating a gamma voltage which are effective in reducing the volume and cost.
  • the present invention provides a programmable gamma correction buffer circuit chip, including an operational amplifier OP, the non-inverting input terminal of the operational amplifier passes through a first resistor R1 Connected to the reference voltage input terminal, the inverting input terminal of the operational amplifier is connected to the output terminal through a reference resistor Rf, and the inverting input terminal of the operational amplifier is connected in parallel with n second resistors Rs, n is
  • the reference voltage Vref generated by the programmable gamma correction buffer circuit chip is equally divided, the reference voltage Vref is used as a reference potential difference for each aliquot, and each of the second resistors Rs has a switch S connected in series.
  • the resistance of the second resistor Rs is the same as the resistance of the reference resistor Rf.
  • the resistance values of the second resistor Rs, the reference resistor Rf, and the first resistor R1 are the same.
  • the present invention further provides a programmable gamma correction buffer circuit chip, comprising: an operational amplifier OP, the non-inverting input terminal of the operational amplifier is connected to a reference voltage input terminal through a first resistor R1, the operational amplifier The inverting input terminal is connected to the output terminal through a reference resistor Rf, and the inverting input terminal of the operational amplifier is connected in parallel with n second resistors Rs, n is a reference generated by the programmable gamma correction buffer circuit chip
  • the voltage Vref is equally divided, the reference voltage Vref is used as a reference potential difference for each aliquot, and each of the second resistors Rs is connected in series with a switch S, the second resistor Rs, the reference resistor Rf, and the The resistance of all three resistors R1 is the same.
  • the invention also provides a method of generating a gamma voltage, comprising:
  • Step S1 a programmable gamma correction buffer circuit chip is provided, wherein the programmable gamma correction buffer circuit chip includes an operational amplifier OP, and the non-inverting input terminal of the operational amplifier passes through the first resistor R1 and the reference voltage The input ends are connected, the inverting input terminal of the operational amplifier is connected to the output terminal through a reference resistor Rf, and the inverting input terminal of the operational amplifier is connected in parallel with n second resistors Rs, n is the programmable gamma
  • the reference voltage Vref generated by the calibrated snubber circuit chip is equally divided, the reference voltage Vref as a reference potential difference of each aliquot, each of the second resistors Rs is connected in series with a switch S;
  • Step S2 obtaining m value from a register of the programmable gamma correction buffer circuit chip, and controlling m switches S to be closed;
  • step S3 the output voltage Vout is calculated.
  • the output voltage Vout is calculated according to the value of m, the resistance of the second resistor Rs and the resistance of the reference resistor Rf.
  • n is an integer greater than 1 and less than or equal to n.
  • the resistance of the second resistor Rs is the same as the resistance of the reference resistor Rf.
  • the resistance values of the second resistor Rs, the reference resistor Rf, and the first resistor R1 are the same.
  • the embodiment of the invention improves the configuration of the programmable gamma correction buffer circuit chip, and replaces the DAC module with the reference voltage generated by the reference voltage as the divided potential difference, without using the MOS tube, reducing The chip size saves cost.
  • 1 is a schematic circuit diagram of a conventional digital-to-analog conversion module.
  • Figure 2 is a schematic illustration of the electrical principle of a programmable gamma correction snubber circuit chip in accordance with an embodiment of the present invention.
  • FIG. 3 is a schematic flow chart of a method for generating a gamma voltage according to Embodiment 2 of the present invention.
  • a first embodiment of the present invention provides a programmable gamma correction buffer circuit chip, including an operational amplifier OP (Operational Amplifier), the non-inverting input terminal of the operational amplifier is input through a first resistor R1 and a reference voltage. Connected to the terminal, the inverting input of the operational amplifier is connected to the output through a reference resistor Rf. The inverting input of the operational amplifier is connected to ground (GND) in parallel with n second resistors Rs, n is a programmable gamma correction The reference voltage Vref generated by the snubber circuit chip is equally divided, and the reference voltage Vref is used as a reference potential difference for each aliquot. Each of the second resistors Rs has a switch S connected in series.
  • OP Operaational Amplifier
  • the OP Since the OP has a very high open-loop gain, under negative feedback, its input signal is in a small range, the phase difference is small, approximately equal (only there is a difference of millivolts), which is equivalent to the non-inverting input.
  • the inverting input is shorted, but it is not short-circuited, that is, it is short.
  • the OP input resistance is very large, and the current flowing into the non-inverting input terminal and the inverting input terminal of the OP is very small, which can be neglected, which is equivalent to an open circuit of the OP input terminal, but the actual is not an open circuit, that is, a virtual disconnection.
  • the voltage of the non-inverting input terminal of OP and the voltage of the inverting input terminal are both reference voltage Vref;
  • the current flowing from the parallel circuits composed of the n second resistors Rs (the resistances of the second resistors Rs are the same) and the switches is the same as the current flowing through the reference resistor Rf, and therefore, the following formula:
  • n is the value of the register in the programmable gamma correction buffer circuit chip, which can be modified according to requirements, and m is an integer greater than 1 and less than or equal to n.
  • the output voltage Vout of the OP output terminal forms a linear relationship with the reference voltage Vref by the formula (2), so that by closing a different number of switches, different signals can be obtained.
  • the output voltage in turn, the respective gamma voltages required for the liquid crystal display panel (TFT-LCD Panel)own
  • TFT-LCD Panel liquid crystal display panel
  • Vout ( 1+Rs/Rf ) Vref;
  • Vout ( l+8xRs/Rf ) Vrefgestion
  • Fig. 2 It can also be seen from Fig. 2 that it is actually an in-phase adder, which replaces the prior art DAC module, and can also output various required voltages without using a MOS transistor, thereby reducing the chip size and saving. The cost.
  • the resistance of the second resistor Rs is the same as the resistance of the reference resistor Rf, and is set to R, then the formula (2) can be further simplified to the following formula (3): That is, the linear relationship between Vout and Vref is directly related to m. After obtaining the value of m, Vout can be directly calculated.
  • the resistance values of the second resistor Rs, the reference resistor Rf, and the first resistor R1 are the same.
  • Embodiment 2 of the present invention provides a method for generating a gamma voltage, including:
  • Step S1 a programmable gamma correction buffer circuit chip is provided, wherein the programmable gamma correction buffer circuit chip includes an operational amplifier OP, and the non-inverting input terminal of the operational amplifier passes through the first resistor R1 and the reference voltage input terminal. Connected, the inverting input of the operational amplifier is connected to the output through a reference resistor Rf. The inverting input of the operational amplifier is connected in parallel with n second resistors Rs, n is a programmable gamma correction buffer circuit chip. The generated reference voltage Vref is equally divided, the reference voltage Vref is used as a reference potential difference for each aliquot, and each second resistor Rs is connected in series with a switch S;
  • Step S2 obtaining m value from a register of the programmable gamma correction buffer circuit chip, and controlling m switches S to be closed;
  • step S3 the output voltage Vout is calculated.
  • step S3 the output voltage Vout is calculated according to the value of m, the resistance of the second resistor Rs, and the resistance of the reference resistor Rf.
  • m is an integer greater than 1 and less than or equal to n.
  • the resistance of the second resistor Rs is the same as the resistance of the reference resistor Rf. Further, the resistance values of the second resistor Rs, the reference resistor Rf, and the first resistor R1 are the same.
  • the embodiment of the present invention improves the configuration of the programmable gamma correction buffer circuit chip, and uses the reference voltage generated by it as the potential difference of each divided portion, and replaces the DAC module with an adder, without using a MOS transistor.
  • the chip size is reduced and the cost is saved.
  • the gamma voltage is also improved, avoiding the use of high-cost, large-volume components.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Picture Signal Circuits (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Amplifiers (AREA)

Abstract

一种可编程伽玛校正缓冲电路芯片及产生伽玛电压的方法，其中，可编程伽玛校正缓冲电路芯片包括运算放大器OP，所述运算放大器的同相输入端通过第一电阻R1与基准电压输入端相连，所述运算放大器的反相输入端通过参考电阻Rf与输出端相连，所述运算放大器的反相输入端对地并联有n个第二电阻Rs，n为将所述可编程伽玛校正缓冲电路芯片产生的基准电压Vref进行等分的数量，所述基准电压Vref作为每一等份的基准电位差，所述每一第二电阻Rs均串联有一个开关S。通过对可编程伽玛校正缓冲电路芯片的构造进行改进，无需采用MOS管，减小了芯片体积，节省了成本。

Description

一种可编程伽玛校正緩冲电路芯片及产生伽马电压的方法
本申请要求于 2014 年 6 月 17 日提交中国专利局、 申请号为 201410269184.1、 发明名称为 "一种可编程伽玛校正緩冲电路芯片及产生伽 马电压的方法" 的中国专利申请的优先权， 上述专利的全部内容通过引用结 合在本申请中。 技术领域
本发明涉及图像显示领域，尤其涉及一种可编程伽玛校正緩冲电路芯片 及产生伽马电压的方法。
背景技术
TFT-LCD驱动原理中数据驱动电路 ( Data Driver )通过伽马 （ gamma ) 电压作为基准产生实现 gamma 2.2 的校正。 可编程伽玛校正緩冲电路芯片
( P Gamma IC ) 则是通过数位逻辑电路（Digital Logic Circuit)经数模转换 DAC ( Digital-to-Analogue Conversion )后， 产生各 gamma电压的集成芯片。 现有的 P— Gamma IC都是将模拟基准电压 Vref ( reference voltage )通过数位 逻辑电路细分为 2s等分（ S为数模转换位数 ),再经 DAC模块中的场效应管
( MOS管）进行选择对应的通道， 最后经过电压跟随器（OP )得到对应的 模拟电压（Analog voltage ), 产生模拟电压可所需的 gamma电压。 在这种情 况下， 共需 Sx2s个 MOS管。 图 1所示为 3-bit DAC模块电路， 从图中可以 看出， 一共有 24 ( 3x8 )个 MOS管。 对于更高位数， 例如 10-bit, 则需要 10240 ( 10x1024 )个 MOS管。 由于 MOS管数量的多少将直接影响到 IC的 体积大小和成本高低， 过多的 MOS管无疑大大增加了 IC的体积和成本。 发明内容
本发明所要解决的技术问题在于， 提供一种有效减小体积、 降低成本的 可编程伽玛校正緩冲电路芯片及产生伽马电压的方法。
为了解决上述技术问题， 本发明提供一种可编程伽玛校正緩冲电路芯 片， 包括运算放大器 OP, 所述运算放大器的同相输入端通过第一电阻 R1 与基准电压输入端相连， 所述运算放大器的反相输入端通过参考电阻 Rf 与 输出端相连， 所述运算放大器的反相输入端对地并联有 n个第二电阻 Rs, n 为将所述可编程伽玛校正緩冲电路芯片产生的基准电压 Vref 进行等分的数 量， 所述基准电压 Vref作为每一等份的基准电位差， 所述每一第二电阻 Rs 均串联有一个开关 S。
其中， 所述第二电阻 Rs的阻值与参考电阻 Rf的阻值相同。
其中， 所述第二电阻 Rs、 参考电阻 Rf以及第一电阻 R1三者的阻值均 相同。
本发明还提供一种一种可编程伽玛校正緩冲电路芯片， 其中， 包括运算 放大器 OP,所述运算放大器的同相输入端通过第一电阻 R1与基准电压输入 端相连， 所述运算放大器的反相输入端通过参考电阻 Rf 与输出端相连， 所 述运算放大器的反相输入端对地并联有 n个第二电阻 Rs, n为将所述可编程 伽玛校正緩冲电路芯片产生的基准电压 Vref进行等分的数量，所述基准电压 Vref作为每一等份的基准电位差， 所述每一第二电阻 Rs均串联有一个开关 S, 所述第二电阻 Rs、 参考电阻 Rf以及第一电阻 R1三者的阻值均相同。
本发明还提供一种产生伽马电压的方法， 包括：
步骤 S1 , 提供一种可编程伽玛校正緩冲电路芯片， 其中， 所述可编程 伽玛校正緩冲电路芯片包括运算放大器 OP, 所述运算放大器的同相输入端 通过第一电阻 R1与基准电压输入端相连， 所述运算放大器的反相输入端通 过参考电阻 Rf 与输出端相连， 所述运算放大器的反相输入端对地并联有 n 个第二电阻 Rs, n 为将所述可编程伽玛校正緩冲电路芯片产生的基准电压 Vref进行等分的数量，所述基准电压 Vref作为每一等份的基准电位差，所述 每一第二电阻 Rs均串联有一个开关 S;
步骤 S2, 从可编程伽玛校正緩冲电路芯片的寄存器获得 m值， 控制 m 个开关 S闭合；
步骤 S3 , 计算得到输出电压 Vout。
其中， 所述步骤 S3中， 所述输出电压 Vout才艮据 m值， 所述第二电阻 Rs的阻值以及参考电阻 Rf的阻值计算得到。
其中， m是大于 1且小于等于 n的整数。 其中， 所述第二电阻 Rs的阻值与参考电阻 Rf的阻值相同。
其中， 所述第二电阻 Rs、 参考电阻 Rf以及第一电阻 R1三者的阻值均 相同。
本发明实施例通过对可编程伽玛校正緩沖电路芯片的构造进行改进，将 其产生的基准电压作为所划分的每一等份的电位差， 取代了 DAC模块， 无 需釆用 MOS管， 减小了芯片体积， 节省了成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面 描述中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。
图 1是现有数模转换模块电路示意图。
图 2是本发明实施例——种可编程伽玛校正緩冲电路芯片的电气原理示 意图。
图 3是本发明实施例二一种产生伽马电压的方法的流程示意图。
具体实施方式
请参照图 2所示， 本发明实施例一提供一种可编程伽玛校正緩冲电路芯 片， 包括运算放大器 OP ( Operational amplifier ), 该运算放大器的同相输入 端通过第一电阻 R1与基准电压输入端相连， 该运算放大器的反相输入端通 过参考电阻 Rf与输出端相连， 该运算放大器的反相输入端对地（GND ) 并 联有 n个第二电阻 Rs, n为将可编程伽玛校正緩冲电路芯片产生的基准电压 Vref进行等分的数量， 基准电压 Vref作为每一等份（step ) 的基准电位差， 每一第二电阻 Rs均串联有一个开关 S。
由于 OP具有极高的开环增益， 在负反馈下， 其输入信号处在很小的范 围内， 相差很小， 近似相等 （仅存在毫伏级的差异）， 相当于把那同相输入 端与反相输入端短接， 但实际又没短接， 即虚短。 另外， OP输入电阻很大， 流入 OP的同相输入端和反相输入端中的电流十分微小， 往往可以忽略， 相 当于 OP的输入端开路， 但实际并非开路， 即虚断。 利用 OP的虚短原理可 知， OP同相输入端电压与反相输入端电压均为基准电压 Vref; 利用 OP的 虚断原理可知， 从 n个第二电阻 Rs (这些第二电阻 Rs的阻值均相同）与开 关组成的并联电路流出的电流， 与流经参考电阻 Rf 的电流相同， 因此， 即 有下述公式：
\'ΚΪ _ \ ut 《 )
Rs.1"議 Rf+Rs 議
其中， m为可编程伽玛校正緩冲电路芯片中寄存器的值， 可以根据需求 进行修改， m是大于 1且小于等于 n的整数。
也就是说， 确定参考电阻 Rf和第二电阻 Rs的阻值后， 通过公式（2 ), OP输出端的输出电压 Vout与基准电压 Vref形成线性关系， 这样， 闭合不同 数量的开关， 即可得到不同的输出电压， 进而得到液晶显示面板（TFT-LCD Panel )所需的各个伽马电压（ Gamma voltage )„ 当从寄存器获得 m的值后， 则对应有 m个开关闭合， 使得 Rs/m的值变小， 通过公式（2 )计算得到输 出电压 Vouto
例如， 图 2所示为将基准电压划分为 1024等份， 则运算放大器的反相 输入端对地（ GND )并联有 1024个第二电阻 Rs ( Rsl , Rs2 , Rs3 , ... , Rsn, n=1024 ), 每一第二电阻 Rs串联有一个开关 S , 开关数也为 1024个。 m的 数值则在 1~1024中取值， 当 m=2时， 则有 2个开关 S闭合， 此时相当于 2 个第二电阻 Rs相并联后， 一端与参考电阻 Rf 串联， 另一端接地， 则 Vout= ( 1+Rs/Rf ) Vref; 同样， 当 m=8时， 则有 8个开关 S闭合， 即 8个第二电 阻 Rs相并联后，一端与参考电阻 Rf 串联，另一端接地，则 Vout=( l+8xRs/Rf ) Vref„
从图 2也可以看出， 其实际为一同相加法器， 取代了现有技术的 DAC 模块， 同样也能实现输出各种所需电压， 无需釆用 MOS管， 减小了芯片体 积， 节省了成本。
作为更优的实现方式， 第二电阻 Rs的阻值与参考电阻 Rf的阻值相同， 设为 R, 则公式（2 )可以进一步简化为如下公式（3 ): 即 Vout与 Vref的线性关系更是直接只与 m相关， 获得 m取值之后， 直 接可以计算得到 Vout。
再进一步地， 为使整个电路更易于实现， 第二电阻 Rs、 参考电阻 Rf以 及第一电阻 R1三者的阻值均相同。
再请参照图 3所示， 本发明实施例二提供一种产生伽马电压的方法， 包 括：
步骤 S1 , 提供一种可编程伽玛校正緩冲电路芯片， 其中， 该可编程伽 玛校正緩冲电路芯片包括运算放大器 OP, 该运算放大器的同相输入端通过 第一电阻 R1与基准电压输入端相连， 该运算放大器的反相输入端通过参考 电阻 Rf与输出端相连， 该运算放大器的反相输入端对地并联有 n个第二电 阻 Rs, n为将可编程伽玛校正緩冲电路芯片产生的基准电压 Vref 进行等分 的数量， 基准电压 Vref作为每一等份（step )的基准电位差， 每一第二电阻 Rs均串联有一个开关 S;
步骤 S2, 从可编程伽玛校正緩冲电路芯片的寄存器获得 m值， 控制 m 个开关 S闭合；
步骤 S3 , 计算得到输出电压 Vout。
具体地， 步骤 S3中， 输出电压 Vout根据 m值， 第二电阻 Rs的阻值以 及参考电阻 Rf 的阻值计算得到。 具体计算方式可参见前述本发明实施例一 中的公式（2 )。 如前所述， m是大于 1且小于等于 n的整数。
同样， 本实施例中， 第二电阻 Rs的阻值与参考电阻 Rf的阻值相同。 进 一步地， 第二电阻 Rs、 参考电阻 Rf以及第一电阻 R1三者的阻值均相同。
本发明实施例通过对可编程伽玛校正緩沖电路芯片的构造进行改进，将 其产生的基准电压作为所划分的每一等份的电位差， 以加法器取代 DAC模 块， 无需釆用 MOS管， 减小了芯片体积， 节省了成本。 同时也使伽马电压 的产生方式得到改良， 避免釆用高成本、 大体积的元器件。
以上所揭露的仅为本发明较佳实施例而已， 当然不能以此来限定本发明 之权利范围， 因此等同变化， 仍属本发明所涵盖的范围。

Claims

权 利 要 求
1、 一种可编程伽玛校正緩冲电路芯片， 其中， 包括运算放大器 OP, 所 述运算放大器的同相输入端通过第一电阻 R1与基准电压输入端相连， 所述 运算放大器的反相输入端通过参考电阻 Rf 与输出端相连， 所述运算放大器 的反相输入端对地并联有 n个第二电阻 Rs, n为将所述可编程伽玛校正緩冲 电路芯片产生的基准电压 Vref进行等分的数量， 所述基准电压 Vref作为每 一等份的基准电位差， 所述每一第二电阻 Rs均串联有一个开关 S。
2、 根据权利要求 1 所述的可编程伽玛校正緩冲电路芯片， 其中， 所述 第二电阻 Rs的阻值与参考电阻 Rf的阻值相同。
3、 根据权利要求 2所述的可编程伽玛校正緩冲电路芯片， 其中， 所述 第二电阻 Rs、 参考电阻 Rf以及第一电阻 R1三者的阻值均相同。
4、 一种可编程伽玛校正緩冲电路芯片， 其中， 包括运算放大器 OP, 所 述运算放大器的同相输入端通过第一电阻 R1与基准电压输入端相连， 所述 运算放大器的反相输入端通过参考电阻 Rf 与输出端相连， 所述运算放大器 的反相输入端对地并联有 n个第二电阻 Rs, n为将所述可编程伽玛校正緩冲 电路芯片产生的基准电压 Vref进行等分的数量， 所述基准电压 Vref作为每 一等份的基准电位差， 所述每一第二电阻 Rs均串联有一个开关 S , 所述第 二电阻 Rs、 参考电阻 Rf以及第一电阻 R1三者的阻值均相同。
5、 一种产生伽马电压的方法， 包括：
步骤 S1 , 提供一种可编程伽玛校正緩冲电路芯片， 其中， 所述可编程 伽玛校正緩冲电路芯片包括运算放大器 OP, 所述运算放大器的同相输入端 通过第一电阻 R1与基准电压输入端相连， 所述运算放大器的反相输入端通 过参考电阻 Rf 与输出端相连， 所述运算放大器的反相输入端对地并联有 n 个第二电阻 Rs, n 为将所述可编程伽玛校正緩冲电路芯片产生的基准电压 Vref进行等分的数量，所述基准电压 Vref作为每一等份的基准电位差，所述 每一第二电阻 Rs均串联有一个开关 S;
步骤 S2 , 从可编程伽玛校正緩冲电路芯片的寄存器获得 m值， 控制 m 个开关 S闭合；
步骤 S3 , 计算得到输出电压 Vout。
6、 根据权利要求 5所述的方法， 其中， 所述步骤 S3中， 所述输出电压 Vout根据 m值， 所述第二电阻 Rs的阻值以及参考电阻 Rf的阻值计算得到。
7、 根据权利要求 6所述的方法， 其中， m是大于 1且小于等于 n的整 数。
8、 根据权利要求 5所述的方法， 其中， 所述第二电阻 Rs的阻值与参考 电阻 Rf的阻值相同。
9、 根据权利要求 7所述的方法， 其中， 所述第二电阻 Rs、 参考电阻 Rf 以及第一电阻 R1三者的阻值均相同。
PCT/CN2014/080830 2014-06-17 2014-06-26 一种可编程伽玛校正缓冲电路芯片及产生伽马电压的方法 Ceased WO2015192389A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/379,845 US20160247482A1 (en) 2014-06-17 2014-06-26 Programmable Gamma Correction Buffer Circuit Chip and Method for Generating Gamma Voltage

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410269184.1 2014-06-17
CN201410269184.1A CN104021771B (zh) 2014-06-17 2014-06-17 一种可编程伽玛校正缓冲电路芯片及产生伽马电压的方法

Publications (1)

Publication Number Publication Date
WO2015192389A1 true WO2015192389A1 (zh) 2015-12-23

Family

ID=51438497

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/080830 Ceased WO2015192389A1 (zh) 2014-06-17 2014-06-26 一种可编程伽玛校正缓冲电路芯片及产生伽马电压的方法

Country Status (3)

Country Link
US (1) US20160247482A1 (zh)
CN (1) CN104021771B (zh)
WO (1) WO2015192389A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10263581B2 (en) * 2016-09-30 2019-04-16 Analog Devices, Inc. Amplifier calibration
CN106548760B (zh) * 2017-01-16 2019-06-07 京东方科技集团股份有限公司 一种伽马电压产生电路及控制方法、源极驱动器
US10068551B1 (en) * 2017-05-01 2018-09-04 Microsoft Technology Licensing, Llc Localized high brightness mode
CN109243355B (zh) * 2018-10-24 2021-04-06 惠科股份有限公司 伽马电压校正电路、方法及显示装置
JP6729670B2 (ja) * 2018-12-11 2020-07-22 セイコーエプソン株式会社 表示ドライバー、電気光学装置及び電子機器
CN110111752A (zh) 2019-04-08 2019-08-09 北海惠科光电技术有限公司 一种驱动电路和显示装置
KR102842816B1 (ko) * 2020-07-02 2025-08-06 엘지디스플레이 주식회사 디스플레이 장치 및 구동 회로
CN119559913B (zh) * 2024-12-23 2025-10-28 上海天马微电子有限公司 一种显示面板及其控制方法、显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313884B1 (en) * 1997-04-07 2001-11-06 U.S. Philips Corporation Gamma correction
JP2002250908A (ja) * 2001-02-23 2002-09-06 Matsushita Electric Ind Co Ltd 液晶表示装置及び画像表示応用機器
CN1437083A (zh) * 2002-02-08 2003-08-20 精工爱普生株式会社 基准电压发生电路和方法、显示驱动电路、显示装置
CN101393730A (zh) * 2008-11-10 2009-03-25 友达光电股份有限公司 伽玛电压转换装置
CN101826308A (zh) * 2009-03-03 2010-09-08 联咏科技股份有限公司 伽玛电压产生装置及其伽玛电压产生器
US20120162184A1 (en) * 2010-12-24 2012-06-28 Samsung Electronics Co., Ltd. Method of driving display panel and display apparatus for performing the same
CN103000157A (zh) * 2012-12-25 2013-03-27 深圳市华星光电技术有限公司 液晶显示器的驱动系统的可编程伽马电路
CN103366667A (zh) * 2013-07-01 2013-10-23 北京京东方光电科技有限公司 伽马电压产生电路及控制方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS609211A (ja) * 1983-06-29 1985-01-18 Fujitsu Ltd 絶対ゲイン調整回路
KR100205371B1 (ko) * 1996-03-26 1999-07-01 구자홍 액정의 다계화 구동회로
JPH11175027A (ja) * 1997-12-08 1999-07-02 Hitachi Ltd 液晶駆動回路および液晶表示装置
CN102684623B (zh) * 2012-05-24 2015-08-26 上海交通大学 一种基于输入支路开关调制的反相放大电路
JP6058289B2 (ja) * 2012-06-05 2017-01-11 サターン ライセンシング エルエルシーＳａｔｕｒｎ Ｌｉｃｅｎｓｉｎｇ ＬＬＣ 表示装置、撮像装置及び階調電圧生成回路

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313884B1 (en) * 1997-04-07 2001-11-06 U.S. Philips Corporation Gamma correction
JP2002250908A (ja) * 2001-02-23 2002-09-06 Matsushita Electric Ind Co Ltd 液晶表示装置及び画像表示応用機器
CN1437083A (zh) * 2002-02-08 2003-08-20 精工爱普生株式会社 基准电压发生电路和方法、显示驱动电路、显示装置
CN101393730A (zh) * 2008-11-10 2009-03-25 友达光电股份有限公司 伽玛电压转换装置
CN101826308A (zh) * 2009-03-03 2010-09-08 联咏科技股份有限公司 伽玛电压产生装置及其伽玛电压产生器
US20120162184A1 (en) * 2010-12-24 2012-06-28 Samsung Electronics Co., Ltd. Method of driving display panel and display apparatus for performing the same
CN103000157A (zh) * 2012-12-25 2013-03-27 深圳市华星光电技术有限公司 液晶显示器的驱动系统的可编程伽马电路
CN103366667A (zh) * 2013-07-01 2013-10-23 北京京东方光电科技有限公司 伽马电压产生电路及控制方法

Also Published As

Publication number Publication date
US20160247482A1 (en) 2016-08-25
CN104021771B (zh) 2017-02-15
CN104021771A (zh) 2014-09-03

Similar Documents

Publication Publication Date Title
WO2015192389A1 (zh) 一种可编程伽玛校正缓冲电路芯片及产生伽马电压的方法
JP5356422B2 (ja) ソースドライバーのガンマ基準電圧出力回路
JP5599040B2 (ja) 基準電圧生成回路、電源装置、液晶表示装置
CN101290743B (zh) 具有伽马校正的有源式矩阵有机发光二极管的驱动电路
TWI530926B (zh) 源極驅動器及顯示裝置
CN103795404B (zh) 一种相位插值器电路及相位插值信号处理方法
US20150279524A1 (en) Gamma resistor adjusting device, driving circuit and display device
CN101114421A (zh) 输出驱动装置及显示装置
US8890787B2 (en) Panel driving device having a source driving circuit, and liquid crystal display apparatus having the same
CN104484070B (zh) 触摸装置的驱动电路、驱动方法、触摸装置和显示装置
TWI477073B (zh) 用於可切換地連接輸入節點及輸出節點之切換電路及方法
JP6524981B2 (ja) リンギング抑制回路
CN104992673A (zh) 一种反相器、栅极驱动电路和显示装置
CN100550651C (zh) 薄膜晶体管型液晶显示屏源驱动芯片的多阈值数模转换器
EP2518900B1 (en) Current steering circuit with feedback
TWI597711B (zh) 源極驅動器及其運作方法
US8493147B2 (en) Differential amplifier and source driver
WO2017128463A1 (zh) 一种数模转换模块、数据驱动电路及液晶显示器
WO2014121474A1 (zh) 液晶显示器及其补偿电路、薄膜晶体管的电压的关闭方法
CN208607896U (zh) 伽马电压产生电路、驱动电路及其显示装置
US9374103B1 (en) Digital-to-analog converter system
US7609105B2 (en) Voltage level generating device
JP2008211792A (ja) Ｌｃｄパネルコラムドライバ用出力アーキテクチャ
US8525716B2 (en) Isolation circuit for a digital-to-analog converter
CN110164387B (zh) 伽马电压产生电路、驱动电路及其显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14379845

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14895172

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14895172

Country of ref document: EP

Kind code of ref document: A1