WO2015190925A2

WO2015190925A2 - Electronic paper display driver system

Info

Publication number: WO2015190925A2
Application number: PCT/NL2015/050425
Authority: WO
Inventors: Daniël WIERMANS
Original assignee: Hj Forever Patents B.V.
Priority date: 2014-06-11
Filing date: 2015-06-11
Publication date: 2015-12-17
Also published as: WO2015190925A3; WO2015190925A4; NL2012985B1

Abstract

The present invention is related to a driver for an electronic paper (e-paper) display. It is further related to a source driver and a timing controlling that are configured to be used in a driver for an e-paper display. It is also related to an e-paper display and to a method for driving an e-paper display. According to the invention, the clock signal system is configured to generate a separate clock signal for each of the n source drivers, wherein the separate clock signals are phase shifted with respect to each other by m times 360/n degrees, with m being an integer ranging from 1 to (n-1). Furthermore, the timing controller is configured to output the source driver data at a rate corresponding to n times the clock frequency, said TCON being further configured to output the packets for the different source drivers in an alternated manner such that each source driver receives a packet of source driver data intended for that source driver during a single clock cycle.

Description

Electronic paper display driver system FIELD OF THE INVENTION

The present invention is related to a driver system for an electronic paper (e-paper) display. It is further related to a source driver and a timing controlling that are configured to be used in a driver system for an e-paper display. It is also related to an e-paper display and to a me^¬ thod for driving an e-paper display.

BACKGROUND OF THE INVENTION

E-paper displays employ display technologies that rely on active matrices to control the pixels. An active ma^¬ trix typically comprises a plurality of source lines and a gate line. Thin film transistors are arranged at the crossing points of the source lines and gate line. By driving the source lines and the gate line, the transistor can be swit^¬ ched between states and the pixel can be driven accordingly.

A known display technology for e-paper displays is that of electrophoretic displays. In this type of displays, charged pigment particles in a pixel are moved in dependence on the voltages generated in that pixel. Depending on the mo^¬ vement of the pixel and the pigment type a particular ap^¬ pearance of a pixel can be obtained such as black, white, co^¬ lored or transparent.

Source drivers are used for applying the required voltages on the source lines. For electrophoretic displays, a source driver is typically configured to drive a plurality of source lines, e.g. 200 or more. The source driver receives source driver data that is put on a data bus by a timing con- troller (TCON) . When an edge, such as a rising edge, is detected in the clock signal that is supplied to the source driver by a clock signal system, the data on the data bus is clocked into a multi-bit shift register comprised in the source driver. This data is subsequently shifted to allow further data to be clocked during a next clock cycle. Once the shift register is filled with data, a latch enable signal is supplied to the source driver. The source driver will then move or copy the data comprised in the shift register to a latch. The latter will hold the data until it is filled with new data. A digital-to-analog converter or level shifter is used to convert or level shift the data in the latch into source voltages to be applied to the source lines.

In electrophoretic displays, a particular color or shade of grey is obtained by applying a waveform to a pixel. Such waveform typically comprises a plurality of voltage le^¬ vels that are sequentially applied to a pixel, e.g. +15V, 0V, 0V, +15V etc. The charged pigment particles will move accor- ding to the applied waveform. Based on the applied waveform and on the state of the pixel prior to applying the waveform, e.g. the previous image, a particular color or shade of grey may be obtained. Special waveforms, the so-called flashing waveforms, may be applied to ensure that a pixel achieves a particular shade of grey or color independently of the previ^¬ ous state of the pixel. During use, such flashing waveforms may be used to reset the display to avoid color drifting.

Most source drivers use multiple bits to address a single source line. This makes it possible to generate multi- pie voltage levels such as -15V, 0V, +15V or intermediate va^¬ lues if desired.

Figure 1 illustrates an example of a known driver system for an electrophoretic display. In this example, a ti^¬ ming controller 1 receives image or video data 2 from an ima- ge source. This data may comprise a bitmap or a part thereof representative of an image to be displayed next on the dis^¬ play. The data comprises information regarding a plurality of pixels. This information may comprise a desired color and/or intensity .

Based on received data 2, timing controller 1 compu^¬ tes the voltages that need to be applied to source lines Sl- S800. To that end, it uses a waveform memory 3 in which waveforms are stored that specify how a particular color transi^¬ tion can be achieved, e.g. a black-to-white transition or vi- ce versa. As an example, if a display is arranged to display 16 shades of grey, the waveform memory may comprise 240 dif^¬ ferent waveforms. These waveforms represent each possible transition excluding transitions between identical colors. Timing controller 1 may further comprise or may be connected to a memory (not shown) in which the current status or desi^¬ red status of a pixel or pixels is stored.

Timing controller 1 further outputs a voltage to a gate driver 5. Gate driver 5 typically applies a high voltage to one gate line of the active matrix and a low voltage to the other gate lines at a time or vice versa. In such manner, pixels are addressed one gate line at a time.

Timing controller 1 is connected via a data bus 6 to source drivers 7, 8. In figure 1, timing controller 1 comprises a clock signal generator for outputting a clock signal 9. Timing controller 1 further outputs 2 separate chip select signals 10, 11.

Next, the operation of the driver in figure 1 will be explained referring to the timing diagram in figure 2.

Starting at t=0, data on data bus 6 is changed. Af^¬ ter t=0, the data on data bus 6 is intended for the first source driver, i.e. source driver 7. This is indicated by chip select signal CS lwhich is high at that time. Source drivers 7, 8 are configured to clock the data on data bus 6 only when they receive a high and/or active chip select sig^¬ nal .

At the first rising edge of clock signal 9 after t=0, data will be clocked into source driver 7. Assuming an 8 bit data bus, 8 bits of data will be clocked. These 8 bits are referred to as a packet of source driver data. This pro^¬ cess has to be repeated several times until the shift regis^¬ ter is filled. Then, source driver 8 will be selected by ma^¬ king chip select signal 10 low and chip select signal 11 high. Thereafter, data will be clocked into source driver 8.

Once the shift registers of both source drivers 7, 8 are fil^¬ led, a high latch enable signal 12 is applied. This causes the data in the shift register of source drivers 7, 8 to be copied or moved into latches in source drivers 7, 8. The data in these latches is level shifted such that appropriate vol^¬ tages are applied to source lines S1-S800. Thereafter, the gate driver can be controlled to address a next gate line and the process of addressing the pixels can be repeated. An example of prior art documents is US2013/147782 (Al) . The document recites a data driving apparatus including two data driving circuits, each including a timing controller with a clock generator and configured to receive a specific portion of data corresponding to a row of pixel in an image frame, and, after receiving the specific portion of the data, process the portion of the data; wherein the two timing con^¬ trollers have different data operation times. One timing con^¬ troller outputs an enable command to another one once the processing of the respective portion of the data is complete. Then, another timing controller starts to process the respective portion of the data and output an output command to the first data driving circuit in response to a finish of the processing of the second portion of the data and thereby con- trolling the two data driving circuits to output the proces^¬ sed data. An operation method thereof and a display using the same are also provided.

Further US 2013/257847 Al recites possible implementations of a matrix display with gate lines and source lines.

The document however relates to managing large amounts of data by just multiplying an amount of processing units (chips), that is adding a further data control system. Such can be done by e.g. splitting a display into sections, and controlling each section by a separate data control sys- tern.

US2013/257847 Al recites a display device including a display panel having pixels arranged at intersections of source lines and gate lines, a plurality of source drivers configured to dispersedly output image data signals to the source lines in response to source control signals and a data packet, a plurality of gate drivers configured to drive gate lines in response to gate control signals so as to be con^¬ nected with pixels corresponding to the source lines, and a timing controller configured to output the data packet, the source control signals, and the gate control signals. At least one of the plurality of source drivers is configured to output carry information associated with an output of the image data signals, and at least another of the plurality of source drivers is configured to output the image data signals in response to the carry information. The problem and soluti^¬ on of this document are not very clear, but it seems to rela^¬ te to handling information in a moving picture in a sophisti- cated way.

US2002/027545 Al recites a shift register, which adopts a shift operation delay for each memory device, or a data conversion control system through the estimation of conversion of data storage state. A driver circuit of LCD is provided, which adopts such a shift register, to thereby pre^¬ vent instantaneous increase of electric power consumption while preventing EMI. Accordingly, shift registers operate as being sequentially delayed for each memory device or data conversion is minimized, thus preventing instantaneous exces- sive consumption of electric power. This document relates to a standard way of operating a display device.

US2009/058788 Al recites an apparatus and method of driving data of a liquid crystal display device is disclosed, which can minimize an electromagnetic interference EMI noise by decreasing an output peak current of a data driver, the apparatus comprising a timing controller for supplying a reference source output enable signal; a delay circuit for de^¬ laying the reference source output enable signal and supply^¬ ing a plurality of source output enable signals provided with the different delay times; and a data driver, including a plurality of data ICs to divide and drive data lines of a li^¬ quid crystal panel into a plurality of data blocks, for dis^¬ persing data output timing of the plurality of data ICs in response to the plurality of source output enable signals. This document relates to a standard way of operating a dis^¬ play device.

US2008/291181 Al recites a method and apparatus for driving a display panel in which a bus link between a timing controller and a source driver block is altered in order to simplify the structure of a circuit. The apparatus includes a timing controller to generate signals including data and a reference signal for driving the display panel at a display driving time. A plurality of source drivers generate signals for driving data lines of the display panel using the signals generated by the timing controller. First signal transmission means are provided for transmitting the data from the timing controller to each of the plurality of source drivers using a point-to-point connection link, and a bus for transmitting the reference signal generated by the timing controller to one of the plurality of source drivers.; Also, second signal transmission means are provided for transmitting the reference signal between the plurality of source drivers using a se- rial cascade connection link. Also this document relates to a standard way of operating a display panel as well as the fol^¬ lowing document.

US2010/156879 Al recites a liquid crystal display and a method of driving the same are provided. The liquid crystal display includes a first source drive IC group out- putting a first feedback lock signal in response to one of a power voltage input through a first lock signal input termi^¬ nal and a lock signal from the timing controller, a second source drive IC group outputting a second feedback lock sig- nal in response to one of the power voltage input through a second lock signal input terminal, the lock signal from the timing controller, and a lock signal transferred from the first source drive IC group, and a comparator that compares the first feedback lock signal with the second feedback lock signal and supplies a comparison result to the timing con^¬ troller .

The above documents do not specifically relate to handling large amounts of data in a short time frame, requi^¬ ring a large band width.

A continuing demand for any display technology is to increase the rate at which images can be displayed, the so- called frame rate. A further demand for display technologies in general is to increase the resolution with which images can be displayed. It can be appreciated that a high data throughput is of the utmost importance when both demands are to be met simultaneously.

Current source driver technology allows for given maximum rate at which data can be clocked, the so-called cy- cle time. A solution to increase the data throughput at this rate even further is to allow for a wider data bus as this would increase the number of bits that can be clocked in a given cycle.

Widening the data bus is not without expense. Rou^¬ ting a wide data bus on the substrate of the display panel may increase the distance between the edge of the substrate and the actual active area, resulting in a widening of the edge (e.g. bevel) of the display. This may be esthetically unappealing.

A second disadvantage of widening the data bus is related to the required pin count of the timing controller. The costs for the timing controller increase sharply when the pin count is increased. The same holds for the connectors used in the system. Typically, a flexible carrier or foil is used to transport the data bus and control signals between the PCB on which the timing controller is mounted and the source and gate drivers which are arranged on the substrate of the display panel. A connector is used to connect the foil to the PCB. Widening the data bus increases the costs of such connector. Moreover, routing a wider data bus becomes cumbersome .

Finally, at high rates, the width of the data bus needs to be compensated for as the time required for a signal to pass through one line of the data bus depends on the posi^¬ tion of this line in the data bus.

An object of the present invention is provide a dri^¬ ver system that allows the display to operate at higher reso^¬ lutions and/or frame rates without or minimizing widening of the data bus.

SUMMARY OF THE INVENTION

A first aspect of the invention by which this object has been achieved is related to a driver system as defined in appended claim 1. According to the present invention, the driver system is characterized in that the single clock sig^¬ nal system is configured to generate a separate clock signal for each and all of the n source drivers, said separate clock signals being phase shifted with respect to each other by m times 360/Ώ degrees, with m being an integer ranging from 1 to (n-1) , and n being the number of source drivers.

Therewith the present invention overcomes problems of the prior art and is capable of handling large amounts of data while maintaining the design benefits of a low speed da^¬ ta architecture, e.g. low pin-count for interconnection and simple board layouts.

DE TAILED DESCRIPTION OF THE INVENTION

The driver system is further characterized in that the TCON is configured to output the source driver data at a rate corresponding to n times the clock frequency, said TCON being further configured to output the packets for the diffe^¬ rent source drivers in an alternated manner such that each source driver receives a packet of source driver data inten- ded for that source driver during a single clock cycle.

The applicant has realized that for present source drivers the time required for the data to be present on the data bus prior to the clock edge (tsetup) and the time for the data to remain present on the data bus after the clock edge (thold) is negligible compared to the cycle time (tcy- cle) of the source driver. Consequently, more source drivers can be used within a given cycle. This is made possible by using dedicated clock signals having the same predefined clock frequency but which are delayed with respect to each other. The number of source drivers n that can be used can be roughly approximated by n = tcycle / {thold + tsetup) .

Using more source drivers allows a higher resolution to be obtained. On the other hand, if a current display re^¬ quires 2 source drivers each driving 400 source lines, the data bus rate can be doubled by using 4 source drivers each driving 200 source lines, wherein the source drivers have si^¬ milar cycle times.

The present invention allows the number or size of source drivers to be optimized for a given display resolution and/or intended frame rate without or minimizing the widening of the data bus.

Each source driver is preferably configured to clock source driver data intended for that source driver when it detects an edge in the respective clock signal. The edge is preferably a rising edge of the clock signal. When a clock signal for a given source driver displays an edge for the clocking of data, it is ensured that the data which is avai- lable on the data bus at that moment, corresponds to data in^¬ tended for that source driver. Compared to the driver illu^¬ strated in figure 1, there is no need to work with chip se^¬ lect signals to alternately select a given source driver. In practice, all source drivers may be selected simultaneously.

The packets outputted by the TCON are preferably ar^¬ ranged in an order that corresponds to the order in delay of the separate clock signals. For instance, when source drivers A, B, and C are supplied with clock signals, fA, fB, and fC, respectively, wherein fC is delayed by 120 degrees compared to fB, which in turn is delayed by 120 degrees compared to fA, the order in which data is outputted by the TCON is given by: dA, dB, dC, dA, dB, dC, dA ... etc, wherein dA, dB, dC represent source driver data intended for source driver A, B, and C, respectively.

Each source driver is typically characterized by a minimum or nominal cycle time. This cycle time represents the minimum or nominal amount of time that a source driver requi^¬ res to clock and/or process the source driver data. The clock frequency preferably corresponds to the maximum cycle time among the minimum or nominal cycle times of the source dri^¬ vers. This ensures that each separate clock signal is below the cycle time of the source driver it is intended for. It is noted that mostly all nominal cycle times of the source dri^¬ vers are the same; in such a case the maximum cycle time is equal to all minimum cycle times.

Preferably, the number of source drivers n is greater than 2, such as 3, 4, 5, 6, 7, or more.

The TCON may be further provided with a latch output for outputting a latch enable signal. Each of the source dri- vers may be provided with a latch input for receiving the latch enable signal, a multi-bit shift register in which the source driver data can be clocked, a latch for receiving and holding multiple bits from the multi-bit shift register when a latch enable signal is received through the latch input, and a digital-to-analog converter and/or level shifter and/or multiplexer for converting and/or level shifting and/or multiplexing the multiple bits that are held by the latch into source voltages for the respective source lines connected to the source driver.

The TCON is preferably configured to output the latch enable signal to each source driver once each source driver has received enough source data packets to completely fill its multi-bit shift register and/or to address all of its connected source lines. In some embodiments, a source driver may be connected to less source lines than its shift register allows for. For instance, a source driver may ad^¬ dress 350 source lines using 2 bits per source line, whereas its shift register is 800 bits. This means that 100 bits remain unused. In this case, a latch enable signal is provi^¬ ded when 700 bits are received for that source driver. The shift register could be reset once the latch enable signal has been received and removed to start a new cycle with the first bit of the shift register.

Each source driver preferably comprises a chip se^¬ lect input for receiving a chip select signal, wherein each source driver is configured to only clock source driver data when the chip select signal is active.

Each source driver preferably comprises an output enable input for receiving an output enable signal, wherein each source driver is preferably configured to only output the source voltages in dependence of the clocked source dri^¬ ver data as defined above when the output enable signal is active and to output predefined source voltages independent of clocked or provided source driver data when the output enable signal is inactive.

The wording active and inactive typically correspond to logical high and low levels, respectively. It should be noted however that the situation may be reversed or that in^¬ termediate analog voltage levels may be assigned to the acti^¬ ve and inactive levels.

The clock signal system may comprise a clock signal generator to generate a single clock signal having a second clock frequency equal to the predefined clock frequency divi^¬ ded by n, and an n bit serial in parallel out shift register, wherein an input of the n bit shift register is connected to the clock signal generator. Here, the n outputs of the n bit shift register will each output a signal having the predefi^¬ ned clock frequency. In an example the clock has a frequency of 100 Hz, there are two drivers, each 1 bit band width. The clock frequency per driver is than 100/2 Hz=50 Hz, i.e. every 1/50 second each driver receives 1 bit. In an example the clock has a frequency of 100 Hz, there are two drivers, each 2 bits band width. The clock frequency per driver is than (100/2) /2 Hz=25 Hz, i.e. every 1/25 second each driver receives 2 bits. In an example the clock has a frequency of 100 Hz, there are four drivers, each 2 bits band width. The clock frequency per driver is than (100/4) /2 Hz=12.5 Hz, i.e. every 1/12.5 second each driver receives 2 bits. Each part of a se^¬ cond in the above examples is than divided in n (1, 2 or 4, respectively) equal parts.

The clock signal system may comprise a clock signal generator to generate a single clock signal having the prede^¬ fined clock frequency, the clock signal system further comprising n-1 delay circuits, each delay circuit being configu^¬ red to delay the single clock signal and to output the delay- ed clock signal to a respective source driver of the n source drivers. Consequently, one source driver is or can be fed di^¬ rectly with the clock signal whereas the other source drivers are fed with a delayed version of this clock signal.

Each delay circuit may have an identical topology. Preferably, the delay circuit is configured to allow a delay to be set. Circuit topologies allowing an operating parameter to be set are known in the art. For example, the delay may be programmed into the delay circuit prior to operating the source driver, for instance as part of the manufacturing pro- cess of the display. Other topologies require the connection of an external component, such as a resistor, by which the delay can be determined, for instance using discrete steps or values . The clock signal system may be arranged in the TCON. Alternatively, a dedicated clock signal generator arranged outside the TCON may be used. Furthermore, each delay circuit may also be arranged in the timing controller. Alternatively, each delay circuit may be arranged in its corresponding sour^¬ ce driver.

A second aspect of the present invention is related to a timing controller suitable for a driver for an electronic paper (e-paper) display, wherein the timing controller is configured as defined above.

A third aspect of the present invention is related to a source driver suitable for a driver for an electronic paper (e-paper) display, wherein the source driver is configured as defined above.

A fourth aspect of the present invention is related to an e-paper display comprising the driver as defined above.

A sixth aspect of the present invention is related to a method for driving an electronic paper (e-paper) display, comprising:

providing n source drivers, with n being an integer greater than 1 ;

generating a clock signal for the source drivers ha^¬ ving a predefined clock frequency;

providing source driver data to each of n source drivers in dependence of a desired image to be displayed next on the e-paper display;

clocking a packet of source driver data during a single clock cycle of the clock signal;

According to the invention, the method is characte- rized in that generating a clock signal comprises generating a separate clock signal for each source driver, wherein the separate clock signals are phase shifted with respect to each other by m times 360/Ώ degrees, with m being an integer ranging from 1 to (n-1) , and in that providing source driver da- ta comprises providing source driver data at a rate corres^¬ ponding to n times the clock frequency and providing packets for the different source drivers in an alternated manner such that each source driver receives a packet of source driver data intended for that source driver during a single clock cycle .

FIGURES

Next, the present invention will be described in mo- re detail referring to the appended drawings, wherein:

Figure 1 illustrates a known driver system;

Figure 2 shows a timing diagram corresponding to the known driver system depicted in figure 1 ;

Figure 3 illustrates an embodiment of a driver system accor- ding to the invention;

Figure 4 shows a timing diagram corresponding to the driver system depicted in figure 3;

Figure 5 shows an embodiment of a source driver according to the present invention; and

Figure 6 shows an embodiment of a timing controller according to the present invention.

Figure 3 illustrates an embodiment of a driver sys^¬ tem according to the invention. It comprises a timing controller 100 which is configured as illustrated in figure 1, except for the fact the chip select signal pins are not con^¬ nected. Clock signal 109 is fed directly to source driver 107, whereas source driver 108 receives the clock signal af^¬ ter it has been delayed by 180 degrees by delay unit 120. Both source drivers 107, 108 have their chip select signal inputs connected in such a way that both source drivers 107, 108 are always selected. As will be elucidated later, accor^¬ ding to the invention, there is no need to individually se^¬ lect a source driver 107, 108.

Next, the operation of the driver in figure 3 will be explained referring to the timing diagram in figure 4.

Starting at t=0, data on data bus 6 is changed. Af^¬ ter t=0, the data on data bus 6 is intended for the first source driver, i.e. source driver 107.

At the first rising edge of clock signal 1 after t=0, data will be clocked into source driver 107. Instead of repeating this process until the shift register of source driver 107 is filled, data is put on data bus 6 that is in^¬ tended for source driver 108. After the data is clocked, data is put on the data bus intended for source driver 107 again. As can be seen, packets for different source drivers 107, 108 are alternately placed on data bus 6. This process has to be repeated several times until the shift register for each source driver 107, 108 is filled. Once the shift registers of both source drivers 107, 108 are filled, a high latch enable signal 12 is applied. This causes the data in the shift re^¬ gister of source drivers 107, 108 to be copied or moved into latches in source drivers 107, 108. The data in these latches is level shifted or converted to analog signals such that ap^¬ propriate voltages are applied to source lines S1-S800. The^¬ reafter, gate driver 5 can be controlled to address a next gate line G1...G1024 and the process of addressing the pixels can be repeated.

It is noted that the clock frequency of the clock signals in figure 2 and 4 is identical. By comparing figures 2 and 4, it can be concluded that the data transfer rate on data bus 6 is doubled in figure 4 when compared to figure 2.

Figure 5 shows an embodiment of a source driver ac- cording to the present invention. For illustrational purposes it will be assumed that this source driver is configured to operate on a 4-bit data bus bl..b4 and is configured to drive

4 source lines sl..s4. Each source line should be supplied with at least 3 different voltage levels. It will be appreci- ated by the skilled person, that the source driver in figure

5 can easily be upscaled to handle more source lines and/or operate on a wider data bus .

As illustrated, source driver 200 comprises an 8-bit shift register 201 that is connected to four 2-bit latches 202 - 205. Latches 202 - 205 are connected to respective le^¬ vel shifters 206 - 209 that transform values held in latches 202 - 205 into voltages to put on source lines sl...s4. Source driver 200 further comprises a delay unit 210 of which a de^¬ lay can be set either programmatically or by connecting an appropriate resistor 211 externally to source driver 200.

Latches 202 - 205 are each electrically connected to the same latch enable signal pin. Once a latch enable signal is received, data will be fetched from shift register 201 to be held in latches 202 - 205.

Level shifters 206 - 209 are each electrically con^¬ nected to the same output enable signal pin. If an active output enable signal is received, the operation of level shifter 206 - 209 is that as described above. However, if an inactive output enable signal is received, a predefined vol^¬ tage is applied to source lines sl...s4.

As can be seen in figure 5, two bits are used to ad^¬ dress 1 source line. This allows 4 possible voltages to be generated for the source line.

Figure 6 shows an embodiment of a timing controller according to the present invention. Timing controller 300 comprises a single clock signal generator 301 that is con^¬ nected to three different delay units 302, 303, 304 that each delay the clock signal from clock signal generator 301 by multiples of 90 degrees, i.e. 90, 180, and 270 degrees. Each of these delayed signals is fed to the outside, as well as the original clock signal, via output pins 310-313. Timing controller 300 is configured to drive 4 source drivers in ac- cordance with the present invention.

Timing controller 300 further comprises a data processor 305 for generating the data to be put on the data bus via output bus 320. The data that is outputted by data pro^¬ cessor 305 depends inter alia on waveforms contained in wave- form memory 3, inputted image or video data 2, and current or desired pixel status information comprised in memory 306.

Although the present invention has been described using detailed embodiments thereof, it should be apparent to the skilled person that various modifications may be possible without departing from the scope of the present invention which is defined by the appended claims.

Claims

1. A driver system for an electronic paper (e-paper) display, comprising:

n source drivers, with n being an integer greater than 1, wherein each source driver is arranged for applying respective source voltages to a plurality of different source lines of an active matrix of the e-paper display, each source driver being configured to output the respective source vol^¬ tages in dependence of source driver data that has been clocked into said source driver using a clock signal;

a clock signal system for generating a clock signal for the source drivers, the clock signal having a predefined clock frequency;

wherein each source driver is configured to clock a packet of source driver data during a single clock cycle of the clock signal;

characterized in that

a single timing controller (TCON) configured to pro^¬ vide the source driver data to all the n source drivers in dependence of a desired image to be displayed next on the e- paper display;

the clock signal system is configured to generate a separate clock signal for each source driver, said separate clock signals being phase shifted with respect to each other by m times 360/Ώ degrees, with m being an integer ranging from 1 to (n-1) ;

and in that the TCON is configured to output the source driver data at a rate corresponding to n times the clock frequency, said TCON being further configured to output the packets for the different source drivers in an alternated manner such that each source driver receives a packet of source driver data intended for that source driver during a single clock cycle.

2. The driver system according to claim 1, wherein each source driver is configured to clock source driver data intended for that source driver when it detects an edge in the respective clock signal, and/or wherein each source dri- ver comprises a chip select input for receiving a chip select signal, wherein each source driver is configured to only clock source driver data when the chip select signal is acti^¬ ve .

3. The driver system according to claim 1 or 2, wherein the packets outputted by the TCON are arranged in an order that corresponds to the order in delay of the separate clock signals.

4. The driver system according to any of the previ- ous claims, wherein each source driver is characterized by a minimum cycle time, said cycle time being the minimum amount of time that a source driver requires to clock and/or process the source driver data, and wherein the clock frequency cor^¬ responds to the maximum of the minimum cycle times of the source drivers.

5. The driver system according to any of the previous claims, wherein the TCON is further provided with a latch output for outputting a latch enable signal, and wherein each of the source drivers is provided with:

a latch input for receiving said latch enable signal ;

a multi-bit shift register in which the source dri^¬ ver data can be clocked;

a latch for receiving and holding multiple bits from the multi-bit shift register when a latch enable signal is received through the latch input; and

a digital-to-analog converter and/or level shifter and/or multiplexer for converting and/or level shifting and/or multiplexing the multiple bits that are held by the latch into source voltages for the respective source lines connected to the source driver,

preferably wherein the TCON is configured to output the latch enable signal to each source driver once each sour^¬ ce driver has received enough source data packets to comple- tely fill its multi-bit shift register and/or to address all of its connected source lines.

6. The driver system according to any of the previous claims, wherein each source driver comprises an output enable input for receiving an output enable signal, wherein each source driver is preferably configured to only output the source voltages in dependence of the clocked source dri^¬ ver data as defined in any of the previous claims when the output enable signal is active and to output predefined sour^¬ ce voltages independent of clocked or provided source driver data when the output enable signal is inactive.

7. The driver system according to any of the previous claims, wherein the clock signal system comprises a clock signal generator to generate a single clock signal having a second clock frequency equal to the predefined clock frequen^¬ cy divided by n, and an n bit serial in parallel out shift register, wherein an input of the n bit shift register is connected to the clock signal generator.

8. The driver system according to any of the claims

1-9, wherein the clock signal system comprises a clock signal generator to generate a single clock signal having the prede^¬ fined clock frequency, the clock signal system further comprising n-1 delay circuits, each delay circuit being configu- red to delay the single clock signal and to output the delay^¬ ed clock signal to a respective source driver of said n sour^¬ ce drivers .

preferably wherein each delay circuit has an identi^¬ cal topology, said delay circuit being configured to allow a delay to be set.

9. The driver system according to any of claims 7-8, wherein the clock signal system is arranged in the TCON.

10. The driver system according to claim 7 or 8, wherein each delay circuit is arranged in the timing control- ler, or

wherein each delay circuit is arranged in its cor^¬ responding source driver.

11. A timing controller suitable for a driver for an electronic paper (e-paper) display, wherein the timing con- troller is configured as defined in claim 9 or 10.

12. A source driver suitable for a driver for an electronic paper (e-paper) display, wherein the source driver is configured as defined in claim 10.

13. An e-paper display comprising the driver system as defined in any of the claims 1-10.

14. A method for driving an electronic paper (e- paper) display such as of claim 13, comprising:

providing n source drivers, with n being an integer greater than 1 ;

characterized in that

said generating a clock signal comprises generating a separate clock signal for each source driver, said separate clock signals being phase shifted with respect to each other by m times 360/Ώ degrees, with m being an integer ranging from 1 to (n-1 ) ;

and in that providing source driver data comprises providing source driver data at a rate corresponding to n times the clock frequency and providing packets for the diffe^¬ rent source drivers in an alternated manner such that each source driver receives a packet of source driver data inten- ded for that source driver during a single clock cycle.