NL2012985B1

NL2012985B1 - Electronic paper display driver system.

Info

Publication number: NL2012985B1
Application number: NL2012985A
Authority: NL
Inventors: Wiermans Daniël
Original assignee: Hj Forever Patents B V
Priority date: 2014-06-11
Filing date: 2014-06-11
Publication date: 2016-07-04
Also published as: WO2015190925A3; WO2015190925A4; WO2015190925A2

Abstract

The present invention is related to a driver for an electronic paper (e-paper) display. It is further related to a source driver and a timing controlling that are configured to be used in a driver for an e-paper display. It is also related to an e-paper display and to a method for driving an epaper display. According to the invention, the clock signal system is configured to generate a separate clock signal for each of the n source drivers, wherein the separate clock signals are phase shifted with respect to each other by m times 360/n degrees, with m being an integer ranging from 1 to (n- 1). Furthermore, the timing controller is configured to output the source driver data at a rate corresponding to n times the clock frequency, said TCON being further configured to output the packets for the different source drivers in an alternated manner such that each source driver receives a packet of source driver data intended for that source driver during a single clock cycle.

Description

Electronic paper display driver system

The present invention is related to a driver system for an electronic paper (e-paper) display. It is further related to a source driver and a timing controlling that are configured to be used in a driver system for an e-paper display. It is also related to an e-paper display and to a method for driving an e-paper display. E-paper displays employ display technologies that rely on active matrices to control the pixels. An active matrix typically comprises a plurality of source lines and a gate line. Thin film transistors are arranged at the crossing points of the source lines and gate line. By driving the source lines and the gate line, the transistor can be switched between states and the pixel can be driven accordingly. A known display technology for e-paper displays is that of electrophoretic displays. In this type of displays, charged pigment particles in a pixel are moved in dependence on the voltages generated in that pixel. Depending on the movement of the pixel and the pigment type a particular appearance of a pixel can be obtained such as black, white, colored or transparent.

Source drivers are used for applying the required voltages on the source lines. For electrophoretic displays, a source driver is typically configured to drive a plurality of source lines, e.g. 200 or more. The source driver receives source driver data that is put on a data bus by a timing controller (TCON). When an edge, such as a rising edge, is detected in the clock signal that is supplied to the source driver by a clock signal system, the data on the data bus is clocked into a multi-bit shift register comprised in the source driver. This data is subsequently shifted to allow further data to be clocked during a next clock cycle. Once the shift register is filled with data, a latch enable signal is supplied to the source driver. The source driver will then move or copy the data comprised in the shift register to a latch. The latter will hold the data until it is filled with new data. A digital-to-analog converter or level shifter is used to convert or level shift the data in the latch into source voltages to be applied to the source lines.

In electrophoretic displays, a particular color or shade of grey is obtained by applying a waveform to a pixel. Such waveform typically comprises a plurality of voltage levels that are sequentially applied to a pixel, e.g. +15V, 0V, 0V, +15V etc. The charged pigment particles will move according to the applied waveform. Based on the applied waveform and on the state of the pixel prior to applying the waveform, e.g. the previous image, a particular color or shade of grey may be obtained. Special waveforms, the so-called flashing waveforms, may be applied to ensure that a pixel achieves a particular shade of grey or color independently of the previous state of the pixel. During use, such flashing waveforms may be used to reset the display to avoid color drifting.

Most source drivers use multiple bits to address a single source line. This makes it possible to generate multiple voltage levels such as -15V, OV, +15V or intermediate values if desired.

Figure 1 illustrates an example of a known driver system for an electrophoretic display. In this example, a timing controller 1 receives image or video data 2 from an image source. This data may comprise a bitmap or a part thereof representative of an image to be displayed next on the display. The data comprises information regarding a plurality of pixels. This information may comprise a desired color and/or intensity.

Based on received data 2, timing controller 1 computes the voltages that need to be applied to source lines S1-S800. To that end, it uses a waveform memory 3 in which waveforms are stored that specify how a particular color transition can be achieved, e.g. a black-to-white transition or vice versa. As an example, if a display is arranged to display 16 shades of grey, the waveform memory may comprise 240 different waveforms. These waveforms represent each possible transition excluding transitions between identical colors. Timing controller 1 may further comprise or may be connected to a memory (not shown) in which the current status or desired status of a pixel or pixels is stored.

Timing controller 1 further outputs a voltage to a gate driver 5. Gate driver 5 typically applies a high voltage to one gate line of the active matrix and a low voltage to the other gate lines at a time or vice versa. In such manner, pixels are addressed one gate line at a time.

Timing controller 1 is connected via a data bus 6 to source drivers 7, 8. In figure 1, timing controller 1 comprises a clock signal generator for outputting a clock signal 9. Timing controller 1 further outputs 2 separate chip select signals 10, 11.

Next, the operation of the driver in figure 1 will be explained referring to the timing diagram in figure 2.

Starting at t=0, data on data bus 6 is changed. After t=0, the data on data bus 6 is intended for the first source driver, i.e. source driver 7. This is indicated by chip select signal CS 1 which is high at that time. Source drivers 7, 8 are configured to clock the data on data bus 6 only when they receive a high and/or active chip select signal.

At the first rising edge of clock signal 9 after t=0, data will be clocked into source driver 7. Assuming an 8 bit data bus, 8 bits of data will be clocked. These 8 bits are referred to as a packet of source driver data. This process has to be repeated several times until the shift register is filled. Then, source driver 8 will be selected by making chip select signal 10 low and chip select signal 11 high. Thereafter, data will be clocked into source driver 8. Once the shift registers of both source drivers 7, 8 are filled, a high latch enable signal 12 is applied. This causes the data in the shift register of source drivers 7, 8 to be copied or moved into latches in source drivers 7, 8. The data in these latches is level shifted such that appropriate voltages are applied to source lines S1-S800. Thereafter, the gate driver can be controlled to address a next gate line and the process of addressing the pixels can be repeated. A continuing demand for any display technology is to increase the rate at which images can be displayed, the so-called frame rate. A further demand for display technologies in general is to increase the resolution with which images can be displayed. It can be appreciated that a high data throughput is of the utmost importance when both demands are to be met simultaneously.

Current source driver technology allows for given maximum rate at which data can be clocked, the so-called cycle time. A solution to increase the data throughput at this rate even further is to allow for a wider data bus as this would increase the number of bits that can be clocked in a given cycle.

Widening the data bus is not without expense. Routing a wide data bus on the substrate of the display panel may increase the distance between the edge of the substrate and the actual active area, resulting in a widening of the edge (e.g. bevel) of the display. This may be esthetically unappealing. A second disadvantage of widening the data bus is related to the required pin count of the timing controller. The costs for the timing controller increase sharply when the pin count is increased. The same holds for the connectors used in the system. Typically, a flexible carrier or foil is used to transport the data bus and control signals between the PCB on which the timing controller is mounted and the source and gate drivers which are arranged on the substrate of the display panel. A connector is used to connect the foil to the PCB. Widening the data bus increases the costs of such connector. Moreover, routing a wider data bus becomes cumbersome.

Finally, at high rates, the width of the data bus needs to be compensated for as the time required for a signal to pass through one line of the data bus depends on the position of this line in the data bus.

An object of the present invention is provide a driver system that allows the display to operate at higher resolutions and/or frame rates without or minimizing widening of the data bus. A first aspect of the invention by which this object has been achieved is related to a driver system as defined in appended claim 1. According to the present invention, the driver system is characterized in that the clock signal system is configured to generate a separate clock signal for each source driver, said separate clock signals being phase shifted with respect to each other by m times 360In degrees, with m being an integer ranging from 1 to (n-1), and n being the number of source drivers.

The driver system is further characterized in that the TCON is configured to output the source driver data at a rate corresponding to n times the clock frequency, said TCON being further configured to output the packets for the different source drivers in an alternated manner such that each source driver receives a packet of source driver data intended for that source driver during a single clock cycle.

The applicant has realized that for present source drivers the time required for the data to be present on the data bus prior to the clock edge if setup) and the time for the data to remain present on the data bus after the clock edge (thold) is negligible compared to the cycle time (tcycle) of the source driver. Consequently, more source drivers can be used within a given cycle. This is made possible by using dedicated clock signals having the same predefined clock frequency but which are delayed with respect to each other. The number of source drivers n that can be used can be roughly approximated by n - tcycle / (thold + tsetup).

Using more source drivers allows a higher resolution to be obtained. On the other hand, if a current display requires 2 source drivers each driving 400 source lines, the data bus rate can be doubled by using 4 source drivers each driving 200 source lines, wherein the source drivers have similar cycle times.

The present invention allows the number or size of source drivers to be optimized for a given display resolution and/or intended frame rate without or minimizing the widening of the data bus.

Each source driver is preferably configured to clock source driver data intended for that source driver when it detects an edge in the respective clock signal. The edge is preferably a rising edge of the clock signal. When a clock signal for a given source driver displays an edge for the clocking of data, it is ensured that the data which is available on the data bus at that moment, corresponds to data intended for that source driver. Compared to the driver illustrated in figure 1, there is no need to work with chip select signals to alternately select a given source driver. In practice, all source drivers may be selected simultaneously.

The packets outputted by the TCON are preferably arranged in an order that corresponds to the order in delay of the separate clock signals. For instance, when source drivers A, B, and C are supplied with clock signals, fA, fB, and fC, respectively, wherein fC is delayed by 120 degrees compared to fB, which in turn is delayed by 120 degrees compared to fA, the order in which data is outputted by the TCON is given by: dA, dB, dC, dA, dB, dC, dA ... etc, wherein dA, dB, dC represent source driver data intended for source driver A, B, and C, respectively.

Each source driver is typically characterized by a minimum or nominal cycle time. This cycle time represents the minimum or nominal amount of time that a source driver requires to clock and/or process the source driver data. The clock frequency preferably corresponds to the maximum cycle time among the minimum or nominal cycle times of the source drivers. This ensures that each separate clock signal is below the cycle time of the source driver it is intended for.

Preferably, the number of source drivers n is greater than 2, such as 3, 4, 5, 6, 7, or more.

The TCON may be further provided with a latch output for outputting a latch enable signal. Each of the source drivers may be provided with a latch input for receiving the latch enable signal, a multi-bit shift register in which the source driver data can be clocked, a latch for receiving and holding multiple bits from the multi-bit shift register when a latch enable signal is received through the latch input, and a digital-to-analog converter and/or level shifter and/or multiplexer for converting and/or level shifting and/or multiplexing the multiple bits that are held by the latch into source voltages for the respective source lines connected to the source driver.

The TCON is preferably configured to output the latch enable signal to each source driver once each source driver has received enough source data packets to completely fill its multi-bit shift register and/or to address all of its connected source lines. In some embodiments, a source driver may be connected to less source lines than its shift register allows for. For instance, a source driver may address 350 source lines using 2 bits per source line, whereas its shift register is 800 bits. This means that 100 bits remain unused. In this case, a latch enable signal is provided when 700 bits are received for that source driver. The shift register could be reset once the latch enable signal has been received and removed to start a new cycle with the first bit of the shift register.

Each source driver preferably comprises a chip select input for receiving a chip select signal, wherein each source driver is configured to only clock source driver data when the chip select signal is active.

Each source driver preferably comprises an output enable input for receiving an output enable signal, wherein each source driver is preferably configured to only output the source voltages in dependence of the clocked source driver data as defined above when the output enable signal is active and to output predefined source voltages independent of clocked or provided source driver data when the output enable signal is inactive.

The wording active and inactive typically correspond to logical high and low levels, respectively. It should be noted however that the situation may be reversed or that intermediate analog voltage levels may be assigned to the active and inactive levels.

The clock signal system may comprise a clock signal generator to generate a single clock signal having a clock frequency equal to the predefined clock frequency divided by n, and an n bit serial in parallel out shift register, wherein an input of the n bit shift register is connected to the clock signal generator. Here, the n outputs of the n bit shift register will each output a signal having the predefined clock frequency.

The clock signal system may comprise a clock signal generator to generate a single clock signal having the predefined clock frequency, the clock signal system further comprising η-1 delay circuits, each delay circuit being configured to delay the single clock signal and to output the delayed clock signal to a respective source driver of the n source drivers. Consequently, one source driver is or can be fed directly with the clock signal whereas the other source drivers are fed with a delayed version of this clock signal.

Each delay circuit may have an identical topology. Preferably, the delay circuit is configured to allow a delay to be set. Circuit topologies allowing an operating parameter to be set are known in the art. For example, the delay may be programmed into the delay circuit prior to operating the source driver, for instance as part of the manufacturing process of the display. Other topologies require the connection of an external component, such as a resistor, by which the delay can be determined, for instance using discrete steps or values.

The clock signal system may be arranged in the TCON. Alternatively, a dedicated clock signal generator arranged outside the TCON may be used. Furthermore, each delay circuit may also be arranged in the timing controller. Alternatively, each delay circuit may be arranged in its corresponding source driver. A second aspect of the present invention is related to a timing controller suitable for a driver for an electronic paper (e-paper) display, wherein the timing controller is configured as defined above. A third aspect of the present invention is related to a source driver suitable for a driver for an electronic paper (e-paper) display, wherein the source driver is configured as defined above. A fourth aspect of the present invention is related to an e-paper display comprising the driver as defined above. A sixth aspect of the present invention is related to a method for driving an electronic paper (e-paper) display, comprising: providing n source drivers, with n being an integer greater than 1; generating a clock signal for the source drivers having a predefined clock frequency; providing source driver data to each of n source drivers in dependence of a desired image to be displayed next on the e-paper display; clocking a packet of source driver data during a single clock cycle of the clock signal;

According to the invention, the method is characterized in that generating a clock signal comprises generating a separate clock signal for each source driver, wherein the separate clock signals are phase shifted with respect to each other by m times 360/« degrees, with m being an integer ranging from 1 to («-1), and in that providing source driver data comprises providing source driver data at a rate corresponding to n times the clock frequency and providing packets for the different source drivers in an alternated manner such that each source driver receives a packet of source driver data intended for that source driver during a single clock cycle.

Next, the present invention will be described in more detail referring to the appended drawings, wherein:

Figure 1 illustrates a known driver system;

Figure 2 shows a timing diagram corresponding to the known driver system depicted in figure 1;

Figure 3 illustrates an embodiment of a driver system according to the invention;

Figure 4 shows a timing diagram corresponding to the driver system depicted in figure 3;

Figure 5 shows an embodiment of a source driver according to the present invention; and

Figure 6 shows an embodiment of a timing controller according to the present invention.

Figure 3 illustrates an embodiment of a driver system according to the invention. It comprises a timing controller 100 which is configured as illustrated in figure 1, except for the fact the chip select signal pins are not connected. Clock signal 109 is fed directly to source driver 107, whereas source driver 108 receives the clock signal after it has been delayed by 180 degrees by delay unit 120. Both source drivers 107, 108 have their chip select signal inputs connected in such a way that both source drivers 107, 108 are always selected. As will be elucidated later, according to the invention, there is no need to individually select a source driver 107, 108.

Next, the operation of the driver in figure 3 will be explained referring to the timing diagram in figure 4.

Starting at t=0, data on data bus 6 is changed. After t=0, the data on data bus 6 is intended for the first source driver, i.e. source driver 107.

At the first rising edge of clock signal 1 after t=0, data will be clocked into source driver 107. Instead of repeating this process until the shift register of source driver 107 is filled, data is put on data bus 6 that is intended for source driver 108. After the data is clocked, data is put on the data bus intended for source driver 107 again. As can be seen, packets for different source drivers 107, 108 are alternately placed on data bus 6. This process has to be repeated several times until the shift register for each source driver 107, 108 is filled. Once the shift registers of both source drivers 107, 108 are filled, a high latch enable signal 12 is applied. This causes the data in the shift register of source drivers 107, 108 to be copied or moved into latches in source drivers 107, 108. The data in these latches is level shifted or converted to analog signals such that appropriate voltages are applied to source lines S1-S800. Thereafter, gate driver 5 can be controlled to address a next gate line G1...G1024 and the process of addressing the pixels can be repeated.

It is noted that the clock frequency of the clock signals in figure 2 and 4 is identical. By comparing figures 2 and 4, it can be concluded that the data transfer rate on data bus 6 is doubled in figure 4 when compared to figure 2.

Figure 5 shows an embodiment of a source driver according to the present invention. For illustrational purposes it will be assumed that this source driver is configured to operate on a 4-bit data bus bl..b4 and is configured to drive 4 source lines sl..s4. Each source line should be supplied with at least 3 different voltage levels. It will be appreciated by the skilled person, that the source driver in figure 5 can easily be upscaled to handle more source lines and/or operate on a wider data bus.

As illustrated, source driver 200 comprises an 8-bit shift register 201 that is connected to four 2-bit latches 202 - 205. Latches 202 - 205 are connected to respective level shifters 206 - 209 that transform values held in latches 202 - 205 into voltages to put on source lines si.. .s4. Source driver 200 further comprises a delay unit 210 of which a delay can be set either programmatically or by connecting an appropriate resistor 211 externally to source driver 200.

Latches 202 - 205 are each electrically connected to the same latch enable signal pin. Once a latch enable signal is received, data will be fetched from shift register 201 to be held in latches 202 - 205.

Level shifters 206 - 209 are each electrically connected to the same output enable signal pin. If an active output enable signal is received, the operation of level shifter 206 - 209 is that as described above. However, if an inactive output enable signal is received, a predefined voltage is applied to source lines si.. .s4.

As can be seen in figure 5, two bits are used to address 1 source line. This allows 4 possible voltages to be generated for the source line.

Figure 6 shows an embodiment of a timing controller according to the present invention. Timing controller 300 comprises a single clock signal generator 301 that is connected to three different delay units 302, 303, 304 that each delay the clock signal from clock signal generator 301 by multiples of 90 degrees, i.e. 90, 180, and 270 degrees. Each of these delayed signals is fed to the outside, as well as the original clock signal, via output pins 310-313. Timing controller 300 is configured to drive 4 source drivers in accordance with the present invention.

Timing controller 300 further comprises a data processor 305 for generating the data to be put on the data bus via output bus 320. The data that is outputted by data processor 305 depends inter alia on waveforms contained in waveform memory 3, inputted image or video data 2, and current or desired pixel status information comprised in memory 306.

Although the present invention has been described using detailed embodiments thereof, it should be apparent to the skilled person that various modifications may be possible without departing from the scope of the present invention which is defined by the appended claims.

Claims

A driver system for an electronic paper (e-paper) display, comprising: n source drivers, wherein n is an integer greater than 1, wherein each source driver is adapted to apply respective source voltages to a plurality of different source lines of an active matrix of the e-paper display, wherein each source driver is adapted to output the respective source voltages in dependence on source driver data clocked in said source driver using a clock signal; a timing control unit (TCON) adapted to provide the source driver data to the source drivers in dependence on a desired image to be subsequently displayed on the e-paper display; a clock signal system for generating a clock signal for the source drivers, the clock signal having a predetermined clock frequency; wherein each source driver is arranged to clock a packet of source driver data during a single clock cycle of the clock signal; characterized in that the clock signal system is adapted to generate a separate clock signal for each source driver, said individual clock signals being mutually phase-shifted by m times 360 In degrees, where m is an integer ranging from 1 to ( n -1); and that the TCON is arranged to output the source driver data at a speed corresponding to n times the clock frequency, the TCON being further adapted to output the packets for the different source drivers in an alternating manner such that each source driver receives a packet of source driver data intended for that source driver during a single clock cycle.

The driver system of claim 1, wherein each source driver is arranged to clock source driver data intended for that source driver when it detects an edge in the respective clock signal.

The driver system according to claim 1 or 2, wherein the packets executed by the TCON are placed in a sequence corresponding to the sequence in delay of the individual clock signals.

Driver system according to one of the preceding claims, wherein each source driver is characterized by a minimum or nominal cycle time, said cycle time being the minimum or nominal time required by a source driver for clocking and / or processing the source driver data, and where the clock frequency corresponds to the maximum cycle time below the minimum or nominal cycle time of the source drivers.

Driver system according to one of the preceding claims, wherein n is greater than 2.

A driver system according to any one of the preceding claims, wherein the TCON is further provided with a buffer output for outputting a buffer active signal, and wherein each of the source drivers is provided with: a buffer input for receiving said buffer active signal; a multi-bit shift register in which the source driver data can be clocked; a buffer for receiving and holding multiple bits from the multi-bit shift register when a buffer active signal is received by the buffer input; and a digital-to-analog converter and / or level shifting unit and / or multiplexer for converting and / or level shifting and / or multiplexing the multiple bits held by the buffer in source voltages for the respective source lines connected to the source driver.

The driver system of claim 6, wherein the TCON is arranged to output the buffer active signal to each source driver when each source driver has received enough source driver data packets to completely fill its multi-bit shift register and / or all of them connected source lines.

A driver system according to any preceding claim, wherein each source driver has a chip select input for receiving a chip select signal, each source driver being arranged to clock in source driver data only when the chip select signal is active.

A driver system according to any one of the preceding claims, wherein each source driver has an output active input for receiving an output active signal, wherein each source driver is preferably arranged to output only the source voltages in dependence on the clocked source driver data as defined in any one of the preceding claims when the output active signal is active and to output predetermined source voltages which are independent of clocked in or provided source driver data when the output active signal is inactive.

10. Driver system according to one of the preceding claims, wherein the clock signal system comprises a clock signal generator for generating a single clock signal which has a clock frequency equal to the predetermined clock frequency divided by n, and an n bit serially in-parallel from shift register wherein an input from the n bit shift register is connected to the clock signal generator.

The driver system of any one of claims 1-9, wherein the clock signal system comprises a clock signal generator for generating a single clock signal having the predetermined clock frequency, the clock signal system further comprising η-1 delay circuits, each delay circuit being arranged to delay the single clock signal and to output the delayed clock signal to a respective source driver of said n source drivers.

The driver system of claim 11, wherein each delay circuit has an identical topology, said delay circuit being arranged to allow a delay to be set.

The driver system of claim 10 or 11 or 12, wherein the clock signal system is placed in the TCON.

The driver system of claim 10 or 11, wherein each delay circuit is located in the timing control unit.

The driver system of claim 10 or 11, wherein each delay circuit is placed in its corresponding source driver.

A timing controller suitable for an electronic paper (e-paper) display driver, the timing controller being arranged as defined in claim 13 or 14.

A source driver controller suitable for a driver for an electronic paper (e-paper) display, the source driver being arranged as defined in claim 15. E-paper display comprising the driver system as defined in any one of claims 1 -15.

A method of controlling an electronic paper (e-paper) display, comprising: providing n source drivers, with n an integer greater than 1; generating a clock signal for the source drivers which has a predetermined clock frequency; providing source driver data to each of the n source drivers in dependence on a desired image to be subsequently displayed on the e-paper display; clocking a packet of source driver data during a single clock cycle of the clock signal; characterized in that said generating a clock signal comprises generating a separate clock signal for each source driver, said individual clock signals being mutually phase-shifted by m times 360 / «degrees, where m is an integer ranging from 1 to (n-1); and in that providing source driver data comprises providing source driver data at a speed corresponding to n times the clock frequency and providing packets for the different source drivers in an alternate manner such that each source driver receives a packet of source driver data which is intended for that source driver during a single clock cycle.