WO2015190147A1 - Clock signal outputting device, control device, and endoscope - Google Patents

Clock signal outputting device, control device, and endoscope Download PDF

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Publication number
WO2015190147A1
WO2015190147A1 PCT/JP2015/057949 JP2015057949W WO2015190147A1 WO 2015190147 A1 WO2015190147 A1 WO 2015190147A1 JP 2015057949 W JP2015057949 W JP 2015057949W WO 2015190147 A1 WO2015190147 A1 WO 2015190147A1
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Prior art keywords
clock signal
endoscope
amplitude
signal output
subject
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PCT/JP2015/057949
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French (fr)
Japanese (ja)
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浩一郎 田渕
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オリンパス株式会社
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Priority to JP2015560899A priority Critical patent/JPWO2015190147A1/en
Priority to CN201590000676.9U priority patent/CN206063121U/en
Publication of WO2015190147A1 publication Critical patent/WO2015190147A1/en

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    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B1/00—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor
    • A61B1/04—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor combined with photographic or television appliances
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B23/00—Telescopes, e.g. binoculars; Periscopes; Instruments for viewing the inside of hollow bodies; Viewfinders; Optical aiming or sighting devices
    • G02B23/24—Instruments or systems for viewing the inside of hollow bodies, e.g. fibrescopes

Definitions

  • the present invention relates to a clock signal output device, a control device including the clock signal output device, and an endoscope.
  • a clock signal which serves as a reference for the operation of each component, is generated on the processor side and transmitted to an image sensor provided at the distal end of the endoscope.
  • an imaging device of an endoscope has been increased in the number of pixels, and a digital imaging signal transmitted to a processor via a transmission cable has also become as high as about 3 Gbps. Under these circumstances, a high-quality clock signal having high noise resistance against phase noise is required to remove signal fluctuations called jitter.
  • EMI Electro Magnetic Interference
  • the output clock signal has a larger amplitude.
  • FIG. 10 is a diagram schematically illustrating differential transmission of a clock signal using CML.
  • CML Current Mode Logic
  • the two open collector circuits 201 and 202 are driven by being pulled up with the power supply voltage Vcc .
  • Vcc the power supply voltage
  • the noise appears as phase noise of the clock signal.
  • FIG. 11 is a diagram schematically showing the differential transmission of the clock signal when the amplitude of the clock signal is adjusted by adjusting the gain using a high-speed analog differential amplifier.
  • the high-speed analog differential amplifier 203 shown in FIG. 11 can improve the noise tolerance of the phase noise, for example, when the amplitude is reduced, the rounding of the clock signal due to transmission becomes remarkable, and the slew rate is deteriorated. Resulting in.
  • FIG. 12 is a diagram schematically showing differential transmission of a clock signal when amplitude adjustment is performed by changing the power supply voltage of the high-speed analog differential amplifier.
  • the waveform is distorted near the upper and lower limits of the power supply voltage due to the transmission of the clock signal. Phase noise will get worse.
  • the present situation is that no technology has been found to realize a high-quality clock signal in the endoscope while sufficiently satisfying the unique requirements of the endoscope.
  • the present invention has been made in view of the above, and an object of the present invention is to provide a clock signal output device, a control device, and an endoscope that can realize high-quality clock signals in an endoscope. To do.
  • a clock signal output device is inserted through a distal end portion of an endoscope that is inserted into a subject and images the inside of the subject and a signal transmission path.
  • a clock signal output device for outputting a clock signal serving as a reference for operation to the tip portion, a signal generator for generating the clock signal, and amplifying the amplitude of the clock signal to a set value
  • An amplification unit ; and an amplitude limiting unit that outputs the clock signal by limiting the amplitude of the clock signal to a limit value less than the set value by changing an upper limit and a lower limit of the clock signal amplified by the amplifier unit. It is characterized by.
  • the clock signal output device is characterized in that, in the above invention, the amplitude limiter can change the limit value.
  • the clock signal output device is characterized in that, in the above invention, the limit value is determined in accordance with characteristics of the endoscope.
  • the clock signal output device is characterized in that, in the above invention, the clock signal output device includes two sets each having the amplification unit and the amplitude limiting unit, and differentially outputs the two clock signals whose phases are inverted. .
  • a control device is a control device that is connected to an endoscope that is inserted into a subject and images the inside of the subject, and that controls the operation of the endoscope, the clock signal output described above
  • An apparatus and a changing unit that changes the limit value based on characteristics of the endoscope are provided.
  • An endoscope according to the present invention is an endoscope that is inserted into a subject and images the inside of the subject, and is provided at a distal end portion, and an imaging device that images the subject and outputs an imaging signal;
  • a connector that is connected to the imaging device via a signal transmission path and is connected to a control device that controls the operation of the endoscope, and that has the clock signal output device described above. It is characterized by that.
  • the endoscope according to the present invention is characterized in that, in the above invention, the connector includes a storage unit that stores characteristics of the endoscope, and a changing unit that changes the limit value based on the characteristics.
  • the clock signal amplitude is limited to a limit value less than the set value by changing the upper and lower limits of the clock signal amplitude, so that a clock signal with good phase noise and slew rate is output. can do. Therefore, it is possible to realize high quality clock signals in the endoscope.
  • FIG. 1 is a diagram showing an external configuration of an endoscope system according to Embodiment 1 of the present invention.
  • FIG. 2 is a block diagram showing a functional configuration of a main part of the endoscope system according to Embodiment 1 of the present invention.
  • FIG. 3 is a diagram illustrating a configuration example of a main part of the limiting amplifier.
  • FIG. 4 is a diagram schematically illustrating a clock signal output from the clock signal output unit.
  • FIG. 5 is a diagram illustrating a waveform of a clock signal received by the image sensor.
  • FIG. 6 is a block diagram illustrating a configuration of a main part of the endoscope system according to the modification of the first embodiment of the present invention.
  • FIG. 1 is a diagram showing an external configuration of an endoscope system according to Embodiment 1 of the present invention.
  • FIG. 2 is a block diagram showing a functional configuration of a main part of the endoscope system according to Embodiment 1 of the present invention.
  • FIG. 7 is a block diagram illustrating a configuration of a main part of the endoscope system according to the second embodiment of the present invention.
  • FIG. 8 is a block diagram illustrating a configuration of a main part of an endoscope system according to a modification of the second embodiment of the present invention.
  • FIG. 9 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to Embodiment 3 of the present invention.
  • FIG. 10 is a diagram schematically showing differential transmission of a clock signal using a conventional CML.
  • FIG. 11 is a diagram schematically showing the differential transmission of the clock signal when adjusting the amplitude of the clock signal by adjusting the gain using a conventional high-speed analog differential amplifier.
  • FIG. 12 is a diagram schematically showing differential transmission of a clock signal when amplitude adjustment is performed by changing a power supply voltage of a conventional high-speed analog differential amplifier.
  • FIG. 1 is a diagram showing an external configuration of an endoscope system according to Embodiment 1 of the present invention.
  • FIG. 2 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to the first embodiment.
  • An endoscope system 1 shown in FIGS. 1 and 2 has an endoscope 2 that captures an in-vivo image of a subject by inserting a distal end portion into the subject, and a predetermined in-vivo image captured by the endoscope 2.
  • a control device (processor) 3 that controls the overall operation of the endoscope system 1, a light source device 4 that generates illumination light emitted from the distal end of the endoscope 2, and a control device 3 includes a display device 5 that displays an in-vivo image subjected to image processing.
  • the endoscope 2 includes an insertion portion 21 having an elongated shape having flexibility, an operation portion 22 that is connected to a proximal end side of the insertion portion 21 and receives input of various operation signals, and an insertion portion from the operation portion 22.
  • a universal cord 23 that extends in a direction different from the direction in which 21 extends and incorporates a plurality of cables connected to the control device 3 or the light source device 4, and is provided at the base end portion of the universal cord 23.
  • the connector 24 is detachable, and includes a connector 24 that transmits and receives electrical signals to and from the control device 3 and passes light emitted from the light source device 4.
  • the clock signal cable built in the insertion portion 21 and the universal cord 23 constitutes a part of a signal transmission path in the endoscope 2.
  • the distal end portion 21a of the insertion portion 21 is provided with an imaging element 101 that has a plurality of pixels arranged on a two-dimensional matrix and photoelectrically converts received light to generate an imaging signal. Further, the distal end portion of the light guide 102 that forms a light guide path of the light emitted from the light source device 4 is inserted into the distal end portion 21a.
  • a condensing optical system is provided on the light receiving surface side of the image sensor 101, and an illumination optical system is provided on the tip side of the light guide 102.
  • the image sensor 101 is a CMOS having a sensor unit that photoelectrically converts light and outputs an electrical signal, and an analog front end (AFE) that performs noise removal and A / D conversion on the electrical signal output from the sensor unit, for example.
  • AFE Analog front end
  • the control device 3 generates an image processing unit 31 that performs predetermined image processing on an imaging signal sent from the endoscope 2 and generates a clock signal that serves as a reference for operation, and outputs the generated clock signal to the endoscope 2 and the like.
  • the image processing unit 31 performs at least part of processing such as synchronization processing, white balance (WB) adjustment processing, gain adjustment processing, gamma correction processing, digital analog (D / A) conversion processing, format conversion processing, and the like.
  • the image processing unit 31 is configured using an FPGA (Field Programmable Gate Array) or the like.
  • the clock signal output unit 32 is a clock signal output device according to the first embodiment, and includes a signal generation unit 35 that generates two clock signals whose phases are inverted from each other, and two clock signals generated by the signal generation unit 35. And two limiting amplifiers 36 that amplify the signal by limiting the amplitude.
  • FIG. 3 is a diagram illustrating a configuration example of a main part of the limiting amplifier 36.
  • the limiting amplifier 36 amplifies the clock signal to a predetermined set value, and limits the amplitude to a limit value less than the set value by changing the upper limit and the lower limit for the clock signal amplified by the amplifier 37.
  • an amplitude limiter 38 that outputs the result. Note that the limiting amplifier 36 shown in FIG. 3 is merely an example.
  • the amplifier 37 includes an amplifier 371 whose plus terminal is grounded, a resistor 372 connected to the minus terminal of the amplifier 371 to which an input voltage is applied, and one end connected to the minus terminal of the amplifier 371 and the other end output from the amplifier 371.
  • This is an inverting amplifier circuit constituted by a resistor 373 connected to a terminal.
  • a power supply voltage Vcc is applied to the amplifier 371.
  • a diode 381 whose anode is connected to the output of the amplifier 37 and a diode 382 whose cathode is connected to the output of the amplifier 37 are connected in series.
  • the amplitude limiter 38 limits the voltage by the upper limit voltage V max on the cathode side of the diode 381 and the lower limit voltage V min on the anode side of the diode 382, thereby limiting the amplitude of the clock signal to a limit value less than the set value. .
  • the values of the upper limit voltage V max applied to the cathode side of the diode 381 and the lower limit voltage V min applied to the anode side of the diode 382 are the length and thickness of the insertion portion 21 and the universal cord 23 of the endoscope 2. It is preferably set accordingly.
  • the amplitude of the clock signal output from the amplitude limiting unit 38 is 1 ⁇ 2 of the amplitude of the clock signal output from the amplifier 371.
  • the control unit 33 is configured using, for example, an FPGA incorporating a CPU (Central Processing Unit) or the like.
  • the storage unit 34 stores various programs for operating the endoscope system 1 and data including various parameters necessary for the operation of the endoscope system 1.
  • the storage unit 34 is configured using a RAM (Random Access Memory), a ROM (Read Only Memory), or the like.
  • the light source device 4 is configured using, for example, a white LED.
  • the pulsed white light that is turned on by the light source device 4 is emitted from the distal end portion 21 a of the insertion portion 21 of the endoscope 2 toward the subject via the light guide 102.
  • a rotation provided with three types of filters having red (R), green (G), and blue (B) wavelength bands on the optical path of white light.
  • a filter is installed, and red light, green light, and blue light are sequentially generated by rotating the rotary filter.
  • you may use combining red LED, green LED, and blue LED and you may use the white light source etc. by a xenon lamp.
  • the display device 5 receives the image data generated by the control device 3 from the control device 3, and displays an image corresponding to the image data.
  • a display device 5 includes a display panel made of liquid crystal or organic EL (Electro Luminescence).
  • FIG. 4 is a diagram schematically showing a clock signal output from the clock signal output unit 32.
  • the clock signal C2 shown in the figure has an amplitude A2 that is smaller than the amplitude A1 (set value) generated by the signal generator 35.
  • the amplitude limiter 38 generates a clock signal C2 having an amplitude A2 (limit value) by limiting the upper limit and the lower limit of the amplitude with respect to the clock signal C1 having the amplitude A1 (described by a one-dot chain line in FIG. 4).
  • FIG. 5 is a diagram illustrating a waveform of a clock signal received by the image sensor 101.
  • the clock signal C3 shown in the figure maintains its rising state due to the limitation on the amplitude. For this reason, the clock signal C3 has a good slew rate. Further, since the dynamic range of the limiting amplifier 36 has not changed, the clock signal C3 has no waveform distortion and has good resistance to phase noise.
  • the clock signal amplitude is limited to a limit value less than the set value by changing the upper limit and the lower limit of the clock signal amplitude.
  • a clock signal with a good rate can be output. Therefore, it is possible to realize high quality clock signals in the endoscope 2.
  • the clock signal is transmitted to the distal end portion of the endoscope by differential transmission, the influence of unnecessary radiation can be reduced in addition to the noise resistance of the phase noise.
  • FIG. 6 is a block diagram illustrating a configuration of a main part of the endoscope system according to the modification of the first embodiment.
  • the endoscope system 6 shown in the figure includes an endoscope 2-1, a control device 3-1, a light source device 4, and a display device 5.
  • the endoscope system 6 is different from the endoscope system 1 in the configuration of the connector 24-1 and the control device 3-1 included in the endoscope 2-1.
  • the endoscope 2-1 has a clock signal output unit 32 which is a clock signal output device according to this modification.
  • the control device 3-1 includes an image processing unit 31, a control unit 33, and a storage unit 34.
  • the modification of the first embodiment having the above-described configuration has the same effects as those of the first embodiment described above.
  • the endoscope 2-1 itself has the clock signal output unit, an optimal clock signal can be set at the time of shipment.
  • FIG. 7 is a block diagram illustrating a configuration of a main part of the endoscope system according to the second embodiment of the present invention.
  • the endoscope system 7 shown in the figure includes an endoscope 2-2, a control device 3-2, a light source device 4, and a display device 5.
  • the configuration of the connector 24-2 is different from the endoscope 2 in the endoscope 2-2.
  • the connector 24-2 includes a control unit 25 that controls the operation of the connector 24-2, and a storage unit 26 that stores the characteristic information Sid of the endoscope 2-2.
  • the characteristic information Sid includes, for example, information on the limit value of the amplitude of the clock signal in addition to information on the model of the endoscope 2-2, cable length, manufacturing, transmission method, transmission rate, and the like.
  • the control unit 25 is configured using, for example, an FPGA.
  • the storage unit 26 is configured using, for example, an EPROM (Erasable Programmable ROM).
  • the control device 3-2 includes an image processing unit 31, a clock signal output unit 32, a control unit 39, and a storage unit 34.
  • the control unit 39 includes a changing unit 40 that changes the amplitude limit value in the clock signal output unit 32 based on the characteristic information Sid stored in the storage unit 26 of the connector 24-2.
  • the changing unit 40 changes the limit value of the amplitude by changing the upper limit voltage V max and the lower limit voltage V min applied to the amplitude limiting unit 38 based on the characteristic information Sid.
  • the clock signal amplitude is limited to less than the set value by changing the upper and lower limits of the clock signal amplitude, so that the phase noise and the slew rate are good.
  • a high-quality clock signal in the endoscope 2-2 can be realized.
  • control device 3-2 can set an optimal amplitude limit value according to the type of the endoscope 2-2 to be connected. Therefore, the highly versatile endoscope system 7 can be realized.
  • the limit value of the amplitude of the clock signal in the clock signal output unit 32 can be adjusted at the time of use without adjusting at the time of manufacture or shipment, the common clock signal output unit Different types of endoscopes can be manufactured using 32, and the productivity of the endoscope can be improved.
  • FIG. 8 is a block diagram showing a configuration of a main part of an endoscope system according to a modification of the second embodiment.
  • the endoscope system 8 shown in the figure includes an endoscope 2-3, a control device 3-1, a light source device 4, and a display device 5.
  • the endoscope 2-3 is different in the configuration of the connector 24-3 from the endoscope 2-2.
  • the connector 24-3 includes a control unit 28 that controls the operation of the connector 24-3, and a storage unit 26 that stores the characteristic information Sid of the endoscope 2-3.
  • the control unit 28 includes a changing unit 29 that changes the limit value of the amplitude in the clock signal output unit 32 based on the characteristic information Sid stored in the storage unit 26.
  • the same effect as in the second embodiment can be obtained.
  • the productivity of the endoscope it is not a good idea to make adjustments according to the type of endoscope at the time of shipment. Therefore, in this modification as well, if the amplitude adjustment in the clock signal output unit 32 is executed after the endoscope system 8 is turned on in actual use, the productivity of the endoscope is improved. This is more preferable.
  • FIG. 9 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to Embodiment 3 of the present invention.
  • An endoscope system 9 shown in the figure includes an endoscope 2-4, a control device 3-3, a light source device 4, and a display device 5.
  • the endoscope system 9 transmits a clock signal in a single end.
  • the endoscope 2-4 has the same configuration as the endoscope 2 except that the transmission path of the clock signal in the universal cord 23-4 or the like is one.
  • the control device 3-3 includes an image processing unit 31, a clock signal output unit 41, a control unit 33, and a storage unit.
  • the clock signal output unit 41 includes a signal generation unit 42 that generates one clock signal, and one limiting unit that amplifies the clock signal generated by the signal generation unit and limits the amplitude to a limit value less than a set value. And an amplifier 36.
  • the amplitude of the clock signal is limited to a limit value less than the set value by changing the upper and lower limits of the clock signal amplitude. Since it is output, it is possible to output a clock signal with good phase noise and slew rate, and it is possible to realize high quality clock signals in the endoscope.
  • the clock signal output unit 41 may be provided on the connector side of the endoscope 2-4, or the characteristic information of the endoscope is stored in the storage unit of the connector.
  • the limit value of the amplitude of the limiting amplifier 36 of the clock signal output unit 41 may be changed based on the information.

Abstract

Provided is clock signal outputting device that is connected, via a signal transmission line, to the leading end of an endoscope which is inserted into a subject and captures images of the inside of the subject, and that outputs a clock signal which serves as an operation reference for the leading end of the endoscope. The clock signal outputting device includes: a signal generating unit that generates a clock signal; an amplifying unit that amplifies the amplitude of the clock signal to a set value; and an amplitude restricting unit that restricts the amplitude of the clock signal to a restricted value less than the set value by changing an upper limit and a lower limit of the clock signal amplified by the amplifying unit, and that outputs the clock signal.

Description

クロック信号出力装置、制御装置および内視鏡Clock signal output device, control device, and endoscope
　本発明は、クロック信号出力装置、該クロック信号出力装置を備えた制御装置および内視鏡に関する。 The present invention relates to a clock signal output device, a control device including the clock signal output device, and an endoscope.
　従来、患者等の被検体の内部を観察する内視鏡システムでは、各構成部位の動作の基準となるクロック信号をプロセッサ側で発生し、内視鏡の先端部に設けられる撮像素子まで伝送している（例えば、特許文献１を参照）。近年、内視鏡の撮像素子は高画素化されてきており、伝送用ケーブルを経由してプロセッサに伝送されるデジタルの撮像信号も３Ｇｂｐｓ程度と高速になっている。このような状況下において、ジッターと呼ばれる信号の揺らぎを取り除くには、位相ノイズに対するノイズ耐性の高い高品位のクロック信号が必要である。 Conventionally, in an endoscope system for observing the inside of a subject such as a patient, a clock signal, which serves as a reference for the operation of each component, is generated on the processor side and transmitted to an image sensor provided at the distal end of the endoscope. (For example, refer to Patent Document 1). In recent years, an imaging device of an endoscope has been increased in the number of pixels, and a digital imaging signal transmitted to a processor via a transmission cable has also become as high as about 3 Gbps. Under these circumstances, a high-quality clock signal having high noise resistance against phase noise is required to remove signal fluctuations called jitter.
　内視鏡の場合、先端部が小さいため、撮像素子の近傍にクロック信号の発生器を設けることが難しい。このため、内視鏡では、特許文献１に記載されているように、長尺の伝送用ケーブルを介してクロック信号を先端部まで伝送しなければならず、クロック信号を高品位化するために様々な要求が課せられる。 In the case of an endoscope, since the tip is small, it is difficult to provide a clock signal generator near the image sensor. For this reason, in the endoscope, as described in Patent Document 1, the clock signal must be transmitted to the tip portion via a long transmission cable, and the clock signal is improved in quality. Various requirements are imposed.
　第１に、位相ノイズのノイズ耐性、および不要輻射（ＥＭＩ：Electro　Magnetic　Interference）の影響の削減が求められる。この点を解決するには、クロック信号を差動伝送するのが好ましい。 First, it is required to reduce the noise tolerance of phase noise and the influence of unnecessary radiation (EMI: Electro Magnetic Interference). In order to solve this problem, it is preferable to differentially transmit the clock signal.
　第２に、伝送用ケーブルのインサーションロスによる振幅の減衰を考慮すると、出力するクロック信号の振幅が大きい方が好ましい。 Second, considering the amplitude attenuation due to the insertion loss of the transmission cable, it is preferable that the output clock signal has a larger amplitude.
　第３に、内視鏡の種類による伝送用ケーブルのケーブル長の違いに適応可能であることが望ましい。このためには、ケーブル長に応じて最適な振幅のクロック信号を生成することが可能な振幅調整機能を具備している必要がある。 Third, it is desirable to be able to adapt to the difference in cable length of the transmission cable depending on the type of endoscope. For this purpose, it is necessary to have an amplitude adjustment function capable of generating a clock signal having an optimum amplitude according to the cable length.
　第４に、内視鏡先端部におけるノイズの影響を小さくすることが求められる。この要求を満足するには、クロック信号のスルーレート（Slew　Rate）を高くすることが考えられる。 Fourth, it is required to reduce the influence of noise at the endoscope tip. To satisfy this requirement, it is conceivable to increase the slew rate of the clock signal.
　以上説明した様々な要求を満たすために、例えば、大振幅の差動信号を高速で伝送可能な方式であるＣＭＬ（Current　Mode　Logic）を用いてクロック信号を伝送することが考えられる。図１０は、ＣＭＬを用いたクロック信号の差動伝送を模式的に示す図である。ＣＭＬでは、２つのオープンコレクタ回路２０１、２０２を電源電圧Ｖccでプルアップして駆動する。しかしながらこの場合には、電源にノイズが含まれていると、そのノイズがクロック信号の位相ノイズとして現れてしまう。 In order to satisfy the various requirements described above, for example, it is conceivable to transmit a clock signal using CML (Current Mode Logic), which is a method capable of transmitting a large amplitude differential signal at high speed. FIG. 10 is a diagram schematically illustrating differential transmission of a clock signal using CML. In CML, the two open collector circuits 201 and 202 are driven by being pulled up with the power supply voltage Vcc . However, in this case, if noise is included in the power supply, the noise appears as phase noise of the clock signal.
　また、上述した要求を満たすために、高速アナログ差動アンプを用いて振幅調整を行うことも考えられる。図１１は、高速アナログ差動アンプを用いてゲインを調整することによってクロック信号の振幅調整を行う場合のクロック信号の差動伝送を模式的に示す図である。図１１に示す高速アナログ差動アンプ２０３によれば、位相ノイズのノイズ耐性を向上させることができるものの、例えば振幅を小さくした場合には、伝送によるクロック信号のなまりが顕著となり、スルーレートが悪化してしまう。 In order to satisfy the above-described requirements, it is also conceivable to perform amplitude adjustment using a high-speed analog differential amplifier. FIG. 11 is a diagram schematically showing the differential transmission of the clock signal when the amplitude of the clock signal is adjusted by adjusting the gain using a high-speed analog differential amplifier. Although the high-speed analog differential amplifier 203 shown in FIG. 11 can improve the noise tolerance of the phase noise, for example, when the amplitude is reduced, the rounding of the clock signal due to transmission becomes remarkable, and the slew rate is deteriorated. Resulting in.
　上述したゲイン調整に基づく振幅調整の問題を解決するため、高速アナログ差動アンプの電源電圧（ダイナミックレンジ）を変化させることによってクロック信号の振幅を調整することも考えられる。図１２は、高速アナログ差動アンプの電源電圧を変化させることによって振幅調整を行う場合のクロック信号の差動伝送を模式的に示す図である。図１２に示すように、高速アナログ差動アンプ２０４において、電源電圧で信号を飽和させることによって振幅を変える場合には、クロック信号の伝送によって電源電圧の上下限付近で波形にひずみが発生し、位相ノイズが悪化してしまう。 In order to solve the problem of amplitude adjustment based on the gain adjustment described above, it is conceivable to adjust the amplitude of the clock signal by changing the power supply voltage (dynamic range) of the high-speed analog differential amplifier. FIG. 12 is a diagram schematically showing differential transmission of a clock signal when amplitude adjustment is performed by changing the power supply voltage of the high-speed analog differential amplifier. As shown in FIG. 12, in the high-speed analog differential amplifier 204, when the amplitude is changed by saturating the signal with the power supply voltage, the waveform is distorted near the upper and lower limits of the power supply voltage due to the transmission of the clock signal. Phase noise will get worse.
国際公開第２０１２／０８１６１８号International Publication No. 2012/081618
　以上説明したように、内視鏡に特有の要求を十分に満足しながら内視鏡におけるクロック信号の高品位化を実現する技術は見出されていないのが現状であった。 As described above, the present situation is that no technology has been found to realize a high-quality clock signal in the endoscope while sufficiently satisfying the unique requirements of the endoscope.
　本発明は、上記に鑑みてなされたものであって、内視鏡におけるクロック信号の高品位化を実現することができるクロック信号出力装置、制御装置、および内視鏡を提供することを目的とする。 The present invention has been made in view of the above, and an object of the present invention is to provide a clock signal output device, a control device, and an endoscope that can realize high-quality clock signals in an endoscope. To do.
　上述した課題を解決し、目的を達成するために、本発明に係るクロック信号出力装置は、被検体に挿入されて該被検体内を撮像する内視鏡の先端部と信号の伝送路を介して接続され、前記先端部に対して動作の基準となるクロック信号を出力するクロック信号出力装置であって、前記クロック信号を発生する信号発生部と、前記クロック信号の振幅を設定値まで増幅する増幅部と、前記増幅部が増幅した前記クロック信号の上限および下限を変化させることによって該クロック信号の振幅を前記設定値未満の制限値に制限して出力する振幅制限部と、を備えたことを特徴とする。 In order to solve the above-described problems and achieve the object, a clock signal output device according to the present invention is inserted through a distal end portion of an endoscope that is inserted into a subject and images the inside of the subject and a signal transmission path. A clock signal output device for outputting a clock signal serving as a reference for operation to the tip portion, a signal generator for generating the clock signal, and amplifying the amplitude of the clock signal to a set value An amplification unit; and an amplitude limiting unit that outputs the clock signal by limiting the amplitude of the clock signal to a limit value less than the set value by changing an upper limit and a lower limit of the clock signal amplified by the amplifier unit. It is characterized by.
　本発明に係るクロック信号出力装置は、上記発明において、前記振幅制限部は、前記制限値を変更可能であることを特徴とする。 The clock signal output device according to the present invention is characterized in that, in the above invention, the amplitude limiter can change the limit value.
　本発明に係るクロック信号出力装置は、上記発明において、前記制限値は、前記内視鏡の特性に応じて定められることを特徴とする。 The clock signal output device according to the present invention is characterized in that, in the above invention, the limit value is determined in accordance with characteristics of the endoscope.
　本発明に係るクロック信号出力装置は、上記発明において、前記増幅部および前記振幅制限部を有する組を２組備え、互いに位相が反転した２つの前記クロック信号を差動出力することを特徴とする。 The clock signal output device according to the present invention is characterized in that, in the above invention, the clock signal output device includes two sets each having the amplification unit and the amplitude limiting unit, and differentially outputs the two clock signals whose phases are inverted. .
　本発明に係る制御装置は、被検体に挿入されて該被検体内を撮像する内視鏡に接続され、該内視鏡の動作を制御する制御装置であって、上記に記載のクロック信号出力装置と、前記内視鏡の特性に基づいて前記制限値を変更する変更部と、を備えたことを特徴とする。 A control device according to the present invention is a control device that is connected to an endoscope that is inserted into a subject and images the inside of the subject, and that controls the operation of the endoscope, the clock signal output described above An apparatus and a changing unit that changes the limit value based on characteristics of the endoscope are provided.
　本発明に係る内視鏡は、被検体に挿入されて該被検体内を撮像する内視鏡であって、先端部に設けられて前記被検体を撮像して撮像信号を出力する撮像素子と、前記撮像素子と信号の伝送路を介して接続されるとともに当該内視鏡の動作を制御する制御装置と通信可能に接続され、上記に記載のクロック信号出力装置を有するコネクタと、を備えたことを特徴とする。 An endoscope according to the present invention is an endoscope that is inserted into a subject and images the inside of the subject, and is provided at a distal end portion, and an imaging device that images the subject and outputs an imaging signal; A connector that is connected to the imaging device via a signal transmission path and is connected to a control device that controls the operation of the endoscope, and that has the clock signal output device described above. It is characterized by that.
　本発明に係る内視鏡は、上記発明において、前記コネクタは、当該内視鏡の特性を記憶する記憶部と、前記特性に基づいて前記制限値を変更する変更部と、を有することを特徴とする。 The endoscope according to the present invention is characterized in that, in the above invention, the connector includes a storage unit that stores characteristics of the endoscope, and a changing unit that changes the limit value based on the characteristics. And
　本発明によれば、クロック信号の振幅の上限および下限を変化させることによってクロック信号の振幅を設定値未満の制限値に制限して出力するため、位相ノイズおよびスルーレートが良好なクロック信号を出力することができる。したがって、内視鏡におけるクロック信号の高品位化を実現することができる。 According to the present invention, the clock signal amplitude is limited to a limit value less than the set value by changing the upper and lower limits of the clock signal amplitude, so that a clock signal with good phase noise and slew rate is output. can do. Therefore, it is possible to realize high quality clock signals in the endoscope.
図１は、本発明の実施の形態１に係る内視鏡システムの外観構成を示す図である。FIG. 1 is a diagram showing an external configuration of an endoscope system according to Embodiment 1 of the present invention. 図２は、本発明の実施の形態１に係る内視鏡システムの要部の機能構成を示すブロック図である。FIG. 2 is a block diagram showing a functional configuration of a main part of the endoscope system according to Embodiment 1 of the present invention. 図３は、リミッティングアンプの要部の構成例を示す図である。FIG. 3 is a diagram illustrating a configuration example of a main part of the limiting amplifier. 図４は、クロック信号出力部が出力するクロック信号を模式的に示す図である。FIG. 4 is a diagram schematically illustrating a clock signal output from the clock signal output unit. 図５は、撮像素子が受信するクロック信号の波形を示す図である。FIG. 5 is a diagram illustrating a waveform of a clock signal received by the image sensor. 図６は、本発明の実施の形態１の変形例に係る内視鏡システムの要部の構成を示すブロック図である。FIG. 6 is a block diagram illustrating a configuration of a main part of the endoscope system according to the modification of the first embodiment of the present invention. 図７は、本発明の実施の形態２に係る内視鏡システムの要部の構成を示すブロック図である。FIG. 7 is a block diagram illustrating a configuration of a main part of the endoscope system according to the second embodiment of the present invention. 図８は、本発明の実施の形態２の変形例に係る内視鏡システムの要部の構成を示すブロック図である。FIG. 8 is a block diagram illustrating a configuration of a main part of an endoscope system according to a modification of the second embodiment of the present invention. 図９は、本発明の実施の形態３に係る内視鏡システムの要部の機能構成を示すブロック図である。FIG. 9 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to Embodiment 3 of the present invention. 図１０は、従来のＣＭＬを用いたクロック信号の差動伝送を模式的に示す図である。FIG. 10 is a diagram schematically showing differential transmission of a clock signal using a conventional CML. 図１１は、従来の高速アナログ差動アンプを用いてゲインを調整することによってクロック信号の振幅調整を行う場合のクロック信号の差動伝送を模式的に示す図である。FIG. 11 is a diagram schematically showing the differential transmission of the clock signal when adjusting the amplitude of the clock signal by adjusting the gain using a conventional high-speed analog differential amplifier. 図１２は、従来の高速アナログ差動アンプの電源電圧を変化させることによって振幅調整を行う場合のクロック信号の差動伝送を模式的に示す図である。FIG. 12 is a diagram schematically showing differential transmission of a clock signal when amplitude adjustment is performed by changing a power supply voltage of a conventional high-speed analog differential amplifier.
　以下、添付図面を参照して、本発明を実施するための形態（以下、「実施の形態」という）を説明する。なお、以下の説明で参照する図面は模式的なものであって、同じ物体を異なる図面で示す場合には、寸法や縮尺等が異なる場合もある。 DETAILED DESCRIPTION Hereinafter, embodiments for carrying out the present invention (hereinafter referred to as “embodiments”) will be described with reference to the accompanying drawings. Note that the drawings referred to in the following description are schematic, and when the same object is shown in different drawings, dimensions, scales, and the like may be different.
（実施の形態１）
　図１は、本発明の実施の形態１に係る内視鏡システムの外観構成を示す図である。図２は、本実施の形態１に係る内視鏡システムの要部の機能構成を示すブロック図である。図１および図２に示す内視鏡システム１は、被検体内に先端部を挿入することによって被検体の体内画像を撮像する内視鏡２と、内視鏡２が撮像した体内画像に所定の画像処理を施すとともに、内視鏡システム１全体の動作を統括して制御する制御装置（プロセッサ）３と、内視鏡２の先端から出射する照明光を発生する光源装置４と、制御装置３が画像処理を施した体内画像を表示する表示装置５と、を備える。 (Embodiment 1)
FIG. 1 is a diagram showing an external configuration of an endoscope system according to Embodiment 1 of the present invention. FIG. 2 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to the first embodiment. An endoscope system 1 shown in FIGS. 1 and 2 has an endoscope 2 that captures an in-vivo image of a subject by inserting a distal end portion into the subject, and a predetermined in-vivo image captured by the endoscope 2. And a control device (processor) 3 that controls the overall operation of the endoscope system 1, a light source device 4 that generates illumination light emitted from the distal end of the endoscope 2, and a control device 3 includes a display device 5 that displays an in-vivo image subjected to image processing.
　内視鏡２は、可撓性を有する細長形状をなす挿入部２１と、挿入部２１の基端側に接続され、各種の操作信号の入力を受け付ける操作部２２と、操作部２２から挿入部２１が延びる方向と異なる方向に延び、制御装置３または光源装置４に接続する複数のケーブルを内蔵するユニバーサルコード２３と、ユニバーサルコード２３の基端部に設けられ、制御装置３および光源装置４に対して着脱自在であり、制御装置３との間で電気信号の送受信を行うとともに光源装置４が出射した光を経由させるコネクタ２４と、を備える。挿入部２１およびユニバーサルコード２３に内蔵されるクロック信号用のケーブルは、内視鏡２における信号の伝送路の一部を構成する。 The endoscope 2 includes an insertion portion 21 having an elongated shape having flexibility, an operation portion 22 that is connected to a proximal end side of the insertion portion 21 and receives input of various operation signals, and an insertion portion from the operation portion 22. A universal cord 23 that extends in a direction different from the direction in which 21 extends and incorporates a plurality of cables connected to the control device 3 or the light source device 4, and is provided at the base end portion of the universal cord 23. The connector 24 is detachable, and includes a connector 24 that transmits and receives electrical signals to and from the control device 3 and passes light emitted from the light source device 4. The clock signal cable built in the insertion portion 21 and the universal cord 23 constitutes a part of a signal transmission path in the endoscope 2.
　挿入部２１の先端部２１ａには、２次元マトリックス上に配設された複数の画素を有し、受光した光を光電変換して撮像信号を生成する撮像素子１０１が設けられる。また、先端部２１ａには、光源装置４が出射した光の導光路をなすライトガイド１０２の先端部が挿通している。撮像素子１０１の受光面側には集光用の光学系が設けられ、ライトガイド１０２の先端側には照明用の光学系が設けられる。 The distal end portion 21a of the insertion portion 21 is provided with an imaging element 101 that has a plurality of pixels arranged on a two-dimensional matrix and photoelectrically converts received light to generate an imaging signal. Further, the distal end portion of the light guide 102 that forms a light guide path of the light emitted from the light source device 4 is inserted into the distal end portion 21a. A condensing optical system is provided on the light receiving surface side of the image sensor 101, and an illumination optical system is provided on the tip side of the light guide 102.
　撮像素子１０１は、例えば光を光電変換して電気信号を出力するセンサ部と、センサ部が出力した電気信号に対してノイズ除去やＡ／Ｄ変換を行うアナログフロントエンド（ＡＦＥ）とを有するＣＭＯＳ（Complementary　Metal　Oxide　Semiconductor）イメージセンサを用いて構成される。 The image sensor 101 is a CMOS having a sensor unit that photoelectrically converts light and outputs an electrical signal, and an analog front end (AFE) that performs noise removal and A / D conversion on the electrical signal output from the sensor unit, for example. (Complementary Metal Oxide Semiconductor) Consists of image sensors.
　制御装置３は、内視鏡２から送られてくる撮像信号に対して所定の画像処理を施す画像処理部３１と、動作の基準となるクロック信号を発生して内視鏡２等へ出力するクロック信号出力部３２と、制御装置３を含む内視鏡システム１の動作を統括して制御する制御部３３と、各種情報を記憶する記憶部３４と、を有する。 The control device 3 generates an image processing unit 31 that performs predetermined image processing on an imaging signal sent from the endoscope 2 and generates a clock signal that serves as a reference for operation, and outputs the generated clock signal to the endoscope 2 and the like. A clock signal output unit 32, a control unit 33 that controls the overall operation of the endoscope system 1 including the control device 3, and a storage unit 34 that stores various types of information.
　画像処理部３１は、例えば同時化処理、ホワイトバランス（ＷＢ）調整処理、ゲイン調整処理、ガンマ補正処理、デジタルアナログ（Ｄ／Ａ）変換処理、フォーマット変換処理等の少なくとも一部の処理を行う。画像処理部３１は、ＦＰＧＡ（Field　Programmable　Gate　Array）等を用いて構成される。 The image processing unit 31 performs at least part of processing such as synchronization processing, white balance (WB) adjustment processing, gain adjustment processing, gamma correction processing, digital analog (D / A) conversion processing, format conversion processing, and the like. The image processing unit 31 is configured using an FPGA (Field Programmable Gate Array) or the like.
　クロック信号出力部３２は、本実施の形態１に係るクロック信号出力装置であり、互いに位相が反転した２つのクロック信号を発生する信号発生部３５と、信号発生部３５が発生した２つのクロック信号の各々に対して振幅に制限を加えて増幅する２つのリミッティングアンプ３６と、を有する。 The clock signal output unit 32 is a clock signal output device according to the first embodiment, and includes a signal generation unit 35 that generates two clock signals whose phases are inverted from each other, and two clock signals generated by the signal generation unit 35. And two limiting amplifiers 36 that amplify the signal by limiting the amplitude.
　図３は、リミッティングアンプ３６の要部の構成例を示す図である。リミッティングアンプ３６は、クロック信号を所定の設定値まで増幅する増幅部３７と、増幅部３７が増幅したクロック信号に対して上限および下限を変化させることによって振幅を設定値未満の制限値に制限して出力する振幅制限部３８とを有する。なお、図３に示すリミッティングアンプ３６はあくまでも一例に過ぎない。 FIG. 3 is a diagram illustrating a configuration example of a main part of the limiting amplifier 36. The limiting amplifier 36 amplifies the clock signal to a predetermined set value, and limits the amplitude to a limit value less than the set value by changing the upper limit and the lower limit for the clock signal amplified by the amplifier 37. And an amplitude limiter 38 that outputs the result. Note that the limiting amplifier 36 shown in FIG. 3 is merely an example.
　増幅部３７は、プラス端子が接地されたアンプ３７１、アンプ３７１のマイナス端子に接続されて入力電圧が加わる抵抗３７２、および一端がアンプ３７１のマイナス端子に接続されるとともに他端がアンプ３７１の出力端子に接続される抵抗３７３によって構成される反転増幅回路である。アンプ３７１には、電源電圧Ｖccが印加される。 The amplifier 37 includes an amplifier 371 whose plus terminal is grounded, a resistor 372 connected to the minus terminal of the amplifier 371 to which an input voltage is applied, and one end connected to the minus terminal of the amplifier 371 and the other end output from the amplifier 371. This is an inverting amplifier circuit constituted by a resistor 373 connected to a terminal. A power supply voltage Vcc is applied to the amplifier 371.
　振幅制限部３８は、増幅部３７の出力にアノードが接続されるダイオード３８１と、増幅部３７の出力にカソードが接続されるダイオード３８２とが直列に接続されている。振幅制限部３８は、ダイオード３８１のカソード側の上限電圧Ｖmaxとダイオード３８２のアノード側の下限電圧Ｖminとによって電圧を制限することにより、クロック信号の振幅を設定値未満の制限値に制限する。ダイオード３８１のカソード側に印加される上限電圧Ｖmaxとダイオード３８２のアノード側に印加される下限電圧Ｖminの値は、内視鏡２が有する挿入部２１およびユニバーサルコード２３の長さや太さに応じて設定されるのが好ましい。例えば、アンプ３７１の電源電圧Ｖccに対して、Ｖmax＝（３／４）Ｖcc、Ｖmin＝（１／４）Ｖccと設定することができる。この場合、振幅制限部３８が出力するクロック信号の振幅は、アンプ３７１が出力するクロック信号の振幅の１／２となる。 In the amplitude limiter 38, a diode 381 whose anode is connected to the output of the amplifier 37 and a diode 382 whose cathode is connected to the output of the amplifier 37 are connected in series. The amplitude limiter 38 limits the voltage by the upper limit voltage V max on the cathode side of the diode 381 and the lower limit voltage V min on the anode side of the diode 382, thereby limiting the amplitude of the clock signal to a limit value less than the set value. . The values of the upper limit voltage V max applied to the cathode side of the diode 381 and the lower limit voltage V min applied to the anode side of the diode 382 are the length and thickness of the insertion portion 21 and the universal cord 23 of the endoscope 2. It is preferably set accordingly. For example, V max = (3/4) V cc and V min = (1/4) V cc can be set for the power supply voltage V cc of the amplifier 371. In this case, the amplitude of the clock signal output from the amplitude limiting unit 38 is ½ of the amplitude of the clock signal output from the amplifier 371.
　制御部３３は、例えばＣＰＵ（Central　Processing　Unit）等を組み込んだＦＰＧＡを用いて構成される。 The control unit 33 is configured using, for example, an FPGA incorporating a CPU (Central Processing Unit) or the like.
　記憶部３４は、内視鏡システム１を動作させるための各種プログラム、および内視鏡システム１の動作に必要な各種パラメータ等を含むデータを記憶する。記憶部３４は、ＲＡＭ（Random　Access　Memory）およびＲＯＭ（Read　Only　Memory）等を用いて構成される。 The storage unit 34 stores various programs for operating the endoscope system 1 and data including various parameters necessary for the operation of the endoscope system 1. The storage unit 34 is configured using a RAM (Random Access Memory), a ROM (Read Only Memory), or the like.
　光源装置４は、例えば白色ＬＥＤを用いて構成される。この場合、光源装置４が点灯するパルス状の白色光は、ライトガイド１０２を経由して内視鏡２の挿入部２１の先端部２１ａから被写体へ向けて照射される。光源装置４が面順次式の照明光を発生する場合には、白色光の光路上に赤（Ｒ）、緑（Ｇ）、青（Ｂ）の波長帯域を有する３種類のフィルタを備えた回転フィルタを設置し、この回転フィルタを回転させることによって赤色光、緑色光、青色光を順次発生させる。なお、光源装置４の光源として、赤色ＬＥＤ、緑色ＬＥＤ、青色ＬＥＤを組み合わせて使用してもよいし、キセノンランプによる白色光源等を使用してもよい。 The light source device 4 is configured using, for example, a white LED. In this case, the pulsed white light that is turned on by the light source device 4 is emitted from the distal end portion 21 a of the insertion portion 21 of the endoscope 2 toward the subject via the light guide 102. When the light source device 4 generates frame-sequential illumination light, a rotation provided with three types of filters having red (R), green (G), and blue (B) wavelength bands on the optical path of white light. A filter is installed, and red light, green light, and blue light are sequentially generated by rotating the rotary filter. In addition, as a light source of the light source device 4, you may use combining red LED, green LED, and blue LED, and you may use the white light source etc. by a xenon lamp.
　表示装置５は、制御装置３が生成した画像データを制御装置３から受信し、該画像データに対応する画像を表示する。このような表示装置５は、液晶または有機ＥＬ（Electro　Luminescence）からなる表示パネルを備える。 The display device 5 receives the image data generated by the control device 3 from the control device 3, and displays an image corresponding to the image data. Such a display device 5 includes a display panel made of liquid crystal or organic EL (Electro Luminescence).
　図４は、クロック信号出力部３２が出力するクロック信号を模式的に示す図である。同図に示すクロック信号Ｃ２は、信号発生部３５が発生した振幅Ａ１（設定値）より小さい振幅Ａ２を有する。振幅制限部３８は、振幅Ａ１のクロック信号Ｃ１（図４において一点鎖線で記載）に対して、振幅の上限と下限に制限を加えることによって振幅Ａ２（制限値）のクロック信号Ｃ２を生成する。 FIG. 4 is a diagram schematically showing a clock signal output from the clock signal output unit 32. As shown in FIG. The clock signal C2 shown in the figure has an amplitude A2 that is smaller than the amplitude A1 (set value) generated by the signal generator 35. The amplitude limiter 38 generates a clock signal C2 having an amplitude A2 (limit value) by limiting the upper limit and the lower limit of the amplitude with respect to the clock signal C1 having the amplitude A1 (described by a one-dot chain line in FIG. 4).
　図５は、撮像素子１０１が受信するクロック信号の波形を示す図である。同図に示すクロック信号Ｃ３は、振幅に制限が加わっていることで立ち上がりが立ったままの状態を維持している。このため、クロック信号Ｃ３は、スルーレートが良好である。また、リミッティングアンプ３６のダイナミックレンジは変化していないため、クロック信号Ｃ３では波形のひずみがなく、位相ノイズに対する耐性も良好である。 FIG. 5 is a diagram illustrating a waveform of a clock signal received by the image sensor 101. The clock signal C3 shown in the figure maintains its rising state due to the limitation on the amplitude. For this reason, the clock signal C3 has a good slew rate. Further, since the dynamic range of the limiting amplifier 36 has not changed, the clock signal C3 has no waveform distortion and has good resistance to phase noise.
　以上説明した本発明の実施の形態１によれば、クロック信号の振幅の上限および下限を変化させることによってクロック信号の振幅を設定値未満の制限値に制限して出力するため、位相ノイズおよびスルーレートが良好なクロック信号を出力することができる。したがって、内視鏡２におけるクロック信号の高品位化を実現することができる。 According to the first embodiment of the present invention described above, the clock signal amplitude is limited to a limit value less than the set value by changing the upper limit and the lower limit of the clock signal amplitude. A clock signal with a good rate can be output. Therefore, it is possible to realize high quality clock signals in the endoscope 2.
　また、本実施の形態１によれば、差動伝送によってクロック信号を内視鏡の先端部へ伝送するため、位相ノイズのノイズ耐性に加えて、不要輻射の影響を削減することができる。 Further, according to the first embodiment, since the clock signal is transmitted to the distal end portion of the endoscope by differential transmission, the influence of unnecessary radiation can be reduced in addition to the noise resistance of the phase noise.
　図６は、本実施の形態１の変形例に係る内視鏡システムの要部の構成を示すブロック図である。同図に示す内視鏡システム６は、内視鏡２－１と、制御装置３－１と、光源装置４と、表示装置５とを備える。内視鏡システム６は、内視鏡２－１が有するコネクタ２４－１および制御装置３－１の構成が、内視鏡システム１と異なる。 FIG. 6 is a block diagram illustrating a configuration of a main part of the endoscope system according to the modification of the first embodiment. The endoscope system 6 shown in the figure includes an endoscope 2-1, a control device 3-1, a light source device 4, and a display device 5. The endoscope system 6 is different from the endoscope system 1 in the configuration of the connector 24-1 and the control device 3-1 included in the endoscope 2-1.
　内視鏡２－１は、本変形例に係るクロック信号出力装置であるクロック信号出力部３２を有する。制御装置３－１は、画像処理部３１と、制御部３３と、記憶部３４とを有する。 The endoscope 2-1 has a clock signal output unit 32 which is a clock signal output device according to this modification. The control device 3-1 includes an image processing unit 31, a control unit 33, and a storage unit 34.
　以上の構成を有する本実施の形態１の変形例が、上述した実施の形態１と同様の効果を奏することはいうまでもない。加えて、本変形例によれば、内視鏡２－１自身がクロック信号出力部を有しているため、最適なクロック信号を出荷時に設定しておくことができる。 Needless to say, the modification of the first embodiment having the above-described configuration has the same effects as those of the first embodiment described above. In addition, according to this modification, since the endoscope 2-1 itself has the clock signal output unit, an optimal clock signal can be set at the time of shipment.
（実施の形態２）
　図７は、本発明の実施の形態２に係る内視鏡システムの要部の構成を示すブロック図である。同図に示す内視鏡システム７は、内視鏡２－２と、制御装置３－２と、光源装置４と、表示装置５とを備える。 (Embodiment 2)
FIG. 7 is a block diagram illustrating a configuration of a main part of the endoscope system according to the second embodiment of the present invention. The endoscope system 7 shown in the figure includes an endoscope 2-2, a control device 3-2, a light source device 4, and a display device 5.
　内視鏡２－２は、内視鏡２と比較して、コネクタ２４－２の構成が異なる。コネクタ２４－２は、コネクタ２４－２の動作を制御する制御部２５と、内視鏡２－２の特性情報Ｓｉｄを記憶する記憶部２６とを有する。ここで、特性情報Ｓｉｄは、例えば内視鏡２－２の機種、ケーブル長、製造、伝送方式、伝送レート等に関する情報に加えてクロック信号の振幅の制限値に関する情報を含む。制御部２５は、例えばＦＰＧＡを用いて構成される。記憶部２６は、例えばＥＰＲＯＭ（Erasable　Programmable　ROM）等を用いて構成される。 The configuration of the connector 24-2 is different from the endoscope 2 in the endoscope 2-2. The connector 24-2 includes a control unit 25 that controls the operation of the connector 24-2, and a storage unit 26 that stores the characteristic information Sid of the endoscope 2-2. Here, the characteristic information Sid includes, for example, information on the limit value of the amplitude of the clock signal in addition to information on the model of the endoscope 2-2, cable length, manufacturing, transmission method, transmission rate, and the like. The control unit 25 is configured using, for example, an FPGA. The storage unit 26 is configured using, for example, an EPROM (Erasable Programmable ROM).
　制御装置３－２は、画像処理部３１と、クロック信号出力部３２と、制御部３９と、記憶部３４とを有する。制御部３９は、コネクタ２４－２の記憶部２６が記憶する特性情報Ｓｉｄに基づいてクロック信号出力部３２における振幅の制限値を変更する変更部４０を有する。変更部４０は、振幅制限部３８に印加される上限電圧Ｖmaxと下限電圧Ｖminを、特性情報Ｓｉｄに基づいて変更することにより、振幅の制限値を変更する。 The control device 3-2 includes an image processing unit 31, a clock signal output unit 32, a control unit 39, and a storage unit 34. The control unit 39 includes a changing unit 40 that changes the amplitude limit value in the clock signal output unit 32 based on the characteristic information Sid stored in the storage unit 26 of the connector 24-2. The changing unit 40 changes the limit value of the amplitude by changing the upper limit voltage V max and the lower limit voltage V min applied to the amplitude limiting unit 38 based on the characteristic information Sid.
　以上説明した本発明の実施の形態２によれば、クロック信号の振幅の上限および下限を変化させることによってクロック信号の振幅を設定値未満に制限して出力するため、位相ノイズおよびスルーレートが良好なクロック信号を出力することができ、内視鏡２－２におけるクロック信号の高品位化を実現することができる。 According to the second embodiment of the present invention described above, the clock signal amplitude is limited to less than the set value by changing the upper and lower limits of the clock signal amplitude, so that the phase noise and the slew rate are good. A high-quality clock signal in the endoscope 2-2 can be realized.
　また、本実施の形態２によれば、制御装置３－２は、接続される内視鏡２－２の種類に応じて最適な振幅の制限値を設定することができる。したがって、汎用性の高い内視鏡システム７を実現することができる。 Further, according to the second embodiment, the control device 3-2 can set an optimal amplitude limit value according to the type of the endoscope 2-2 to be connected. Therefore, the highly versatile endoscope system 7 can be realized.
　加えて、本実施の形態２によれば、クロック信号出力部３２におけるクロック信号の振幅の制限値を製造または出荷時に調整することなく、使用時に調整することができるため、共通のクロック信号出力部３２を用いて異なる種類の内視鏡を製造することができ、内視鏡の生産性を向上させることができる。 In addition, according to the second embodiment, since the limit value of the amplitude of the clock signal in the clock signal output unit 32 can be adjusted at the time of use without adjusting at the time of manufacture or shipment, the common clock signal output unit Different types of endoscopes can be manufactured using 32, and the productivity of the endoscope can be improved.
　図８は、本実施の形態２の変形例に係る内視鏡システムの要部の構成を示すブロック図である。同図に示す内視鏡システム８は、内視鏡２－３と、制御装置３－１と、光源装置４と、表示装置５とを備える。 FIG. 8 is a block diagram showing a configuration of a main part of an endoscope system according to a modification of the second embodiment. The endoscope system 8 shown in the figure includes an endoscope 2-3, a control device 3-1, a light source device 4, and a display device 5.
　内視鏡２－３は、内視鏡２－２と比較して、コネクタ２４－３の構成が異なる。コネクタ２４－３は、コネクタ２４－３の動作を制御する制御部２８と、内視鏡２－３の特性情報Ｓｉｄを記憶する記憶部２６と、を有する。制御部２８は、記憶部２６が記憶する特性情報Ｓｉｄに基づいてクロック信号出力部３２における振幅の制限値を変更する変更部２９を有する。 The endoscope 2-3 is different in the configuration of the connector 24-3 from the endoscope 2-2. The connector 24-3 includes a control unit 28 that controls the operation of the connector 24-3, and a storage unit 26 that stores the characteristic information Sid of the endoscope 2-3. The control unit 28 includes a changing unit 29 that changes the limit value of the amplitude in the clock signal output unit 32 based on the characteristic information Sid stored in the storage unit 26.
　本変形例によれば、実施の形態２と同様の効果を得ることができる。なお、本変形例の場合、内視鏡２－３を製造する段階で、クロック信号出力部３２の振幅を調整して出荷することも考えられる。しかしながら、内視鏡の生産性を考慮した場合、出荷時に内視鏡の種類に応じた調整を行うのは得策ではない。そこで、本変形例においても、実際に使用する際に内視鏡システム８に電源を入れてからクロック信号出力部３２における振幅調整を実行するようにすれば、内視鏡の生産性を向上させることができるのでより好ましい。 According to this modification, the same effect as in the second embodiment can be obtained. In the case of this modification, it may be considered that the amplitude of the clock signal output unit 32 is adjusted before the endoscope 2-3 is manufactured. However, considering the productivity of the endoscope, it is not a good idea to make adjustments according to the type of endoscope at the time of shipment. Therefore, in this modification as well, if the amplitude adjustment in the clock signal output unit 32 is executed after the endoscope system 8 is turned on in actual use, the productivity of the endoscope is improved. This is more preferable.
（実施の形態３）
　図９は、本発明の実施の形態３に係る内視鏡システムの要部の機能構成を示すブロック図である。同図に示す内視鏡システム９は、内視鏡２－４と、制御装置３－３と、光源装置４と、表示装置５とを備える。内視鏡システム９は、クロック信号をシングルエンド伝送する。 (Embodiment 3)
FIG. 9 is a block diagram illustrating a functional configuration of a main part of the endoscope system according to Embodiment 3 of the present invention. An endoscope system 9 shown in the figure includes an endoscope 2-4, a control device 3-3, a light source device 4, and a display device 5. The endoscope system 9 transmits a clock signal in a single end.
　内視鏡２－４は、ユニバーサルコード２３－４等におけるクロック信号の伝送路が１本であることを除いて、内視鏡２と同様の構成を有する。 The endoscope 2-4 has the same configuration as the endoscope 2 except that the transmission path of the clock signal in the universal cord 23-4 or the like is one.
　制御装置３－３は、画像処理部３１と、クロック信号出力部４１と、制御部３３と、記憶部３４とを有する。クロック信号出力部４１は、１つのクロック信号を発生する信号発生部４２と、信号発生部が発生したクロック信号を増幅して振幅を設定値未満の制限値に制限して出力する１つのリミッティングアンプ３６とを有する。 The control device 3-3 includes an image processing unit 31, a clock signal output unit 41, a control unit 33, and a storage unit. The clock signal output unit 41 includes a signal generation unit 42 that generates one clock signal, and one limiting unit that amplifies the clock signal generated by the signal generation unit and limits the amplitude to a limit value less than a set value. And an amplifier 36.
　以上説明した本発明の実施の形態３によれば、実施の形態１等と同様、クロック信号の振幅の上限および下限を変化させることによってクロック信号の振幅を設定値未満の制限値に制限して出力するため、位相ノイズおよびスルーレートが良好なクロック信号を出力することができ、内視鏡におけるクロック信号の高品位化を実現することができる。 According to the third embodiment of the present invention described above, similarly to the first embodiment, the amplitude of the clock signal is limited to a limit value less than the set value by changing the upper and lower limits of the clock signal amplitude. Since it is output, it is possible to output a clock signal with good phase noise and slew rate, and it is possible to realize high quality clock signals in the endoscope.
　なお、本実施の形態３において、クロック信号出力部４１を内視鏡２－４のコネクタ側に設けてもよいし、コネクタの記憶部に内視鏡の特性情報を記憶させておき、この特性情報に基づいてクロック信号出力部４１のリミッティングアンプ３６の振幅の制限値を変更するようにしてもよい。 In the third embodiment, the clock signal output unit 41 may be provided on the connector side of the endoscope 2-4, or the characteristic information of the endoscope is stored in the storage unit of the connector. The limit value of the amplitude of the limiting amplifier 36 of the clock signal output unit 41 may be changed based on the information.
　１、６、７、８、９　内視鏡システム
　２、２－１、２－２、２－３、２－４　内視鏡
　３、３－１、３－２、３－３　制御装置
　４　光源装置
　５　表示装置
　２１　挿入部
　２１ａ　先端部
　２２　操作部
　２３、２３－４　ユニバーサルコード
　２４、２４－１、２４－２、２４－３　コネクタ
　２５、２８、３３、３９　制御部
　２６、３４　記憶部
　２９、４０　変更部
　３１　画像処理部
　３２、４１　クロック信号出力部
　３５、４２　信号発生部
　３６　リミッティングアンプ
　３７　増幅部
　３８　振幅制限部
　１０１　撮像素子
　１０２　ライトガイド
　２０１、２０２　オープンコレクタ回路
　２０３、２０４　高速アナログ差動アンプ
　３７１　アンプ
　３７２、３７３　抵抗
　３８１、３８２　ダイオード
　Ｃ１、Ｃ２、Ｃ３　クロック信号
　Ｓｉｄ　特性情報 1, 6, 7, 8, 9 Endoscope system 2, 2-1, 2-2, 2-3, 2-4 Endoscope 3, 3-1, 3-2, 3-3 Control device 4 Light source Device 5 Display device 21 Insertion portion 21a Tip portion 22 Operation portion 23, 23-4 Universal code 24, 24-1, 24-2, 24-3 Connector 25, 28, 33, 39 Control portion 26, 34 Storage portion 29, 40 Changing unit 31 Image processing unit 32, 41 Clock signal output unit 35, 42 Signal generating unit 36 Limiting amplifier 37 Amplifying unit 38 Amplitude limiting unit 101 Image sensor 102 Light guide 201, 202 Open collector circuit 203, 204 High-speed analog differential Amplifier 371 Amplifier 372, 373 Resistor 381, 382 Diode C1, C2, C3 Clock signal Sid Characteristic information

Claims (7)

  1. 　被検体に挿入されて該被検体内を撮像する内視鏡の先端部と信号の伝送路を介して接続され、前記先端部に対して動作の基準となるクロック信号を出力するクロック信号出力装置であって、
    　前記クロック信号を発生する信号発生部と、
    　前記クロック信号の振幅を設定値まで増幅する増幅部と、
    　前記増幅部が増幅した前記クロック信号の上限および下限を変化させることによって該クロック信号の振幅を前記設定値未満の制限値に制限して出力する振幅制限部と、
    　を備えたことを特徴とするクロック信号出力装置。     A clock signal output device that is connected to a distal end portion of an endoscope that is inserted into a subject and images the inside of the subject through a signal transmission path, and that outputs a clock signal serving as a reference of operation to the distal end portion. Because
    A signal generator for generating the clock signal;
    An amplifier for amplifying the amplitude of the clock signal to a set value;
    An amplitude limiter that limits and outputs the amplitude of the clock signal to a limit value less than the set value by changing an upper limit and a lower limit of the clock signal amplified by the amplifier;
    A clock signal output device comprising:
  2. 　前記振幅制限部は、
    　前記制限値を変更可能であることを特徴とする請求項１に記載のクロック信号出力装置。     The amplitude limiter is
    The clock signal output device according to claim 1, wherein the limit value is changeable.
  3. 　前記制限値は、前記内視鏡の特性に応じて定められることを特徴とする請求項１に記載のクロック信号出力装置。 The clock signal output device according to claim 1, wherein the limit value is determined according to a characteristic of the endoscope.
  4. 　前記増幅部および前記振幅制限部を有する組を２組備え、互いに位相が反転した２つの前記クロック信号を差動出力することを特徴とする請求項１に記載のクロック信号出力装置。 2. The clock signal output device according to claim 1, wherein two sets of the amplification unit and the amplitude limiting unit are provided, and the two clock signals whose phases are inverted are differentially output.
  5. 　被検体に挿入されて該被検体内を撮像する内視鏡に接続され、該内視鏡の動作を制御する制御装置であって、
    　請求項１に記載のクロック信号出力装置と、
    　前記内視鏡の特性に基づいて前記制限値を変更する変更部と、
    　を備えたことを特徴とする制御装置。     A control device that is inserted into a subject and connected to an endoscope that images the inside of the subject and controls the operation of the endoscope,
    A clock signal output device according to claim 1;
    A changing unit that changes the limit value based on the characteristics of the endoscope;
    A control device comprising:
  6. 　被検体に挿入されて該被検体内を撮像する内視鏡であって、
    　先端部に設けられて前記被検体を撮像して撮像信号を出力する撮像素子と、
    　前記撮像素子と信号の伝送路を介して接続されるとともに当該内視鏡の動作を制御する制御装置と通信可能に接続され、請求項１に記載のクロック信号出力装置を有するコネクタと、
    　を備えたことを特徴とする内視鏡。     An endoscope that is inserted into a subject and images the inside of the subject,
    An image sensor provided at the distal end to image the subject and output an imaging signal;
    A connector having the clock signal output device according to claim 1, connected to the imaging device via a signal transmission path and communicably connected to a control device that controls the operation of the endoscope,
    An endoscope characterized by comprising:
  7. 　前記コネクタは、
    　当該内視鏡の特性を記憶する記憶部と、
    　前記特性に基づいて前記制限値を変更する変更部と、
    　を有することを特徴とする請求項６に記載の内視鏡。     The connector is
    A storage unit for storing the characteristics of the endoscope;
    A changing unit for changing the limit value based on the characteristics;
    The endoscope according to claim 6, further comprising:
PCT/JP2015/057949 2014-06-11 2015-03-17 Clock signal outputting device, control device, and endoscope WO2015190147A1 (en)

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