WO2015188511A1 - Procédé et appareil de traitement d'opération de mémoire flash non-et, et dispositif logique - Google Patents

Procédé et appareil de traitement d'opération de mémoire flash non-et, et dispositif logique Download PDF

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Publication number
WO2015188511A1
WO2015188511A1 PCT/CN2014/087232 CN2014087232W WO2015188511A1 WO 2015188511 A1 WO2015188511 A1 WO 2015188511A1 CN 2014087232 W CN2014087232 W CN 2014087232W WO 2015188511 A1 WO2015188511 A1 WO 2015188511A1
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Prior art keywords
nand flash
address
protection table
address protection
protection
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PCT/CN2014/087232
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English (en)
Chinese (zh)
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沈楠科
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中兴通讯股份有限公司
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Publication of WO2015188511A1 publication Critical patent/WO2015188511A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

Definitions

  • the present invention relates to the field of communications, and in particular to a NAND Flash operation processing method, apparatus, and logic device.
  • NAND Flash Non-volatile memories
  • NOR Flash NOR Flash
  • NAND Flash NAND Flash
  • NOR Flash NOR Flash
  • NAND Flash NAND Flash memory
  • NOR Flash memory has a much faster write speed than NOR Flash memory and has a faster erase speed. It is faster than NOR Flash memory, has a large single-chip capacity, and has low cost per unit storage capacity. It is suitable for storing large amounts of data. Due to technical development needs and cost reasons, NAND Flash has been widely used in various electronic products.
  • NAND Flash In various occasions where NAND Flash is selected, improper operation from software may cause NAND Flash to be erased by mistake, which may cause serious consequences, especially when the boot and system running versions used for system booting are erroneously erased. It may even cause the system to fail to start.
  • NAND Flash has an unreliable problem caused by erroneous erasure and writing.
  • the invention provides a NAND Flash operation processing method, device and logic device to solve the problem that the NAND Flash in the related art is unreliable due to error erasure and writing.
  • a NAND Flash operation processing method including: establishing an address protection table for protecting a NAND Flash protection area; and determining whether an address for operating the NAND Flash exists in the address protection table In the case where the judgment result is YES, the operation on the NAND Flash is masked.
  • the address protection table for protecting the NAND flash protection area includes: an importance degree division level for protecting different areas of the NAND Flash protection area; corresponding to the different areas according to the division level Address, establish an address protection table.
  • the method further includes: updating the address protection table.
  • determining whether an address for operating the NAND Flash exists in the address protection table comprises: parsing a signal command from the central processing unit CPU to operate the NAND flash; comparing the signal command Whether the address of the NAND Flash matches the address in the address protection table; in the case of matching, it is determined whether an address operating on the NAND Flash exists in the address protection table.
  • masking the operation of the NAND Flash comprises: determining whether an operation type of the operation of the NAND Flash is a modification operation; and if the determination result is YES, masking the operation of the NAND Flash.
  • a NAND Flash operation processing apparatus includes: an establishment module configured to establish an address protection table for protecting a NAND Flash protection area; and a determination module configured to determine to perform the NAND Flash Whether the address of the operation exists in the address protection table; and the masking module is configured to mask the operation of the NAND Flash if the determination result of the determination module is YES.
  • the establishing module includes: a dividing unit, configured to divide a level of importance of protecting different areas of the NAND Flash protection area; and establishing a unit, which is set to an address corresponding to the different area after the dividing level, Create an address protection table.
  • the apparatus further comprises: an update module configured to update the address protection table.
  • the determining module comprises: a parsing unit configured to parse a signal command from the central processing unit CPU to operate the NAND flash; and a comparing unit configured to compare the NAND flash for the signal command Whether the address matches the address in the address protection table; the determining unit is configured to determine, in the case of matching, whether an address operating on the NAND Flash exists in the address protection table.
  • the masking module includes: a determining unit configured to determine whether an operation type of the operation of the NAND Flash is a modification operation; and a shielding unit configured to block the determination result of the determining unit as yes The operation of the NAND Flash.
  • a logic device comprising the apparatus of any of the above.
  • an address protection table for protecting a NAND flash protection area is established; whether an address for operating the NAND Flash exists in the address protection table is determined; and if the determination result is yes, the shielding is performed.
  • the operation of NAND Flash solves the problem that NAND Flash exists in related technologies.
  • the problem of unreliable storage caused by erasing and writing achieves the effect of not only effectively preventing the important storage area from being damaged, but also effectively improving the reliability of the NAND Flash stored data.
  • FIG. 1 is a flowchart of a NAND Flash operation processing method according to an embodiment of the present invention
  • FIG. 2 is a block diagram showing the structure of a NAND Flash operation processing apparatus according to an embodiment of the present invention
  • FIG. 3 is a structural block diagram of a setup module 22 in a NAND Flash operation processing apparatus according to an embodiment of the present invention
  • FIG. 4 is a block diagram showing a preferred structure of a NAND Flash operation processing apparatus according to an embodiment of the present invention
  • FIG. 5 is a structural block diagram of a determining module 24 in a NAND Flash operation processing apparatus according to an embodiment of the present invention
  • FIG. 6 is a structural block diagram of a masking module 26 in a NAND Flash operation processing apparatus according to an embodiment of the present invention
  • FIG. 7 is a structural block diagram of a logic device in accordance with an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of an architecture for preventing NAND Flash from being erased and erroneously written according to an embodiment of the present invention
  • FIG. 9 is a functional explanatory diagram of an implementation method for preventing NAND Flash from being erroneously erased and erroneously written according to an embodiment of the present invention.
  • FIG. 10 is a flowchart of an implementation method for preventing NAND FLASH from being erroneously erased and erroneously written according to an embodiment of the present invention
  • FIG. 11 is a flow diagram of adding or modifying a protected area to prevent an NAND FLASH from being erased and miswritten by an implementation in accordance with an embodiment of the present invention.
  • FIG. 1 is a flowchart of a NAND Flash operation processing method according to an embodiment of the present invention. As shown in FIG. 1, the flow includes the following steps:
  • Step S102 establishing an address protection table for protecting the NAND Flash protection area
  • Step S104 determining whether an address for operating the NAND Flash exists in the address protection table
  • step S106 if the determination result is YES, the operation on the NAND Flash is masked.
  • the storage area of the NAND Flash is protected according to the establishment of the address protection table, which not only effectively solves the problem that the NAND Flash area is not protected in the related art, and the storage caused by the erroneous erasure and writing of the NAND Flash is unreliable. It may even cause the system to fail to boot, and effectively improve the reliability of the data stored in the NAND Flash.
  • an address protection table for protecting a NAND Flash protection area When establishing an address protection table for protecting a NAND Flash protection area, a plurality of methods may be used. For example, when different protection areas need to be treated differently, the importance level of protection of different areas of the NAND Flash protection area may be divided; An address protection table is established according to addresses corresponding to different areas after the level is divided. Through such processing, the data stored in the NAND Flash area is distinguished to a significant extent. For example, the protection level can be set to be the highest for which it is particularly important that it cannot be deleted, and can be set slightly lower for the general importance.
  • the address protection table may also be updated.
  • the importance of the NAND Flash storage area changes during different periods, and therefore, the address needs to be The protection table is updated accordingly to suit the needs of different periods.
  • the signal command for operating the NAND Flash from the CPU of the central processing unit may be parsed first; the address and address protection table of the NAND Flash for comparing the signal command may be Whether the addresses in the match match; in the case of matching, it is determined whether the address operating on the NAND Flash exists in the address protection table.
  • the operation on the NAND Flash is masked, the operation of erasing or modifying important data (protecting data stored in the corresponding area of the address) (for example, some simple read operations) is also blocked. , which may affect the user experience.
  • important data protecting data stored in the corresponding area of the address
  • a NAND Flash operation processing device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and has not been described again.
  • the term "module” A combination of software and/or hardware that can implement a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • FIG. 2 is a block diagram showing the structure of a NAND Flash operation processing apparatus according to an embodiment of the present invention. As shown in FIG. 2, the apparatus includes a setup module 22, a determination module 24, and a masking module 26. The apparatus will be described below.
  • the establishing module 22 is configured to establish an address protection table for protecting the NAND flash protection area; the determining module 24 is connected to the establishing module 22, and configured to determine whether an address for operating the NAND Flash exists in the address protection table; 26, connected to the above determining module 24, configured to mask the operation of the NAND Flash when the determination result of the determining module is YES.
  • FIG. 3 is a structural block diagram of a setup module 22 in a NAND Flash operation processing apparatus according to an embodiment of the present invention.
  • the setup module 22 includes a division unit 32 and an establishment unit 34.
  • the setup module 22 is described below. .
  • the dividing unit 32 is configured to divide the importance level of the different areas of the NAND Flash protection area; the establishing unit 34 is connected to the dividing unit 32, and is configured to establish an address protection table according to addresses corresponding to different areas after the dividing level .
  • FIG. 4 is a block diagram of a preferred structure of a NAND Flash operation processing apparatus according to an embodiment of the present invention. As shown in FIG. 4, the apparatus includes, in addition to all the structures shown in FIG. 2, an update module 42, which is updated below. Module 42 is described.
  • the update module 42 is coupled to the setup module 22 and the determination module 24, and is configured to update the address protection table.
  • FIG. 5 is a structural block diagram of the determining module 24 in the NAND Flash operation processing apparatus according to an embodiment of the present invention. As shown in FIG. 5, the determining module 24 includes: a parsing unit 52, a comparing unit 54, and a determining unit 56. The determination module 24 is described.
  • the parsing unit 52 is configured to parse a signal command from the central processing unit CPU for operating the NAND flash; the comparing unit 54 is connected to the parsing unit 52, and is configured to compare the address and address protection table of the NAND flash for which the signal command is directed Whether the addresses match, the determining unit 56 is connected to the comparing unit 54 described above, and is arranged to determine, in the case of matching, whether an address operating on the NAND Flash exists in the address protection table.
  • FIG. 6 is a structural block diagram of a masking module 24 in a NAND Flash operation processing apparatus according to an embodiment of the present invention.
  • the masking module 26 includes: a determining unit 62 and a shielding unit 64, and the masking module 26 is performed below. Description.
  • the judging unit 62 is configured to determine whether the operation type of the operation of the NAND flash is a modification operation; the masking unit 64 is connected to the judging unit 62, and is configured to mask the NAND flash if the judgment result of the judging unit is YES. operating.
  • the logic device 70 includes the NAND Flash operation processing device 72 of any of the above.
  • the implementation method of preventing NAND flash from being erased and misprogrammed (false write) is through such address filtering and masking method to prevent a specific storage area from being damaged during an erroneous operation.
  • the following processing methods can be used to achieve:
  • FIG. 8 is a schematic diagram of an architecture for preventing NAND flash from being erroneously erased and erroneously written according to an embodiment of the present invention.
  • the physical components included in the implementation method mainly include: a central processing unit (Central Processing Unit) , referred to as CPU), logic device (Field Programmable Gate Array (FPGA) or Complex Programmable Logic Device (CPLD)), NAND Flash.
  • CPU Central Processing Unit
  • FPGA Field Programmable Gate Array
  • CPLD Complex Programmable Logic Device
  • the CPU can access the internal Flash of the logic device through the control interface while providing the Flash interface to the logic device.
  • the interface that the CPU accesses the internal Flash of the logic device can be various types, such as interfaces in the form of IIC, LOCAL BUS, SPI, etc., which depend on the interface provided by the processor.
  • the logic device can be either FPGA or CPLD.
  • the various logic devices on the market have built-in Flash.
  • the address protection table is stored in the Flash of the logic device.
  • the CPU can read, write, and store the address protection table.
  • the protected area may be a boot area, a boot area, a large version area, and other storage areas for important information.
  • the physical block addresses corresponding to these protected areas are stored in the address protection table.
  • the logic device extracts the Row Address corresponding to these block addresses and compares it with the Row Address in the NAND Flash port. Once the same, the erase or program command is masked.
  • the solution further includes establishment and update of the protection address table, signal analysis of the NAND Flash interface, masking of the error erasing and misprogramming commands, and status indication.
  • the protection of the flash memory generally uses the staggered address space to make the Flash cannot be accessed, and this method is limited to the application of the NOR Flash.
  • the above address protection table the protection against false erase and misprogramming of the boot area, the boot area, the large version area, and other important information storage areas on the NAND Flash is realized, and the protection method is protected by this protection method.
  • no additional intervention is required by the software, which reduces the complexity of the software, reduces the workload of the processor, and improves the system reliability.
  • FIG. 9 is a functional explanatory diagram of an implementation method for preventing NAND flash from being erroneously erased and erroneously written according to an embodiment of the present invention.
  • the functional components of the scheme include: 101 processors. (CPU), 102 NAND Flash, 103 address protection table, 104 NAND Flash I/O interface parser, 105 NAND Flash I/O address filter, 106 access status indicator.
  • the 101 processor can access the 103 address protection table in the internal Flash of the logic device through the control interface, and provide the Flash interface to the logic device.
  • the CPU accesses the internal Flash interface of the logic device. It can be various types, such as IIC, LOCAL BUS, SPI, etc. The type of the specific interface depends on the CPU.
  • the logic device can be either FPGA or CPLD.
  • the CPU can access (read and write) the 103 address protection table in the built-in Flash of the logic device.
  • the 104 NAND Flash I/O interface parser in the logic device parses the signal from the CPU's Flash interface. The parsed address is compared with the 103 address protection table.
  • the 105 NAND Flash I/O address filter determines whether to mask the wipe. In addition to or programming commands.
  • the 106 access status indicator indicates the current state in which erasure, programming, or normal access is prohibited.
  • This flag can have a check digit to distinguish it from the value when Flash was not written.
  • the memory device is 102 NAND Flash, and each block on the 102 NAND Flash can be read, erased, and programmed.
  • NAND Flash is used to store boot code, boot code, large version code, other important information, and other relatively less important information.
  • FIG. 10 is a flowchart of a method for preventing NAND FLASH from being erroneously erased and erroneously written according to an embodiment of the present invention. As shown in FIG. 10, the process includes the following steps:
  • Step A After the system is reset or powered on, the logic device first causes the CPU to be in a reset state, waiting for the logic to read the address protection table;
  • Step B The logic reads the address protection table from the built-in Flash
  • Step C If the interval that does not require protection is read from the head of the address protection table, the protection address is processed in the default manner in the logic code, for example, transparently transmitting the address and the command. Otherwise, the protection interval is extracted according to the information in the flash;
  • Step D The logic determines the address to be filtered according to the extracted protection interval information, for example, the Row Address of the protected block;
  • Step E Release the reset of the processor CPU to enable the CPU to start
  • Step F After the processor CPU is started, accessing the NAND Flash, the logic collects the interface information, first determines the type of the command, and if the parsed command is not Erase or Program edit, it is a read operation. (Read), the command is directly transmitted to the NAND Flash, and the normal access to the NAND Flash;
  • Step G If the logic parsed command is Erase or Program, compare the Row Address of the protected block in step D. If the address does not match, the command is directly transmitted to the NAND Flash, and the NAND Flash is normally accessed.
  • Step H If the logic parsed command is Erase or Program, compare the Row Address of the protected block in step D. If the address matches, the corresponding command is masked and fed back to the flag register to display an illegal Erase or Program.
  • FIG. 11 is a flowchart of adding or modifying a protected area to prevent an NAND FLASH from being erased and miswritten by an implementation method according to an embodiment of the present invention. As shown in FIG. 11, if a guard interval needs to be changed, the flow includes the following step:
  • Step A The system background starts the version update in the NAND Flash
  • Step B The system notifies the logic to release the logical address protection, and transparently transmits all the commands of the originally set NAND FLASH protected interval;
  • Step C The system starts downloading and updating the content in the NAND Flash
  • Step D If the system downloads the update NAND Flash fails, the download update is terminated, and the update failure flag is set, and the logical address protection is restored.
  • Step E If the system downloads and updates the NAND Flash successfully, the address protection table is updated, and the update success flag is set at the same time;
  • Step F Update the protection flag of the address protection table to indicate that there is an address range that needs to be protected
  • Step G The logic initiates address filtering in accordance with the updated address protection table.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • the above embodiments and preferred embodiments solve the problem that the NAND Flash in the related art is unreliable due to erroneous erasure and writing, thereby achieving not only the effective avoidance of the important storage area being damaged, but also The effect of the reliability of the data stored in the NAND Flash is effectively improved.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

L'invention concerne un procédé et un appareil de traitement d'opération de mémoire flash NON-ET et un dispositif logique. Le procédé consiste : à établir une table de protection d'adresse pour protéger une région de protection de mémoire flash NON-ET; à déterminer si une adresse à laquelle la mémoire flash NON-ET est mise en œuvre existe ou non dans la table de protection d'adresse ; et dans le cas où un résultat de détermination est positif, à protéger une opération effectuée sur la mémoire flash NON-ET. La présente invention résout le problème dans l'état de la technique selon lequel la mémoire flash NON-ET n'est pas correctement effacée et écrite, ce qui permet d'obtenir l'effet que non seulement une région de mémorisation importante peut être efficacement empêchée d'être endommagée, mais la fiabilité d'une mémoire flash NON-ET pour mémoriser des données est également améliorée de manière efficace.
PCT/CN2014/087232 2014-06-09 2014-09-23 Procédé et appareil de traitement d'opération de mémoire flash non-et, et dispositif logique WO2015188511A1 (fr)

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CN201410253586.2A CN105279094A (zh) 2014-06-09 2014-06-09 NAND Flash操作处理方法、装置及逻辑器件
CN201410253586.2 2014-06-09

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CN107145805B (zh) * 2017-03-21 2020-01-17 芯海科技（深圳）股份有限公司 一种flash/mtp内部数据防误擦写的实现方法
CN107608905B (zh) * 2017-09-11 2020-05-12 杭州中天微系统有限公司 擦写Flash数据的方法及装置
CN111966611B (zh) * 2020-08-03 2023-12-12 南京扬贺扬微电子科技有限公司 具有逻辑转物理地址架构的spi闪存控制芯片
CN113407453A (zh) * 2021-06-29 2021-09-17 芯天下技术股份有限公司 数据保护位的验证方法、装置、电子设备及存储介质

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