WO2015188420A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2015188420A1
WO2015188420A1 PCT/CN2014/081699 CN2014081699W WO2015188420A1 WO 2015188420 A1 WO2015188420 A1 WO 2015188420A1 CN 2014081699 W CN2014081699 W CN 2014081699W WO 2015188420 A1 WO2015188420 A1 WO 2015188420A1
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WO
WIPO (PCT)
Prior art keywords
sub
array substrate
line
pixel unit
pixel
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Ceased
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PCT/CN2014/081699
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English (en)
French (fr)
Inventor
王聪
施明宏
杜鹏
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/416,449 priority Critical patent/US9507228B2/en
Publication of WO2015188420A1 publication Critical patent/WO2015188420A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present invention relates to the field of display technologies, and in particular to an array substrate and a display device.
  • liquid crystal displays have become the most common flat panel display devices.
  • the liquid crystal display is composed of an array substrate and a color filter substrate.
  • the array substrate is provided with an array of thousands of sub-pixel units, and a grid line and a data line for separating the sub-pixel units.
  • the array substrate is usually provided with a common electrode line parallel to the gate line.
  • a color film layer and a black matrix are disposed on the color filter substrate, wherein the position of the color film layer corresponds to the sub-pixel unit on the array substrate, and the position of the black matrix corresponds to the sub-pixels such as the gate line, the data line and the common electrode line on the array substrate.
  • the black matrix has a large accumulation, and thus the conventional liquid crystal display has a technique of lower aperture ratio.
  • the present invention provides an array substrate comprising a plurality of sub-pixel units arranged in an array, and a plurality of signal lines; one of the adjacent two signal lines is located on a first direction side of the corresponding sub-pixel unit The other signal line is located on the second direction side of the corresponding sub-pixel unit;
  • the first direction side and the second direction side are respectively opposite sides of the sub-pixel unit.
  • the signal line is a gate line corresponding to each sub-pixel unit of each row.
  • the array substrate further includes a plurality of common electrode lines corresponding to the sub-pixel units of each row.
  • the gate lines and the common electrode lines corresponding to the same row of sub-pixel units are located on the same side of the row of sub-pixel units.
  • the common electrode line is located between the machine line and the row of sub-pixel units.
  • the outline is located between the common electrode line and the row of sub-pixel units.
  • the pole line is disposed in the same layer as the common electrode line.
  • the sub-pixel unit includes a storage capacitor and a pixel electrode;
  • the storage capacitor is connected to the machine line, and the other end of the storage capacitor is connected to the pixel electrode.
  • the signal line is a data line corresponding to each column of the sub-pixel unit.
  • the present invention also provides a display device comprising a color film substrate and the above array substrate;
  • the color film substrate is provided with a color film layer and a black matrix, the color film layer corresponding to the sub-pixel unit on the array substrate, and the position of the black matrix corresponds to the array substrate An area other than the sub-pixel unit.
  • one signal line is located on the first direction side of the corresponding sub-pixel unit, and the other signal line adjacent to the signal line is located in the corresponding sub-pixel.
  • a second direction side of the unit, and the first direction side and the second direction side are respectively opposite sides of the sub-pixel unit, so that two adjacent signal lines are disposed close to each other, that is, the adjacent 3 ⁇ 4 signal lines are located Corresponding two rows (columns) between sub-pixel units.
  • the edge of the black matrix on the color filter substrate has a part exceeding the edge of the signal line. If the width of the excess portion is S, the width of the two signal lines is A, and the spacing between the two signal lines For L, the width of the black matrix covering the two signal lines is 2A+2S+L.
  • each signal line is separately set, and the width of the black matrix covering each signal line is A+2S, and the total width of the black matrix covering the two signal lines is 2A+4S. Therefore, compared with the prior art, in the technical solution provided by the present invention, the width of the black matrix covering every two signal lines is reduced by 2S-L, and the spacing L of the adjacent two signal lines can be set very small. Therefore, the area of the black matrix can be significantly reduced, the aperture ratio of the liquid crystal display can be improved, and the technical problem of the low aperture ratio of the conventional liquid crystal display can be solved.
  • FIG. 1 is a schematic view of an array substrate according to Embodiment 1 of the present invention.
  • Figure 2 is a partial schematic view of the portion of the - line and common electrode lines of Figure 1;
  • FIG. 3 is a schematic view of a conventional array substrate
  • Figure 4 is a partial schematic view of the portion of the line and the common electrode line of Figure 3;
  • FIG. 5 is a schematic view of an array substrate according to a second embodiment of the present invention -
  • FIG. 6 is a partial schematic view of the portion of the machine line of FIG.
  • FIG. 7 is a schematic diagram of an array substrate provided by an embodiment of the present invention.
  • Figure 8 is a partial schematic view of the data line portion of Figure 7;
  • Figure 9 is a partial schematic view of the portion of the data line of Figure 3. detailed description
  • Embodiments of the present invention provide an array substrate including a plurality of sub-pixel units arranged in an array, and thousands of signal lines dividing the sub-pixel units.
  • One of the adjacent two signal lines is located on the first direction side of the corresponding sub-pixel unit, and the other signal line is located on the second direction side of the corresponding sub-pixel unit, and the first direction side and the The two direction sides are respectively opposite sides of the sub-pixel unit.
  • one signal line is located on a first direction side of the corresponding sub-pixel unit, and another signal line adjacent to the signal line is located on a second direction side of the corresponding sub-pixel unit.
  • the first direction side and the second direction side are respectively opposite sides of the sub-pixel unit, so that the adjacent two signal lines are close to each other, that is, The two adjacent signal lines are located between their corresponding two rows (columns) of sub-pixel units.
  • the edge of the black matrix on the color filter substrate has a part exceeding the edge of the signal line.
  • the width of the excess portion is S
  • the width of the two signal lines is A
  • the width of the black matrix covering the two signal lines is 2 ⁇ +28+ ⁇
  • each signal line is separately set, and the width of the black matrix covering each signal line is A+2S.
  • the total width of the black matrix covering the two signal lines is 2A+4S. Therefore, compared with the prior art, in the technical solution provided by the embodiment of the present invention, the width of the black matrix covering every two signal lines is reduced by 2S-L, and the spacing L of the adjacent two signal lines can be set very much.
  • Embodiment 1 The array substrate provided by the embodiment of the present invention includes a plurality of sub-pixel units arranged in an array, and a plurality of signal lines.
  • the signal lines in this embodiment are gate lines 2 corresponding to each row of sub-pixel units 1, as shown in FIG.
  • G(ii) and G(n+1) where G(n) is located on the lower side (first direction side) of the sub-pixel unit 1 corresponding thereto, G(ii ten 1) Located on the upper side of the sub-pixel unit 1 corresponding thereto (the second direction side, and the first direction side and the second direction side are respectively opposite sides of the sub-pixel unit).
  • G(n+2) is located on the lower side of the corresponding sub-pixel unit 1
  • G(n+3) is located in the corresponding sub-pixel unit.
  • G(n+!) and G(n+2) can also be regarded as two adjacent gate lines, which is equivalent to G(n+2) located on the lower side of the corresponding sub-pixel unit 1 (first The direction side), G(n+1) is located on the upper side of the sub-pixel unit 1 corresponding thereto (the second direction side, the first side 1 side and the second direction side are respectively opposite sides of the sub-pixel unit).
  • the array substrate provided by the embodiment of the present invention further includes a common electrode line 3 corresponding to each row of sub-pixel units 1 for supplying a voltage to a common electrode (not shown) corresponding to each sub-pixel unit 1.
  • the gate line 2 and the common electrode line 3 may be disposed in the same layer, so that the » line 2 and the common electrode line 3 can be simultaneously formed in one patterning process.
  • the gate line 2 and the common electrode line 3 corresponding to the same row of sub-pixel units 1 are located on the same side of the row of sub-pixel units 1, so that the machine line 2 and the common electrode line 3 can be collectively
  • the black matrix is covered to reduce the number of black matrices. For example, in FIG. 1, G(n) and COM(n) are both located on the lower side of the sub-pixel unit 1 corresponding thereto, and G(n+! and COM(trH) are both located on the sub-pixel unit 1 corresponding thereto.
  • G(n), COM(n), COM(n+l), and G(n+1) can all be covered by the same black matrix.
  • the common electrode line 3 in the gate line 2 and the common electrode line 3 corresponding to the same row of sub-pixel units 1, the common electrode line 3 is located between the ⁇ line 2 and the row of sub-pixel units 1, so that the common electrode line 3 is larger than the gate line. 2 is closer to the sub-pixel unit 1 to It is convenient for the common electrode line 3 to supply a voltage to the common electrode.
  • COM(n) is closer to the corresponding sub-pixel unit 1 than G( n )
  • COM(n+l) is closer to the corresponding sub-pixel unit 1 than G(n+1).
  • G(n) is located on the lower side of the sub-pixel unit 1 corresponding thereto, and G(n+1) adjacent to G(n) is located on the sub-pixel unit 1 corresponding thereto.
  • Side such that adjacent G(n) and G(n+1) are disposed close to each other, that is, G(ii) and G(irfl) are located between the two rows of sub-pixel units 1 corresponding thereto, and the two rows are
  • the common electrode lines COM(n) and COM(n+1) corresponding to the pixel unit 1 are also located between the two rows of sub-pixel units 1.
  • the edge of the black matrix 5 on the color filter substrate has a portion exceeding the edge of the polar line 2, and if the width of the excess portion is S, the gate line 2, the common electrode line 3 and The total width of the spacing is A', and the spacing between G(n) and G(ii+1) is L, covering G(n), COM(n), COM(n+l), G(n+1)
  • the width of the black matrix 5 is 2A' + 2S + L.
  • each pole line 2 and each common electrode line 3 are separately provided, and the width of the black matrix 5 covering G(n) and C()M(n) is A. , +2S, the width of the black short matrix 5 covering G(n+1) and COM(n+l) is also +2S, then covers G(n), COM(n), COM(n+l), G
  • the total width of the black matrix 5 of (n+1) is 2A' + 4S.
  • the total width of the black matrix 5 covering every two gate lines 2 and two common electrode lines 3 is reduced by 2S-L, and adjacent two
  • the pitch L of the grid lines 2 can be set very small, and the smaller the L, the smaller the width of the black matrix 5, so that the area of the black matrix 5 can be significantly reduced, the aperture ratio of the liquid crystal display can be improved, and the existing liquid crystal can be solved.
  • the polar lines may be disposed between the common electrode lines and the row of sub-pixel units.
  • the common electrode line corresponds to two rows of sub-pixel units, and the common electrode line supplies voltage to the common electrodes of the two rows of sub-pixel units.
  • the array substrate includes a plurality of sub-pixel units 1 arranged in an array, and a plurality of gate lines. As shown in Figure 5.
  • the two adjacent machine wires for example, G(ti) and G(n+1), where G(n) is located on the lower side of the corresponding sub-pixel unit 1, and G(n+1) is located corresponding thereto.
  • G(tr 2) is located on the side of the corresponding sub-pixel unit 1
  • G(n+3) is located in the corresponding sub-pixel unit 1 The upper side.
  • the sub-pixel unit 1 includes a storage capacitor 6 and a pixel electrode (not shown), and one end of the storage capacitor 6 is connected to the machine line 2. , the other end of the storage capacitor 6 The pixel electrodes are connected. Specifically, an overlapping portion between the pixel electrode and the gate line 2 can be formed, and the overlapping portion forms the storage capacitor 6, thereby eliminating the common electrode line.
  • the width of the edge of the black matrix 5 beyond the edge of the gate line 2 is S
  • the width of the gate line 2 is A
  • the spacing between G(n) and G(trH) is L.
  • the width of the black matrix 5 covering G(n) and G(n+1) is 2A+2S+L.
  • the width A of the » line in this embodiment is only a part of A' in the first embodiment, so the technical solution provided by the embodiment can be further reduced.
  • the width of the black matrix 5 gives the liquid crystal display a higher aperture ratio.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the array substrate provided by the embodiment of the invention includes a plurality of sub-pixel units 1 arranged in an array, and a plurality of signal lines.
  • the signal lines in this embodiment are data lines 4 corresponding to each column of sub-pixel units 1, as shown in FIG.
  • the left side of the corresponding sub-pixel unit 1 (the second direction side, and the first direction side and the second direction side are respectively opposite sides of the sub-pixel unit).
  • D(n+2) is located on the right side of the corresponding sub-pixel unit 1
  • D(n+3) is located in the corresponding sub-pixel The left side of the pixel unit 1.
  • G(n+1) and G(n+2) may be regarded as two adjacent data lines 4, and G(n+2) is equivalent to the right of the sub-pixel unit 1 corresponding thereto.
  • the side (the first direction side), G(n+1) is located on the left side of the sub-pixel unit 1 corresponding thereto (the second direction side, and the first direction side and the second direction side are respectively opposite sides of the sub-pixel unit ).
  • the array substrate according to an embodiment of the present invention D (n) to the right of the corresponding sub-pixel unit I, and D (n) adjacent to the D (n + 1) corresponding thereto in the left sub-pixel units 1
  • the side is such that adjacent D(n) and D(n+1) are disposed close to each other, that is, D(n) and D(n+1) are located between the two rows of sub-pixel units 1 corresponding thereto. As shown in FIG.
  • the edge of the black matrix 5 on the color filter substrate has a portion exceeding the edge of the data line 4, and if the width of the excess portion is S, the width of the data line 4 is ⁇ , ⁇ )
  • the distance between ( ⁇ and D i+ ) is L, and the width of the black matrix covering D(n) and D(n+1) is 2B+2S+L,
  • each data line 4 is separately provided, and the width of the black matrix 5 covering D(n) is B 2S, and the width of the black matrix 5 covering D (ii+I) is set. Also for B+2S, the total width of the black matrix 5 covering: D(n) and ⁇ ) ( ⁇ +1) is 2B+4S.
  • the width of the black matrix 5 covering each two data lines 4 is reduced by 2S-L, and the spacing L of adjacent two data lines 4 can be
  • the setting is very small, the smaller the L is, the smaller the width of the black matrix 5 is, so that the area of the black matrix 5 can be significantly reduced, the aperture ratio of the liquid crystal display is improved, and the existing liquid crystal display has a low mouth-opening rate.
  • the first embodiment, the second embodiment, and the third embodiment of the embodiment may be combined.
  • the gate lines on the array substrate are disposed such that adjacent two pole lines are located between the two rows of sub-pixel units corresponding thereto; meanwhile, the data lines on the array substrate are also set to two adjacent data.
  • the line is located between the two rows of sub-pixel units corresponding thereto, so that the width of the black matrix corresponding to the position of the gate line and the data line can be reduced, thereby increasing the aperture ratio of the liquid crystal display to a greater extent.
  • a display device which may specifically be a display device such as a liquid crystal television, a liquid crystal display, a mobile phone, or a tablet computer.
  • the display device comprises a color film substrate and the array substrate provided in the first embodiment, the second embodiment or the third embodiment.
  • a color film layer and a black matrix are disposed on the color filter substrate, wherein the position of the color film layer corresponds to the sub-pixel unit on the array substrate, and the position of the black matrix corresponds to the gate line, the data line, and the public outside the sub-pixel unit on the array substrate. Electrode lines, thin film transistors, board side traces, etc.
  • the display device provided by the embodiment of the present invention has the same technical features as the array substrate provided in the first embodiment, the second embodiment, and the third embodiment, so that the same technical problem can be solved and the same technical effect can be achieved. While the embodiments of the present invention have been described above, the described embodiments are merely illustrative of the embodiments of the invention, and are not intended to limit the invention. Any modification and variation in the form and details of the embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention. , still subject to the scope defined by the appended claims.

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Abstract

一种阵列基板，包括阵列式排布的若干个子像素单元（1），以及若干条信号线（2）；相邻的两条信号线（2）中，其中一条信号线（2）位于与其对应的子像素单元（1）的第一方向侧，另一条信号线（2）位于与其对应的子像素单元（1）的第二方向侧；所述第一方向侧和所述第二方向侧分别为子像素单元（1）的相对两侧；一种显示装置，包括上述阵列基板。该阵列基板及显示装置可用于液晶电视、液晶显示器、手机、平板电脑等显示装置。

Description

阵列基板及显示装置 本申请要求享有 2014年 6月 11日提交的名称为 "阵列基板及显示装置" 的中国专利 申请 CN201410258802.2的优先权， 其全部内容通 引用并入本文中。 技术领域
本发明涉及显示技术领域， 具体地说， 涉及一种阵列基板及显示装置。
随着显示技术的发展， 液晶显示器已经成为最为常见的平板显示装置。
液晶显示器由阵列基板和彩膜基板组成。阵列基板上设置有阵列式排布的若千个子像 素单元， 以及分隔出各子像素单元的纵横交错的栅线和数据线， 阵列基板上通常还设置有 与栅线平行的公共电极线。彩膜基板上设置有彩膜层和黑矩阵，彩膜层的位置对应于阵列 基板上的子像素单元，黑矩阵的位置对应于阵列基板上的栅线、数据线和公共电极线等子 像素单元以外的区域， 以防止子像素单元以外的区域发生漏光。
现有的液晶显示器中， 为了能够完全覆盖栅线、数据线和公共电极线等部分， 黑矩阵 的靣积较大， 因此现有的液晶显示器存在开口率较低的技术 1¾题。 发明内容
本发明的目的在于提供一种阵列基板及显示装置，以解决现有的液晶显示器存在的开 口率较低的技术问题。
本发明提供一种阵列基板,包括阵列式排布的若干个子像素单元，以及若干条信号线； 相邻的两条信号线中，其中一条信号线位于与其对应的子像素单元的第一方向侧，另 一条信号线位于与其对应的子像素单元的第二方向侧；
所述第一方向侧和所述第二方向侧分别为子像素单元的相对两侧。
在一种实现方式中， 所述信号线为与每行所述子像素单元对应的栅线。 进一步， 该阵列基板还包括对应亍每行所述子像素单元的若干条公共电极线。
优选的，与同一行子像素单元对应的栅线和公共电极线，均位于该行子像素单元的同 侧。
优选的， 与同一行子像素单元对应的 «线和公共电极线中， 公共电极线位于機线与该 行子像素单元之间。
或者，与同一行子像素单元对应的栅线和公共电极线中，概线位于公共电极线与该行 子像素单元之间。
优选的， 所述極线与所述公共电极线同层设置。 进一步， 所述子像素单元中包括存储电容和像素电极；
所述存储电容的一端与機线相连， 所述存储电容的另一端与所述像素电极相连。 在另一种实现方式中， 所述信号线为与每列所述子像素单元对应的数据线。 本发明还提供一种显示装置， 包括彩膜基板和上述的阵列基板；
所述彩膜基板上设置有彩膜层和黑短阵，所述彩膜层的位置对应于所述阵列基板上的 子像素单元， 所述黑短阵的位置对应于所述阵列基板上的子像素单元以外的区域。
本发明带来了以下有益效果：本发明提供的阵列基板中，一条信号线位于与其对应的 子像素单元的第一方向侧，与该信号线相邻的另一条信号线位于与其对应的子像素单元的 第二方向侧， 且第一方向侧和第二方向侧分别为子像素单元的相对两侧，从而使相邻的两 条信号线靠近设置， 即该相邻的 ¾条信号线位于与其对应的两行 （列） 子像素单元之间。 为了防止漏光，彩膜基板上的黑矩阵的边缘会有一部分超出信号线的边缘，如果该超出的 部分的宽度为 S， 这两条信号线的宽度均为 A, 这两条信号线的间距为 L, 则覆盖这两条 信号线的黑矩阵的宽度为 2A+2S+L。
现有技术中， 各条信号线单独设置， 覆盖每条信号线的黑矩阵的宽度均为 A+2S, 则 覆盖两条信号线的黑矩阵的总宽度为 2A+4S。 因此， 与现有技术相比， 本发明提供的技 术方案中， 覆盖每两条信号线的黑矩阵的宽度减少了 2S- L, 而相邻两条信号线的间距 L 可以设置得非常小， 从而能够显著减小黑矩阵的面积， 提高液晶显示器的开口率， 解决了 现有的液晶显示器的开口率较低的技术问题。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地丛说明书中变得显 而易见， 或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要 求书以及 ^图中所特别指出的结构来实现和获得。
附圏说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图 做简单的介绍：
图 1是本发明实施例一提供的阵列基板的示意图；
图 2是图 1中 »线和公共电极线部分的局部示意图；
图 3是现有的阵列基板的示意图；
图 4是图 3中«线和公共电极线部分的局部示意图；
图 5是本发明实施例二提供的阵列基板的示意图- 图 6是图 5中機线部分的局部示意图；
图 7是本发明实施例≡提供的阵列基板的示意图；
图 8是图 7中数据线部分的局部示意图；
图 9是图 3中数据线部分的局部示意图。 具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式,借此对本发明如何应用技术 手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是, 只要不构成冲突， 本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形 成的技术方案均在本发明的保护范围之内。
本发明实施例提供了一种阵列基板，包括阵列式排布的若干个子像素单元， 以及分割 出子像素单元的若千条信号线。相邻的两条信号线中，其中一条信号线位于与其对应的子 像素单元的第一方向侧，另一条信号线位于与其对应的子像素单元的第二方向侧，且第一 方向侧和第二方向侧分别为子像素单元的相对两侧。
本发明实施例提供的阵列基板中，一条信号线位于与其对应的子像素单元的第一方向 侧，与该信号线相邻的另一条信号线位于与其对应的子像素单元的第二方向侧，且第一方 向侧和第二方向侧分别为子像素单元的相对两侧，从而使相邻的两条信号线靠近设置， 即 该相邻的两条信号线位亍与其对应的两行（列）子像素单元之间。 为了防止漏光， 彩膜基 板上的黑矩阵的边缘会有一部分超出信号线的边缘， 如果该超出的部分的宽度为 S, 这两 条信号线的宽度均为 A, 这两条信号线的间距为 L， 则覆盖这两条信号线的黑矩阵的宽度 为 2Α+28+Ι^ 现有技术中， 各条信号线单独设置， 覆盖每条信号线的黑矩阵的宽度均为 A+2S， 则 覆盖两条信号线的黑矩阵的总宽度为 2A+4S。 因此， 与现有技术相比， 本发明实施例提 供的技术方案中， 覆盖每两条信号线的黑矩阵的宽度减少了 2S- L， 而相邻两条信号线的 间距 L可以设置得非常小， 从而能够显著减小黑矩阵的面积， 提高液晶显示器的开口率， 解决了现有的液晶显示器的开口率较低的技术问题。 实施例一； 本发明实施例提供的阵列基板包括阵列式排布的若干个子像素单元，以及若干条信号 线。 本实施例中的信号线为与每行子像素单元 1对应的栅线 2， 如图 1所示。 相邻的两条 栅线 2中， 例如 G(ii)和 G(n+1), 其中 G(n)位于与其对应的子像素单元 1的下侧 （第一方 向侧） ， G(ii十 1)位于与其对应的子像素单元 1的上侧（第二方向侧， 且第一方向侧和第二 方向侧分别为子像素单元的相对两侧） 。 又如， 相邻的 G(n+2)和 G(irB)中， G(n+2)位于 与其对应的子像素単元 1的下侧， G(n+3)位于与其对应的子像素单元 1的上侧。 此外， 还可以将 G(n+!)和 G(n+2)视为相邻的两条栅线， 则相当于 G(n+2) 位于与其 对应的子像素单元 1的下侧（第一方向侧）， G(n+1)位于与其对应的子像素单元 1的上侧 (第二方向侧， 第一方 1 侧和第二方向侧分别为子像素单元的相对两侧） 。 本发明实施例提供的阵列基板中，进一步还包括对应于每行子像素单元 1的公共电极 线 3， 用于为每个子像素单元 1对应的公共电极 （图中未示出）提供电压。 栅线 2与公共 电极线 3可以同层设置， 从而使 »线 2与公共电极线 3可以在一次构图工艺中同时形成。 作为一个优选方案， 与同一行子像素单元 1对应的栅线 2和公共电极线 3， 均位于该 行子像素单元 1的同侧，使该機线 2和该公共电极线 3可以共同由一条黑矩阵覆盖， 以减 少黑矩阵的条数。 例如图 1中， G(n)和 COM(n)均位于与其对应的子像素单元 1的下侧， 又如 G(n+!)和 COM(trH)均位亍与其对应的子像素单元 1 的上侧， 这样就可以使 G(n)、 COM(n), COM(n+l)、 G(n+1)都由同一条黑矩阵覆盖。 本实施例中， 与同一行子像素单元 1对应的栅线 2和公共电极线 3中， 公共电极线 3 位于搠线 2与该行子像素单元 1之间， 使公共电极线 3比栅线 2更靠近子像素单元 1 , 以 方便公共电极线 3为公共电极提供电压。 例如图 1中， COM(n)比 G(n)更靠近其所对应的 子像素单元 1 , 又如 COM(n+l)比 G(n+1)更靠近其所对应的子像素单元 1。
本发明实施例提供的阵列基板中， G(n)位于与其对应的子像素单元 1的下侧，与 G(n) 相邻的 G(n+1)位于与其对应的子像素单元 1的上侧， 从而使相邻的 G(n)和 G(n+1)靠近设 置， 即 G(ii)和 G(irfl)位于与其对应的两行子像素单元 1之间， 并 与这两行子像素单元 1对应的公共电极线 COM(n)和 COM(n+l), 也位亍这两行子像素单元 1之间。
如图 2所示， 为了防止漏光， 彩膜基板上的黑矩阵 5 的边缘会有一部分超出極线 2 的边缘， 如果该超出的部分的宽度为 S， 栅线 2、 公共电极线 3及其间距的总宽度为 A' , G(n)和 G(ii+1)的间距为 L, 则覆盖 G(n)、 COM(n), COM(n+l)、 G(n+1)的黑矩阵 5的宽度 为 2A' +2S+L。
如图 3和图 4所示， 现有技术中， 各条極线 2、 各条公共电极线 3单独设置， 覆盖 G(n)和 C()M(n)的黑矩阵 5的宽度为 A， +2S, 覆盖 G(n+1)和 COM(n+l)的黑短阵 5的宽 度也为 +2S, 则覆盖 G(n)、 COM(n), COM(n+l)、 G(n+1)的黑矩阵 5 的总宽度为 2A' +4S。 因此， 与现有技术相比， 本发明实施例提供的技术方案中， 覆盖每两条栅线 2 和两条公共电极线 3的黑矩阵 5的总宽度减少了 2S- L, 而相邻两条栅线 2的间距 L可以 设置得非常小， L越小， 黑矩阵 5的宽度就越小， 从而能够显著减小黑矩阵 5的面积， 提 高液晶显示器的开口率， 解决了现有的液晶显示器的开口率较低的技术问题。
在其他实施方式中，与同一行子像素单元对应的栅线和公共电极线中，也可以将極线 设置于公共电极线与该行子像素单元之间。并且，还可以进一步将两条靠近的公共电极线 合并为一条公共电极线，从而进一步减小黑矩阵的宽度。该条公共电极线对应两行子像素 单元， 该条公共电极线为两行子像素单元的公共电极提供电压。 实施例二；
本实施例与实施例一基本相同， 阵列基板中包括阵列式排布的若干个子像素单元 1 , 以及若干条栅线。 如图 5所示。 相邻的两条機线 2中， 例如 G(ti)和 G(n+1)， 其中 G(n)位 于与其对应的子像素单元 1的下侧， G(n+1)位于与其对应的子像素单元 1的上侧。 又如， 相邻的 G(n+2)和 G(tr 3)中， G(tr 2)位于与其对应的子像素单元 1的 侧， G(n+3)位于与 其对应的子像素单元 1的上侧。
本实施例与实施例一之间的不同点在于，如图 5所示，子像素单元 1中包括存储电容 6和像素电极（图中未示出） ， 存储电容 6的一端与機线 2相连， 存储电容 6的另一端与 像素电极相连。具体的， 可以使像素电极与栅线 2之间具有重叠部分， 该重叠部分形成存 储电容 6, 从而省去了公共电极线。
如图 6所示， 本实施例中， 黑矩阵 5的边缘超出栅线 2边缘的部分的宽度为 S, 栅线 2 的宽度为 A， G(n)和 G(trH)的间距为 L, 则覆盖 G(n)和 G(n+1)的黑矩阵 5 的宽度为 2A+2S+L。 相比于实施例一中宽度为 2A' +2S+L的黑矩阵， 本实施例中 »线的宽度 A只 是实施例一中 A' 的一部分，因此本实施例提供的技术方案能够进一步减小黑矩阵 5的宽 度, 使液晶显示器具有更高的开口率。
实施例三：
本发明实施例提供的阵列基板包括阵列式排布的若干个子像素单元 1 , 以及若干条信 号线。 本实施例中的信号线为与每列子像素单元 1对应的数据线 4， 如图 7所示。 相邻的 两条数据线 4 ,例如 D(n)和 D(n+!)，其中 D(n)位于与其对应的子像素单元 1的右侧（第 一方向侧） ， D(trH)位于与其对应的子像素单元 1的左侧（第二方向侧， 且第一方向侧和 第二方向侧分别为子像素单元的相对两侧） 。 又如， 相邻的 D(n+2)和 D(n+3)中， D(n+2) 位于与其对应的子像素单元 1的右侧， D(n+3)位于与其对应的子像素单元 1的左侧。 此夕卜，还可以将 G(n+1)和 G(n+2)视为相邻的两条数据线 4， 则相当于 G(n+2) 位于与 其对应的子像素单元 1的右侧（第一方向侧） ， G(n+1)位于与其对应的子像素单元 1的左 侧 （第二方向侧， 且第一方向侧和第二方向侧分别为子像素单元的相对两侧） 。
本发明实施例提供的阵列基板中， D(n)位于与其对应的子像素单元 I的右侧，与 D(n) 相邻的 D(n+1)位于与其对应的子像素单元 1的左侧， 从而使相邻的 D(n)和 D(n+1)靠近设 置， 即 D(n)和 D(n+1)位于与其对应的两行子像素单元 1之间。 如图 8所示， 为了防止漏光， 彩膜基板上的黑矩阵 5的边缘会有一部分超出数据线 4 的边缘，如果该超出的部分的宽度为 S，数据线 4的宽度为 Β， Ι)(τι和 D i+ )的间距为 L, 则覆盖 D(n)和 D(n+1)的黑矩阵的宽度为 2B+2S+L,,
如图 3和图 9所示， 现有技术中， 各条数据线 4单独设置， 覆盖 D(n)的黑矩阵 5的 宽度为 B 2S， 覆盖 D(ii+I)的黑矩阵 5的宽度也为 B+2S, 则覆盖 :D(n)和 Ι)(τι+1)的黑矩阵 5的总宽度为 2B+4S。 因此， 与现有技术相比， 本发明实施例提供的技术方案中， 覆盖每 两条数据线 4的黑矩阵 5的宽度减少了 2S- L, 而相邻两条数据线 4的间距 L可以设置得 非常小， L越小， 黑矩阵 5的宽度就越小， 从而能够显著减小黑矩阵 5的面积， 提高液晶 显示器的开口率， 解决了现有的液晶显示器的幵口率较低的技术 题。 应当说明的是， 在具体实施中， 也可以将实施例一、 实施例二与实施例三相结合。 也 就是，将阵列基板上的栅线设置为，相邻的两条極线位于与其对应的两行子像素单元之间； 同时，阵列基板上的数据线也设置为，相邻的两条数据线位于与其对应的两行子像素单元 之间， 使与栅线、数据线位置对应的黑矩阵的宽度都能够得以减小， 从而更大程度的提高 液晶显示器的开口率。 实施例四； 本发明实施例提供一种显示装置， 具体可以为液晶电视、 液晶显示器、 手机、 平板电 脑等显示装置。该显示装置包括彩膜基板和上述实施例一、实施例二或实施例三中提供的 阵列基板。彩膜基板上设置有彩膜层和黑矩阵，彩膜层的位置对应于阵列基板上的子像素 单元， 黑矩阵的位置对应于阵列基板上的子像素单元以外的栅线、 数据线、 公共电极线、 薄膜晶体管、 板边走线等区域。 本发明实施例提供的显示装置与上述实施例一、实施例二、实施例三提供的阵列基板 具有相同的技术特征， 所以也能解决相同的技术问题， 达到相同的技术效果。 虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的 实施方式， 并非用以限定本发明。任何本发明所属技术领域内的技术人员， 在不脱离本发 明所公幵的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但 本发明的专利保护范围， 仍须以所附的权利要求书所界定的范围为准。

Claims

棚要求书
一种阵列基板， 包括阵列式排布的若干个子像素单元， 以及若千条信号线； 相邻的两条信号线中，其中一条信号线位于与其对应的子像素单元的第一方向侧，另 一条信号线位于与其对应的子像素单元的第二方向侧；
所述第一方向侧和所述第二方向侧分别为子像素单元的相对两侧。
2、 如权利要求 1所述的阵列基板， 其中， 所述信号线为与每行所述子像素单元对应 的栅线。
3、 如权利要求 2所述的阵列基板， 其中， 还包括对应于每行所述子像素单元的若干 条公共电极线。
4、 如权利要求 3所述的阵列基板， 其中， 与同一行子像素单元对应的栅线和公共电 极线， 均位于该行子像素单元的同侧。
5、 如权利要求 4所述的阵列基板， 其中， 与同一行子像素单元对应的栅线和公共电 极线中， 公共电极线位亍栅线与该行子像素单元之间。
6、 如权利要求 4所述的阵列基板， 其中， 与同一行子像素单元对应的概线和公共电 极线中， 機线位于公共电极线与该行子像素单元之间。
7、 如权利要求 3所述的阵列基板， 其中， 所述概线与所述公共电极线同层设置。
8、 如权利要求 2所述的阵列基板， 其中， 所述子像素单元中包括存储电容和像素电 极：
所述存储电容的一端与 «线相连， 所述存储电容的另一端与所述像素电极相连。
9、 如权利要求 1所述的阵列基板， 其中， 所述信号线为与每列所述子像素单元对应 的数据线。
10、 一种显示装置， 其中， 包括彩膜基板和阵列基板； 所述阵列基板包括阵列式排布的若干个子像素单元， 以及若干条信号线；相邻的两条 信号线中，其中一条信号线位于与其对应的子像素单元的第一方向侧，另一条信号线位于 与其对应的子像素单元的第二方向侧;所述第一方向侧和所述第二方向侧分别为子像素单 元的相对两侧；
所述彩膜基板上设置有彩膜层和黑矩阵,所述彩膜层的位置对应于所述阵列基板上的 子像素单元， 所述黑矩阵的位置对应于所述阵列基板上的子像素单元以外的区域。
PCT/CN2014/081699 2014-06-11 2014-07-04 阵列基板及显示装置 Ceased WO2015188420A1 (zh)

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