Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
  • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
  • H05B45/30—Driver circuits
  • H05B45/395—Linear regulators
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/01—Details
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
  • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
  • H05B45/10—Controlling the intensity of the light
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
  • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
  • H05B45/30—Driver circuits
  • H05B45/37—Converter circuits
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
  • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
  • H05B45/30—Driver circuits
  • H05B45/395—Linear regulators
  • H05B45/397—Current mirror circuits
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
  • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
  • H05B45/50—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
  • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
  • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Definitions

• a flash LED driver typically includes an output stage and a current regulator that regulates the output current of the output stage.
• the current regulator may include an error amplifier that is connected to the output stage in a feedback loop.
• Headroom voltage refers to the voltage drop between the driver's voltage supply and the output voltage of the driver.
• the feedback loop tends to drive the output stage into the linear region, thus reducing the system loop gain.
• the output stage is driven into the saturation region with much larger gain (e.g., 50-60 dB or higher), which reduces phase margin and thus system stability.
• a given PMIC can be exposed to a wide range of headroom voltage conditions and load conditions and so its design is not likely to be adequate for all use cases.
• a circuit may include a driver stage for driving an external load.
• the driver stage may be connected in a control loop configuration with a control circuit.
• a headroom sensor may provide a headroom signal to control a response characteristic of the control loop.
• a load sensor may provide a load signal to further control the response characteristic of the control loop.
• the gain of the response characteristic may be varied according to the headroom signal.
• a bandwidth of the response characteristic may be varied according to the headroom signal.
• the headroom signal may vary the dominant pole location of the response characteristic.
• an internal zero of the response characteristic may be set by the load signal.
• Fig. 1 shows an example of a high level block diagram of a circuit in accordance with the present disclosure.
• Figs. 2, 2A, and 2B illustrate frequency response curves.
• Fig. 3 shows an illustrative embodiment in accordance with the present disclosure.
• Fig. 3A shows some details for a load sensor.
• FIG. 4 shows some details for an illustrative embodiment of OP amp 304.
• Fig. 4A shows an alternative embodiment of Fig. 4.
• Figs. 5A - 5D illustrate frequency response curves that characterize aspects of the present disclosure.
• Figs. 6A - 6D illustrate frequency response curves that characterize further aspects of the present disclosure.
• Fig. 1 shows a circuit 100 in accordance with the present disclosure.
• the circuit 100 may comprise a driver stage 112 having a drive output 112a that can be connected to drive a load 10.
• the load 10 may be any kind of a load.
• the load 10 may be an LED flash component of a camera; e.g., a digital camera or a camera in a portable computing device such as a computer tablet, a smartphone, and so on.
• a control circuit 114 may provide a control signal 114a that can be used to control operation of the driver stage 112.
• the control circuit 114 may be configured with the driver stage 112 as a feedback control loop 110, with the driver output 112a feeding back to an input (e.g., 1 st input) of the control circuit.
• a response characteristic of the control loop 110 may be set or otherwise altered in accordance with a signal indicative of the headroom voltage of the circuit 100 during operation when the circuit is driving the load 10.
• Headroom voltage refers to the voltage drop between the driver's voltage supply (e.g., VIN) and the output voltage (e.g., VOUT) of the driver 112; e.g., VIN - VOUT-
• circuit 100 may include a headroom sensing circuit 116 that senses a headroom of the circuit.
• the headroom sensing circuit 116 may produce a headroom signal that is indicative of or otherwise representative of the headroom voltage of circuit 100.
• the headroom signal can be provided to another input (e.g., 2 nd input) of the control circuit 114 to affect the response characteristic of the control loop 110. This aspect of the present disclosure will be discussed in more detail below.
• the response characteristic of the control loop 110 may be further set or otherwise altered in accordance with a signal indicative of electrical loading on the circuit 100 due to load 10 during operation; e.g., electrical loading may be represented by the current flowing through the load.
• circuit 100 may include a load sensing circuit 118 that can generate a load signal indicative of or otherwise representative of the electrical loading on the circuit.
• the load signal can be provided to another input (e.g., 3 rd input) of the control circuit 114 to affect the response characteristic of the control loop 110. This aspect of the present disclosure will be discussed in more detail below.
• the response characteristic of the control loop 110 may be represented by a frequency response curve 200 (e.g., a Bode plot).
• the response characteristic of the control loop 110 may be characterized by a gain (sometimes referred to as the closed loop gain) that varies with frequency, as illustrated in the frequency response curve 200.
• the response characteristic of the control loop 110 may be further characterized by a bandwidth (fbandwidth), which is conventionally defined as the frequency at which the closed loop gain falls by -3 dB.
• the plot shown in Fig. 2 is a straight-line plot of the actual response characteristic, which is continuous and has a 3 dB drop-off at the pole position PD.
• the frequency response curve 200 shown in Fig. 2 represents poles PD, PL of the response characteristic of the control loop 110. It will be appreciated, that in general, the response characteristic of control loop 110 may include any number and combination of poles and zeroes.
• the response characteristic of control loop 110 may be expressed as a transfer function represented by the following Laplace transform:
• G is the closed loop gain
• s is the complex frequency ja>
• the disclosed embodiments describe the behavior of the response characteristic at poles PD and PL, and at a zero relating to pole Pi_.
• embodiments in accordance with the present disclosure need not be restricted to the poles and zeroes specifically disclosed in the present disclosure, and that other embodiments may involve other poles and/or zeroes of the response characteristic of the control loop 110.
• the lowest frequency pole PD is sometimes referred to as the "dominant pole" because it dominates the effect of any higher frequency poles.
• the dominant pole typically defines the bandwidth of the response characteristic of the control loop 110.
• the load 10 that is driven by the driver stage 112 can affect the response characteristic of the control loop 110.
• the load 10 introduces an external pole PL to the frequency response curve of the control loop 110.
• the location or position of external pole PL depends on the size of the load 10 (e.g., expressed as an impedance Z). This effect is illustrated in Figs. 2, 2A, and 2B for different sized loads.
• Figs. 2, 2A, and 2B further illustrate that as the size of the load 10 increases (e.g., increasing impedance Z), the external pole PL moves closer to the dominant pole PD.
• each non-dominant pole closer than a decade away from the unity gain bandwidth of the feedback loop will reduce phase margin, which can ultimately degrade the control loop stability.
• the effect of the external pole on stable operation of the control loop 110 can be small; e.g., the location of external pole PL in Fig. 2 may be sufficiently far away from dominant pole PD SO that the control loop 110 will be stable.
• the external pole Pi_ b may be close enough to the dominant pole PD that the phase margin is so small that unstable operation can result.
• the load may be an LED flash unit 30, such as might be found in digital cameras, portable computing devices, smart phones, etc.
• the driver stage 112 may comprise a transistor P 2 , such as a power
• the transistor P 2 may provide a drive current from the supply voltage Vi N to the LED flash unit 30.
• the control circuit 114 may comprise an OP amp 304 and a constant current source IREF-
• the control circuit 114 may further include a current mirror, comprising a transistor Pi and the driver stage transistor P2, that is driven by the output VDRVR of OP amp 304.
• the driver stage 112 and control circuit 114 may constitute the control loop 110.
• the OP amp 304 in control circuit 114 may control the driver stage transistor P 2 in a feedback loop by regulating the drive current (provided as feedback voltage VFB) based on a reference provided by the constant current source IREF (provided as VREF).
• the constant current source IREF may be a small current source (e.g., 10 ⁇ ).
• the device dimensions of Pi and P 2 in the current mirror may be designed to provide a suitable P1/P2 current ratio in order to provide a suitable drive current to operate the LED flash unit 30.
• the P1/P2 current ratio may be 1: 10,000, giving a current gain of 10,000 at P 2 . It will be appreciated of course that in other embodiments, Pi and P2 can be designed to provide any suitable current gain.
• the headroom sensing circuit 116 may generate a headroom signal indicative of or otherwise representative of the headroom voltage of the circuit 100.
• the headroom sensing circuit 116 may comprise a comparator 302 to compare the driver stage output voltage VOUT provided to the load (e.g., LED flash unit 30) against the supply voltage (e.g., VIN).
• the headroom signal HDRM_out produced by the headroom sensing circuit 116 is thus representative of the headroom voltage of the circuit 100 and may feed into the control circuit 114.
• HDRM out feeds into a control input IN1 of the OP amp 304 of control circuit 114.
• resistor divider networks may be used to reduce the voltage levels that feed into comparator 302.
• the output voltage VOUT on the load 30 may be divided down by the resistor divider comprising R 4 and R 5 .
• the supply voltage VIN can be divided down in similar fashion as described below.
• the headroom sensing circuit 116 may include a programmable current source IBIAS-
• the inset in Fig. 3 defines the constant K, which in a particular embodiment also sets forth a relationship among the resistance values of resistors Ri - R 5 .
• the load that is being driven by the driver stage 112 can change, depending what the load is, how it is being used, etc. ; for example, an LED flash device 30 can operate in different modes; e.g., flash, strobe, etc.
• the size of the load can affect the response characteristic of the control loop 110.
• the load sensing circuit 118 may produce a signal Ld_sns_out that represents the drive current from the driver stage 112 that can feed into the control circuit 114.
• the Ld_sns_out signal feeds into a control input IN 2 of the OP amp 304 of control circuit 114.
• the load sensing circuit 118 may comprise a current sensor.
• load sensing circuit 118' may comprise a mirrored sense transistor Psense that mirrors the current flow through the driver stage transistor P 2 .
• a comparator 306 may compare the current flow through Psense against a reference and output a signal Ld_sns_out that represents the level of the drive current flowing into the load 30.
• the load sensing circuit 118 may be load current programming circuit (not shown) that programs the load current, and the Ld_sns_out signal may be based on a parameter (e.g., stored in a programming register) used to program the load current.
• the response characteristic of the control loop 110 can be set based on the headroom signal HDRM_out, or the load signal Ld_sns_out, or both.
• the HDRM out signal may be used to set the gain of the response characteristic, or the bandwidth of the response characteristic, or both.
• the Ld_sns_out signal may be used to set the position of a zero of the response characteristic. As will be discussed below, this can improve stability in the control loop 110 as changes in the headroom voltage and loading conditions (e.g., current load) occur during operation of circuit 100.
• OP amp 304 illustrates how the HDRM_out and Ld_sns_out signals may be used to set the response characteristic of control loop 110.
• the response characteristic of the control loop 110 may be set by setting circuit elements in the OP amp 304.
• the OP amp 304 may comprise an opamp device 404 having an inverting input and a non-inverting input.
• the reference voltage VREF may be connected to the non-inverting input through resistor RB.
• the feedback voltage VFB may be connected to the inverting input through resistor RA.
• the opamp device 404 may include a gain control input G that varies the gain of the opamp device.
• the HDRM out signal may be coupled directly to or otherwise connected to the gain control input G, thereby allowing the HDRM_out signal to control the gain of the opamp device 404.
• circuit element Zi may represent a wire for a direct connection of the HDRM_out signal to the gain control input G, or Zi may represent some intervening electronic circuitry that can provide gain control as some function of the HDRM_out signal.
• circuit element Z 2 may represent a wire or some appropriate intervening electronic circuitry.
• the OP amp 304 may include a compensation network 402 of any suitable design.
• the response characteristic (e.g., transfer function H(s)) of the control loop 110 may be expressed in terms of the circuit elements comprising the compensation network.
• the compensation network 402 may comprise one or more circuit elements that can be adjusted or otherwise varied using the HDRM out signal and/or the Ld_sns_out signal in order to vary the response characteristic of control loop 110.
• the compensation network 402 may comprise a resistor element Rc connected in series with a capacitor element Cci , and a shunt capacitor Cc2 connected in parallel with the Rc/Cci pair.
• the resistor element Rc may provide a selectable resistance. Setting the resistance value of resistor Rc can set the position of a zero in the response characteristic of control loop 110.
• the capacitor Cc2 may provide a selectable capacitance. Setting the capacitance value of capacitor Cc2 can set the position of the dominant pole in the response characteristic of control loop 110.
• the H DRM out signal may be coupled directly to or otherwise connected to a selector input of the variable capacitor Cc2-
• circuit element Zi may represent a wire or some appropriate intervening electronic circuitry and likewise, circuit element Z 3 may represent a wire or some intervening electronic circuitry. Accordingly, the H DRM_out signal may be used to set the dominant pole position of the response characteristic of control loop 110.
• Ld_sns_out signal may be coupled directly or otherwise connected to a selector input of the variable resistor Rc.
• Circuit element Z4 may represent a wire for a direct connection of the Ld_sns_out signal to the selector input of the variable resistor Rc, or Z 4 may represent some intervening electronic circuitry that can set resistor Rc as some function of the Ld_sns_out signal. Accordingly, the Ld_sns_out signal may be used to set a zero position of the response characteristic of control loop 110.
• circuit elements Zi - Z4 are wires representing straight through connections, such as illustrated for example in Fig. 4A.
• frequency response curves 502 - 508 can be used to illustrate the effects on the response characteristic of control loop 110 when the headroom signal H DRM_out is applied in accordance with the present disclosure.
• control loop 110 having a gain G1 and bandwidth fb as determined by the dominant pole PD.
• Fig. 5A illustrates that the headroom signal H DRM_out can vary the gain and/or the dominant pole position (and hence the bandwidth) of the response characteristic.
• Fig. 5B shows how the frequency response curve 504 changes if just the gain is varied, for example, if the gain is reduced to G2 ⁇ Gi .
• the H D RM_out signal can be used to reduce the gain in order to improve stability in the control loop 110.
• the H DRM_out signal can control the gain of the opamp device 404 to vary the gain of the frequency response curve. Reducing the gain brings the unity gain bandwidth of the control loop 110 back from frequency fi to frequency f 2 . This improves stability if non- dominant poles exist within a decade or closer to f i .
• Fig. 5C shows how the frequency response curve 506 changes if just the dominant pole is varied, for example, from f b to f b ' ⁇ f b - Since the dominant pole determines the bandwidth, varying the dominant pole (e.g., P D to P D ') has the effect of varying the bandwidth of the response characteristic.
• the H DRM_out signal when the headroom voltage exceeds the threshold voltage, can be used to reduce the bandwidth in order to improve stability in the control loop 110.
• the HDRM_out signal can be used to increase the bandwidth to improve the response time of the control loop 110.
• the H DRM_out signal can control the value of the variable capacitor Cc2 to vary the dominant pole position of the frequency response curve.
• the HDRM out signal may control both the gain and the dominant pole position (i.e., bandwidth) of the response characteristic of control loop 110.
• the frequency response curve 508 shown in Fig. 5D illustrates an example in which the gain and bandwidth are reduced.
• the HDRM out signal when the headroom voltage exceeds the threshold voltage, the HDRM out signal can be used to reduce both the gain and the bandwidth of the response characteristic in order to improve stability in the control loop 110. Conversely, when the headroom voltage falls below the threshold voltage, the HDRM out signal can be used to increase the gain and bandwidth to improve the response time of the control loop 110.
• the gain and bandwidth may change together, as HDRM out changes.
• the gain and bandwidth may be varied independently of each other.
• circuit elements Zi - Z 3 (Fig. 4) may be suitable control circuitry to isolate the H DRM out signal from the gain control input and capacitor Cc 2 for independent operation.
• frequency response curves 602, 604 can be used to illustrate the effects on the response characteristic of control loop 110 when the load signal Ld_sns_out is applied in accordance with the present disclosure.
• the load 10 e.g. LED flash unit 30, Fig. 3 introduces an external pole that can affect the response characteristic of the control loop 110.
• the response characteristic of the control loop 110 without a load is represented by the frequency response curve 602.
• an external pole PL due to the load may be introduced, which may result in frequency response curve 604.
• the additional drop off occurring a frequency fi_ reduces stability of the control loop 110 due to a decrease in phase margin.
• the Ld_sns_out signal may be used to set a zero position of an internal zero in the control loop 110 to compensate for the external pole PL.
• the Ld_sns_out signal can control the value of variable resistor Rc to vary an internal zero of the response characteristic. This effect is illustrated in Fig. 6B, where the Ld_sns_out signal can set the zero position of an internal zero ZL to cancel the effect of the external pole PL and eliminate the drop off at frequency fL to improve stability.
• the load changes, so will the pole position of the external pole, as illustrated in Fig. 6C.
• the load may be such as to introduce external pole P a to the response characteristic; in another situation, the load may be such as to introduce a different external pole, e.g., P b , to the response characteristic, and so on.
• the response characteristic of the control loop 110 changes.
• the stability of the control loop 110 can therefore vary according to the load, as illustrated by the frequency response curves, 612a, 612, b, 612c, 612d.
• designing a control circuit 114 (Fig. 1) to maintain stability under any load condition can be challenging, since the designer has no control over what load the circuit 100 will be connected to or how the load may change during operation.
• the load sensor 118 can produce a Ld_sns_out signal that is representative of or otherwise tracks the load.
• Ld_sns_out signal can be used to adjust an internal zero of the control loop 110 (e.g., via variable resistor Rc) to compensate for varying external poles resulting from varying loads, and thus improve stability in the control loop 110 as represented by the frequency response curve 612.
• This effect is illustrated in Fig. 6D, which illustrates that the internal zero can vary to track the external pole as the load varies.
• circuits in accordance with the present disclosure allow for automatic adjustment of the loop gain and/or dominant pole position of the control loop based on voltage headroom during operation, when a load is being driven.
• circuits in accordance with the present disclosure allow for automatically varying the zero position of an internal zero of the control loop based on load condition of the load being driven by the circuit.

Landscapes

• Amplifiers (AREA)
• Dc-Dc Converters (AREA)
• Control Of Electric Motors In General (AREA)
• Steering Control In Accordance With Driving Conditions (AREA)
• Circuit Arrangement For Electric Light Sources In General (AREA)
• Continuous-Control Power Sources That Use Transistors (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

Family

ID=53298606

Family Applications (1)

Country Status (5)

Families Citing this family (5)

Citations (9)

Family Cites Families (14)

• 2014
  • 2014-06-02 US US14/293,489 patent/US9190986B1/en active Active
• 2015
  • 2015-05-18 EP EP23212750.6A patent/EP4326006A3/en active Pending
  • 2015-05-18 EP EP15727508.2A patent/EP3150028B1/en active Active
  • 2015-05-18 WO PCT/US2015/031381 patent/WO2015187351A1/en not_active Ceased
  • 2015-05-18 JP JP2016570035A patent/JP2017518573A/ja active Pending
  • 2015-05-18 CN CN201580028622.8A patent/CN106471739B/zh active Active
  • 2015-10-14 US US14/883,317 patent/US9635724B2/en active Active

Patent Citations (9)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events