WO2015180211A1 - 液晶显示面板驱动方法 - Google Patents

液晶显示面板驱动方法 Download PDF

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Publication number
WO2015180211A1
WO2015180211A1 PCT/CN2014/079713 CN2014079713W WO2015180211A1 WO 2015180211 A1 WO2015180211 A1 WO 2015180211A1 CN 2014079713 W CN2014079713 W CN 2014079713W WO 2015180211 A1 WO2015180211 A1 WO 2015180211A1
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Prior art keywords
polarity
gate
gate line
pixel
liquid crystal
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PCT/CN2014/079713
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English (en)
French (fr)
Inventor
杜鹏
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/375,430 priority Critical patent/US20150348483A1/en
Publication of WO2015180211A1 publication Critical patent/WO2015180211A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of liquid crystal display panels, and in particular, to a liquid crystal display panel driving method. Background technique
  • the TFT-LCD (Thin Film Transistor Liquid Crystal Display) has the characteristics of small size, low power consumption, and no radiation, and has occupied a dominant position in the current flat panel display market.
  • the TFT-LCD mainly includes an array substrate and a color filter substrate which are sandwiched together and sandwiched between the liquid crystals, and a gate line for providing a scan signal is formed on the array substrate (the data line of the Gate Line providing the data signal (the data line forms the pixel point)
  • the pixel electrode and the thin film transistor, each pixel electrode is controlled by a thin film transistor. When the thin film transistor is turned on, the pixel electrode is charged during the on time, and after the thin film transistor is turned off, the pixel electrode voltage is maintained until the next scan is recharged.
  • a black matrix and a colored resin are formed on the color filter substrate.
  • the typical polarity inversion mode is: Frame Inversion (Line Inversion ⁇ Line Inversion) ) and dot inversion (Dot Inversion ⁇ polarity in the polarity reversal, when the pixel voltage signal is higher than the common electrode signal, it is called positive polarity, When the pixel voltage signal is lower than the common electrode signal, it is called negative polarity.
  • HSD Half Source Driving
  • FIG. 1 is a schematic diagram of a circuit structure of an existing TFT-LCD panel using an HSD architecture and dot inversion.
  • the method includes: a plurality of data lines providing data signals (datal ⁇ Data5 and a plurality of gate lines for providing scanning signals ( Gatel-GateS and several pixels (P)) provided by crossing the data lines; each pixel (P) is connected with one data a line and a gate line, and the polarity of each pixel (P) is opposite to the polarity of the upper, lower, left, and right pixels adjacent thereto;
  • the pixel (P) includes a thin film transistor (Tr) and a pixel electrode (D); the thin film transistor (Tr) has a gate (g X source (s ⁇ drain (d); the pixel electrode (D) Electrically connected to the drain (d) of the thin film transistor (Tr); specifically, each pixel on the liquid crystal display panel can be equivalent to a parallel structure of a liquid crystal capacitor (C LC ) and a storage capacitor (C stg ), and a liquid crystal capacitor ( C LC ) One side electrode of the storage capacitor (C stg ) is connected to the pixel electrode ( D ), and the other side electrode is connected to the common electrode line (VC0M ).
  • the thin film transistor (Tr) can charge the pixel electrode (D) at different times.
  • the gate lines are sequentially turned on in the order of 1, 2, 3, ..., ⁇ , ⁇ +1, and the data lines are switched once in polarity when each of the two gate lines is turned on.
  • the liquid crystal display panel adopting the HSD architecture uses the traditional driving method, and the resolution of the HD is 60 Hz, the signal of the data line needs to be switched every two pixels (Pixel) when the liquid crystal display panel is working.
  • the polarity of the primary drive voltage that is, approximately every 21.7 ⁇ ⁇ , requires switching the polarity once.
  • the signal frequency is too high, which increases the power consumption on the data line; on the other hand, the charging time of the HSD architecture pixel is very short, and the resistor-capacitor delay effect (RC Delay) of the signal switching on the data line is further Affecting the charging condition of the pixel is not conducive to the improvement of the display quality, and this problem is more serious when the resolution of the liquid crystal display panel is improved.
  • RC Delay resistor-capacitor delay effect
  • An object of the present invention is to provide a liquid crystal display panel driving method, which can significantly reduce the frequency of signal positive and negative polarity switching on a data line, thereby reducing the frequency of the dot inversion mode.
  • the power consumption of the entire HSD architecture panel effectively improves the charging of the pixels and improves the display quality.
  • the present invention provides a liquid crystal display panel driving method, including: Step 100: providing a plurality of data lines for providing data signals, and a plurality of gate lines for providing scan signals disposed along the data lines (G Gate to Gatem) And a plurality of pixels (P), each pixel is connected to one data line and one gate line, and the polarity of each pixel is opposite to the polarity of the upper, lower, left and right pixels adjacent thereto;
  • Step 200 The gate lines of the pixels corresponding to the driving voltage of the first polarity are sequentially turned on in order, and the signal writing of the half frames is completed;
  • Step 300 The gate lines of the pixels corresponding to the driving voltage of the second polarity are sequentially turned on in sequence, and the signal writing of the other half of the frames is completed;
  • the first polarity is opposite to the polarity of the second polarity.
  • the signal of the data line switches the polarity of the driving voltage twice during one frame time, the first polarity being negative polarity and the second polarity being positive polarity.
  • the m is a multiple of 4.
  • the order in which the gate lines are turned on in the step 200 is from small to large according to the gate line number.
  • the order in which the gate lines are turned on in the step 300 is from small to large according to the gate line number.
  • the order in which the gate lines are turned on in the step 300 is from the largest to the smallest by the gate line number.
  • the m is 1536
  • the numbering sequence is sequentially turned on to complete the signal writing of one frame, and the corresponding data signal is in the first gate line to the 1536th gate line
  • the driving voltage of Gatel ⁇ Gatel536 is turned on for the first polarity, and the driving voltage is the second polarity during the period from the second gate line to the 1535th gate line (Gate2 ⁇ Gatel535).
  • the m is 1536, and the gate line is in accordance with 1 ⁇ 4 ⁇ 5 ⁇ . ⁇ 4n ⁇ 4n+l ⁇ . ⁇ 1533 ⁇ 1536 ⁇ 1535 ⁇ 1534 ⁇ ... 4n+3 ⁇
  • the number order of 4n+2 ⁇ ... ⁇ 3 ⁇ 2 is turned on sequentially, and the signal writing of one frame is completed, and the corresponding data signal is turned on from the first gate line to the 1536th gate line (Gatel ⁇ Gatel536).
  • the segment time driving voltage is the first polarity, and the driving voltage is the second polarity during the period from the gate line to the second gate line ( Gatel 535 ⁇ Gate 2 ) being turned on.
  • the pixel (P) includes a thin film transistor (Tr) and a pixel electrode (D); the thin film transistor (Tr) has a gate (g X source (s ⁇ drain (d); the pixel electrode (D) Electrically connected to the drain (d) of the thin film transistor (Tr); one of the gate (g) of the thin film transistor (Tr) and the second n+2 gate line disposed in the pixel (P) of the odd row of the same row a common connection; a gate (g) of a thin film transistor (Tr) and a second n+1 gate in a pixel (P) of an even-numbered column of the same row a common connection of the line; the source ( s ) of the thin film transistor ( Tr ) is commonly connected to a certain data line in the pixel ( P ) of the same column, and is arranged in the 2n+2th column and the 2nd+3th column The source (s) of the thin film transistor (Tr) in the pixel (P) is electrically
  • the liquid crystal display panel adopts an HSD architecture.
  • the invention also provides a liquid crystal display panel driving method, comprising:
  • Step 100 providing a plurality of data lines for providing data signals, and a plurality of gate lines (gates to gates and pixels (P) for providing scan signals, which are disposed across the data lines, and each of the pixels is connected with one data line and one gate a polar line, and the polarity of each pixel is opposite to the polarity of the upper, lower, left, and right pixels adjacent thereto;
  • gate lines gate lines to gates and pixels (P) for providing scan signals
  • Step 200 The gate lines of the pixels corresponding to the driving voltage of the first polarity are sequentially turned on in order, and the signal writing of the half frames is completed;
  • Step 300 The gate lines of the pixels corresponding to the driving voltage of the second polarity are sequentially turned on in sequence, and the signal writing of the other half of the frames is completed;
  • the first polarity is opposite to the polarity of the second polarity
  • the signal of the data line switches the polarity of the driving voltage twice, the first polarity is a negative polarity, and the second polarity is a positive polarity;
  • the m is a multiple of 4;
  • the numbering sequence is turned on sequentially, and the signal writing of one frame is completed, and the corresponding data signal is in the first gate line to the 1536th gate line (Gatel ⁇
  • the driving voltage of the gate is controlled to be the first polarity, and the driving voltage is the second polarity during the period from the second gate line to the gate line ( Gate2 ⁇ Gatel535) being turned on;
  • the pixel (P) includes a thin film transistor (Tr) and a pixel electrode (D); the thin film transistor (Tr) has a gate (g X source (s ⁇ drain (d); the pixel electrode (D) Electrically connected to the drain (d) of the thin film transistor (Tr); one of the gate (g) of the thin film transistor (Tr) and the second n+2 gate line disposed in the pixel (P) of the odd row of the same row a common connection; a gate (g) of a thin film transistor (Tr) is disposed in common with a certain one of the 2n+1th gate lines in a pixel (P) of an even-numbered column of the same row; and is disposed in a pixel (P) of the same column a source (s) of the thin film transistor (Tr) is commonly connected to a certain data line, and is disposed in a source (s) of the thin film transistor (Tr) in the pixel (P) of the 2n+2th column and the 2
  • the liquid crystal display panel adopts an HSD architecture.
  • the present invention provides a liquid crystal display panel driving method, which redesigns the driving mode of the HSD-structured liquid crystal display panel in the dot inversion mode, and passes the gate line of the pixel corresponding to the driving voltage as the first polarity.
  • the number is sequentially turned on in order from small to large, and the signal writing of half frame is completed;
  • the gate lines of the pixels corresponding to the driving voltage of the second polarity are sequentially turned on in order from small to large, or correspondingly driven
  • the gate lines of the pixels having the second polarity are sequentially turned on in order from the largest to the smallest, and the signal writing of the other half frames is completed.
  • the polarity of the first polarity is opposite to the polarity of the second polarity.
  • the signal of the data line only needs to switch the polarity of the driving voltage twice in one frame time, which significantly reduces the frequency of switching between the positive and negative polarity of the signal on the data line, thereby reducing the power consumption of the entire HSD architecture liquid crystal display panel, and effectively Improve pixel charging and improve display quality.
  • FIG. 1 is a schematic diagram of a circuit structure of a conventional TFT-LCD panel using an HSD architecture and a dot inversion
  • Figure 2 is a timing diagram of Figure 1 when the conventional driving mode is used
  • FIG. 3 is a schematic flow chart of a driving method of a liquid crystal display panel according to the present invention.
  • Figure 4 is a timing chart of the first embodiment of Figure 1 when the driving method of the present invention is employed;
  • Fig. 5 is a timing chart showing the second embodiment of Fig. 1 when the driving method of the present invention is employed. detailed description
  • the present invention provides a liquid crystal display panel driving method, including: Step 100: providing a plurality of data lines for providing data signals, and a plurality of gate lines for providing scan signals disposed across the data lines (Gatel ⁇ Gatem and several pixels (P), each pixel is connected with one data line and one gate line, and the polarity of each pixel is opposite to the polarity of the upper, lower, left and right pixels adjacent thereto;
  • Step 200 The gate lines of the pixels corresponding to the driving voltage of the first polarity are sequentially turned on in sequence. Complete half-frame signal writing;
  • Step 300 The gate lines of the pixels corresponding to the driving voltage of the second polarity are sequentially turned on in sequence, and the signal writing of the other half of the frames is completed;
  • the first polarity is opposite to the polarity of the second polarity.
  • the signal of the data line switches the polarity of the driving voltage twice during one frame time.
  • the m is a multiple of 4.
  • the pixel (P) includes a thin film transistor (Tr) and a pixel electrode (D); the thin film transistor (Tr) has a gate (g X source (s ⁇ drain (d); the pixel electrode (D) Electrically connected to the drain (d) of the thin film transistor (Tr); one of the gate (g) of the thin film transistor (Tr) and the second n+2 gate line disposed in the pixel (P) of the odd row of the same row a common connection; a gate (g) of a thin film transistor (Tr) is disposed in common with a certain one of the 2n+1th gate lines in a pixel (P) of an even-numbered column of the same row; and is disposed in a pixel (P) of the same column a source (s) of the thin film transistor (Tr) is commonly connected to a certain data line, and is disposed in a source (s) of the thin film transistor (Tr) in the pixel (P) of the 2n+2th column and the 2
  • the liquid crystal display panel adopts an HSD architecture.
  • FIG. 4 is the first embodiment of FIG. Timing diagram of an embodiment.
  • m 1536
  • -X second polarity positive polarity (+)
  • the second data line (Data 2 ) in FIG. 1 liquid crystal display panel resolution
  • the resolution is 1366x768, the operating frequency is 60Hz.
  • the numbering sequence is turned on sequentially, and the signal writing of one frame is completed, and the data signal corresponding to the second data line (Data 2 ) is in the first gate line to the first S36 gate line (Gatel ⁇ Gatel536).
  • the driving voltage is negative (-), and the driving voltage is positive (+) during the period from the second gate line to the 1535th gate line (Gate2 ⁇ Gatel535).
  • the polarity needs to be switched twice.
  • the second data line (Data2) switches the signal polarity every 8.33ms, and the corresponding signal 'frequency is 46.08 when using the traditional driving method (see Figure 2).
  • kHz P is pulled down to 120Hz, that is, the corresponding signal 'frequency drop' is 1/384 when using the traditional drive mode.
  • the frequency of positive and negative polarity switching of the signal on the data line is significantly reduced, thereby reducing the power consumption of the entire HSD architecture panel, and on the other hand, the effect of the delay effect of the data line resistance and capacitance on the pixel charging can be alleviated. Helps improve the quality of the display.
  • FIG. 3 and FIG. 5 are timing diagrams of the second embodiment of FIG. 1 when the driving method of the present invention is employed.
  • m is 1536
  • the first polarity is negative
  • -X second polarity is The positive polarity (+) is taken as an example.
  • the second data line (Data2) in FIG. 1 (the resolution of the liquid crystal display panel is HD, the resolution is 1366 ⁇ 768, and the operating frequency is 60 Hz) is taken as an example.
  • the number sequence of ... ⁇ 3 ⁇ 2 is turned on in turn, and the signal writing of one frame is completed.
  • the data signal corresponding to the second data line (Data2) is driven to a negative polarity (-) during the period from the first gate line to the 1536th gate line (Gatel ⁇ Gatel536), and is at the 1535th gate line.
  • the second gate line (Gatel535 ⁇ Gate2) is turned on, the driving voltage is positive (+), and it is only necessary to switch the polarity twice in one frame time.
  • the gate lines are turned on in the same number order, that is, the first gate line.
  • the 1536th gate line 'the second gate line to the 1535th gate line (Gatel ⁇ Gate 1536, Gate2 ⁇ Gate 1535), that is, the order of the gate lines in the step 200 is turned on by the gate line number.
  • the order of the gate lines in the step 300 is from small to large according to the gate line number; and in the second embodiment, the first 1/2 and the last 1/2 of each frame.
  • the numbering sequence of the gate lines is reversed, that is, the first gate line to the 1536th gate line 'the 1535th gate line to the second gate ⁇ Gatel ⁇ Gate 1536, Gatel535 ⁇ Gate 2)
  • the order in which the gate lines are turned on in step 200 is from small to large according to the gate line number, and the order in which the gate lines in the step 300 are turned on is from the gate line number to the large small.
  • both the first embodiment and the second embodiment of the present invention can achieve the purpose of reducing the power consumption of the liquid crystal display panel.
  • the present invention provides a liquid crystal display panel driving method, which redesigns the driving mode of the HSD-structured liquid crystal display panel in the dot inversion mode, and presses the gate line of the pixel corresponding to the driving voltage to the first polarity.
  • the gate line numbers are sequentially turned on in the order of small to large, and the signal writing of the half frame is completed; the gate lines of the pixels corresponding to the driving voltage of the second polarity are sequentially guided in the order of the gate line numbers from small to large.
  • the gate lines of the pixels corresponding to the driving voltage of the second polarity are sequentially turned on in descending order of the gate line numbers, and the signal writing of the other half frames is completed, the first polarity and the second polarity.
  • the opposite polarity of the polarity makes the signal of the data line only need to switch the polarity of the driving voltage twice in one frame time, which significantly reduces the frequency of positive and negative polarity switching of the signal on the data line, thereby reducing the entire HSD architecture.
  • the power consumption of the liquid crystal display panel effectively improves the charging of the pixels and improves the quality of the display.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种液晶显示面板驱动方法，包括：提供数个数据线、数个栅极线（Gate1~Gatem）及数个像素（P）；每一个像素（P）连接一条数据线与一条栅极线，且每一个像素单元的极性与该像素单元相邻的上下左右的像素单元的极性都是相反的；对应驱动电压为第一极性的像素（P）的栅极线按顺序依次导通，完成半个帧的信号写入；对应驱动电压为第二极性的像素（P）的栅极线按顺序依次导通，完成另外半个帧的信号写入，所述第一极性与第二极性的极性相反，栅极线的条数m为4的倍数。通过该液晶显示面板驱动方法，数据线的信号在一个帧的时间内只需切换两次驱动电压的极性，降低了整个面板的功耗，改善了像素（P）的充电情况，提高显示品质。

Description

液晶显示面板驱动方法 技术领域
本发明涉及液晶显示面板领域，尤其涉及一种液晶显示面板驱动方法。 背景技术
TFT-LCD ( Thin Film transistor liquid crystal display ,薄膜晶体管液晶显 示器 )具有体积小、 低功耗、 无辐射等特点，在当前平板显示器巿场中占 据了主导地位。 TFT-LCD主要包括对盒在一起并将液晶夹设其间的阵列基 板和彩膜基板，阵列基板上形成有提供扫描信号的栅极线（ Gate Line 提 供数据信号的数据线 ( Data Line 形成像素点的像素电极和薄膜晶体管， 每个像素电极由薄膜晶体管控制。 当薄膜晶体管导通时，像素电极在导通 时间内充电，薄膜晶体管关断后，像素电极电压将维持到下一次扫描时重 新充电。 彩膜基板上形成有黑矩阵和彩色树脂。
液晶显示器在显示画面时，为了防止液晶老化，通常会采取极性反转 模式，典型的极性反转模式有：帧反转 ( Frame Inversion 行反转 ( Line Inversion \ 歹 ϋ反转 ( Column Inversion )禾口点反转 ( Dot Inversion \ 所谓极 性反转中的极性，当像素电压信号高于公共电极信号时，称之为正极性， 当像素电压信号低于公共电极信号时，称之为负极性。
目前，在液晶显示面板生产过程中， P牵低制作成本是一项非常重要的 内容。 现有的一种 HSD ( Half Source Driving ,半源极驱动）架构，它是将 提供扫描信号的栅极线的数量加倍，而提供数据信号的数据线的数量减半， 和传统的架构相比，信号线的总数量会有明显的减少，从而减少源极 ( Source )驱动 IC ( Integrated Circuit ,集成电路）的数量，达到降低制作 成本的目的。
现在液晶显示面板驱动方式中，点反转是显示效果最好的一种反转方 式。请参阅图 1 ,为现有的采用 HSD架构和点反转的 TFT-LCD面板的电路 结构示意图。 包括：数个提供数据信号的数据线 ( Datal~Data5 与数据线 交叉设置的数个提供扫描信号的栅极线 ( Gatel-GateS 及数个像素（ P )； 每一个像素（ P )连接一条数据线与一条栅极线，且每一个像素（ P )的极 性与与其相邻的上下左右的像素的极性都是相反的；
所述像素（ P )包括薄膜晶体管 ( Tr )及像素电极（ D )；所述薄膜晶体 管（ Tr )具有栅极 ( g X 源极（ s λ 漏极（ d ) ;所述像素电极 ( D )电性连 接于薄膜晶体管（ Tr )的漏极（ d )；具体地，液晶显示面板上的每一个像 素可等效成液晶电容（ CLC )与存储电容（ Cstg )的并联结构，液晶电容（ CLC ) 与存储电容（ Cstg )的一侧电极与像素电极（ D )连接，另一侧电极与公共 电极线 ( VC0M )连接。
配置在同一行奇数列的像素（ P )中薄膜晶体管（ Tr )的栅极（ g )与 第 2η+2 ( η=0 , 1 , 2... )栅极线 ( Gate2、 Gate4、 Gate6、 Gate8 )的某一条 公共连接；配置在同一行偶数列的像素（ P )中薄膜晶体管（ Tr )的栅极 ( g ) 与第 2η+1 ( η=0 , 1 , 2... )栅极线 ( Gatel、 Gate 3、 Gate 5、 Gate7 )的某一 条公共连接；配置在同一列的像素（ P )中薄膜晶体管 ( Tr )的源极（ s )与 某一条数据线公共连接，且配置在第 2n+2列与第 2n+3列的像素（ P )中薄 膜晶体管 ( Tr )的源极 ( s )均电性连接于相对应的第 η+2 ( η=0 , 1 , 2... ) 条数据线。
所述薄膜晶体管 ( Tr )可在不同时刻对所述像素电极（ D )进行充电。 请参阅图 2 ,为图 1 采用传统驱动方式时的时序图，以 HD ( High Definition ,高清 )解析度为例。 栅极线按照 1 , 2 , 3…… η , η+1的编号顺序 依次导通，数据线在每两条栅极线导通的时间就要切换一次极性。
以第二数据线 ( Data2 )为例，第一栅极线 ( Gatel )导通时第二数据线
( Data2 )的驱动电压为负极性 ( - ) ,第二栅极缴 Gate2 第三栅极绂 Gate3 ) 导通时第二数据线（ Data2 )的驱动电压为正极性（ + ) ,第四栅极线（ Gate4 第五栅极线 ( Gate5 )导通时第二数据线 ( Data2 )的驱动电压又切换为负极 性（ - 当栅极线编号为 4n+2和 4η+3 ( η=0 , 1 , 2... )时第二数据线（ Data2 ) 的驱动电压为正极性（ + ) ,而栅极线编号为 4η和 4η+1 ( η=0 , 1 , 2... )时 第二数据线（ Data2 )的驱动电压为负极性（- ) ,每给两个像素充电，第二 数据线 ( Data2 )的信号就需要切换一次驱动电压的极性。
由此可见，采用 HSD架构的液晶显示面板如果使用传统的驱动方式， 以 HD的解析度，工作频率为 60Hz ,则液晶显示面板工作时，数据线的信 号每两个像素（ Pixel )就需要切换一次驱动电压的极性，即大约每 21.7μδ 就需要切换一次极性，在整个帧（ Fmme )的时间内，总共需要切换 768次 极性，对应的信号频率为 768x 60=46.08kHz。 这样的缺点一方面是信号频 率太高，增加了数据线上的功率消耗；另一方面是 HSD架构像素的充电时 间很短，数据线上信号切换的电阻电容延迟效应 ( RC Delay )也会进一步 影响像素的充电情况，不利于显示品质的提高，而当液晶显示面板分辨率 提高时，这个问题会更加严重。 发明内容
本发明的目的在于提供一种液晶显示面板驱动方法，在实现点反转方 式的基础上，显著的降低了数据线上信号正负极性切换的频率，进而降低 整个 HSD架构面板的功耗，有效改善像素的充电情况，提高显示品质。 为实现上述目的，本发明提供一种液晶显示面板驱动方法，包括： 步骤 100、提供数个提供数据信号的数据线、与数据线交叉设置的数个 提供扫描信号的栅极线 ( Gatel〜 Gatem 及数个像素（ P ) ,每一个像素连 接一条数据线与一条栅极线，且每一个像素的极性与与其相邻的上下左右 的像素的极性都是相反的；
步骤 200、 对应驱动电压为第一极性的像素的栅极线按顺序依次导通， 完成半个帧的信号写入；
步骤 300、 对应驱动电压为第二极性的像素的栅极线按顺序依次导通， 完成另外半个帧的信号写入；
所述第一极性与第二极性的极性相反。
在一个帧的时间内，所述数据线的信号切换两次驱动电压的极性，所 述第一极性为负极性，所述第二极性为正极性。
所述 m为 4的倍数。
所述步骤 200中的栅极线导通的顺序为按栅极线编号由小到大。
所述步骤 300中的栅极线导通的顺序为按栅极线编号由小到大。
所述步骤 300中的栅极线导通的顺序为按栅极线编号由大到小。 所述 m为 1536 ,栅极线按照 1→4→5→ .··.··→4η→4η+1→ .··.··→1533→ 1536→2→3→ ......4η+2→4η+3→ ......→1534→1535的编号顺序依次导通，完 成一个帧的信号写入，对应的数据信号在第一栅极线至第 1536栅极线 ( Gatel→Gatel536 )导通的这段时间驱动电压为第一极性，而在第二栅极 线至第 1535栅极线 ( Gate2→Gatel535 )导通的这段时间驱动电压为第二极 性。
所述 m为 1536 ,栅极线按照 1→4→5→ .··.··→4n→4n+l→ .··.··→1533→ 1536→1535→1534→…… 4n+3→4n+2→……→3→2的编号顺序依次导通，完 成一个帧的信号写入，对应的数据信号在第一栅极线至第 1536栅极线 ( Gatel→Gatel536 )导通的这段时间驱动电压为第一极性，而在第 栅极线至第 2栅极线 ( Gatel535→Gate2 )导通的这段时间驱动电压为第二 极性。
所述像素（ P )包括薄膜晶体管 ( Tr )及像素电极（ D )；所述薄膜晶体 管（ Tr )具有栅极 ( g X 源极（ s λ 漏极（ d ) ;所述像素电极 ( D )电性连 接于薄膜晶体管 ( Tr )的漏极 ( d ) ;配置在同一行奇数列的像素（ P )中薄 膜晶体管 ( Tr )的栅极（ g )与第 2n+2栅极线的某一条公共连接；配置在 同一行偶数列的像素（ P )中薄膜晶体管 ( Tr )的栅极（ g )与第 2n+l栅极 线的某一条公共连接；配置在同一列的像素（ P )中薄膜晶体管 ( Tr )的源 极（ s )与某一条数据线公共连接，且配置在第 2n+2列与第 2n+3列的像素 ( P )中薄膜晶体管 ( Tr )的源极 ( s )均电性连接于相对应的第 n+2条数 据线。
所述液晶显示面板采用 HSD架构。
本发明还提供一种液晶显示面板驱动方法，包括：
步骤 100、提供数个提供数据信号的数据线、与数据线交叉设置的数个 提供扫描信号的栅极线 ( Gatel〜 Gatem 及数个像素（ P ) ,每一个像素连 接一条数据线与一条栅极线，且每一个像素的极性与与其相邻的上下左右 的像素的极性都是相反的；
步骤 200、 对应驱动电压为第一极性的像素的栅极线按顺序依次导通， 完成半个帧的信号写入；
步骤 300、 对应驱动电压为第二极性的像素的栅极线按顺序依次导通， 完成另外半个帧的信号写入；
所述第一极性与第二极性的极性相反；
在一个帧的时间内，所述数据线的信号切换两次驱动电压的极性，所 述第一极性为负极性，所述第二极性为正极性； 所述 m为 4的倍数；
所述步骤 200中的栅极线导通的顺序为按栅极线编号由小到大； 所述步骤 300中的栅极线导通的顺序为按栅极线编号由小到大； 所述 m为 1536 ,栅极线按照 1→4→5→ .··.··→4n→4n+l→ .··.··→1533→ 1536→2→3→ ......4n+2→4n+3→ ......→1534→1535的编号顺序依次导通，完 成一个帧的信号写入，对应的数据信号在第一栅极线至第 1536栅极线 ( Gatel→Gatel536 )导通的这段时间驱动电压为第一极性，而在第二栅极 线至第 栅极线（ Gate2→Gatel535 )导通的这段时间驱动电压为第二极 性；
所述像素（ P )包括薄膜晶体管 ( Tr )及像素电极（ D )；所述薄膜晶体 管（ Tr )具有栅极 ( g X 源极（ s λ 漏极（ d ) ;所述像素电极 ( D )电性连 接于薄膜晶体管 ( Tr )的漏极 ( d ) ;配置在同一行奇数列的像素（ P )中薄 膜晶体管 ( Tr )的栅极（ g )与第 2n+2栅极线的某一条公共连接；配置在 同一行偶数列的像素（ P )中薄膜晶体管 ( Tr )的栅极（ g )与第 2n+l栅极 线的某一条公共连接；配置在同一列的像素（ P )中薄膜晶体管 ( Tr )的源 极（ s )与某一条数据线公共连接，且配置在第 2n+2列与第 2n+3列的像素 ( P )中薄膜晶体管 ( Tr )的源极 ( s )均电性连接于相对应的第 n+2条数 据线；
所述液晶显示面板采用 HSD架构。
本发明的有益效果：本发明提供一种液晶显示面板驱动方法，其重新 设计点反转方式下的 HSD架构液晶显示面板的驱动方式，通过对应驱动电 压为第一极性的像素的栅极线按编号由小到大的顺序依次导通，完成半个 帧的信号写入；对应驱动电压为第二极性的像素的栅极线按编号由小到大 的顺序依次导通，或者对应驱动电压为第二极性的像素的栅极线按编号由 大到小的顺序依次导通，完成另外半个帧的信号写入，该第一极性与第二 极性的极性相反，使数据线的信号在一个帧的时间内只需要切换两次驱动 电压的极性，显著的降低了数据线上信号正负极性切换的频率，进而降低 整个 HSD架构液晶显示面板的功耗，有效改善像素的充电情况，提高显示 品质。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本 发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发 明加以限制。 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明 的技术方案及其它有益效果显而易见。
附图中，
图 1为现有的采用 HSD架构和点反转的 TFT-LCD面板的电路结构示 意图；
图 2为图 1采用传统驱动方式时的时序图；
图 3为本发明液晶显示面板驱动方法的流程示意图；
图 4为图 1采用本发明驱动方法时第一实施例的时序图；
图 5为图 1采用本发明驱动方法时第二实施例的时序图。 具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图 3并结合图 1 ,本发明提供一种液晶显示面板驱动方法 ,包括： 步骤 100、提供数个提供数据信号的数据线、与数据线交叉设置的数个 提供扫描信号的栅极线 ( Gatel〜 Gatem 及数个像素（ P ) ,每一个像素连 接一条数据线与一条栅极线，且每一个像素的极性与与其相邻的上下左右 的像素的极性都是相反的；
步骤 200、 对应驱动电压为第一极性的像素的栅极线按顺序依次导通， 完成半个帧的信号写入；
步骤 300、 对应驱动电压为第二极性的像素的栅极线按顺序依次导通， 完成另外半个帧的信号写入；
所述第一极性与第二极性的极性相反。
在一个帧的时间内，所述数据线的信号切换两次驱动电压的极性。
所述 m为 4的倍数。
所述像素（ P )包括薄膜晶体管 ( Tr )及像素电极（ D )；所述薄膜晶体 管（ Tr )具有栅极 ( g X 源极（ s λ 漏极（ d ) ;所述像素电极 ( D )电性连 接于薄膜晶体管 ( Tr )的漏极 ( d ) ;配置在同一行奇数列的像素（ P )中薄 膜晶体管 ( Tr )的栅极（ g )与第 2n+2栅极线的某一条公共连接；配置在 同一行偶数列的像素（ P )中薄膜晶体管 ( Tr )的栅极（ g )与第 2n+l栅极 线的某一条公共连接；配置在同一列的像素（ P )中薄膜晶体管 ( Tr )的源 极（ s )与某一条数据线公共连接，且配置在第 2n+2列与第 2n+3列的像素 ( P )中薄膜晶体管 ( Tr )的源极 ( s )均电性连接于相对应的第 n+2条数 据线。
所述液晶显示面板采用 HSD架构。
请参阅图 4并结合图 1、 图 3 ,图 4为图 1采用本发明驱动方法时第一 实施例的时序图。 以 m为 1536、 第一极性为负极性（- X 第二极性为正极 性（ + )为例，具体地，以图 1中的第二数据线（ Data2 ) (液晶显示面板解 析度为 HD ,分辨率为 1366x768 ,工作频率为 60Hz )为例，栅极线按照 1 →4→5→ →4n→4n+l→ →1533→1536→2→3→ 4n+2→4n+3 →……→1534→1535的编号顺序依次导通，完成一个帧的信号写入，对应第 二数据线（ Data2 )的数据信号在第一栅极线至第 1S36栅极线（ Gatel→ Gatel536 )导通的这段时间驱动电压为负极性（- ) ,而在第二栅极线至第 1535栅极线 ( Gate2→Gatel535 )导通的这段时间驱动电压为正极性（ + ) , 在一个帧的时间内，只需要切换两次极性，第二数据线 ( Data2 )每 8.33ms 才会切换一次信号极性 ,对应的信号'频率由采用传统驱动方式 (请参见图 2 ) 时的 46.08kHz P牵低到 120Hz ,即对应的信号'频率降 ί氐到采用传统驱动方式 时的 1/384。 在实现点反转方式的基础上，一方面显著的降低了数据线上信 号正负极性切换的频率，进而降低整个 HSD架构面板的功耗，另一方面也 可以减轻数据线电阻电容延迟效应对像素充电的影响，有利于提高显示的 品质。
请参阅图 5并结合图 1、 图 3 ,图 5为图 1采用本发明驱动方法时第二 实施例的时序图。 同样以 m为 1536、 第一极性为负极性（- X 第二极性为 正极性 ( + )为例，具体地，以图 1中的第二数据线 ( Data2 ) (液晶显示面 板解析度为 HD ,分辨率为 1366x768 ,工作频率为 60Hz )为例，栅极线按 照 1→4→5→ .··.··→4n→4n+l→ .··.··→1533→1536→1535→1534→ .··.·· 4n+3 →4n+2→ ......→3→2的编号顺序依次导通，完成一个帧的信号写入。 对应 第二数据线 ( Data2 )的数据信号在第一栅极线至第 1536栅极线（ Gatel→ Gatel536 )导通的这段时间驱动电压为负极性（- ) ,而在第 1535栅极线至 第 2栅极线 ( Gatel535→Gate2 )导通的这段时间驱动电压为正极性 ( + ) , 在一个帧的时间内，也只需要切换两次极性。
与本发明第一实施例不同的是，第一实施例每个帧的前 1/2和后 1/2的 时间内，栅极线开启都是按照相同的编号顺序，即第一栅极线至第 1536栅 极线 '第二栅极线至第 1535栅极线（ Gatel→Gate 1536 ,Gate2→Gate 1535 ) , 即所述步骤 200中的栅极线导通的顺序为按栅极线编号由小到大，所述步 骤 300中的栅极线导通的顺序为按栅极线编号由小到大；而第二实施例， 每个帧的前 1/2和后 1/2的时间内，栅极线开启的编号顺序是相反的，即第 —栅极线至第 1536栅极线 '第 1535栅极线至第 2栅极绂 Gatel→Gate 1536 , Gatel535→Gate 2 ) ,即所述步骤 200中的栅极线导通的顺序为按栅极线编 号由小到大，所述步骤 300中的栅极线导通的顺序为按栅极线编号由大到 小。 但本发明的第一实施例与第二实施例都可以达到降 ί氏液晶显示面板功 耗的目的。
综上所述，本发明提供一种液晶显示面板驱动方法，其重新设计点反 转方式下的 HSD架构液晶显示面板的驱动方式，通过对应驱动电压为第一 极性的像素的栅极线按栅极线编号由小到大的顺序依次导通，完成半个帧 的信号写入；对应驱动电压为第二极性的像素的栅极线按栅极线编号由小 到大的顺序依次导通，或者对应驱动电压为第二极性的像素的栅极线按栅 极线编号由大到小的顺序依次导通，完成另外半个帧的信号写入，该第一 极性与第二极性的极性相反，使数据线的信号在一个帧的时间内只需要切 换两次驱动电压的极性，显著的降低了数据线上信号正负极性切换的频率， 进而降低整个 HSD架构液晶显示面板的功耗，有效改善像素的充电情况， 提局显 品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形 都应属于本发明权利要求的保护范围。

Claims

杈 利 要 求
1、 一种液晶显示面板驱动方法，包括：
步骤 100、提供数个提供数据信号的数据线、与数据线交叉设置的数个 提供扫描信号的栅极线、 及数个像素，每一个像素连接一条数据线与一条 栅极线，且每一个像素的极性与与其相邻的上下左右的像素的极性都是相 反的；
步骤 200、 对应驱动电压为第一极性的像素的栅极线按顺序依次导通， 完成半个帧的信号写入；
步骤 300、 对应驱动电压为第二极性的像素的栅极线按顺序依次导通， 完成另外半个帧的信号写入；
所述第一极性与第二极性的极性相反。
2、 如权利要求 1所述的液晶显示面板驱动方法，其中，在一个帧的时 间内，所述数据线的信号切换两次驱动电压的极性，所述第一极性为负极 性，所述第二极性为正极性。
3、 如权利要求 1所述的液晶显示面板驱动方法，其中，所述 m为 4 的倍数。
4、 如权利要求 1所述的液晶显示面板驱动方法，其中，所述步骤 200 中的栅极线导通的顺序为按栅极线编号由小到大。
5、 如权利要求 1所述的液晶显示面板驱动方法，其中，所述步骤 300 中的栅极线导通的顺序为按栅极线编号由小到大。
6、 如权利要求 1所述的液晶显示面板驱动方法，其中，所述步骤 300 中的栅极线导通的顺序为按栅极线编号由大到小。
7、如权利要求 3所述的液晶显示面板驱动方法，其中，所述 m为 1536 , 栅极线按照 1→4→5→……→4n→4n+l→……→1533→1536→2→3→…… 4n+2→4n+3→……→1534→1535 的编号顺序依次导通，完成一个帧的信号 写入，对应的数据信号在第一栅极线至第 1536栅极线导通的这段时间驱动 电压为第一极性，而在第二栅极线至第 1535栅极线导通的这段时间驱动电 压为第二极性。
8、如权利要求 3所述的液晶显示面板驱动方法，其中，所述 m为 1536 , 栅极线按照 1→4→5→ .··.··→4n→4n+l→ .··.··→1533→1536→1535→1534 →…… 4n+3→4n+2→……→3→2的编号顺序依次导通，完成一个帧的信号写 入，对应的数据信号在第一栅极线至第 1536栅极线导通的这段时间驱动电 压为第一极性，而在第 1535栅极线至第 2栅极线导通的这段时间驱动电压 为第二极性。
9、 如权利要求 1所述的液晶显示面板驱动方法，其中，所述像素包括 薄膜晶体管及像素电极；所述薄膜晶体管具有栅极、 源极、 漏极；所述像 素电极电性连接于薄膜晶体管的漏极；配置在同一行奇数列的像素中薄膜 晶体管的栅极与第 2n+2栅极线的某一条公共连接；配置在同一行偶数列的 像素中薄膜晶体管的栅极与第 2n+l栅极线的某一条公共连接；配置在同一 列的像素中薄膜晶体管的源极与某一条数据线公共连接，且配置在第 2n+2 列与第 2n+3列的像素中薄膜晶体管的源极均电性连接于相对应的第 n+2条 数据线。
10、 如权利要求 1所述的液晶显示面板驱动方法，其中，所述液晶显 示面板采用 HSD架构。
11、 一种液晶显示面板驱动方法，包括：
步骤 100、提供数个提供数据信号的数据线、与数据线交叉设置的数个 提供扫描信号的栅极线、 及数个像素，每一个像素连接一条数据线与一条 栅极线，且每一个像素的极性与与其相邻的上下左右的像素的极性都是相 反的；
步骤 200、 对应驱动电压为第一极性的像素的栅极线按顺序依次导通， 完成半个帧的信号写入； 步骤 300、 对应驱动电压为第二极性的像素的栅极线按顺序依次导通， 完成另外半个帧的信号写入；
所述第一极性与第二极性的极性相反；
其中，在一个帧的时间内，所述数据线的信号切换两次驱动电压的极 性，所述第一极性为负极性，所述第二极性为正极性；
其中，所述 m为 4的倍数；
其中，所述步骤 200中的栅极线导通的顺序为按栅极线编号由小到大； 其中，所述步骤 300中的栅极线导通的顺序为按栅极线编号由小到大； 其中，所述 m为 1536 ,栅极线按照 1→4→5→ ......→4n→4n+l→ ......→
1533→1536→2→3→ .··.·· 4n+2→4n+3→ .··.··→1534→1535 的编号顺序依次 导通，完成一个帧的信号写入，对应的数据信号在第一栅极线至第 1536栅 极线导通的这段时间驱动电压为第一极性，而在第二栅极线至第 1535栅极 线导通的这段时间驱动电压为第二极性；
其中，所述像素包括薄膜晶体管及像素电极；所述薄膜晶体管具有栅 极、 源极、 漏极；所述像素电极电性连接于薄膜晶体管的漏极；配置在同 一行奇数列的像素中薄膜晶体管的栅极与第 2n+2栅极线的某一条公共连 接；配置在同一行偶数列的像素中薄膜晶体管的栅极与第 2n+l栅极线的某 一条公共连接；配置在同一列的像素中薄膜晶体管的源极与某一条数据线 公共连接，且配置在第 2n+2列与第 2n+3列的像素中薄膜晶体管的源极均 电性连接于相对应的第 n+2条数据线；
其中，所述液晶显示面板采用 HSD架构。
PCT/CN2014/079713 2014-05-27 2014-06-12 液晶显示面板驱动方法 Ceased WO2015180211A1 (zh)

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