WO2015180152A1

WO2015180152A1 - Multi-machine frequency converter

Info

Publication number: WO2015180152A1
Application number: PCT/CN2014/078968
Authority: WO
Inventors: 柯冬生
Original assignee: 深圳市英威腾电气股份有限公司
Priority date: 2014-05-30
Filing date: 2014-05-30
Publication date: 2015-12-03
Also published as: CN105431792A; CN105431792B

Abstract

Provided is a multi-machine frequency converter, which may comprise: a master control unit, and N1 execution units coupled in series by means of a communications port, said N1 execution unit sharing a common DC bus; the first communications port of the master control unit is connected to the second communications port of the first of the N1 execution units; the N1 execution units comprise N11 rectifier units and N12 inverter units; N11 is a positive integer, and N12 is a positive integer greater than 1; said first execution unit is an execution unit located at an edge position of said N1 execution units connected in series by means of a communications port. The technical solution provided by the embodiments of the present invention is conducive to reducing the complexity of frequency converter wiring configurations in the context of multiple machines, improving the stability and reliability in multi-machine operation of frequency converters.

Description

Multi-machine frequency converter

The invention mainly relates to the field of power electronics technology, and in particular to a multi-machine frequency converter. Background technique

At present, most of the inverters on the market are single-machine inverters. The single-unit inverters use a control unit to directly control an inverter unit. The control unit generally does not control the rectifier unit. The specific structure can be as shown in Figure 1-a.

The single-machine inverter should be operated synchronously (ie, the speed/torque of the load motor of at least two single-machine inverters is the same or the output of the corresponding or at least two single-machine inverters is connected in parallel with the load motor or asynchronous to realize the factory macro) At least two single-machine inverters form a multi-machine system of the inverter, and each inverter is based on the RS485 bus communication mode. The structure of the 485 bus communication mode is shown in Figure 1-b. The console transmits the system running frequency to each inverter through the 485 bus. Each inverter transmits the status feedback information to the console through the bus. In addition, the system gives the shutdown signal and the torque signal sent by the main inverter to the slave inverter through a separate signal line connection. Such multiple frequency converters are connected to realize complicated control line wiring, and the serial bus wiring is too long.

In the process of research and practice, the inventors found that the existing inverter system has some defects in the dual-machine or multi-machine master-slave control application: 485 bus mode communication exists, the master-slave communication mode itself has weak anti-interference , the shortcomings of poor signal transmission stability. Due to the limitation of communication methods, it is difficult to transmit signals over long distances. Moreover, the master-slave system has a complicated control structure, and multiple signal lines work at the same time, and the installation operation is cumbersome. Summary of the invention

The embodiment of the invention provides a multi-machine frequency converter, in order to simplify the complexity of the wiring structure under the multi-machine scene of the inverter and improve the stability and reliability of the multi-machine operation of the inverter.

A first aspect of the embodiment of the present invention provides a multi-machine frequency converter, which may include:

a main control unit, N1 execution units connected in series through a communication port, wherein the N1 execution units share a common DC bus; The first communication port of the main control unit is connected to the second communication port of the first execution unit of the N1 execution units, wherein the N1 execution units comprise a total of Nil rectification units and N12 inverses. a variable unit, the Nil is a positive integer, the N12 is a positive integer greater than 1, and the first execution unit is an execution unit at one end edge position among the N1 execution units connected in series through a communication port.

Optionally, the second communication port of the main control unit is connected to the first communication port of the second execution unit of the N1 execution units, where the second execution unit is the serial connection through the communication port. An execution unit at the other end edge position among the N1 execution units.

Optionally, the multi-machine frequency converter further includes N2 execution units connected in series through a communication port, wherein the N2 execution units share the DC bus;

a second communication port of the main control unit is connected to a first communication port of a third execution unit of the N2 execution units connected in series through a communication port, where the N2 is a positive integer, and the N2 execution units are The rectifying unit and/or the inverting unit are included, wherein the third executing unit is an executing unit at one end edge position among the N2 executing units connected in series through the communication port.

Optionally, the first execution unit is an inverter unit, and the first communication port of the first execution unit is connected to the second communication port of the fourth execution unit of the N1 execution units, where The fourth execution unit is a rectification unit or an inverter unit;

Or the first execution unit is a rectification unit, and the first communication port of the first execution unit is connected to the second communication port of the fifth execution unit of the N1 execution units, wherein the fifth execution The unit is a rectification unit or an inverter unit.

Optionally, the communication port is a fiber communication port or an Ethernet communication port or a level signal communication port or a differential communication interface.

A second aspect of the embodiment of the present invention provides a multi-machine frequency converter, which may include:

The main control unit, N3 execution units connected in series through the communication port, and N4 execution units connected in series through the communication port;

The N3 execution units and the N4 execution units share a common DC bus;

The first communication port of the main control unit is connected to a second communication port of a sixth execution unit of the N3 execution units connected in series through a communication port, and the second communication port of the main control unit Connecting with a first communication port of a seventh one of the N4 execution units connected in series via a communication port;

The N3 execution units and the N4 execution units include XI rectification units and X2 inverter units, wherein the XI is a positive integer, and the X2 is a positive integer greater than 1, the The six execution unit is an execution unit at one end edge position among the N3 execution units connected in series through the communication port, and the seventh execution unit is an execution unit at one end edge position among the N4 execution units connected in series through the communication port. .

Optionally, the sixth execution unit is a rectification unit, and the first communication port of the sixth execution unit is connected to a second communication port that is connected to the ninth execution unit of the N3 execution units, where the ninth The execution unit is a rectifying unit or an inverter unit;

Optionally, the sixth execution unit is an inverter unit, and the first communication port of the sixth execution unit is connected to the second communication port of the eighth execution unit of the N3 execution units, where The eighth execution unit is a rectification unit or an inverter unit.

A third aspect of the embodiment of the present invention provides a multi-machine frequency converter, which may include:

a main control unit, N5 rectifying units, N6 inverter units connected in series through a communication port, wherein the N5 rectifying units and the N6 inverter units have a common DC bus;

The first communication port of the main control unit is connected to the second communication port of the first inverter unit of the N6 inverter units, the N5 is a positive integer, and the N6 is a positive integer greater than 1. The first inverter unit is an inverter unit at one end edge position among the N6 inverter units connected in series through a communication port.

Optionally, the second communication port of the main control unit is connected to the first communication port of the second inverter unit of the N6 inverter units, wherein the second inverter unit is connected in series through the communication port. Among the N6 inverter units, the inverter unit is located at the other end edge position.

A fourth aspect of the embodiments of the present invention provides a multi-machine frequency converter, which may include: a main control unit, N9 rectifying units, N7 inverter units connected in series through a communication port, and N8 inverter units connected in series through a communication port; wherein, the N9 rectifying units, the N7 inverter units, and the N8 inverter units common to the DC bus;

The first communication port of the main control unit is connected to a second communication port of the first inverter unit of the N7 inverter units connected in series through the communication port, and the second communication port of the main control unit is Connecting, by the first communication port of the second inverter unit of the N8 inverter units connected in series by the communication port;

The N7 and the N8 are positive integers, and the first inverter unit is an inverter unit at one end edge position of the N7 inverter units connected in series through a communication port, where the second inverse The variable unit is an inverter unit at one end edge position among the N8 inverter units connected in series through the communication port.

It can be seen that in some embodiments of the present invention, the multi-machine frequency converter includes a main control unit and a plurality of execution units, which is advantageous for effectively reducing the parallel cost compared with the existing inverter multi-machine system. The 485 bus communication mode in the conventional inverter multi-machine system is replaced by the serial communication mode between the main control unit of the inverter and the multiple execution units, thereby facilitating the elimination of the defects of poor anti-interference and short transmission distance of the transmission signal. It is beneficial to realize the ultra-long transmission with strong anti-interference ability, which is beneficial to improve the stability and reliability of the multi-machine operation scene of the inverter. The interconnection structure between the main control unit and the execution unit is relatively simple, and the installation and wiring are relatively simple. It can be seen that the structure of the embodiment of the present invention is advantageous for simplifying the wiring structure complexity of the multi-machine scene of the inverter. Moreover, since the execution units are connected in series through the communication port, this is advantageous for improving the scalability of the multi-machine operation of the inverter, and multiple execution units can be connected in series through the communication port according to different scenarios to meet the corresponding requirements. DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any inventive labor. Figure 1-a is a schematic diagram of a stand-alone frequency converter provided by the prior art;

Figure 1-b is a parallel diagram of a plurality of single-machine frequency converters provided by the prior art;

FIG. 2-a is a schematic diagram of a multi-machine frequency converter according to an embodiment of the present invention; FIG.

FIG. 2 is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention; FIG.

2-c is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention;

2-d is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention;

2 e is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention;

2-f is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention;

2-g is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention;

FIG. 3 - a is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention;

FIG. 3 - b is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention;

3 - c are schematic diagrams of another multi-machine frequency converter according to an embodiment of the present invention;

FIG. 3 - d is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention;

3 e is a schematic diagram of another multi-machine frequency converter provided by an embodiment of the present invention;

Figure 4-a is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention;

Figure 4-b is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention.

detailed description

In order to make the object, the features and the advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are only a part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

The terms "first", "second", "third", "fourth" and the like in the specification and claims of the present invention and the above drawings are used to distinguish different objects, and are not intended to describe a specific order. Furthermore, the terms "comprising" and "having" and "the" are intended to cover the meaning E.g A process, method, system, product, or device that comprises a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units not listed, or alternatively also includes Other steps or units inherent to these processes, methods, products or equipment.

First, the multi-machine frequency converter provided by the embodiment of the present invention includes: a main control unit, at least one rectifying unit, and at least two inverter units, wherein some or all of the rectifying units in the multi-machine frequency converter may be the main control unit The controlled rectification unit is controlled, or it may be an uncontrollable rectification unit that is not controlled by the main control unit. The related structure will be exemplified below with reference to the accompanying drawings.

Referring first to FIG. 2-a, FIG. 2-a is a schematic structural diagram of a multi-machine frequency converter according to an embodiment of the present invention. As shown in FIG. 2-a, a multi-machine frequency converter provided by an embodiment of the present invention may include:

The main control unit 201 and the N1 execution units 202 connected in series through the communication port, the N1 execution unit common DC bus 210.

The first communication port P1 of the main control unit 201 is connected to the second communication port P0 of the first execution unit among the N1 execution units 202. Wherein, the first execution unit is an execution unit at one end edge position among the above-mentioned N1 execution units connected in series through the communication port (wherein, in the example architecture of FIG. 2-a, one end edge position of the N1 execution units after the series connection is remaining The first execution unit of the second communication port P0, and the other end edge position is the second execution unit of the remaining first communication port P1).

The execution unit 202 is a rectification unit or an inverter unit. The N1 execution units 202 include a total of Nil rectification units and N12 inverter units. The Nil is a positive integer, and the N12 is a positive integer greater than 1.

Wherein, each execution unit 202 in FIG. 2-a includes two communication ports (communication port P0 and communication port P1). Of course, the functions of the two communication ports may be the same or similar, and in some scenarios, the two communication The ports are interchangeable. The communication port P0 and the communication port P1 of each of the execution units in the intermediate position in the N1 execution units 202 are connected to the other execution units 202, respectively, to realize the concatenation of the N1 execution units 202.

The main control unit 201 can send a command word, a data word (for example, a data word including a pulse width modulation (PWM), such as a voltage angle and a voltage modulation ratio) and/or a state through the first communication port P1. Words, etc. The first execution unit can pass its second communication The port P0 receives the command word, the data word and/or the status word from the main control unit 201, and the first execution unit can forward it through the first communication port P1 (for the transparently transmittable data, it can be directly forwarded, for the processing to be processed The data can then be forwarded after processing) the received command word from the master unit 201, the data receive command word, the data word and/or the status word, and the like.

It should be noted that the "forwarding" in the embodiments of the present invention may be that the received data is directly forwarded without modification, or may be forwarded after the received data is correspondingly repaired, for example, for the received command. The transparently transceivable content of the word, data word and/or status word can be directly forwarded without modification, and the content of the received command word, data word and/or status word cannot be transparently transmitted. It is forwarded after modification.

The N1 execution units 202 may generate a synchronization signal according to information such as a reference clock and a time compensation value sent by the main control unit; and may also be based on a command word and a data word from the main control unit 201 (eg, including a voltage angle and a voltage modulation ratio, etc.) The data word of the PWM wave key data) and/or the status word are correspondingly operated. For example, the N1 execution units 202 can enter a state of power-on startup or hibernation according to a command word from the main control unit 201. For another example, the N1 execution units 202 may generate synchronized pulse width modulated waves according to data words from the main control unit 201 including PWM voltage key data such as voltage angle and voltage modulation ratio; and use the generated pulse width wave to drive the motor to operate.

It can be seen that the present invention provides a multi-machine frequency converter capable of achieving parallel synchronization and/or asynchronous operation, which is significantly reduced compared with the prior art method of implementing parallel functions by using multiple frequency converters. The realization cost; replace the 485 bus communication mode in the conventional inverter multi-machine system by serial communication mode (such as switched Ethernet communication mode) between the main control unit of the inverter and multiple execution units, which is beneficial to Eliminating the defects of poor anti-interference and short transmission distance of the transmission signal is beneficial to realize the ultra-long transmission with strong anti-interference ability, which is beneficial to improve the stability and reliability of the multi-machine operation scene of the inverter. The interconnection structure between the main control unit and the execution unit is relatively simple, and the installation and wiring are relatively simple. It can be seen that this structure is advantageous for simplifying the wiring structure complexity of the multi-machine scene of the inverter. And because the execution units are connected in series through the communication port, this is beneficial to improve the scalability of the multi-machine operation of the inverter, and multiple execution units can be connected in series through the communication port according to different scenarios to meet the corresponding requirements.

On the basis of FIG. 2-a, the main control unit 201 further includes a second communication port P0, and the main control unit 201 can A command word, a data word, and/or a status word or the like is transmitted through the second communication port P0.

In some embodiments of the present invention, as shown in FIG. 2-b, the second communication port P0 of the main control unit 201 may also be connected to the first communication port P1 of the second execution unit of the N1 execution units 202. Forming a communication loop design structure, the main control unit 201 can send a command word, a data word, and/or a status word to each execution unit 202 through the second communication port P0 and/or the first communication port P1, which is equivalent to providing two The communication channel for transmitting information and the introduction of the communication loop enable the communication channel between the units to have a redundant backup function, and the anti-fault and fault tolerance capabilities are enhanced, which is beneficial to further improve the stability and reliability of the system operation.

In other embodiments of the present invention, as shown in FIG. 2-c, the multi-machine frequency converter may further include N2 execution units 203 connected in series through a communication port, wherein the N2 execution units 203 share a common DC bus 210.

The second communication port P0 of the main control unit 201 is connected to the first communication port P1 of the third execution unit among the N2 execution units 203 connected in series through the communication port, wherein the N2 is a positive integer, and the N2 is The execution unit includes a rectification unit and/or an inverter unit, wherein the third execution unit is an execution unit at one end edge position among the N2 execution units 203 connected in series through the communication port.

2 - exemplifies that the above-mentioned main control unit 201 includes two communication ports, both of which are connected to the communication port of the execution unit, and the main difference from the architecture shown in FIG. 2-b is that the main control unit A communication loop is not formed between the 201 and the execution unit. Of course, the main control unit 201 can also include more communication ports, and each communication port of the main control unit 201 can be connected to the communication port of the execution unit in the manner shown in Figure 2-c.

As shown in FIG. 2-d and FIG. 2-e, in some embodiments of the present invention, the first execution unit may be an inverter unit, and the first communication port P1 of the first execution unit may be the same as the N1 The second communication port P0 of the fourth execution unit among the execution units is connected, wherein the fourth execution unit is a rectification unit or an inverter unit.

For example, as shown in FIG. 2-f and FIG. 2-g, in some embodiments of the present invention, the first execution unit may be a rectification unit, and the first communication port P1 and the N1 execution units of the first execution unit are The second communication port P0 of the fifth execution unit is connected, wherein the fifth execution unit is a rectification unit or Inverter unit.

It can be understood that, for example, FIG. 2-d, FIG. 2-e, FIG. 2-f, and FIG. 2-g exemplify that, in the N1 execution units connected in series through the communication port, the rectifying unit and the inverting unit may be staggered with each other. Of course, the rectifying unit and the inverting unit may also not be staggered with each other.

In some embodiments of the invention, the communication port of the execution unit and the control unit may be a fiber optic communication port or an Ethernet communication port or a level signal communication port or a differential communication interface or other type of communication port.

The following mainly takes the architecture shown in Figure 2-a as an example to illustrate some ways to generate synchronization signals in multi-machine inverters. The way in which synchronous signals are generated in multi-machine inverters under other architectures can be analogized.

In some embodiments of the present invention, the main control unit 201 is configured to periodically send a first system reference clock signal generated by a first system reference clock; calculate each of the N12 inverter units And a time compensation value corresponding to the inverter unit, and transmitting the time compensation value corresponding thereto to each of the N12 inverter units.

Each of the N12 inverter units is configured to perform time offset compensation on the local clock by using the received time compensation value after receiving the time compensation value corresponding thereto. Generating, according to the phase-locked loop, the clock signal generated by the currently received first reference clock of the main control unit 201 for synchronizing the synchronization signal of the pulse width modulated wave generated by the inverter unit .

In other embodiments of the present invention, some of the possible pulse width modulated wave key data for the operational control of the multi-machine frequency converter are exemplified. Each of the N12 inverter units is configured to generate a synchronization signal; generating a pulse width modulated wave based on the received pulse width modulated wave key data from the main control unit 201, by using the The pulse width modulated wave generated by the synchronization signal synchronization correction drives the motor to operate by the pulse width modulated wave after the synchronization correction. Referring to FIG. 3-a, FIG. 3-a is a schematic structural diagram of another multi-machine frequency converter according to another embodiment of the present invention. As shown in FIG. 3-a, another multi-machine frequency converter provided by another embodiment of the present invention may include: The main control unit 301, the N3 execution units 302 connected in series through the communication port, and the N4 execution units 303 connected in series through the communication port.

The N3 execution units and the N4 execution units share a common DC bus 310.

The first communication port P1 of the main control unit 301 is connected to the second communication port P0 of the sixth execution unit of the N3 execution units connected in series through the communication port, and the second communication port P0 and the pass of the main control unit are The first communication port P1 of the seventh execution unit of the above-described N4 execution units connected in series with the communication port is connected.

The N3 execution units and the N4 execution units include XI rectification units and X2 inverter units, wherein the XI is a positive integer, the X2 is a positive integer greater than 1, and the sixth execution unit passes An execution unit at one end edge position among the above-mentioned N3 execution units connected in series with the communication port, wherein the seventh execution unit is an execution unit at one end edge position among the N4 execution units connected in series through the communication port. Wherein, N3 and N4 are positive integers, and the sum of N3 and N4 is greater than or equal to 3.

The N3 execution units and the N4 execution units located on both sides of the main control unit 301 in the architecture shown in FIG. 3-a are compared with the architecture shown in FIG. 2-a in the foregoing embodiment. The CCP includes XI rectifier units and X2 inverter units. That is, at least one inverter unit can be deployed on both sides of the main control unit 301. In the architecture shown in Figure 2-a, one of the main control units 301 At least two inverter units and at least one rectifier unit are deployed on the side (the N1 execution units 202 include a total of Nil rectifier units and N12 inverter units).

The main control unit 301 can send a command word, a data word, and/or a status word to the N3 execution units 302 and the N4 execution units 303 through the first communication port P1 and the second communication port P0, respectively, and specifically send and forward. The process is similar to the previous part and will not be described here.

For example, as shown in FIG. 3-b and FIG. 3-c, in some embodiments of the present invention, the sixth execution unit may be a rectification unit, and the first communication port P1 of the sixth execution unit may be executed with the N3. The second communication port P0 of the ninth execution unit among the units is connected, wherein the ninth execution unit is a rectification unit or an inverter unit.

For example, as shown in FIG. 3-d and FIG. 3-e, in some embodiments of the present invention, the sixth execution unit may be an inverter unit, and the first communication port P1 and the N3 execution units of the sixth execution unit. middle The second communication port po of the eighth execution unit is connected, wherein the eighth execution unit is a rectification unit or an inverter unit.

It can be understood that, for example, FIG. 3-b, FIG. 3-c, FIG. 3-d, and FIG. 3-e exemplify that in the N3 execution units connected in series through the communication port, the rectifying unit and the inverting unit can be staggered with each other. Of course, the rectifying unit and the inverting unit may also not be staggered with each other.

It can be seen that the present invention provides a multi-machine frequency converter capable of achieving parallel synchronous and/or asynchronous operation, which is obviously compared with the prior art method of implementing parallel functions by using multiple frequency converters. The implementation cost is reduced; wherein, in the serial communication mode (such as switched Ethernet communication mode) between the main control unit of the frequency converter and the multiple execution units, the 485 bus communication mode in the conventional inverter multi-machine system is replaced. Furthermore, it is advantageous to eliminate the defect that the transmission signal has poor anti-interference and short transmission distance, and is beneficial to realize ultra-long transmission with strong anti-interference ability, thereby improving the stability and reliability of the multi-machine operation scene of the inverter. The interconnection structure between the main control unit and the execution unit is relatively simple, and the installation and wiring are relatively simple. It can be seen that this structure is advantageous for simplifying the wiring structure complexity of the multi-machine scene of the inverter. Moreover, since the execution units are connected in series through the communication port, this is advantageous for improving the scalability of the multi-machine operation of the inverter, and multiple execution units can be connected in series through the communication port according to different scenarios to meet the corresponding requirements.

The following mainly takes the architecture shown in Figure 3-a as an example to illustrate some ways to generate synchronization signals in multi-machine inverters. The way in which synchronous signals are generated in multi-machine inverters under other architectures can be analogized.

In some embodiments of the present invention, the main control unit 301 is configured to periodically send a first system reference clock signal generated by the first system reference clock, and calculate each of the X2 inverter units. And a time compensation value corresponding to the inverter unit, and transmitting the time compensation value corresponding thereto to each of the X2 inverter units. Each of the X2 inverter units is configured to perform time offset compensation on the local clock by using the received time compensation value after receiving the time compensation value corresponding thereto. And the first system reference clock signal sent by the currently received main control unit 301 is step-locked with the local clock after time offset compensation based on a phase locked loop, based on the local clock. Clock signal generation for synchronous correction A synchronization signal of a pulse width modulated wave generated by the inverter unit.

The following is an example of the architecture shown in Figure 3-a. An example of the operation control of a multi-machine inverter is given. The operation control mode of multi-machine inverters under other architectures can be analogized.

In some embodiments of the present invention, the main control unit 301 is configured to send, to each of the X2 inverter units, pulse width modulated wave key data corresponding thereto. Each of the X2 inverter units is configured to generate a synchronization signal; generate a pulse width modulated wave based on the received pulse width modulated wave key data from the main control unit 301, and use the synchronization signal The pulse width modulated wave generated by the synchronous correction drives the motor to operate by the pulse width modulated wave after the synchronization correction. Referring to FIG. 4-a, FIG. 4-a is a schematic structural diagram of another multi-machine frequency converter according to another embodiment of the present invention. As shown in FIG. 4-a, another multi-machine frequency converter provided by another embodiment of the present invention may include: a main control unit 401, N5 rectifying units 402, and N6 inverter units 403 connected in series through a communication port. .

The N5 rectifying units 402 and the N6 inverter units 403 share a common DC bus 410. The first communication port P1 of the main control unit 401 is connected to the second communication port P0 of the first inverter unit of the N6 inverter units, wherein the N5 is a positive integer, and the N6 is greater than 1. Integer, the first inverter unit is an inverter unit at one end edge position among the N6 inverter units connected in series via a communication port. In the example architecture of FIG. 4-a, one end edge position of the N6 inverter units after the series connection is the first inverter unit of the remaining second communication port P0, and the other end edge position is the second of the remaining first communication port P1. The inverter unit is connected, and the second communication port P0 remaining in the first inverter unit is connected to the first communication port P1 of the above-mentioned main control unit 401.

It can be seen that in the architecture shown in the example of FIG. 4-a, N5 rectifying units 402 are uncontrollable rectifying units that are not controlled by the main control unit 401. In the foregoing embodiment, as shown in the architecture shown in FIG. 2-a to FIG. 2-g or the architecture shown in the example of 2-a to 2-e, some rectifying units are controllable rectifying units that can be controlled by the main control unit.

The main control unit 401 can send a command word, a data word, and/or a status word to the first inverting unit through the first communication port P1, and the specific sending and forwarding processes are similar to the foregoing, and are not described herein.

It can be seen that the present invention provides a multi-machine frequency converter capable of achieving parallel synchronization and/or no Simultaneous operation, compared with the prior art method of implementing parallel function by using multiple frequency converters, significantly reduces the implementation cost; replacing serial communication between the main control unit and the inverter unit of the inverter The 485 bus communication mode in the conventional inverter multi-machine system is beneficial to eliminate the defects of poor anti-interference and short transmission distance of the transmission signal, which is beneficial to realize the ultra-long transmission with strong anti-interference ability, which is beneficial to improve the multi-machine operation of the inverter. Stable reliability of the scene. The interconnection structure between the main control unit and the inverter unit is relatively simple, and the installation and wiring are relatively simple. It can be seen that this structure is advantageous for simplifying the wiring structure complexity of the multi-machine operation scene of the inverter. Moreover, since the inverter units are connected in series through the communication port, this is advantageous for improving the scalability of the multi-machine operation scene of the inverter, and multiple inverter units can be connected in series through the communication port according to different scenarios to meet the corresponding requirements.

Referring to FIG. 4-b, FIG. 4-b shows that in some embodiments of the present invention, the main control unit 401 includes a second communication port P0, which is the same as the second inverter unit of the N6 inverter units. A communication port PI connection, wherein the second inverter unit is an inverter unit at another edge position among the N6 inverter units connected in series through the communication port.

It can be understood that FIG. 4-b shows a communication loop design structure. The communication loop is introduced so that the communication channel between the units has a redundancy backup function, and the main control unit 401 can pass the first communication port P1 and/or The second communication port P0 sends a command word, a data word and/or a status word to each inverter unit, which is equivalent to providing two communication channels for transmitting information, and the anti-fault and fault tolerance capability is enhanced, which is beneficial to further improve the system. Reliability of operation.

In some embodiments of the invention, the communication port of the inverter unit, the rectifying unit, and the control unit may be a fiber optic communication port or an Ethernet communication port or a level signal communication port or a differential communication interface or other type of communication port.

The following is an example of the architecture shown in Figure 4-a. An example of how to generate a synchronization signal in a multi-machine inverter is given. The way in which synchronous signals are generated in multi-machine inverters under other architectures can be analogized.

In some embodiments of the present invention, the main control unit 401 is configured to periodically send a first system reference clock signal generated by the first system reference clock, and calculate each of the N6 inverter units. And a time compensation value corresponding to the inverter unit, and transmitting the time compensation value corresponding thereto to each of the N6 inverter units. Each of the N6 inverter units is configured to use the received time after receiving the time compensation value corresponding thereto. The compensation value performs time offset compensation on the local clock, and the first system reference clock signal sent by the currently received main control unit 401 and the local clock after performing time offset compensation are stepped based on the phase locked loop. Locking, generating a synchronization signal for synchronously correcting a pulse width modulated wave generated by the inverter unit based on a clock signal generated by the local clock.

The following mainly takes the architecture shown in Figure 4-a as an example to illustrate some ways of operating control of multi-machine inverters. The operation control mode of multi-machine inverters under other architectures can be analogized.

In some embodiments of the present invention, the main control unit 401 is configured to send, to each of the N6 inverter units, pulse width modulated wave key data corresponding thereto. Each of the N6 inverter units is configured to generate a synchronization signal; generate a pulse width modulated wave based on the received pulse width modulated wave key data from the main control unit 401, and utilize the synchronization signal The pulse width modulated wave generated by the synchronous correction drives the motor to operate by the pulse width modulated wave after the synchronization correction. Referring to FIG. 5, FIG. 5 is a schematic structural diagram of another multi-machine frequency converter according to another embodiment of the present invention. As shown in FIG. 5, another multi-machine frequency converter provided by another embodiment of the present invention may include:

The main control unit 501, N9 rectifying units 502, N7 inverter units 503 connected in series through the communication port, and N8 inverter units 504 connected in series through the communication port. The N9 rectifier units, the N7 inverter units, and the N8 inverter units have a common DC bus 510.

The first communication port P1 of the main control unit 501 is connected to the second communication port P0 of the third inverter unit of the N7 inverter units 503 connected in series via the communication port, and the second communication of the main control unit 501 is The port P0 is connected to the first communication port P1 of the fourth inverter unit of the above-described N8 inverter units 504 connected in series via the communication port.

The N7 and the N8 are positive integers, and the third inverter unit is an inverter unit having one end edge position among the N7 inverter units connected in series via a communication port, wherein the fourth inverter unit is a communication unit. An inverter unit at one end edge position among the above-mentioned N8 inverter units connected in series.

In the example architecture of FIG. 5, one end edge position of the N7 inverter units 503 after the series connection is the third inverter unit of the remaining second communication port P0, and the other end edge position is the remaining first communication port P1. The fifth inverting unit is connected, and the remaining second communication port P0 of the third inverting unit is connected to the first communication port P1 of the main control unit 501. One end edge position of the N8 inverter units 504 after the series connection is the fourth inverter unit of the remaining first communication port P1, and the other end edge position is the sixth inverter unit of the remaining second communication port P0, and the fourth inverter The remaining first communication port P1 of the unit is connected to the second communication port P0 of the above-mentioned main control unit 501.

It can be seen that in the architecture shown in the example of FIG. 5, N9 rectifying units 502 are uncontrollable rectifying units that are not controlled by the main control unit 501. In the foregoing embodiment, in the architecture shown in FIG. 2-a to FIG. 2-g or the architecture shown in the example of 2-a to 2-e, some rectifying units are controllable rectifying units that can be controlled by the main control unit.

In the architecture shown in FIG. 5, at least one inverter unit can be deployed on each side of the main control unit 501, and the architecture shown in FIG. 4-a is in the architecture shown in FIG. At least two inverter units are deployed on one side of the main control unit 301.

The main control unit 501 can send a command word, a data word, and/or a status word to the third inverting unit and the second inverting unit through the first communication port P1 and the second communication port P0, respectively, and specifically send and forward. The process is similar to the previous part and will not be described here.

It can be seen that the present invention provides a multi-machine frequency converter capable of achieving parallel synchronous and/or asynchronous operation, which is obviously compared with the prior art method of implementing parallel functions by using multiple frequency converters. The implementation cost is reduced; the 485 bus communication mode in the conventional inverter multi-machine system is replaced by the serial communication mode between the main control unit and the inverter unit of the inverter, thereby facilitating the elimination of poor anti-interference of the transmission signal and the transmission distance. Short defects are conducive to the realization of ultra-long transmission with strong anti-interference ability, which is beneficial to improve the stability and reliability of the multi-machine operation scene of the inverter. The interconnection structure between the main control unit and the inverter unit is relatively simple, and the installation and wiring are relatively simple. It can be seen that this structure is advantageous for simplifying the wiring structure complexity of the multi-machine operation scene of the inverter. Moreover, since the inverter units are connected in series through the communication port, this is advantageous for improving the scalability of the multi-machine operation scenario of the inverter, and multiple inverter units can be connected in series through the communication port according to different scenarios to meet the corresponding requirements.

The following mainly takes the architecture shown in Figure 5 as an example, and introduces one of the synchronous signals generated in the multi-machine frequency converter. Some ways. The way in which synchronous signals are generated in multi-machine inverters under other architectures can be analogized. In some embodiments of the present invention, the main control unit 501 is configured to periodically send the first system reference clock signal generated by the first system reference clock; calculate each inverse of the N10 inverter units. And changing a time compensation value corresponding to the unit, and transmitting the time compensation value corresponding thereto to each of the N10 inverter units.

Each of the N10 inverter units is configured to perform time offset compensation on the local clock by using the received time compensation value after receiving the time compensation value corresponding thereto. Generating, according to the phase-locked loop, the clock signal generated by the first system reference ground clock sent by the currently received main control unit 501, for synchronizing the synchronization signal of the pulse width modulated wave generated by the inverter unit. The N10 inverter units include the N7 inverter units and the N8 inverter units.

The following mainly takes the architecture shown in Figure 5 as an example to give an example of some possible ways of operating control of a multi-machine inverter. The operation control mode of multi-machine inverters under other architectures can be analogized.

In some embodiments of the present invention, the main control unit 501 is configured to send, to each of the N10 inverter units, pulse width modulated wave key data corresponding thereto;

The N10 inverter units include the N7 inverter units and the N8 inverter units.

Each of the N10 inverter units is configured to generate a synchronization signal; generating a pulse width modulated wave based on the received pulse width modulated wave key data from the main control unit 501, and synchronizing with the synchronization signal The pulse width modulated wave generated by the correction is used to drive the motor operation by the pulse width modulated wave after the synchronization correction.

In the above embodiments, the descriptions of the various embodiments are different, and the details are not described in detail in an embodiment, and the related descriptions of other embodiments can be referred to.

A person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the device described above can refer to the corresponding process in the foregoing method embodiments, and details are not described herein again. In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the above units is only a logical function division, and may be additionally implemented in actual implementation. Sub-modes, such as multiple units or components, may be combined or integrated into another system, or some features may be omitted or not implemented. In addition, the mutual coupling or direct connection or communication connection shown or discussed may be an indirect coupling or communication connection through some port, device or unit, and may be electrical or otherwise. The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment. In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. The above-described integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium.

The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the embodiments are modified, or the equivalents of the technical features are replaced by the equivalents; and the modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

Rights request

1. A multi-machine frequency converter, comprising:

a main control unit, N1 execution units connected in series through a communication port, wherein the N1 execution unit common DC bus lines;

The first communication port of the main control unit is connected to the second communication port of the first execution unit of the N1 execution units, wherein the N1 execution units comprise a total of Nil rectification units and N12 inverses. a variable unit, the Nil is a positive integer, the N12 is a positive integer greater than 1, and the first execution unit is an execution unit at one end edge position among the N1 execution units connected in series through a communication port.

2. The multi-machine frequency converter according to claim 1, wherein

a second communication port of the main control unit is connected to a first communication port of a second execution unit of the N1 execution units, wherein the second execution unit is the N1 execution units connected in series through a communication port The execution unit at the other end edge position.

3. The multi-machine frequency converter according to claim 1, wherein

The multi-machine frequency converter further includes N2 execution units connected in series through a communication port, and the N2 execution units share the DC bus;

The multi-machine frequency converter according to any one of claims 1 to 3, characterized in that

The first execution unit is an inverter unit, and the first communication port of the first execution unit is connected to a second communication port of the fourth execution unit of the N1 execution units, wherein the fourth execution unit Is a rectifier unit or an inverter unit;

Or,

The first execution unit is a rectification unit, and the first communication port of the first execution unit is connected to a second communication port of the fifth execution unit of the N1 execution units, wherein the fifth execution unit is Rectifier unit or inverter unit.

The multi-machine frequency converter according to any one of claims 1 to 4, wherein the communication port is a fiber optic communication port or an Ethernet communication port or a level signal communication port or a differential communication interface.

6. A multi-machine frequency converter, comprising:

The N3 execution units and the N4 execution units share a common DC bus;

The first communication port of the main control unit is connected to a second communication port of a sixth execution unit of the N3 execution units connected in series through a communication port, and the second communication port of the main control unit communicates with the second communication port. a first communication port of the seventh execution unit of the N4 execution units connected in series;

7. The multi-machine frequency converter according to claim 6, wherein

The sixth execution unit is a rectification unit, and the first communication port of the sixth execution unit is connected to a second communication port connected to the ninth execution unit of the N3 execution units, wherein the ninth execution unit Is a rectifier unit or an inverter unit;

Or

The sixth execution unit is an inverter unit, and the first communication port of the sixth execution unit is connected to the second communication port of the eighth execution unit of the N3 execution units, wherein the eighth execution unit It is a rectifier unit or an inverter unit.

The multi-machine frequency converter according to any one of claims 6 to 7, characterized in that

The communication port is a fiber optic communication port or an Ethernet communication port or a level signal communication port or a differential communication interface.

9. A multi-machine frequency converter, comprising: a main control unit, N5 rectifying units, N6 inverter units connected in series through a communication port, wherein the N5 rectifying units and the N6 inverter units have a common DC bus;

10. The multi-machine frequency converter according to claim 9, wherein:

The second communication port of the main control unit is connected to the first communication port of the second inverter unit of the N6 inverter units, wherein the second inverter unit is the N6 connected in series through the communication port. An inverter unit in the inverter unit at the other end edge position.

The multi-machine frequency converter according to any one of claims 9 to 10, wherein the communication port is a fiber optic communication port or an Ethernet communication port or a level signal communication port or a differential communication interface.

12. A multi-machine frequency converter, comprising:

a main control unit, N9 rectifying units, N7 inverter units connected in series through a communication port, and N8 inverter units connected in series through a communication port; wherein, the N9 rectifying units, the N7 inverter units, and the N8 inverter units common to the DC bus;

13. The multi-machine frequency converter according to claim 12, wherein