WO2015176363A1 - 显示装置的驱动方法及用于该方法的显示装置的电路结构 - Google Patents

显示装置的驱动方法及用于该方法的显示装置的电路结构 Download PDF

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Publication number
WO2015176363A1
WO2015176363A1 PCT/CN2014/081431 CN2014081431W WO2015176363A1 WO 2015176363 A1 WO2015176363 A1 WO 2015176363A1 CN 2014081431 W CN2014081431 W CN 2014081431W WO 2015176363 A1 WO2015176363 A1 WO 2015176363A1
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Prior art keywords
signal
clock signal
voltage signal
charge sharing
sharing control
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Ceased
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PCT/CN2014/081431
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English (en)
French (fr)
Inventor
秦杰辉
陈伟
谭小平
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/371,736 priority Critical patent/US20160275898A1/en
Publication of WO2015176363A1 publication Critical patent/WO2015176363A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display devices, and more particularly to a method of driving a display device and a circuit structure of the display device for the method. Background technique
  • a display device such as a liquid crystal display (LCD)
  • LCD liquid crystal display
  • the liquid crystal display applies a voltage to the two electrodes to form an electric field in the liquid crystal layer that provides an image by controlling the transmission of light through the liquid crystal layer. If the electric field is applied to the liquid crystal layer in one direction for a long time, image degradation will occur. In order to prevent such degradation, in each frame, column or pixel, the polarity of the data voltage with respect to the common voltage is inverted.
  • the circuit of the liquid crystal display device includes: a gate driver for transmitting a strobe signal to the gate line to turn on or off a switching element of each pixel; a gray voltage generator for generating a plurality of gray voltages; and a data driver And for selecting a voltage corresponding to the image data from the gray voltage and applying the data voltage to the data line in the display signal line; and a signal controller for controlling the components.
  • a gate driver for transmitting a strobe signal to the gate line to turn on or off a switching element of each pixel
  • a gray voltage generator for generating a plurality of gray voltages
  • a data driver And for selecting a voltage corresponding to the image data from the gray voltage and applying the data voltage to the data line in the display signal line
  • a signal controller for controlling the components.
  • a pair of opposing gate drivers are placed on the left and right sides of the panel to apply a strobe signal.
  • the next strobe signal is transmitted by overlapping the next strobe signal with the previous strobe signal after a predetermined time elapses.
  • a parasitic capacitance is formed in the pixels.
  • the data voltage is slightly reduced due to the kickback voltage generated by the parasitic capacitance on the falling edge, and thereafter, due to the kickback voltage generated at the falling edge of the next strobe signal, the data The voltage is reduced again. This causes a voltage difference between the positive pixel voltage and the negative pixel voltage, resulting in flicker.
  • a kickback voltage proportional to the difference between the gate on voltage and the gate off voltage causes problems such as flickering of the display and an increase in power consumption.
  • FIG. 1 is a timing diagram of a conventional display device clock signal, taking a first pre-clock signal (CPV1 first charge sharing control signal (GCS1 and first clock signal (CK1) as an example. Include: first pre-clock Signal (CPV1 first charge sharing control signal (GCS1 and based on the first pre-clock signal (CPV1) and the first charge sharing control signal (GCS1) formed at high power A first clock signal (CK1) that oscillates between the voltage signal (VH) and the low voltage signal (VL).
  • first pre-clock Signal CPV1 first charge sharing control signal
  • CPV1 first charge sharing control signal CPV1 and based on the first pre-clock signal (CPV1) and the first charge sharing control signal (GCS1) formed at high power
  • a first clock signal (CK1) that oscillates between the voltage signal (VH) and the low voltage signal (VL).
  • the first pre-clock signal (CPV1) When the first pre-clock signal (CPV1) is at a high level, it is set to " ⁇ , when it is at a level of ⁇ , it is set to "0"; when the first charge-sharing control signal (GCS1) is at a high level, it is set to "1", which is ⁇ When the first pre-clock signal (CPV1) is set to "0" and before the rising edge, the first charge sharing control signal (GCS1) is set to ' ⁇ , and the first clock signal (CK1) is low.
  • the voltage signal (VL) is cut to the intermediate voltage signal (VF), and after the rising edge of the first pre-clock signal (CPV1), the first charge sharing control signal (GCS1) is set to "0” to make the first clock signal (CK1) Switching from the intermediate voltage signal (VF) to the high voltage signal (VH I, the first pre-clock signal (CPV1) is set to " ⁇ " and before the falling edge, the first charge sharing control signal (GCS1) is set to " ⁇ ", the first clock is set The signal (CK1) is switched from the high voltage signal (VH) to the intermediate voltage signal (VF), and after the falling edge of the first pre-clock signal (CPV1), the first charge sharing control signal (GCS1) is set to "0", The first clock signal (CK1) is cut by the intermediate voltage signal (VF) to the low voltage signal (the same as VL, the second pre-clocked signal (CPV2) is straight The first pre- ⁇ clock signal (CPVn) case and so on, the conduction time as needed, based on the timing obtained.
  • the charge sharing control signal triggers the intermediate voltage signal (VF) before the rising edge of the pre-clock signal (CPV), which is pre-charging, which can increase the reaction rate of the circuit, thus possibly generating a multi-channel clock signal (CKl)
  • CKl multi-channel clock signal
  • Another object of the present invention is to provide a circuit structure of a display device for the method, which improves the clock signal from a high voltage drop by controlling the on and off of a switch and a transistor in a circuit by a pre-clock signal and a charge sharing control signal.
  • the present invention provides a driving method of a display device, comprising: Step 100: providing a pre-clock signal (CPV) and a charge sharing control signal (GCS); Step 110, providing a pre-clocking signal (CPV) and a charge Sharing a control signal (GCS) to form a clock signal (CK) that oscillates between a high voltage signal (VH) and a low voltage signal (VL); Step 120, when the pre-clock signal (CPV) is high, "1" " , at the time of ⁇
  • Step 130 The pre-clock signal (CPV) is set in a range of “ ⁇ , charge sharing control
  • the signal (GCS) is set to ' ⁇ , the trigger clock signal (CK) rises from the low voltage signal (VL) to the intermediate voltage signal (VF), or the trigger clock signal (CK) drops from the high voltage signal (VH) to the intermediate voltage signal ( VF I
  • the step 130 further includes: in the interval where the pre-clock signal (CPV) is set to T, the charge sharing control signal (GCS) is set to "0", and the trigger clock signal (CK) is raised from the intermediate voltage signal (VF) to the high voltage.
  • the signal (VH), or the trigger clock signal (CK) drops from the intermediate voltage signal (VF) to the low voltage signal (VL X
  • the number of pre-clock signals (CPV) is several, the number of charge sharing control signals (GCS) is several, and the number of clock signals (CK) is several.
  • the invention also provides a driving method of a display device, comprising:
  • Step 100 providing a pre-clock signal (CPV) and a charge sharing control signal (GCS);
  • Step 110 providing a high voltage signal (VH) and a low voltage formed based on a pre-clock signal (CPV) and a charge sharing control signal (GCS) a clock signal (CK) oscillating between the signals (VL);
  • Step 120 setting "1" when the pre-clock signal (CPV) is high, and setting "0" when the level is ⁇ ; the charge sharing control signal (GCS) is set to " ⁇ " when high voltage is set to "0" when the voltage is ⁇ ;
  • Step 130 The charge sharing control is performed in the interval where the pre-clock signal (CPV) is set
  • the signal (GCS) is set to ' ⁇
  • the trigger clock signal (CK) rises from the low voltage signal (VL) to the intermediate voltage signal (VF)
  • the trigger clock signal (CK) drops from the high voltage signal (VH) to the intermediate voltage signal ( VF ) ;
  • the step 130 further includes: in the interval where the pre-clock signal (CPV) is set to T, the charge sharing control signal (GCS) is set to "0", and the trigger clock signal (CK) is raised from the intermediate voltage signal (VF) to the high voltage.
  • the signal ( VH ) or the trigger clock signal ( CK ) is dropped from the intermediate voltage signal ( VF ) to the low voltage signal ( VL ) ;
  • the number of pre-clock signals (CPV) is several, the number of charge sharing control signals (GCS) is several, and the number of clock signals (CK) is several.
  • the present invention also provides a circuit structure of a display device for the method, comprising: a high voltage signal (VH low voltage signal (VL intermediate voltage signal (VF pre-clock signal (CPV charge sharing control signal (GCS based pre-clock signal ( CPV) A clock signal formed between the high voltage signal (VH) and the low voltage signal (VL) formed by the charge sharing control signal (GCS) (CK first switch (SW1 second switch (SW2 third switch (SW3 ⁇ ) The first transistor (Tl and the second transistor ( ⁇ 2 X
  • the first transistor (T1) has a first gate (G1 first collector ( cl X and first emitter (el), and the second transistor (T2) has a second gate (G2 second collector) (c2), and a second emitter (e2);
  • the first switch (SW1) is electrically connected to the first emitter (el), and the other end is electrically connected to the clock signal (CK);
  • the second switch (SW2) is electrically connected to the second collector (c2), and the other end is electrically connected to the clock signal (CK);
  • one end of the third switch (SW3) is electrically connected to the intermediate voltage signal (VF)
  • the other end is electrically connected to the clock signal (CK);
  • the first gate (G1) is electrically connected to the pre-clock signal (CPV), and the second gate (G2) is electrically connected to the pre-clock signal ( CPV);
  • the first collector (cl) is electrically connected to a high voltage signal (VH), and the second emitter (e2) is electrically connected to a
  • pre-clock signal When the pre-clock signal (CPV) is at a high level, it is set to " ⁇ , when it is low level, it is set to "0"; when the charge sharing control signal (GCS) is at a high level, it is set to " ⁇ , when the level is ⁇ ", it is set to 0.
  • the pre-clock signal (CPV) controls the conduction of the high voltage signal (VH) and the f ⁇ voltage signal (VL);
  • the first transistor (T1) and the second transistor (?2) are both insulated gate bipolar transistors.
  • the number of pre-clock signals (CPV) is several
  • the number of charge sharing control signals (GCS) is several
  • the number of clock signals (CK) is several.
  • the present invention provides a driving method of a display device and a circuit configuration of the display device therefor, in which a charge sharing control signal (GCS) is set in a section in which a pre-clock signal is set to "1" ', the trigger clock signal (CK) rises from the low voltage signal (VL) to the intermediate voltage signal (VF), or the trigger clock signal (CK) drops from the high voltage signal (VH) to the intermediate voltage signal 3 ⁇ 4 VF by triggering the intermediate voltage
  • GCS charge sharing control signal
  • CK rises from the low voltage signal
  • VF intermediate voltage signal
  • VH intermediate voltage signal
  • the time point is controlled within the interval of the pre-clock signal set to " ⁇ ", which can effectively avoid the overlap between the individual clock signals and cause waveform confusion, thereby improving the clock signal from high voltage drop to low voltage or low voltage rise to high.
  • the kickback voltage generated at the voltage and reduces power consumption.
  • 1 is a timing diagram of a conventional display device clock signal
  • FIG. 2 is a flow chart of a driving method of a display device according to the present invention.
  • FIG. 3 is a timing chart of a clock signal of a display device of the present invention.
  • FIG. 4 is a schematic view showing the circuit structure of a display device of the present invention. detailed description
  • the present invention provides a driving method of a display device, including:
  • Step 100 providing a pre-clock signal (CPV) and a charge sharing control signal (GCS);
  • Step 110 providing a high voltage signal (VH) and a low voltage formed based on a pre-clock signal (CPV) and a charge sharing control signal (GCS) a clock signal (CK) oscillating between the signals (VL);
  • Step 120 setting "1" when the pre-clock signal (CPV) is high, and setting "0" when the level is ⁇ ; the charge sharing control signal (GCS) is set to " ⁇ " when it is high level.
  • CPV pre-clock signal
  • GCS charge sharing control signal
  • Step 130 The interval of the pre-clock signal (CPV) is set to T, the charge sharing control signal (GCS) is set to T, and the trigger clock signal (CK) is raised from the low voltage signal (VL) to the intermediate voltage signal (VF), or The trigger clock signal (CK) is dropped from the high voltage signal (VH) to the intermediate voltage signal (VF X
  • the step 130 further includes: in the interval where the pre-clock signal (CPV) is set to T, the charge sharing control signal (GCS) is set to "0", and the trigger clock signal (CK) is raised from the intermediate voltage signal (VF) to the high voltage.
  • the signal (VH), or the trigger clock signal (CK) drops from the intermediate voltage signal (VF) to the low voltage signal (VL X
  • the number of pre-clock signals (CPV) is several, the number of charge sharing control signals (GCS) is several, and the number of clock signals (CK) is several.
  • FIG. 3 is a timing diagram of a clock signal of a display device according to the present invention.
  • the first pre-clock signal (CPV1 first charge sharing control signal ( GCS1 and the first clock signal ( CK1 ) is taken as an example.
  • the first pre-clock signal is included.
  • (CPV1 first charge sharing control signal (GCS1 and based on the first pre-clock signal (CPV1) and the first charge sharing control signal (GCS1) oscillate between the high voltage signal (VH) and the low voltage signal (VL) a first clock signal (CK1).
  • the first pre-clock signal (CPV1) is at a high level, it is set to "?, when the level is ⁇ ", the first charge sharing control signal (GCS1) is high.
  • the first clock signal (CK1) is cut from the intermediate voltage signal (VF) to the low voltage signal (VL).
  • VL low voltage signal
  • FIG. 4 is a schematic diagram of a circuit structure of a display device according to the present invention.
  • the first pre-clock signal (CPV1 first charge sharing control signal (GCS1) and the first clock signal (CK1) are taken as an example.
  • the present invention also provides a circuit structure of a display device for the method, comprising: a high voltage signal (VH low voltage signal (VL intermediate voltage signal (VF first pre-clock signal (CPVl first charge sharing control signal (GCS1) a first clock signal that is oscillated between a high voltage signal (VH) and a low voltage signal (VL) based on the first pre-clock signal (CPV1) and the first charge sharing control signal (GCS1) (CK1 first switch (SW1) a second switch (SW2), a third switch (SW3), a first transistor (T1 and a second transistor (T2), the first transistor (T1) having a first gate (G1 first collector (cl), and a first emitter (el), the second transistor (T2) has a second gate (G2 second collector (c2 and second emitter (e2); the first switch (SW1) - terminal electrical Connected to the first emitter (el), the other end is electrically connected to the first clock signal (CK1); the second switch (SW2) is
  • the first pre-clocking signal CPV1 is passed through the first pre-clocking signal CPV1, the first open SW1 second switch (SW2 Three switches (SW3 first transistor (Tl and second transistor (T2) are turned on and off, select output high voltage signal (VH low voltage signal (VL) or middle
  • SW3 first transistor (Tl and second transistor (T2) are turned on and off, select output high voltage signal (VH low voltage signal (VL) or middle
  • One of the voltage signals (VF) is used as the first clock signal (CK1 I first clock signal (CK1) changes from a high voltage signal (VH) to a low voltage signal (VL), or from a low voltage signal (VL) to a high voltage
  • the first transistor (T1) and the second transistor ( ⁇ ) are both Insulated Gate Bipolar Transistors (IGBTs)
  • the second pre-clock signal (CPV2) up to the nth pre-clock signal (CPVn) and so on, the timing of its turn-on can be obtained according to the timing.
  • the present invention provides a driving method of a display device and a circuit structure of the display device used in the method.
  • the charge sharing control signal (GCS) is set to " ⁇ ".
  • the trigger clock signal (CK) rises from the ⁇ voltage signal (VL) to the intermediate voltage signal (VF), or the trigger clock signal (CK) drops from the high voltage signal (VH) to the intermediate voltage signal (VF).
  • the time point is controlled within the interval where the pre-clock signal is set to "1", which can effectively avoid the overlap between the individual clock signals and cause waveform confusion, thereby improving the clock signal from high voltage drop to low voltage or low voltage rise to The kickback voltage generated at high voltage and reduces power consumption.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示装置的驱动方法及用于该方法的显示装置的电路结构。该显示装置的驱动方法包括：提供预时钟信号（CPV）、电荷分享控制信号（GCS）（100）；基于预时钟信号（CPV）与电荷分享控制信号（GCS）形成的在高电压信号（VH）和低电压信号（VL）之间摇摆的时钟信号（CK）（110）；该预时钟信号（CPV）为高电平时置"1"，低电平时置"0"；所述电荷分享控制信号（GCS）为高电平时置"1"，低电平时置"0"（120）；该预时钟信号（CPV）置"1"的区间内，电荷分享控制信号（GCS）置"1"，触发时钟信号（CK）由低电压信号（VL）上升到中间电压信号（VF），或触发时钟信号（CK）由高电压信号（VH）下降到中间电压信号（VF）（130）。

Description

显示装置的驱动方法及用于该方法的显示装置的电踣结构 技术领域
本发明涉及显示装置领域，尤其涉及一种显示装置的驱动方法及用于 该方法的显示装置的电路结构。 背景技术
显示装置，例如液晶显示器 ( LCD ) ,包括分别具有像素电极和公共电 极的两个显示板以及放置在显示板之间并具有介电各向异性的液晶层。 液 晶显示器将电压施加到两个电极使液晶层中形成电场，该液晶层通过控制 穿过液晶层的光传输来提供图像。 如果长时间将电场在一个方向上施加到 液晶层，将会产生图像降级。 为了防止这样的降级，在每一帧、 列或像素， 周期姻每关于公共电压的数据电压的极性反转。
液晶显示装置的电路包括：栅极驱动器，用于将选通信号传输至栅极 线，以开启或关闭各个像素的开关元件；灰度电压发生器，用于生成多个 灰度电压；数据驱动器，用于从灰度电压中选取对应于图像数据的电压， 并将数据电压施加给显示信号线中的数据线；以及信号控制器，用于控制 这些部件。 以与用于形成像素的开关元件相同的工艺形成栅极驱动器，随 后将栅极驱动器集成在面板中。 通过减半来减小数据线的数量，而不是使 栅极线的数量加倍，从而实现了相同的分辨率并降低了成本。 此外，在面 板的左侧和右侧设置一对相对的栅极驱动器，以施加选通信号。 为了在一 帧期间施加选通信号，在施加前一选通信号之后，通过在经过预定时间之 后将下一选通信号与前一选通信号重叠来传输下一选通信号。
当信号线重叠时，在像素中形成寄生电容。 在施加数据电压之后，由 于由寄生电容在下降沿所生成的反冲电压 ( kickback voltage ) ,数据电压轻 微地减小，此后，由于在下一选通信号的下降沿所生成的反冲电压，数据 电压再次减小。 这样就造成正像素电压和负像素电压之间的电压差，从而 导致闪烁。在液晶显示器中，与选通开（ gate on voltage )电压和选通关（ gate off voltage )电压之间的差成比例的反冲电压引起了足以使显示出现闪烁以 及功耗变大等问题。
因此，可以通过触发中间电压，来改善反冲电压产生的相关问题。 请 参阅图 1 ,为现有的显示装置时钟信号的时序图，以第一预时钟信号 ( CPV1 第一电荷分享控制信号（ GCS1 及第一时钟信号（ CK1 )为例。 包括：第一预时钟信号 ( CPV1 第一电荷分享控制信号（ GCS1 及基于 第一预时钟信号（ CPV1 )与第一电荷分享控制信号 ( GCS1 )形成的在高电 压信号（ VH )和低电压信号 ( VL )之间摇摆的第一时钟信号 ( CK1 )。 所 述第一预时钟信号 ( CPV1 )为高电平时置 "Γ ,为 ί氏电平时置 "0"；所述 第一电荷分享控制信号 ( GCS1 )为高电平时置 "1" ,为 ί氏电平时置 "0"； 所述第一预时钟信号（ CPV1 )置 "0" 且上升沿之前，第一电荷分享控制 信号（ GCS1 )置 ' Τ ,将第一时钟信号（ CK1 )由低电压信号 ( VL )切至 中间电压信号（ VF ) ,并在第一预时钟信号 ( CPV1 )上升沿之后，将第一 电荷分享控制信号（ GCS1 )置 "0" ,使第一时钟信号 ( CK1 )由中间电压 信号 ( VF )切至高电压信号 ( VH I 所述第一预时钟信号 ( CPV1 )置 "Γ 且下降沿之前，第一电荷分享控制信号（ GCS1 )置 " Γ ,将第一时钟信号 ( CK1 )由高电压信号（ VH )切至中间电压信号（ VF ) ,并在第一预时钟 信号（ CPV1 )下降沿之后，将第一电荷分享控制信号 ( GCS1 )置 "0" ,使 第一时钟信号（ CK1 )由中间电压信号（ VF )切至低电压信号（ VL 同 理，第二预时钟信号 ( CPV2 )直至第 η预时钟信号 ( CPVn )的情况依此类 推，其导通的时机可以根据需要，依据时序得到。
现有技术中电荷分享控制信号（ GCS )触发中间电压信号（ VF )在预 时钟信号（ CPV )上升沿之前，此为预充电，可以提高电路的反应速率， 如此可能产生多路时钟信号（ CKl〜CKn )之间的波形有重叠。 发明内容
本发明的目的在于提供一种显示装置的驱动方法，可以有效避免各个 时钟信号之间有重叠而致使出现波形混乱的现象，进而改善时钟信号从高 电压下降到低电压或者低电压上升到高电压时产生的反冲电压，并且降低 功耗。
本发明的另一目的在于提供一种用于该方法的显示装置的电路结构， 通过预时钟信号与电荷分享控制信号控制电路中开关与晶体管的导通与关 闭，来改善时钟信号从高电压下降到低电压或者低电压上升到高电压时， 产生的反冲电压的相关问题。
为实现上述目的，本发明提供一种显示装置的驱动方法，包括： 步骤 100、 提供预时钟信号（ CPV )及电荷分享控制信号 ( GCS )； 步骤 110、 提供基于预时钟信号（ CPV )与电荷分享控制信号（ GCS ) 形成的在高电压信号（ VH )与低电压信号（ VL )之间摇摆的时钟信号（ CK )； 步骤 120、 所述预时钟信号 ( CPV )为高电平时置 "1" ,为 ί氏电平时置
"0"；所述电荷分享控制信号（ GCS )为高电压时置 "Γ ,为 ί氏电压时置
"0"；
步骤 130、 所述预时钟信号（ CPV )置 "Γ 的区间内，电荷分享控制 信号（ GCS )置 'Τ ,触发时钟信号 ( CK )由低电压信号 ( VL )上升到中 间电压信号（ VF ) ,或者触发时钟信号 ( CK )由高电压信号 ( VH )下降到 中间电压信号 ( VF I
所述步骤 130还包括：所述预时钟信号（ CPV )置 T 的区间内，电 荷分享控制信号（ GCS )置 "0" ,触发时钟信号（ CK )由中间电压信号 ( VF ) 上升到高电压信号（ VH ) ,或者触发时钟信号 ( CK )由中间电压信号 ( VF ) 下降到低电压信号 ( VL X
所述预时钟信号 ( CPV )为数个，所述电荷分享控制信号 ( GCS )为数 个，所述时钟信号 ( CK )为数个。
本发明还提供一种显示装置的驱动方法，包括：
步骤 100、 提供预时钟信号（ CPV )及电荷分享控制信号 ( GCS )； 步骤 110、 提供基于预时钟信号（ CPV )与电荷分享控制信号（ GCS ) 形成的在高电压信号（ VH )与低电压信号（ VL )之间摇摆的时钟信号（ CK )； 步骤 120、 所述预时钟信号 ( CPV )为高电平时置 "1" ,为 ί氏电平时置 "0"；所述电荷分享控制信号（ GCS )为高电压时置 "Γ ,为 ί氏电压时置 "0"；
步骤 130、 所述预时钟信号（ CPV )置 Τ 的区间内，电荷分享控制 信号（ GCS )置 'Τ ,触发时钟信号 ( CK )由低电压信号 ( VL )上升到中 间电压信号（ VF ) ,或者触发时钟信号 ( CK )由高电压信号 ( VH )下降到 中间电压信号（VF ) ;
所述步骤 130还包括：所述预时钟信号（ CPV )置 T 的区间内，电 荷分享控制信号（ GCS )置 "0" ,触发时钟信号（ CK )由中间电压信号 ( VF ) 上升到高电压信号（ VH ) ,或者触发时钟信号 ( CK )由中间电压信号 ( VF ) 下降到低电压信号 ( VL ) ;
所述预时钟信号 ( CPV )为数个，所述电荷分享控制信号 ( GCS )为数 个，所述时钟信号 ( CK )为数个。
本发明还提供一种用于该方法的显示装置的电路结构，包括：高电压 信号（ VH 低电压信号（ VL 中间电压信号 ( VF 预时钟信号 ( CPV 电荷分享控制信号 ( GCS 基于预时钟信号 ( CPV )与电荷分享控制信号 ( GCS )形成的在高电压信号（ VH )与低电压信号（ VL )之间摇摆的时钟 信号 ( CK 第一开关（ SW1 第二开关（ SW2 第三开关（ SW3 λ 第 —晶体管 ( Tl 及第二晶体管 ( Τ2 X
所述第一晶体管 ( T1 )具有第一栅极 ( Gl 第一集电极（ cl X 及第 一发射极（ el ) ,所述第二晶体管 ( T2 )具有第二栅极（ G2 第二集电极 ( c2 )、 及第二发射极 (e2);所述第一开关 ( SW1 )—端电性连接于第一发 射极（ el ) ,另一端电性连接于时钟信号 (CK);所述第二开关（ SW2 )— 端电性连接于第二集电极（ c2 ) ,另一端电性连接于时钟信号 (CK);所述 第三开关 ( SW3 )一端电性连接于中间电压信号（ VF ) ,另一端电性连接于 时钟信号 (CK);所述第一栅极 ( G1 )电性连接于预时钟信号（ CPV ) ,所 述第二栅极 ( G2 )电性连接于预时钟信号（ CPV )；所述第一集电极 (cl ) 电性连接于高电压信号（ VH ) ,所述第二发射极 ( e2 )电性连接于低电压信 号（VL);
所述预时钟信号（ CPV )为高电平时置 "Γ ,为低电平时置 "0"；所 述电荷分享控制信号 ( GCS )为高电平时置 "Γ ,为 ί氏电平时置 "0"； 所述预时钟信号 ( CPV )控制高电压信号 ( VH )与 f氐电压信号（ VL ) 的导通；
所述电荷分享控制信号（ GCS )置 "0" 期间，第一开关 ( SW1 )及第 二开关 ( SW2 )导通；所述电荷分享控制信号（ GCS )置 Τ 期间，第三 开关（ SW3 )导通。
通过所述预时钟信号 ( CPV )与所述电荷分享控制信号（ GCS )控制第 —开关 ( SW1 第二开关 ( SW2 第三开关 ( SW3 第一晶体管 ( T1 )、 及第二晶体管（ T2 )的导通与关闭，选择输出高电压信号（ VH )、 低电压 信号（ VL )或者中间电压信号 ( VF )中的一个作为时钟信号（ CK I
所述第一晶体管 ( T1 )与第二晶体管（ Τ2 )均为绝缘栅双极型晶体管。 所述预时钟信号 ( CPV )为数个，所述电荷分享控制信号 ( GCS )为数 个，所述时钟信号 ( CK )为数个。
本发明的有益效果：本发明提供一种显示装置的驱动方法及用于该方 法的显示装置的电路结构，在预时钟信号置 "1" 的区间内，电荷分享控制 信号（ GCS )置 'Τ' ,触发时钟信号 ( CK )由低电压信号 ( VL )上升到中 间电压信号（ VF ) ,或者触发时钟信号 ( CK )由高电压信号 ( VH )下降到 中间电压信 ¾ VF 通过将中间电压触发的时间点控制在预时钟信号置 "Γ 的区间内，可以有效避免各个时钟信号之间有重叠而致使出现波形混乱的 现象，进而改善时钟信号从高电压下降到低电压或者低电压上升到高电压 时产生的反冲电压，并且降低功耗。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本 发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发 明加以限制。 附图说明 下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明 的技术方案及其它有益效果显而易见。
附图中，
图 1为现有的显示装置时钟信号的时序图；
图 2为本发明显示装置的驱动方法的流程图；
图 3为本发明的显示装置时钟信号的时序图；
图 4为本发明的显示装置的电路结构示意图。 具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图 2 ,本发明提供一种显示装置的驱动方法，包括：
步骤 100、 提供预时钟信号（ CPV )及电荷分享控制信号 ( GCS )； 步骤 110、 提供基于预时钟信号（ CPV )与电荷分享控制信号（ GCS ) 形成的在高电压信号（ VH )和低电压信号（ VL )之间摇摆的时钟信号（ CK )； 步骤 120、 所述预时钟信号 ( CPV )为高电平时置 "1" ,为 ί氏电平时置 "0"；所述电荷分享控制信号（ GCS )为高电平时置 "Γ ,为 ί氏电平时置 步骤 130、 所述预时钟信号（ CPV )置 T 的区间内，电荷分享控制 信号（ GCS )置 T ,触发时钟信号 ( CK )由低电压信号 ( VL )上升到中 间电压信号（ VF ) ,或者触发时钟信号 ( CK )由高电压信号 ( VH )下降到 中间电压信号 ( VF X
所述步骤 130还包括：所述预时钟信号（ CPV )置 T 的区间内，电 荷分享控制信号（ GCS )置 "0" ,触发时钟信号（ CK )由中间电压信号（ VF ) 上升到高电压信号（ VH ) ,或者触发时钟信号 ( CK )由中间电压信号 ( VF ) 下降到低电压信号 ( VL X
所述预时钟信号 ( CPV )为数个，所述电荷分享控制信号 ( GCS )为数 个，所述时钟信号 ( CK )为数个。
请参阅图 3 ,为本发明的显示装置时钟信号时序图，以第一预时钟信号 ( CPV1 第一电荷分享控制信号（ GCS1 及第一时钟信号（ CK1 )为例。 包括：第一预时钟信号 ( CPV1 第一电荷分享控制信号（ GCS1 及基于 第一预时钟信号 ( CPV1 )与第一电荷分享控制信号 ( GCS1 )形成的在高电 压信号（ VH )和低电压信号 ( VL )之间摇摆的第一时钟信号 ( CK1 )。 所 述第一预时钟信号 ( CPV1 )为高电平时置 "Γ ,为 ί氏电平时置 "0"；所述 第一电荷分享控制信号 ( GCS1 )为高电平时置 "1" ,为 ί氏电平时置 "0"； 所述第一预时钟信号（ CPVl )置 "Γ 的区间内，先将第一电荷分享控制 信号（ GCS1 )置 ' T ,使第一时钟信号（ CK1 )由低电压信号 ( VL )切至 中间电压信号（ VF ) ,接着将第一电荷分享控制信号（ GCS1 )置 "0" ,使 第一时钟信号（ CK1 )由中间电压信号 ( VF )切至高电压信号（ VH )；再 将第一电荷分享控制信号（ GCS1 )置 "Γ ,使第一时钟信号 ( CK1 )由高 电压信号 ( VH )切至中间电压信号（ VF ) ,再接着将第一电荷分享控制信 号（ GCS1 )置 "0" ,使第一时钟信号 ( CK1 )由中间电压信号 ( VF )切至 低电压信号 ( VL )。 通过将中间电压信号 ( VF )触发的时间点控制在第一 预时钟信号（ CPV1 )置"1"的区间内，可以有效避免各个时钟信号（ CK1、…、 CKn )之间有重叠而致使出现波形混乱的现象。
请参阅图 4并结合图 3 ,图 4为本发明的显示装置的电路结构示意图， 以第一预时钟信号（ CPVl 第一电荷分享控制信号（ GCS1 )、及第一时钟 信号（ CK1 )为例。 本发明还提供一种用于该方法的显示装置的电路结构， 包括：高电压信号 ( VH 低电压信号 ( VL 中间电压信号 ( VF 第一 预时钟信号 ( CPVl 第一电荷分享控制信号 ( GCS1 基于第一预时钟信 号（ CPV1 )与第一电荷分享控制信号 ( GCS1 )形成的在高电压信号 ( VH ) 与低电压信号 ( VL )之间摇摆的第一时钟信号 ( CK1 第一开关（ SW1 第二开关（ SW2 )、第三开关（ SW3 )、第一晶体管（ Tl 及第二晶体管（ T2 \ 所述第一晶体管 ( T1 )具有第一栅极（ Gl 第一集电极 ( cl )、 及第一发 射极（ el ) ,所述第二晶体管 ( T2 )具有第二栅极 ( G2 第二集电极 ( c2 及第二发射极（ e2 )；所述第一开关（ SW1 )—端电性连接于第一发射极（ el ) , 另一端电性连接于第一时钟信号 ( CK1 )；所述第二开关（ SW2 )—端电性 连接于第二集电极 ( c2 ) ,另一端电性连接于第一时钟信号 ( CK1 )；所述第 三开关 ( SW3 )一端电性连接于中间电压信号（ VF ) ,另一端电性连接于第 一时钟信号（ CK1 )；所述第一栅极（ G1 )电性连接于第一预时钟信号 ( CPV1 ) ,所述第二栅极（ G2 )电性连接于第一预时钟信号 ( CPV1 )；所 述第一集电极 ( cl )电性连接于高电压信号（ VH ) ,所述第二发射极 ( e2 ) 电性连接于低电压信号 ( VL ) ;所述第一预时钟信号 ( CPV1 )控制高电压 信号 ( VH )与氐电压信号 ( VL )的导通；所述第一电荷分享控制信号（ GCS1 ) 置 "0" 期间，第一开关 ( SW1 )及第二开关 ( SW2 )导通；所述第一电荷 分享控制信号（ GCS1 )置 "Γ 期间，第三开关（ SW3 )导通。 通过第一 预时钟信 CPV1 第一电荷分享控制信 GCS1腔制第一开 SW1 第二开关（ SW2 第三开关（ SW3 第一晶体管（ Tl 及第二晶体管（ T2 ) 的导通与关闭，选择输出高电压信号 ( VH 低电压信号（ VL )或者中间 电压信号 ( VF )中的一个作为第一时钟信号（ CK1 I第一时钟信号 ( CK1 ) 从高电压信号 ( VH )向低电压信号 ( VL )变化，或者从低电压信号 ( VL ) 向高电压信号 ( VH )变化时，经过中间电压信号（ VF I
所述第一晶体管 ( T1 )与第二晶体管（ Ί )均为绝缘栅双极型晶体管 ( Insulated Gate Bipolar Transistor , IGBT \
同理，第二预时钟信号 ( CPV2 )直至第 η预时钟信号（ CPVn )的情况 依此类推，其导通的时机可以根据需要，依据时序得到。
综上所述，本发明提供一种显示装置的驱动方法及用于该方法的显示 装置的电路结构，在预时钟信号置 "1"的区间内，电荷分享控制信号（ GCS ) 置 "Γ ,触发时钟信号（ CK )由氐电压信号（ VL )上升到中间电压信号（ VF ) , 或者触发时钟信号（ CK )由高电压信号 ( VH )下降到中间电压信号 ( VF )。 通过将中间电压触发的时间点控制在预时钟信号置 "1" 的区间内，可以有 效避免各个时钟信号之间有重叠而致使出现波形混乱的现象，进而改善时 钟信号从高电压下降到低电压或者低电压上升到高电压时产生的反冲电 压，并且降低功耗。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形 都应属于本发明权利要求的保护范围

Claims

杈 利 要 求
1、 一种显示装置的驱动方法，包括：
步骤 100、 提供预时钟信号及电荷分享控制信号；
步骤 110、提供基于预时钟信号与电荷分享控制信号形成的在高电压信 号与低电压信号之间摇摆的时钟信号；
步骤 120、 所述预时钟信号为高电平时置 "1" ,为 ί氏电平时置 "0"；所 述电荷分享控制信号为高电平时置 "1" ,为 ί氏电平时置 "0"；
步骤 130、所述预时钟信号置 "1"的区间内，电荷分享控制信号置 "1" , 触发时钟信号由低电压信号上升到中间电压信号，或者触发时钟信号由高 电压信号下降到中间电压信号。
2、 如权利要求 1所述的显示装置的驱动方法，其中，所述步骤 130还 包括：所述预时钟信号置 "1" 的区间内，电荷分享控制信号置 "0" ,触发 时钟信号由中间电压信号上升到高电压信号，或者触发时钟信号由中间电 压信号下降到低电压信号。
3、 如权利要求 1所述的显示装置的驱动方法，其中，所述预时钟信号 为数个，所述电荷分享控制信号为数个，所述时钟信号为数个。
4、 一种显示装置的驱动方法，包括： 步骤 100、 提供预时钟信号及电荷分享控制信号；
步骤 110、提供基于预时钟信号与电荷分享控制信号形成的在高电压信 号与低电压信号之间摇摆的时钟信号；
步骤 120、 所述预时钟信号为高电平时置 "1" ,为 ί氏电平时置 "0"；所 述电荷分享控制信号为高电平时置 "1" ,为 ί氏电平时置 "0"；
步骤 130、所述预时钟信号置 "1"的区间内，电荷分享控制信号置 "1" , 触发时钟信号由低电压信号上升到中间电压信号，或者触发时钟信号由高 电压信号下降到中间电压信号；
其中，所述步骤 130还包括：所述预时钟信号置 "1" 的区间内，电荷 分享控制信号置 "0" ,触发时钟信号由中间电压信号上升到高电压信号， 或者触发时钟信号由中间电压信号下降到 ί氐电压信号；
其中，所述预时钟信号为数个，所述电荷分享控制信号为数个，所述 时钟信号为数个。
5、 一种显示装置的电路结构，包括：高电压信号、 ί氐电压信号、 中间 电压信号、 预时钟信号、 电荷分享控制信号、 基于预时钟信号与电荷分享 控制信号形成的在高电压信号与低电压信号之间摇摆的时钟信号、 第一开 关、 第二开关、 第三开关、 第一晶体管、 及第二晶体管； 所述第一晶体管具有第一栅极、 第一集电极、 及第一发射极，所述第 二晶体管具有第二栅极、 第二集电极、 及第二发射极；
所述第一开关一端电性连接于第一发射极，另一端电性连接于时钟信 号；所述第二开关一端电性连接于第二集电极，另一端电性连接于时钟信 号；所述第三开关一端电性连接于中间电压信号，另一端电性连接于时钟 信号；所述第一栅极电性连接于预时钟信号，所述第二栅极电性连接于预 时钟信号；所述第一集电极电性连接于高电压信号，所述第二发射极电性 连接于低电压信号。
6、 如权利要求 5所述的显示装置的电路结构，其中，所述预时钟信号 为高电平时置 " ,为 ί氏电平时置 "0"；所述电荷分享控制信号为高电平 时置 "1" ,为 ί氏电平时置 "0"。
7、 如权利要求 6所述的显示装置的电路结构，其中，所述电荷分享控 制信号置 "0" 期间，第一开关及第二开关导通；所述电荷分享控制信号置
"1" 期间，第三开关导通。
8、 如权利要求 5所述的显示装置的电路结构，其中，所述预时钟信号 控制高电压信号与低电压信号的导通。
9、 如权利要求 8所述的显示装置的电路结构，其中，所述预时钟信号 与所述电荷分享控制信号控制第一开关、 第二开关、 第三开关、 第一晶体 管、 及第二晶体管的导通与关闭，选择输出高电压信号、 低电压信号或者 中间电压信号中的一个作为时钟信号。
10、 如权利要求 5所述的显示装置的电路结构，其中，所述第一晶体 管与第二晶体管均为绝缘栅双极型晶体管。
11、 如权利要求 5所述的显示装置的电路结构，其中，所述预时钟信 号为数个，所述电荷分享控制信号为数个，所述时钟信号为数个。
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