WO2015165202A1 - 一种基于汉明码存取数据的方法及集成随机存取存储器 - Google Patents

一种基于汉明码存取数据的方法及集成随机存取存储器 Download PDF

Info

Publication number
WO2015165202A1
WO2015165202A1 PCT/CN2014/087226 CN2014087226W WO2015165202A1 WO 2015165202 A1 WO2015165202 A1 WO 2015165202A1 CN 2014087226 W CN2014087226 W CN 2014087226W WO 2015165202 A1 WO2015165202 A1 WO 2015165202A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
read
write
fetched
ecc
Prior art date
Application number
PCT/CN2014/087226
Other languages
English (en)
French (fr)
Inventor
郭彬
Original Assignee
深圳市中兴微电子技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市中兴微电子技术有限公司 filed Critical 深圳市中兴微电子技术有限公司
Priority to EP14890817.1A priority Critical patent/EP3125251A4/en
Publication of WO2015165202A1 publication Critical patent/WO2015165202A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

Definitions

  • the present invention relates to the field of data storage technologies, and in particular, to a method for writing and reading data based on a Hamming code and an integrated random access memory (IRAM) implementing the above method.
  • IRAM integrated random access memory
  • ECC Error checking and correction
  • IRAM In computer systems, maintaining the correctness and consistency of data is an important basis for the normal operation of a computer. In the process of storing or transmitting data, there is a possibility of distorting data due to interference, device failure, and the like. Therefore, some measures must be taken to detect and correct the distortion data in time. As a commonly used large-capacity storage device, IRAM can only be used for storing large-capacity data. It cannot guarantee the accuracy of data written or read data, and cannot be corrected when data is wrong. wrong.
  • the embodiments of the present invention are expected to provide a method for writing and reading data based on a Hamming code and an IRAM for implementing the method, which solves the problem that the IRAM cannot guarantee the data written or read by the IRAM.
  • An embodiment of the present invention provides a method for writing data based on a Hamming code.
  • the method includes: parsing a received read/write instruction, acquiring a read/write state of the read/write instruction, and determining that the read/write state is a write state. And performing error checking and correcting ECC encoding on the to-be-stored data carried by the read/write instruction to generate a corresponding first check code, and storing the to-be-stored data and the first check code.
  • the read/write instructions are format converted before the received read/write instructions are parsed.
  • the embodiment of the present invention further provides a method for reading data based on a Hamming code, the method comprising: parsing a received read/write instruction, acquiring a read/write state of the read/write instruction; determining that the read/write status is When the state is read, the data to be fetched is obtained according to the read/write instruction, and the data to be fetched is detected by using an error check and correction ECC code to obtain a detection result, and the data to be fetched is directly sent according to the detection result, or The data to be fetched is sent after error correction, or an alarm is triggered.
  • the read/write instructions are format converted before the received read/write instructions are parsed.
  • the first check code corresponding to the data to be fetched and the data to be fetched is obtained according to the read/write command, and the data to be fetched is ECC encoded to generate a second check code; And detecting, by using the ECC code, the to-be-obtained data to obtain a detection result, and directly sending the to-be-obtained data according to the detection result, or sending the to-be-obtained data to perform error correction, and then sending, Or triggering the alarm includes: performing an XOR operation on the first check code and the second check code to generate an XOR result; directly sending the to-be-obtained data according to the XOR result, or Send data after error correction, or trigger an alarm.
  • the sending the data to be directly sent according to the detection result, or sending the error to be sent after the error correction is performed, or triggering the alarm is specifically: Case 1: when the XOR result is full If there is a single bit of 1, the data to be fetched is directly sent; Case 2: when the number of 0s and 1s in the XOR result is the same, the data to be fetched is error-corrected and then sent; In case 1 and case 2, an alarm is triggered.
  • An embodiment of the present invention further provides an integrated random access memory (IRAM) based on Hamming code write data, the IRAM comprising: a first control module, a first ECC module, and a first storage module; wherein the first control module And configured to parse the received read/write instruction to obtain a read/write status of the read/write instruction; the first ECC module is configured to determine that the read/write status is a write status, and the read/write instruction is Carrying the stored data to perform error checking and correcting the ECC code to generate a corresponding first check code; the first storage module is configured to store the to-be-stored data and the first check code.
  • IRAM integrated random access memory
  • the first control module is further configured to perform format conversion on the read/write instruction.
  • the first ECC module includes: a first determining sub-module, a first encoding sub-module; wherein the first determining sub-module is configured to determine whether the to-be-stored data has invalid data, If the data to be stored has invalid data, the storage data corresponding to the operation address carried by the read/write instruction is acquired, and valid data to be stored is generated according to the stored data; the first coding submodule is configured to The data to be stored is ECC encoded to generate a first check code.
  • the first control module, the first ECC module, the first storage module, the first determining submodule, and the first encoding submodule may use a central processing unit when performing processing (CPU, Central Processing Unit), digital signal processor (DSP, Digital Singnal Processor) or Programmable Array Array (FPGA).
  • CPU Central Processing Unit
  • DSP Digital Singnal Processor
  • FPGA Programmable Array Array
  • the embodiment of the present invention further provides an integrated random access memory (IRAM) based on reading data of a Hamming code, the IRAM comprising: a second control module, a second ECC module, and a second storage module; wherein the second control module And configured to parse the received read/write instruction to obtain a read/write state of the read/write instruction; the second ECC module is configured to determine that the read/write status is a read status, according to the read/write instruction Acquiring the data to be fetched, detecting the to-be-obtained data by using an error check and correcting the ECC code to obtain a detection result, and directly transmitting the to-be-obtained data according to the detection result, or sending the to-be-obtained data for error correction and then sending Or triggering an alarm; the second storage module is configured to store the to-be-take data and the first check code corresponding to the to-be-obtained data.
  • IRAM integrated random access memory
  • the second control module is further configured to perform format conversion on the read/write instruction.
  • the second ECC module includes: a second coding sub-module and a verification sub-module; wherein the second coding sub-module is configured to acquire the to-be-take data and the location according to the read/write instruction Determining a first check code corresponding to the data, and performing ECC encoding on the data to be generated to generate a second check code; the check submodule configured to: use the first check code and the The second check code performs an exclusive OR operation to generate an XOR result, and the data to be fetched is directly sent according to the XOR result, or the data to be fetched is error-corrected, and then an alarm is triggered.
  • the check sub-module is specifically configured as the case 1: when the result of the XOR is all 0s or 1 of a single bit exists, the data to be fetched is directly sent; Case 2: when the difference is If the number of 0s and 1s is the same, the data to be fetched is sent after error correction; if not, the alarm is triggered.
  • the second control module, the second ECC module, the second storage module, the first The second coding sub-module and the verification sub-module may use a central processing unit (CPU), a digital signal processor (DSP, Digital Singnal Processor) or a programmable logic array (FPGA, Field-) when performing processing. Programmable Gate Array) implementation.
  • CPU central processing unit
  • DSP digital signal processor
  • FPGA programmable logic array
  • the embodiment of the present invention further provides a method for writing and reading data based on Hamming code and an IRAM for implementing the method.
  • the method for writing data includes: parsing the received read/write instruction, and acquiring the The read/write state of the read/write instruction; determining that the read/write state is a write state, performing ECC encoding on the to-be-stored data carried by the read/write instruction to generate a corresponding first check code, and storing the to-be-stored data And storing the data with the first check code.
  • the method for reading data includes: determining that the read/write state is a read state, acquiring data to be fetched according to the read/write instruction, and using the ECC code to wait for the data to be fetched. The data is detected to obtain a detection result, and the to-be-obtained data is directly sent according to the detection result, or the to-be-obtained data is error-corrected, and then an alarm is triggered.
  • the embodiment of the present invention solves the problem that the IRAM cannot guarantee the accuracy of the data written or the read data, and the error correction cannot be performed when the data is in error. Meanwhile, the method of the embodiment of the present invention adopts the Hamming code. Overcoming the shortcomings of the traditional parity check that only the parity of the data block can be detected, the check code is tedious and cannot be corrected, and the single-bit error correction of the IRAM data is completed by the ECC check method, and the function of double-bit error detection is completed.
  • the IRAM itself has the ability to identify data errors and issue an alarm when the data is read incorrectly, thereby improving the correctness and reliability of the IRAM stored data.
  • FIG. 1 is a schematic flowchart of a method for writing data based on a Hamming code according to an embodiment of the present invention
  • FIG. 2 is a schematic flowchart of a method for reading data based on a Hamming code according to an embodiment of the present invention
  • FIG. 3 is a schematic flowchart of a method for accessing data based on a Hamming code according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of an IRAM based on Hamming code writing data according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of an IRAM based on Hamming code reading data according to an embodiment of the present invention. schematic diagram;
  • FIG. 6 is a schematic structural diagram of an IRAM based on Hamming code access data according to an embodiment of the present invention.
  • the received read/write instruction is parsed to obtain the read/write status of the read/write instruction; and when the read/write status is the write status, the to-be-stored data carried by the read/write instruction is determined.
  • ECC encoding to generate a corresponding first check code, and storing the to-be-stored data and the first check code; determining that the read/write state is a read state, acquiring, according to the read/write instruction The data is taken, and the data to be fetched is detected by using the ECC code to obtain a detection result, and the data to be fetched is directly sent according to the detection result, or the data to be fetched is error-corrected, and then an alarm is triggered.
  • FIG. 1 is a schematic flowchart of a method for writing data based on a Hamming code according to an embodiment of the present invention. As shown in the figure, the method includes the following steps:
  • Step 101 Parsing the received read/write instruction, and acquiring the read/write status of the read/write instruction;
  • the IRAM parses the received read/write instruction, acquires the read/write status of the read/write instruction, and reads and writes the read/write instruction when the received read/write instruction is a write command.
  • Write state at this time, write data to the IRAM; here, specifically write data to the static random access memory (SRAM) in the IRAM; here the data written to the IRAM is called For data to be stored, it can also be called data to be written.
  • SRAM static random access memory
  • the IRAM formats the read and write instructions before parsing the received read and write instructions; here, the IRAM will receive advanced scalability based on the Advanced Microcontroller Bus Architecture (AMBA) protocol.
  • AZA Advanced Microcontroller Bus Architecture
  • Interface (AXI, Advanced eXtensible Interface) command is converted to the SRAM interface pair used inside IRAM
  • the specific conversion process is to convert the five-channel AXI protocol into a single-channel SRAM protocol; here, the specific conversion process is the same as the prior art conversion method, and will not be described here.
  • the converted SRAM commands include: read and write enable wen, indicating read and write enable, high level for read operation, low level for write operation; chip select enable cen, indicating chip select enable, low level for slice
  • the selection is valid;
  • the address addr indicates the address corresponding to the read/write operation;
  • the data data indicates the write data corresponding to the write operation or the data read by the read operation;
  • the effective digit byten indicates the effective number of bits in the write data, and the active level is valid. .
  • Step 102 Determine that the read/write state is a write state, perform ECC encoding on the to-be-stored data carried in the read/write command to generate a corresponding first check code, and store the to-be-stored data with the first Check code for storage;
  • the wen received by the IRAM is a high level, and the write operation is currently performed.
  • the IRAM performs ECC encoding on the data to be stored carried by the read/write instruction; wherein the ECC code is encoded by using the Hamming code.
  • the IRAM determines whether the data to be stored has invalid data before the ECC encoding is performed; and if the data to be stored has invalid data, the storage data corresponding to the operation address carried by the read/write instruction is acquired, according to the storage.
  • the data generates valid data to be stored, and the valid data to be stored is ECC-encoded to generate a corresponding first check code; here, when the data to be stored has invalid data, the current data to be stored is invalid pending data. It needs to be combined with the stored data saved in the corresponding operation address in IRAM to generate valid data to be saved.
  • the data to be stored is all valid, the data to be stored is directly ECC encoded.
  • the IRAM When the IRAM obtains the data to be stored, it determines whether the data to be stored has invalid data according to the value of the byten carried by the read/write instruction. When the byten is all 0, it indicates that all the data to be stored are valid, and there is no invalid data; when the byten is not all 0, indicating that there is invalid data in the current data to be stored, and a "read and write operation" is required, that is, the operation address carried according to the read/write instruction is
  • the SRAM obtains the stored data stored in the IRAM itself, and updates the data corresponding to the data bit with the byten 0 in the stored data to the stored data, and generates valid data to be stored; at this time, the generated valid is to be generated.
  • the stored data is ECC encoded to generate a first check code, and the valid pending data and the generated first check code are stored in the SRAM.
  • FIG. 2 is a schematic flowchart of a method for reading data based on a Hamming code according to an embodiment of the present invention. As shown in the figure, the method includes the following steps:
  • Step 201 Parsing the received read/write instruction, and acquiring the read/write status of the read/write instruction;
  • the IRAM parses the received read/write instruction to obtain the read/write status of the read/write instruction, and when the received read/write instruction is a read command, the read/write status of the read/write instruction
  • data is read from the IRAM; here, the data is specifically read from the SRAM in the IRAM, and the data read from the IRAM is referred to as data to be fetched, which may also be referred to as data to be read. .
  • the IRAM performs format conversion on the read and write instructions before parsing the received read/write instructions; the specific conversion process is consistent with step 101; here, the difference from step 101 is that the level values of wen are different, step 101 The wen in the middle is low, indicating that the write operation is performed. The wen in this step is high, indicating that the read operation is performed.
  • Step 202 Determine, when the read/write state is the read state, obtain the data to be fetched according to the read/write command, and use the ECC code to detect the to-be-obtained data to obtain a detection result, and the to-be-taked according to the detection result
  • the data is directly sent, or the data to be fetched is error-corrected, sent, or triggered.
  • the IRAM further acquires the first check code corresponding to the data to be fetched and the data to be fetched according to the read/write instruction, and performs ECC encoding on the data to be fetched to generate a second check code; and generates a second check code.
  • the XOR operation is performed by performing an exclusive OR operation on the first check code and the second check code, and the data to be fetched is directly sent according to the XOR result, or the data to be fetched is error-corrected, and then triggered, or triggered.
  • the XOR result includes the following cases: all 0s, single bits 1, 0 and 1 are the same and other cases except the above; correspondingly, the data to be fetched is directly sent according to the XOR result, Or the data to be fetched is sent after error correction, or the alarm is triggered as follows:
  • an alarm is triggered to remind the current read/write instruction that the data reading from the IRAM fails.
  • the data to be fetched in step 202 can be read into the IRAM through step 101, and read when the read command is received, and the first check code corresponding to the data to be fetched read at this time is read. That is, the first check code generated in step 102.
  • the embodiments of the present invention respectively provide a method for writing and reading data based on a Hamming code.
  • the two methods can be simultaneously applied to an IRAM to implement a method.
  • a method for reading data based on a Hamming code the method comprising the steps of:
  • Step 301 Parse the received read/write instruction, and obtain the read/write status of the read/write instruction.
  • the IRAM when the IRAM receives the read/write instruction, it parses the received read/write instruction, and the received read/write instruction can be a write command or a read command, and when the received read/write command is a write command, read The read/write state of the write command is the write state, and the data is written to the IRAM; when the read/write command received is the read command, the read/write state of the read/write instruction is the read state, and the data is read from the IRAM.
  • the IRAM performs different operations according to the read/write status of the read/write instruction. Specifically, when the read/write status of the read/write instruction is the write status, step 302a is performed; when the read/write status of the read/write instruction is the read status, Step 302b is performed.
  • Step 302a in the same step 102, performing ECC editing on the to-be-stored data carried by the read/write instruction. Generating a corresponding check code, and storing the to-be-stored data and the first check code;
  • step 302b in the same step 202, the data to be fetched is obtained according to the read/write instruction, and the data to be fetched is detected by using the ECC code, and the data to be fetched is directly sent according to the detection result, or the data to be fetched is directly corrected. Send, or trigger an alarm after the error.
  • the read/write instruction may be buffered according to the read/write status; wherein the read/write instruction is cached in a first-in first-out manner;
  • the write state is first cached, and a certain buffer time is reserved between the IRAM receiving the read command and the processing read/write command, for the IRAM to process the read/write command, and the clock for the data to be stored and the data to be fetched, the check, etc.
  • the processing of the cycle avoids the problem of partial read and write commands being lost due to the excessive speed of receiving and reading instructions.
  • the IRAM When the IRAM receives the read/write instruction, it automatically generates a data transfer start message indicating that the read/write instruction is started to indicate that the IRAM is currently processing the read/write instruction, and when the IRAM stores the stored data, or sends the data to be fetched, After the alarm is triggered, a data transmission end message that handshakes with the data transmission start information is generated, indicating that the current IRAM has processed the current read/write instruction and can start processing the new read/write instruction.
  • the check code generated by the data to be stored after the ECC encoding is the first check code; when the read/write state is the read state, the read/write command reads the read command.
  • the data to be stored at this time is already in the read state because it is already stored in the IRAM.
  • the data to be saved at this time is the data to be fetched.
  • the read and write status of read and write commands is determined by wen and cen.
  • cen invalid IRAM does not have read/write capability; when cen is valid, the current read is determined according to the level of wen.
  • Write state where high level is a read operation and low level is a write operation.
  • an embodiment of the present invention provides an IRAM 400, where the IRAM 400 includes: a first control module 401, a first ECC module 402, and a first storage module 403;
  • the first control module 401 is configured to parse the received read and write instructions to obtain the read The read and write status of the write instruction.
  • the first control module 401 is further configured to perform format conversion on the read and write instructions.
  • the first ECC module 402 is configured to: when determining that the read/write state is a write state, performing ECC encoding on the to-be-stored data carried by the read/write instruction to generate a corresponding check code;
  • the first ECC module 402 includes: a first judging sub-module 421, and a first encoding sub-module 422.
  • the first judging sub-module 421 is configured to determine whether the in-store data has invalid data, and the data to be stored exists. In the case of invalid data, the stored data corresponding to the operation address carried by the read/write instruction is acquired, and valid data to be stored is generated according to the stored data; the first encoding sub-module 422 is configured to perform ECC on the to-be-stored data. Encode to generate a first check code.
  • the first storage module 403 is configured to store the to-be-stored data and the first check code.
  • the embodiment of the present invention further provides an IRAM 500 for reading data based on a Hamming code, the IRAM 500 comprising: a second control module 501, a second ECC module 502, and a second storage module 503;
  • the second control module 501 is configured to parse the received read/write command and obtain the read/write status of the read/write command.
  • the second control module 501 is further configured to perform format conversion on the read and write instructions.
  • the second ECC module 502 is configured to: when the read/write state is determined to be a read state, acquire data to be fetched according to the read/write command, and use the ECC code to detect the data to be fetched, according to the detection result, The data to be fetched is directly sent, or the data to be fetched is error-corrected, and then sent, or an alarm is triggered;
  • the second ECC module 502 includes: a second encoding sub-module 521, a syndrome module 522;
  • the second encoding sub-module 521 is configured to acquire the first check code corresponding to the to-be-obtained data and the to-be-obtained data according to the read/write instruction, and perform ECC encoding on the to-be-obtained data to generate a second school Code check
  • a verification submodule 522 configured to perform an exclusive OR of the first check code and the second check code The operation generates an XOR result, and the data to be fetched is directly sent according to the XOR result, or the data to be fetched is error-corrected, and then an alarm is triggered.
  • the verification sub-module 522 is specifically configured to be the first case: when the result of the exclusive OR is all 0s or 1 of a single bit, the data to be fetched is directly sent; Case 2: when the result of the exclusive OR is If the number of 0s and 1s is the same, the data to be fetched is error-corrected and sent; if not, the alarm is triggered.
  • the second storage module 503 is configured to store the to-be-take data and the first check code corresponding to the to-be-obtained data.
  • the second ECC module further includes an error correction sub-module 523 configured to perform error correction on the data to be retrieved that needs to be corrected by the verification sub-module 522, and send the error-corrected data to be sent out.
  • the embodiment of the present invention further provides an IRAM 600 for accessing data based on a Hamming code.
  • the IRAM 600 includes: a control module 601, an ECC module 602, and a storage module 603;
  • the control module 601 is configured to parse the received read/write command and obtain the read/write status of the read/write command.
  • the control module 601 is further configured to perform format conversion on the read and write instructions.
  • the ECC module 602 is configured to: when the read/write state is a write state, perform ECC encoding on the to-be-stored data carried by the read/write instruction to generate a corresponding first check code; when the read/write state is a read state Obtaining the data to be fetched according to the read/write instruction, detecting the data to be fetched by using the ECC code, and directly sending the data to be fetched according to the detection result, or sending the data to be fetched after error correction Or triggering an alarm; wherein, for the same data, it is called data to be written in the write state, and is called data to be fetched in the read state.
  • the ECC module 602 includes: an encoding submodule 621 and a syndrome module 622;
  • the encoding sub-module 621 is configured to: when the read/write state is a write state, perform ECC encoding on the to-be-stored data carried by the read/write instruction to generate a corresponding first check code; when the read/write state is When the state is read, the data to be fetched and the corresponding first check code are obtained according to the read/write instruction, and the data to be fetched is ECC encoded to generate a second check code;
  • the verification sub-module 622 is configured to perform an exclusive OR operation on the first check code corresponding to the data to be fetched and the second check code to generate an XOR result, and directly send the data to be fetched according to the XOR result, or Send data after error correction, or trigger an alarm.
  • the syndrome module 622 is specifically configured to be the first case: when the result of the XOR is all 0s or 1 of a single bit, the data to be fetched is directly sent; Case 2: when the XOR is In the result, the number of 0s and 1s is the same, and the data to be fetched is error-corrected and sent; if not, the first one and the second case trigger an alarm.
  • the storage module 603 is configured to store the first check code corresponding to the data to be fetched and the data to be fetched.
  • the ECC module 602 further includes a determining sub-module 624, and an error correcting sub-module 623 configured to perform error correction on the data to be sent sent by the syndrome module 622, and send the error-corrected data to be sent out. .
  • the ECC module 602 further includes a determining sub-module 624 configured to determine, when the read/write state is in a write state, whether data stored in the read/write instruction has invalid data; and the data to be stored exists. In the case of invalid data, the stored data corresponding to the operation address carried by the read/write instruction is acquired, and valid data to be stored is generated according to the stored data.
  • the ECC module 602 further includes: a buffer sub-module 625 configured to perform ECC encoding on the to-be-stored data carried by the read/write instruction to generate a corresponding first check code, or according to the read/write instruction. Before the data to be fetched is acquired, the read/write instruction is cached according to the read/write state.
  • the device or system device provided by the present invention can be used as a separate system, or a logic unit for performing different functions in an existing terminal such as a personal computer (PC).
  • PC personal computer
  • the control module 601, the ECC module 602, and the storage module 603 can be a central processing unit (CPU), a digital signal processor (DSP), or a programmable gate array (FPGA, Field) located in the PC. Programmable Gate Array) implementation.
  • the embodiment of the present invention solves the problem that the IRAM cannot guarantee the accuracy of the data written or the read data, and the error correction cannot be performed when the data is in error. Meanwhile, the method of the embodiment of the present invention adopts the Hamming code. Overcoming the shortcomings of the traditional parity check that only the parity of the data block can be detected, the check code is tedious and cannot be corrected, and the single-bit error correction of the IRAM data is completed by the ECC check method, and the function of double-bit error detection is completed.
  • the IRAM itself has the ability to identify data errors and issue an alarm when the data is read incorrectly, thereby improving the correctness and reliability of the IRAM stored data.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

本发明提供了一种基于汉明码写入、读取数据的方法及采用该方法的IRAM，其中，该写入数据的方法包括：对接收到的读写指令进行解析，获取所述读写指令的读写状态确定所述读写状态为写状态时，将所述读写指令携带的待存数据进行错误检查与纠正ECC编码以生成对应的第一校验码，并将所述待存数据与所述第一校验码进行存储。

Description

一种基于汉明码存取数据的方法及集成随机存取存储器 技术领域
本发明涉及数据存储技术领域，尤其涉及一种基于汉明码写入、读取数据的方法及实现上述方法的集成随机存取存储器(IRAM，Integrate Random Access Memory)。
背景技术
本申请发明人在实现本申请实施例技术方案的过程中，至少发现相关技术中存在如下技术问题：
错误检查与纠错(ECC，Error Checking and Correcting)校验是在传统奇偶校验基础上发展而来的，主要利用数据块的行列奇偶校验信息生成ECC码，检出给定数据块是否失真并具有对该数据块自动一位纠错的能力。它克服了传统奇偶校验只能检测出数据块奇数位出错、校验码冗长，不能纠错的局限性。
在计算机系统中，保持数据的正确性和一致性是计算机正常工作的一个重要基础。而数据在进行储存或者传输的过程中，由于干扰、器件故障等原因就存在着使数据失真的可能性。因此必须采取一些措施及时检出及纠正失真的数据。而目前的IRAM作为一种常用的大容量储存设备，只能用于进行大容量数据的存储，无法保证其写入的数据或读取的数据的准确率，并且在数据发生错误时无法进行纠错。
发明内容
有鉴于此，本发明实施例期望提供一种基于汉明码写入、读取数据的方法及实现该方法的IRAM，解决了IRAM无法保证其写入的数据或读取 的数据的准确率，并且在数据发生错误时无法进行纠错的问题。
本发明的技术方案是这样实现的：
本发明实施例提供一种基于汉明码写入数据的方法所述方法包括：对接收到的读写指令进行解析，获取所述读写指令的读写状态；确定所述读写状态为写状态时，将所述读写指令携带的待存数据进行错误检查与纠正ECC编码以生成对应的第一校验码，并将所述待存数据与所述第一校验码进行存储。
上述方案中，对接收到的读写指令进行解析之前，将所述读写指令进行格式转换。
上述方案中，在将所述读写指令携带的待存数据进行ECC编码之前，判断所述待存数据是否存在无效数据；在所述待存数据存在无效数据的情况下，获取所述读写指令携带的操作地址对应的存储数据，根据所述存储数据生成有效的待存数据。
本发明实施例还提供一种基于汉明码读取数据的方法，所述方法包括：对接收到的读写指令进行解析，获取所述读写指令的读写状态；确定所述读写状态为读状态时，根据所述读写指令获取待取数据，采用错误检查与纠正ECC编码对所述待取数据进行检测得到检测结果，根据所述检测结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警。
上述方案中，对接收到的读写指令进行解析之前，将所述读写指令进行格式转换。
上述方案中，根据所述读写指令获取所述待取数据及所述待取数据对应的第一校验码，并将所述待取数据进行ECC编码以生成第二校验码；相应的，所述采用ECC编码对所述待取数据进行检测得到检测结果，根据所述检测结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、 或触发告警包括：将所述第一校验码与所述第二校验码进行异或操作生成异或结果；根据所述异或结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警。
上述方案中，所述根据所述检测结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警具体为：情况一：当所述异或结果为全0或存在单比特的1，则将所述待取数据直接发送；情况二：当所述异或结果中0与1的个数相同，则将所述待取数据进行纠错后发送；若非所述情况一和所述情况二，则触发告警。
本发明实施例还提供一种基于汉明码写入数据的集成随机存取存储器IRAM，所述IRAM包括：第一控制模块、第一ECC模块以及第一存储模块；其中，所述第一控制模块，配置为对接收到的读写指令进行解析，获取所述读写指令的读写状态；所述第一ECC模块，配置为确定所述读写状态为写状态时，将所述读写指令携带的待存数据进行错误检查与纠正ECC编码以生成对应的第一校验码；所述第一存储模块，配置为存储所述待存数据和所述第一校验码。
上述方案中，所述第一控制模块还配置为将所述读写指令进行格式转换。
上述方案中，所述第一ECC模块包括：第一判断子模块、第一编码子模块；其中，所述第一判断子模块，配置为判断所述待存数据是否存在无效数据，在所述待存数据存在无效数据的情况下，获取所述读写指令携带的操作地址对应的存储数据，根据所述存储数据生成有效的待存数据；所述第一编码子模块，配置为将所述待存数据进行ECC编码以生成第一校验码。
所述第一控制模块、所述第一ECC模块、所述第一存储模块、所述第一判断子模块、所述第一编码子模块在执行处理时，可以采用中央处理器 (CPU，Central Processing Unit)、数字信号处理器(DSP，Digital Singnal Processor)或可编程逻辑阵列(FPGA，Field－Programmable Gate Array)实现。
本发明实施例还提供一种基于汉明码读取数据的集成随机存取存储器IRAM，所述IRAM包括：第二控制模块、第二ECC模块以及第二存储模块；其中，所述第二控制模块，配置为对接收到的读写指令进行解析，获取所述读写指令的读写状态；所述第二ECC模块，配置为确定所述读写状态为读状态时，根据所述读写指令获取待取数据，采用错误检查与纠正ECC编码对所述待取数据进行检测得到检测结果，根据所述检测结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警；所述第二存储模块，配置为存储所述待取数据和所述待取数据对应的第一校验码。
上述方案中，所述第二控制模块还配置为将所述读写指令进行格式转换。
上述方案中，所述第二ECC模块，包括：第二编码子模块、校验子模块；其中，所述第二编码子模块，配置为根据所述读写指令获取所述待取数据及所述待取数据对应的第一校验码，并将所述待取数据进行ECC编码以生成第二校验码；所述校验子模块，配置为将所述第一校验码与所述第二校验码进行异或操作生成异或结果，根据所述异或结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警。
上述方案中，所述校验子模块具体配置为情况一：当所述异或的结果为全0或存在单比特的1，则将所述待取数据直接发送；情况二：当所述异或的结果中0与1的个数相同，则将所述待取数据进行纠错后发送；若非所述情况一和所述情况二，则触发告警。
所述第二控制模块、所述第二ECC模块、所述第二存储模块、所述第 二编码子模块、所述校验子模块在执行处理时，可以采用中央处理器(CPU，Central Processing Unit)、数字信号处理器(DSP，Digital Singnal Processor)或可编程逻辑阵列(FPGA，Field－Programmable Gate Array)实现。
本发明实施例还提供了一种基于汉明码写入、读取数据的方法及实现该方法的IRAM，对于该写入数据的方法，包括：对接收到的读写指令进行解析，获取所述读写指令的读写状态；确定所述读写状态为写状态时，将所述读写指令携带的待存数据进行ECC编码以生成对应的第一校验码，并将所述待存数据与所述第一校验码进行存储；对于读取数据的方法，包括：确定所述读写状态为读状态时，根据所述读写指令获取待取数据，采用ECC编码对所述待取数据进行检测得到检测结果，根据所述检测结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警。
采用本发明实施例，解决了IRAM无法保证其写入的数据或读取的数据的准确率，并且在数据发生错误时无法进行纠错的问题；同时，本发明实施例的方法采用了汉明码，克服了传统奇偶校验只能检出数据块奇偶位的错误，校验码冗长且无法纠错的缺点，通过ECC校验的方式完成对IRAM数据单比特错误纠正，双比特错误检测的功能，使得IRAM本身具有识别数据错误的能力，并在数据的读取出错时发出告警，从而提高了IRAM存储数据的正确性与可靠性。
附图说明
图1为本发明实施例提供的基于汉明码写入数据的方法的流程示意图；
图2为本发明实施例提供的基于汉明码读取数据的方法的流程示意图；
图3为本发明实施例提供的基于汉明码存取数据的方法的流程示意图；
图4为本发明实施例提供的一种基于汉明码写入数据的IRAM的结构示意图；
图5为本发明实施例提供的一种基于汉明码读取数据的IRAM的结构 示意图；
图6为本发明实施例提供的一种基于汉明码存取数据的IRAM的结构示意图。
具体实施方式
在本发明实施例中，对接收到的读写指令进行解析，获取所述读写指令的读写状态；确定所述读写状态为写状态时，将所述读写指令携带的待存数据进行ECC编码以生成对应的第一校验码，并将所述待存数据与所述第一校验码进行存储；确定所述读写状态为读状态时，根据所述读写指令获取待取数据，采用ECC编码对所述待取数据进行检测得到检测结果，根据所述检测结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警。
下面通过附图及具体实施例对本发明再做进一步的详细说明。
图1为本发明实施例提供的基于汉明码写入数据的方法的流程示意图，如图所示，该方法包括以下几个步骤：
步骤101，对接收到的读写指令进行解析，获取所述读写指令的读写状态；
具体的，IRAM在接收到读写指令时，对接收到的读写指令进行解析，获取读写指令的读写状态，当接收到的读写指令为写命令时，读写指令的读写状态为写状态，此时，向IRAM中写入数据；这里，具体的向IRAM中的静态随机存取存储器(SRAM，Static Random Access Memory)中写入数据；这里将向IRAM中写入的数据称为待存数据，也可称为待写入数据。
IRAM在对接收到的读写指令进行解析之前，将所述读写指令进行格式转换；这里，IRAM将接收到的基于高级微控制器总线结构(AMBA，Advanced Microcontroller Bus Architecture)协议的高级可扩展接口(AXI，Advanced eXtensible Interface)命令转换为IRAM内部采用的SRAM接口对 应的读写命令，具体的转换过程为五通道的AXI协议转换为单通道的SRAM协议；这里，具体的转换过程与现有技术的转换方法相同，在此不再赘述。
转换后的SRAM命令包括：读写使能wen，表示读写使能，高电平为读操作，低电平为写操作；片选使能cen，表示片选使能，低电平表示片选有效；地址addr，表示读写操作对应的地址；数据data，表示写操作对应的写数据或者读操作读出的数据；有效位数byten，表示写数据中有效的位数，低电平有效。
步骤102，确定所述读写状态为写状态时，将所述读写指令携带的待存数据进行ECC编码以生成对应的第一校验码，并将所述待存数据与所述第一校验码进行存储；
这里，IRAM接收到的wen为高电平，当前执行写入操作，此时，IRAM将读写指令携带的待存数据进行ECC编码；其中，ECC编码采用汉明码进行编码。
IRAM在将待存数据进行ECC编码之前，判断待存数据是否存在无效数据；在待存数据存在无效数据的情况下，获取所述读写指令携带的操作地址对应的存储数据，根据所述存储数据生成有效的待存数据，将有效的待存数据进行ECC编码以生成对应的第一校验码；这里，当待存数据存在无效数据时，当前的待存数据为无效的待存数据，需经过与IRAM中对应的操作地址保存的存储数据结合，以生成有效的待存数据。这里，当待存数据全部有效时，直接将待存数据进行ECC编码。
IRAM获取待存数据时，根据读写指令携带的byten的值判断待存数据是否存在无效数据，当byten为全0时，表明当前待存数据全部有效，不存在无效的数据；当byten不全为0时，表明当前待存数据存在无效的数据，需要进行“读再写操作”，也就是说，先根据读写指令携带的操作地址从 SRAM中获取保存在IRAM中本身保存的存储数据，将待存数据中与byten为0的数据位对应的数据更新到存储数据中，生成有效的待存数据；此时，将生成的有效的待存数据进行ECC编码生成第一校验码，并将有效的待存数据与生成的第一校验码存储在SRAM中。
图2为本发明实施例提供的基于汉明码读取数据的方法的流程示意图，如图所示，该方法包括以下几个步骤：
步骤201，对接收到的读写指令进行解析，获取所述读写指令的读写状态；
具体的，IRAM在接收到读写指令时，对接收到的读写指令进行解析，获取读写指令的读写状态，当收到的读写指令为读命令时，读写指令的读写状态为读状态，此时，从IRAM读取数据；这里，具体的从IRAM中的SRAM中读取数据，并将从IRAM中读取的数据称为待取数据，也可称为待读取数据。
IRAM在对接收到的读写指令进行解析之前，将所述读写指令进行格式转换；具体的转换过程同步骤101一致；这里，与步骤101的区别在于，wen的电平值不同，步骤101中的wen为低电平，表示执行写入操作，本步骤中的wen为高电平，表示执行读取操作。
步骤202，确定所述读写状态为读状态时，根据所述读写指令获取待取数据，采用ECC编码对所述待取数据进行检测得到检测结果，根据所述检测结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警；
这里，IRAM还根据所述读写指令获取待取数据及待取数据对应的第一校验码，并将所述待取数据进行ECC编码生成第二校验码；在生成第二校验码之后，将第一校验码与第二校验码进行异或操作生成异或结果，根据异或结果将待取数据直接发送、或将待取数据进行纠错后发送，或触发告 警；其中，异或结果包括以下多种情况：全0、单比特1、0与1的个数相同以及除上述情况以外的其它情况；对应的，根据异或结果将待取数据直接发送、或将待取数据进行纠错后发送，或触发告警具体为：
情况一：当所述异或的结果为全0或存在单比特的1，则将所述待取数据直接发送；
情况二：当所述异或结果中0与1的个数相同，则将所述待取数据进行纠错后发送；
若非所述情况一和情况二，则触发告警，以提醒当前读写指令从IRAM读出数据失败。
在实际应用中，步骤202中的待取数据可通过步骤101、写入IRAM中，在接收到读指令时，进行读取，而此时读取的待取数据所对应的第一校验码即为在步骤102中生成的第一校验码。
如图1、图2所示，本发明实施例分别提供了一种基于汉明码写入、读取数据的方法，在实际应用中，这两种方法可同时应用于一个IRAM中，实现一种基于汉明码读取数据的方法，该方法包括以下步骤：
步骤301：对接收到的读写指令进行解析，获取所述读写指令的读写状态；
这里，IRAM接收到读写指令时，对接收到的读写指令进行解析，接收到的读写指令可为写命令，也可为读命令，当收到的读写指令为写命令时，读写指令的读写状态为写状态，向IRAM中写入数据；当收到的读写指令为读命令时，读写指令的读写状态为读状态，从IRAM中读取数据。
IRAM根据接收到读写指令的读写状态不同执行的操作不同，具体的，当读写指令的读写状态为写状态时，执行步骤302a；当读写指令的读写状态为读状态时，执行步骤302b。
步骤302a，同步骤102，将所述读写指令携带的待存数据进行ECC编 码生成对应的校验码，并将所述待存数据与所述第一校验码进行存储；
步骤302b，同步骤202，根据所述读写指令获取待取数据，采用ECC编码对待取数据进行检测，根据所述检测结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警。
IRAM在步骤101、步骤201以及步骤301中获取读写指令的读写状态之后，可根据读写状态缓存所述读写指令；其中，以先入先出的方式缓存读写指令；这里，将读写状态先进行缓存，在IRAM接收到读取指令与处理读写指令之间留一定的缓冲时间，用于IRAM处理读写指令，进行待存数据和待取数据的编码、校验等占用时钟周期的处理，避免了因接收读写指令的速度过快而导致部分读写指令丢失的问题。
当IRAM接收到读写指令时，会自动生成表示开始处理读写指令的数据传输开始信息，以表明IRAM当前正在处理读写指令，当IRAM将带存数据存储后、或将待取数据发出、或触发告警后，生成与数据传输开始信息进行握手的数据传输结束信息，表明当前IRAM对当前的读写指令已处理结束，可以开始新的读写指令的处理。
在本发明实施例中，在读取指令状态为写状态时，待存数据经过ECC编码后生成的校验码为第一校验码；当读写状态为读状态的读写指令读取该待存数据时，此时的待存数据由于已存储在IRAM中，处于被读取的状态，相应的，此时的待存数据为待取数据。
在实际应用中，读写命令的读写状态由wen与cen共同确定，在cen无效的情况下，IRAM不具备读写能力；在cen有效的情况下，根据wen的电平值确定当前的读写状态，其中，高电平为读操作，低电平为写操作。
为实现上述方法，本发明实施例提供一种IRAM400，该IRAM400包括：第一控制模块401、第一ECC模块402以及第一存储模块403；其中，
第一控制模块401，配置为对接收到的读写指令进行解析，获取所述读 写指令的读写状态。
第一控制模块401，还配置为将所述读写指令进行格式转换。
第一ECC模块402，配置为确定所述读写状态为写状态时，将所述读写指令携带的待存数据进行ECC编码生成对应的校验码；
第一ECC模块402包括：第一判断子模块421、第一编码子模块422；其中，第一判断子模块421，配置为判断所述待存数据是否存在无效数据，在所述待存数据存在无效数据的情况下，获取所述读写指令携带的操作地址对应的存储数据，根据所述存储数据生成有效的待存数据；第一编码子模块422，配置为将所述待存数据进行ECC编码以生成第一校验码。
第一存储模块403，配置为存储待存数据和第一校验码。
本发明实施例还提供一种基于汉明码读取数据的IRAM500，该IRAM500包括：第二控制模块501、第二ECC模块502以及第二存储模块503；
第二控制模块501，配置为对接收到的读写指令进行解析，获取所述读写指令的读写状态。
第二控制模块501，还配置为将所述读写指令进行格式转换。
第二ECC模块502，配置为确定所述读写状态为读状态时，根据所述读写指令获取待取数据，采用ECC编码对所述待取数据进行检测，根据所述检测结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警；
第二ECC模块502包括：第二编码子模块521、校验子模块522；
第二编码子模块521，配置为根据所述读写指令获取所述待取数据和所述待取数据对应的第一校验码，并将所述待取数据进行ECC编码以生成第二校验码；
校验子模块522，配置为将所述第一校验码与所述第二校验码进行异或 操作生成异或结果，根据所述异或结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警。
校验子模块522，具体配置为情况一：当所述异或的结果为全0或存在单比特的1，则将所述待取数据直接发送；情况二：当所述异或的结果中0与1的个数相同，则将所述待取数据进行纠错后发送；若非所述情况一和所述情况二，则触发告警。
第二存储模块503，配置为存储所述待取数据和所述待取数据对应的第一校验码。
在实际应用中，第二ECC模块还包括纠错子模块523，配置为对校验子模块522发送的需要纠错的待取数据进行纠错，并将纠错后的待取数据发送出去。
本发明实施例还提供一种基于汉明码存取数据的IRAM600，如图6所示，所述IRAM600包括：控制模块601、ECC模块602以及存储模块603；
控制模块601，配置为对接收到的读写指令进行解析，获取所述读写指令的读写状态。
控制模块601，还配置为将所述读写指令进行格式转换。
ECC模块602，配置为当所述读写状态为写状态时，将所述读写指令携带的待存数据进行ECC编码生成对应的第一校验码；当所述读写状态为读状态时，根据所述读写指令获取待取数据，采用ECC编码对所述待取数据进行检测，根据所述检测结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警；其中，对于同样的数据，在写状态时称为待写数据，在读状态时称为待取数据。
ECC模块602包括：编码子模块621、校验子模块622；
编码子模块621，配置为当所述读写状态为写状态时，将所述读写指令携带的待存数据进行ECC编码生成对应的第一校验码；当所述读写状态为 读状态时，根据所述读写指令获取待取数据及其对应的第一校验码，并将待取数据进行ECC编码生成第二校验码；
校验子模块622，配置为将待取数据对应的第一校验码与第二校验码进行异或操作生成异或结果，根据异或结果将待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警。
这里，校验子模块622，具体配置为情况一：当所述异或的结果为全0或存在单比特的1，则将所述待取数据直接发送；情况二：当所述异或的结果中0与1的个数相同，将所述待取数据进行纠错后发送；若非上情况一和情况二，则触发告警。
存储模块603，配置为存储待取数据和待取数据对应的第一校验码。
如图6所示，ECC模块602还包括判断子模块624；纠错子模块623，配置为对校验子模块622发送的待取数据进行纠错，并将纠错后的待取数据发送出去。
如图6所示，ECC模块602还包括判断子模块624，配置为当所述读写状态为写状态时，判断所述读写指令携带的数据是否存在无效数据；在所述待存数据存在无效数据的情况下，获取所述读写指令携带的操作地址对应的存储数据，根据所述存储数据生成有效的待存数据。
如图6所示，ECC模块602还包括：缓存子模块625，配置为在将所述读写指令携带的待存数据进行ECC编码生成对应的第一校验码、或根据所述读写指令获取待取数据之前，根据所述读写状态缓存所述读写指令。
在实际应用中，本发明提供的装置或系统装置可作为一个单独的系统，还可以是在现有的终端如个人计算机(PC，Personal Computer)中增加完成不同功能的逻辑单元。
当在PC中增加逻辑单元时，第一控制模块401、第一ECC模块402、第一存储模块403、第二控制模块501、第二ECC模块502、第二存储模块 503、控制模块601、ECC模块602以及存储模块603可由位于PC中的中央处理器(CPU，Central Processing Unit)、数字信号处理器(DSP，Digital Signal Processor)、或可编程门阵列(FPGA，Field Programmable Gate Array)实现。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
采用本发明实施例，解决了IRAM无法保证其写入的数据或读取的数据的准确率，并且在数据发生错误时无法进行纠错的问题；同时，本发明实施例的方法采用了汉明码，克服了传统奇偶校验只能检出数据块奇偶位的错误，校验码冗长且无法纠错的缺点，通过ECC校验的方式完成对IRAM数据单比特错误纠正，双比特错误检测的功能，使得IRAM本身具有识别数据错误的能力，并在数据的读取出错时发出告警，从而提高了IRAM存储数据的正确性与可靠性。

Claims (14)

  1. 一种基于汉明码写入数据的方法，所述方法包括：
    对接收到的读写指令进行解析，获取所述读写指令的读写状态；
    确定所述读写状态为写状态时，将所述读写指令携带的待存数据进行错误检查与纠正ECC编码以生成对应的第一校验码，并将所述待存数据与所述第一校验码进行存储。
  2. 根据权利要求1所述的方法，其中，所述方法还包括：对接收到的读写指令进行解析之前，将所述读写指令进行格式转换。
  3. 根据权利要求1所述的方法，其中，所述方法还包括：在将所述读写指令携带的待存数据进行ECC编码之前，判断所述待存数据是否存在无效数据；在所述待存数据存在无效数据的情况下，获取所述读写指令携带的操作地址对应的存储数据，根据所述存储数据生成有效的待存数据。
  4. 一种基于汉明码读取数据的方法，所述方法包括：
    对接收到的读写指令进行解析，获取所述读写指令的读写状态；
    确定所述读写状态为读状态时，根据所述读写指令获取待取数据，采用错误检查与纠正ECC编码对所述待取数据进行检测得到检测结果，根据所述检测结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警。
  5. 根据权利要求4所述的方法，其中，所述方法还包括：对接收到的读写指令进行解析之前，将所述读写指令进行格式转换。
  6. 根据权利要求4所述的方法，其中，所述方法还包括：根据所述读写指令获取所述待取数据及所述待取数据对应的第一校验码，并将所述待取数据进行ECC编码以生成第二校验码；
    相应的，所述采用ECC编码对所述待取数据进行检测得到检测结果，根据所述检测结果将所述待取数据直接发送、或将所述待取数据进行纠错 后发送、或触发告警包括：
    将所述第一校验码与所述第二校验码进行异或操作生成异或结果；根据所述异或结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警。
  7. 根据权利要求6所述的方法，其中，所述根据所述检测结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警具体为：
    情况一：当所述异或结果为全0或存在单比特的1，则将所述待取数据直接发送；
    情况二：当所述异或结果中0与1的个数相同，则将所述待取数据进行纠错后发送；
    若非所述情况一和所述情况二，则触发告警。
  8. 一种基于汉明码写入数据的集成随机存取存储器IRAM，所述IRAM包括：第一控制模块、第一ECC模块以及第一存储模块；其中，
    所述第一控制模块，配置为对接收到的读写指令进行解析，获取所述读写指令的读写状态；
    所述第一ECC模块，配置为确定所述读写状态为写状态时，将所述读写指令携带的待存数据进行错误检查与纠正ECC编码以生成对应的第一校验码；
    所述第一存储模块，配置为存储所述待存数据和所述第一校验码。
  9. 根据权利要求8所述的IRAM，其中，所述第一控制模块，还配置为将所述读写指令进行格式转换。
  10. 根据权利要求8所述的方法，其中，所述第一ECC模块包括：第一判断子模块、第一编码子模块；其中，
    所述第一判断子模块，配置为判断所述待存数据是否存在无效数据， 在所述待存数据存在无效数据的情况下，获取所述读写指令携带的操作地址对应的存储数据，根据所述存储数据生成有效的待存数据；
    所述第一编码子模块，配置为将所述待存数据进行ECC编码以生成第一校验码。
  11. 一种基于汉明码读取数据的集成随机存取存储器IRAM，所述IRAM包括：第二控制模块、第二ECC模块以及第二存储模块；其中，
    所述第二控制模块，配置为对接收到的读写指令进行解析，获取所述读写指令的读写状态；
    所述第二ECC模块，配置为确定所述读写状态为读状态时，根据所述读写指令获取待取数据，采用错误检查与纠正ECC编码对所述待取数据进行检测得到检测结果，根据所述检测结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警；
    所述第二存储模块，配置为存储所述待取数据和所述待取数据对应的第一校验码。
  12. 根据权利要求11所述的IRAM，其中，所述第二控制模块，还配置为将所述读写指令进行格式转换。
  13. 根据权利要求11所述的IRAM，其中，所述第二ECC模块，包括：第二编码子模块、校验子模块；其中，
    所述第二编码子模块，配置为根据所述读写指令获取所述待取数据及所述待取数据对应的第一校验码，并将所述待取数据进行ECC编码以生成第二校验码；
    所述校验子模块，配置为将所述第一校验码与所述第二校验码进行异或操作生成异或结果，根据所述异或结果将所述待取数据直接发送、或将所述待取数据进行纠错后发送、或触发告警。
  14. 根据权利要求13所述的IRAM，其中，所述校验子模块，配置为 情况一：当所述异或的结果为全0或存在单比特的1，则将所述待取数据直接发送；情况二：当所述异或的结果中0与1的个数相同，则将所述待取数据进行纠错后发送；若非所述情况一和所述情况二，则触发告警。
PCT/CN2014/087226 2014-04-30 2014-09-23 一种基于汉明码存取数据的方法及集成随机存取存储器 WO2015165202A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP14890817.1A EP3125251A4 (en) 2014-04-30 2014-09-23 Hamming code-based data access method and integrated random access memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410183884.9A CN105023616A (zh) 2014-04-30 2014-04-30 一种基于汉明码存取数据的方法及集成随机存取存储器
CN201410183884.9 2014-04-30

Publications (1)

Publication Number Publication Date
WO2015165202A1 true WO2015165202A1 (zh) 2015-11-05

Family

ID=54358093

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/087226 WO2015165202A1 (zh) 2014-04-30 2014-09-23 一种基于汉明码存取数据的方法及集成随机存取存储器

Country Status (3)

Country Link
EP (1) EP3125251A4 (zh)
CN (1) CN105023616A (zh)
WO (1) WO2015165202A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109903806A (zh) * 2019-04-01 2019-06-18 江苏华存电子科技有限公司 一种双模式检错内存及双模式检错方法
CN111949433A (zh) * 2019-05-15 2020-11-17 北京兆易创新科技股份有限公司 非易失性存储器工作参数的处理方法、控制装置及存储器
CN113835927B (zh) * 2021-09-23 2023-08-11 武汉深之度科技有限公司 一种指令执行方法、计算设备及存储介质
CN114816268A (zh) * 2022-05-31 2022-07-29 长鑫存储技术有限公司 数据处理电路、方法及半导体存储器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1389872A (zh) * 2001-06-04 2003-01-08 株式会社东芝 半导体存储器
CN102339641A (zh) * 2010-07-23 2012-02-01 北京兆易创新科技有限公司 检错/纠错校验模块及该模块读写数据的方法
CN102378967A (zh) * 2009-04-02 2012-03-14 美光科技公司 扩展式单位错误校正及多位错误检测
CN102903394A (zh) * 2011-07-26 2013-01-30 爱思开海力士有限公司 半导体存储装置和具有半导体存储装置的半导体系统

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7051264B2 (en) * 2001-11-14 2006-05-23 Monolithic System Technology, Inc. Error correcting memory and method of operating same
JP2005327437A (ja) * 2004-04-12 2005-11-24 Nec Electronics Corp 半導体記憶装置
US20080183984A1 (en) * 2007-01-31 2008-07-31 Dale Beucler Memory system with read-modify-write
KR100907218B1 (ko) * 2007-03-28 2009-07-10 삼성전자주식회사 읽기 레벨 제어 장치 및 그 방법
US8145805B2 (en) * 2008-06-09 2012-03-27 Emulex Design & Manufacturing Corporation Method for re-sequencing commands and data between a master and target devices utilizing parallel processing

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1389872A (zh) * 2001-06-04 2003-01-08 株式会社东芝 半导体存储器
CN102378967A (zh) * 2009-04-02 2012-03-14 美光科技公司 扩展式单位错误校正及多位错误检测
CN102339641A (zh) * 2010-07-23 2012-02-01 北京兆易创新科技有限公司 检错/纠错校验模块及该模块读写数据的方法
CN102903394A (zh) * 2011-07-26 2013-01-30 爱思开海力士有限公司 半导体存储装置和具有半导体存储装置的半导体系统

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3125251A4 *

Also Published As

Publication number Publication date
EP3125251A1 (en) 2017-02-01
EP3125251A4 (en) 2017-06-28
CN105023616A (zh) 2015-11-04

Similar Documents

Publication Publication Date Title
KR101750662B1 (ko) 데이터 에러 교정용 회로, 장치, 및 방법
TWI546814B (zh) 具有錯誤校正邏輯之記憶體裝置
JP4925659B2 (ja) アクセス時間が減少したフラッシュメモリ装置
US9454422B2 (en) Error feedback and logging with memory on-chip error checking and correcting (ECC)
US20160124803A1 (en) Storage Device Data Access Method and Storage Device
US9191030B2 (en) Memory controller, data storage device, and memory controlling method
US11393550B2 (en) Memory system with error detection
KR102214556B1 (ko) 메모리 장치 및 모듈
US20140089761A1 (en) Method, apparatus and system for providing error correction information
US10992322B2 (en) Data storage system and associated method for saving storage space and eliminating data errors
WO2015165202A1 (zh) 一种基于汉明码存取数据的方法及集成随机存取存储器
US20130080854A1 (en) Address error detection
CN103531246A (zh) 快速以读代写的存储器纠错方法
US8429485B2 (en) Method and apparatus for detecting free page and a method and apparatus for decoding error correction code using the method and apparatus for detecting free page
US10911181B2 (en) Method for checking address and control signal integrity in functional safety applications, related products
US10490243B2 (en) Memory device and information processing apparatus
US9354970B2 (en) Method and apparatus for encoding erroneous data in an error correction code protected memory
CN115729746A (zh) 一种基于crc和ecc存储数据保护方法
US20190163569A1 (en) Memory and method of operating the memory
US11809272B2 (en) Error correction code offload for a serially-attached memory device
US20240053904A1 (en) Efficient security metadata encoding in error correcting code (ecc) memory without dedicated ecc bits
US20230367671A1 (en) Ddr dimm, memory system and operation method thereof
US10579470B1 (en) Address failure detection for memory devices having inline storage configurations
WO2020199133A1 (en) Method for checking address and control signal integrity in functional safety applications, related products
JP5916204B2 (ja) メモリ装置及びメモリパトロールによるデータ化け回避方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14890817

Country of ref document: EP

Kind code of ref document: A1

REEP Request for entry into the european phase

Ref document number: 2014890817

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2014890817

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE