WO2015162712A1 - Semiconductor module and power converter using same - Google Patents

Semiconductor module and power converter using same Download PDF

Info

Publication number
WO2015162712A1
WO2015162712A1 PCT/JP2014/061355 JP2014061355W WO2015162712A1 WO 2015162712 A1 WO2015162712 A1 WO 2015162712A1 JP 2014061355 W JP2014061355 W JP 2014061355W WO 2015162712 A1 WO2015162712 A1 WO 2015162712A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor module
main terminal
potential side
conductor
semiconductor
Prior art date
Application number
PCT/JP2014/061355
Other languages
French (fr)
Japanese (ja)
Inventor
行武　正剛
徹 増田
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to PCT/JP2014/061355 priority Critical patent/WO2015162712A1/en
Publication of WO2015162712A1 publication Critical patent/WO2015162712A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the present invention relates to a power conversion device such as a power module and an inverter device incorporating a semiconductor switching element used in the power conversion device.
  • the conventional high voltage (for example, 1200 V or higher) semiconductor module for switching has a structure in which holes are formed in both the module main terminal electrode surface and the external bus bar main terminal surface and tightened with bolts. It was. For this reason, the structure which makes a current path oppose in the main terminal part of the module was not taken. Further, as a connection technique that does not depend on bolt tightening, there is JP-A-2006-148098 (Patent Document 1).
  • connection is made to a receptacle provided on a backplane having a power bus layer (see means for solving the problems).
  • the module and the bus bar are connected without using bolting in a configuration called an edge card connector.
  • the forward path and the return path of the current can be configured to always face each other.
  • a specific connection portion is not disclosed.
  • the object of the present invention is to suppress parasitic inductance that increases at the main terminal connection portion between the semiconductor module and the external bus bar, to secure a heat dissipation path for this connection portion, and also to carry the semiconductor module and assemble it to the inverter device.
  • An object of the present invention is to provide a semiconductor module having ease of handling and a power converter using the same.
  • a semiconductor module of the present invention is, for example, a semiconductor module including a plurality of semiconductor switching elements, the main terminal on the high potential side of the semiconductor module, and the low potential side of the semiconductor module.
  • the main terminal of the semiconductor module is formed of a surface in which main connection surfaces face each other in the semiconductor module.
  • the power converter of the present invention is characterized by comprising the semiconductor module of the present invention.
  • the loop area of the current can be minimized in the module main terminal connection portion and the main terminal connection portion does not appear outside the module, the module can be easily handled. Furthermore, it becomes easy to dissipate heat from the main terminal connection portion.
  • the semiconductor module of the present invention includes, for example, the semiconductor module 0 including a plurality of semiconductor switching elements, the power terminal 1T on the high potential side of the semiconductor module 0 and the power terminal on the low potential side of the semiconductor module 0. 2T is constituted by opposing surfaces in the semiconductor module 0.
  • the high potential side main terminal and the low potential side main terminal are provided inside the semiconductor module, and the high potential side main terminal is provided.
  • At least one of the main terminal on the high potential side and the main terminal on the low potential side has a structure in contact with a main heat radiating plate that radiates heat generated from the semiconductor via an insulator. It may be.
  • each of the high potential side main terminal and the low potential side main terminal is in contact with the first conductor and the second conductor on at least two surfaces. You may make it have a surface.
  • each of the main terminal on the high potential side and the main terminal on the low potential side has a taper angle and is in contact with the first conductor and the second conductor. You may make it have.
  • each of the high-potential side main terminal and the low-potential side main terminal is a plane perpendicular to a plane forming the main terminal, and the first conductor and the second potential You may make it have a surface which contacts a conductor.
  • the power converter of the present invention is characterized by including the semiconductor module of the present invention.
  • FIG. 1 is an example of an image diagram of a cross-sectional configuration of a power module according to a first embodiment of the present invention.
  • Reference numeral 5a denotes a switching semiconductor element such as an IGBT or a MOSFET. In the present embodiment, a case where a MOSFET is used as the switching semiconductor element 5a will be described as an example.
  • Reference numeral 5b denotes a reflux diode.
  • the connection layer 6a is an electrical and thermal connection between the drain of the switching semiconductor element 5a and the first wiring layer 1
  • the connection layer 6b is an electrical and thermal connection between the cathode of 5b and the first wiring layer 1.
  • the wiring layer 1 is connected via an insulating layer 3 to a housing 4 that also serves as a heat dissipation base, and constitutes a main heat dissipation path.
  • the connection layer 7a is connected to the source of the switching semiconductor element 5a and the second wiring layer 2, and the connection layer 7b is connected to the anode of 5b and the second wiring layer 2 to carry out electrical and thermal connection. Yes.
  • the connection layer 7c is responsible for electrical connection between the gate of the switching semiconductor element 5a and the control signal wiring 2c.
  • 0 is a semiconductor module, and an external bus bar 10 is connected to the left opening in the figure.
  • 11 of the bus bar 10 is a wiring layer 11 connected to the first wiring layer 1 of the semiconductor module, and 12 is a wiring layer 12 connected to the second wiring layer 2 of the semiconductor module.
  • Reference numeral 13 denotes an insulating layer, which provides insulation between the wiring layer 11 and the wiring layer 12.
  • the bus bar 10 is inserted into the semiconductor module 0 and realizes an electrically good connection by using a sandwiching means (not shown) for reducing the resistance of the contact portion. Further, the portions not shown around the semiconductor elements 5a and 5b are filled with, for example, an insulator such as silicon gel, and are responsible for the insulation of the high breakdown voltage semiconductor elements.
  • the portion connecting the semiconductor module and the external bus bar is formed by the adjacent opposing surfaces, the parasitic inductance can be reduced. Further, protrusions such as main terminals are eliminated from the outside of the semiconductor module, which facilitates handling during mounting.
  • FIG. 2 is an example of an image diagram of a cross-sectional configuration of the power module according to the second embodiment of the present invention. Differences from the embodiment of FIG. 1 will be mainly described.
  • the semiconductor elements 5a and 5b are flip-chip mounted and have a structure in which the most heat-generating surface of the semiconductor element is directed to the main heat dissipation path side.
  • the first wiring layer 2 connected to the high potential power source has a structure folded at the right end in the drawing.
  • FIG. 3a shows a configuration in which the wiring layer is tapered to facilitate insertion during fitting.
  • FIG. 3b shows a configuration in which terminals stacked in a strip shape are stacked several times. By comprising in this way, while making a contact area increase significantly, since it contacts on both sides of strip shape, the quality of contact can be improved.
  • FIG. 3c shows a configuration in which each terminal contacts at two or more surfaces formed into a tapered shape.
  • connection portions having different potentials face each other through the thin insulating layer, the parasitic inductance can be greatly reduced.
  • FIG. 4 is an image view of the connecting portion between the semiconductor module and the external bus bar as viewed from the direction perpendicular to the current path surface.
  • 1 is a connection terminal portion on the semiconductor module side
  • 11 is a connection terminal portion on the external bus bar side.
  • the compression direction for reducing the contact resistance of the connection portion is a direction perpendicular to the current path surface. For this reason, since there is no insulating layer on the line where the compressive force is applied, there is no stress on the insulating layer due to compression, and there is no need to consider deterioration of the reliability of the insulating layer.
  • FIG. 5 is a structural diagram showing an example of the structure of the pressing plate for reducing the contact resistance of the main terminal connecting portion of the present invention.
  • 31 and 32 are pressing plates, and a module-side bus bar (not shown) and a main terminal connecting portion of an external bus bar are sandwiched between the two pressing plates.
  • the holding plate is sandwiched from above and below with bolts 33 and tightened with bolts 33 to reduce the contact resistance of the connecting portion.
  • Protruding portions 34 are provided in the portion where the pressing plate is sandwiched, and portions where the contact load is increased are provided in a matrix to further reduce the contact resistance.
  • FIG. 6 is a diagram showing an example of an inverter circuit when the semiconductor module of the present invention is applied to a power converter.
  • Reference numeral 40 denotes a three-phase (U, V, W) inverter.
  • Reference numeral 41 denotes a semiconductor module according to the present invention, which includes a switching element 42 and a reflux diode element 43.
  • Reference numeral 44 denotes a smoothing filter capacitor, and reference numeral 50 denotes an electric motor serving as a load.
  • the rated voltage is a loss under one class. It is possible to use a semiconductor module that suppresses the above. Therefore, the loss and cost of the inverter can be reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Inverter Devices (AREA)

Abstract

In order to suppress parasitic inductance that increases in a main terminal connection portion between a semiconductor module and an external bus bar, secure a heat-dissipating path for the connection portion, and ensure easy handling when the semiconductor module is conveyed and assembled to an inverter device, this semiconductor module is characterized in that in a semiconductor module (0) with a plurality of built-in semiconductor switching elements, a high-potential-side power supply terminal (1T) of the semiconductor module (0) and a low-potential-side power supply terminal (2T) of the semiconductor module (0) are formed from surfaces facing each other within the semiconductor module (0). Further, this power converter is characterized by being configured to be provided with the abovementioned semiconductor module.

Description

半導体モジュールおよびそれを用いた電力変換器Semiconductor module and power converter using the same
　本発明は、電力変換装置に用いられる半導体スイッチング素子を内蔵したパワーモジュール及びインバータ装置などの電力変換装置に関する。 The present invention relates to a power conversion device such as a power module and an inverter device incorporating a semiconductor switching element used in the power conversion device.
　従来、半導体モジュールのモジュール主端子電極と外部バスバーの主端子との接続をボルトの締め付けによらない方法で行う技術として、電力バス層を有するバックプレーン上に設けられたレセプタクルに接続するものがあった（例えば、特許文献１参照）。 Conventionally, as a technique for connecting a module main terminal electrode of a semiconductor module and a main terminal of an external bus bar by a method that does not use bolt tightening, there is a technique of connecting to a receptacle provided on a backplane having a power bus layer. (For example, see Patent Document 1).
特開２００６－１４８０９８号公報JP 2006-148098 A
　一般に、電力変換器などの大電流のスイッチングを伴うシステムにおいては、電流経路を対向させることによって、発生する磁束を相殺させ、回路のインダクタンスを低減させることは、従来から知られている。しかしながら、従来の高電圧（たとえば、１２００Ｖ以上）のスイッチング用の半導体モジュールは、モジュール主端子電極の面と外部バスバーの主端子面との双方の電極面に穴を開けてボルトで締め付ける構造であった。このため、モジュールの主端子部分では電流経路を対向させる構造は採られていなかった。また、ボルトの締め付けによらない接続技術として、特開２００６－１４８０９８（特許文献１）がある。この公報には、電力バス層を有するバックプレーン上に設けられたレセプタクルに接続すると記載されている（課題を解決するための手段参照）。特許文献１によれば、エッジカードコネクタという構成で、ボルトでの締め付けを用いず、モジュールとバスバーを接続している。これによれば、電流の往路と復路は常に面で対向する構成をとることができる。しかしながら、具体的な接続部については開示されていない。 Generally, in a system involving switching of a large current, such as a power converter, it has been conventionally known that a magnetic flux generated is canceled by opposing current paths to reduce circuit inductance. However, the conventional high voltage (for example, 1200 V or higher) semiconductor module for switching has a structure in which holes are formed in both the module main terminal electrode surface and the external bus bar main terminal surface and tightened with bolts. It was. For this reason, the structure which makes a current path oppose in the main terminal part of the module was not taken. Further, as a connection technique that does not depend on bolt tightening, there is JP-A-2006-148098 (Patent Document 1). In this publication, it is described that connection is made to a receptacle provided on a backplane having a power bus layer (see means for solving the problems). According to Patent Document 1, the module and the bus bar are connected without using bolting in a configuration called an edge card connector. According to this, the forward path and the return path of the current can be configured to always face each other. However, a specific connection portion is not disclosed.
　本発明の目的は、半導体モジュールと外部バスバーとの主端子接続部分で増大してしまう寄生インダクタンスの抑制と、この接続部の放熱経路の確保、更には半導体モジュールの運搬時やインバータ装置への組み付けの際の取り回しのし易さを有する半導体モジュールとこれを用いた電力変換器を提供することにある。 The object of the present invention is to suppress parasitic inductance that increases at the main terminal connection portion between the semiconductor module and the external bus bar, to secure a heat dissipation path for this connection portion, and also to carry the semiconductor module and assemble it to the inverter device. An object of the present invention is to provide a semiconductor module having ease of handling and a power converter using the same.
　上記課題を解決するために、本発明の半導体モジュールは、例えば、複数の半導体スイッチング素子を内蔵した半導体モジュールであって、前記半導体モジュールの高電位側の主端子と、前記半導体モジュールの低電位側の主端子とが、前記半導体モジュール内で、主な接続面が対向した面で構成されることを特徴とする。 In order to solve the above-described problems, a semiconductor module of the present invention is, for example, a semiconductor module including a plurality of semiconductor switching elements, the main terminal on the high potential side of the semiconductor module, and the low potential side of the semiconductor module. The main terminal of the semiconductor module is formed of a surface in which main connection surfaces face each other in the semiconductor module.
　また、本発明の電力変換器は、本発明の半導体モジュールを備えて構成されることを特徴とする。 Moreover, the power converter of the present invention is characterized by comprising the semiconductor module of the present invention.
　本発明によれば、モジュール主端子接続部において、電流のループ面積を最小化でき、且つ、モジュール外部に主端子接続部が出ない構成となるため、モジュールの取り回しが容易になる。更に、主端子接続部の放熱がし易くなる。 According to the present invention, since the loop area of the current can be minimized in the module main terminal connection portion and the main terminal connection portion does not appear outside the module, the module can be easily handled. Furthermore, it becomes easy to dissipate heat from the main terminal connection portion.
本発明の実施例１に係る半導体モジュールの断面構成のイメージ図である。It is an image figure of the cross-sectional structure of the semiconductor module which concerns on Example 1 of this invention. 本発明の実施例２に係る半導体モジュールの断面構成のイメージ図である。It is an image figure of the cross-sectional structure of the semiconductor module which concerns on Example 2 of this invention. 本発明の実施例３に係る半導体モジュールにおけるバスバー接続部の断面構造の一例のイメージ図である。It is an image figure of an example of the cross-sectional structure of the bus-bar connection part in the semiconductor module which concerns on Example 3 of this invention. 本発明の実施例３に係る半導体モジュールにおけるバスバー接続部の断面構造の他の一例のイメージ図である。It is an image figure of another example of the cross-sectional structure of the bus-bar connection part in the semiconductor module which concerns on Example 3 of this invention. 本発明の実施例３に係る半導体モジュールにおけるバスバー接続部の断面構造の更に他の一例のイメージ図である。It is an image figure of another example of the cross-sectional structure of the bus-bar connection part in the semiconductor module which concerns on Example 3 of this invention. 本発明の実施例４に係る半導体モジュールにおけるバスバー接続部の平面構造の一例のイメージ図である。It is an image figure of an example of the plane structure of the bus-bar connection part in the semiconductor module which concerns on Example 4 of this invention. 本発明の実施例５に係る半導体モジュールにおけるバスバー接続部の押さえ板の一例のイメージ図である。It is an image figure of an example of the pressing board of the bus-bar connection part in the semiconductor module which concerns on Example 5 of this invention. 本発明の実施例６に係る電力変換器の回路ブロック構成の一例を示す図である。It is a figure which shows an example of the circuit block structure of the power converter which concerns on Example 6 of this invention.
　上記の通り、本発明の半導体モジュールは、例えば、複数の半導体スイッチング素子を内蔵した半導体モジュール０において、半導体モジュール０の高電位側の電源端子１Ｔと、前記半導体モジュール０の低電位側の電源端子２Ｔが、前記半導体モジュール０内で、対向した面で構成されることを特徴とする。 As described above, the semiconductor module of the present invention includes, for example, the semiconductor module 0 including a plurality of semiconductor switching elements, the power terminal 1T on the high potential side of the semiconductor module 0 and the power terminal on the low potential side of the semiconductor module 0. 2T is constituted by opposing surfaces in the semiconductor module 0.
　より具体的には、本発明の半導体モジュールは、上記の構成において、前記高電位側の主端子と、前記低電位側の主端子とが前記半導体モジュールの内側に設けられ、前記高電位側の主端子に繋ぎ込む第一の導電体と、前記低電位側の主端子に繋ぎ込む第二の導電体と、前記第一の導電体と前記第二の導電体との間に挟まれた絶縁体とを備えて構成されるラミネートブスバーが外部から前記半導体モジュール内に挿入された場合に、前記高電位側の主端子と前記低電位側の主端子とで前記ラミネートブスバーを挟み込む構造を有することを特徴とする。 More specifically, in the semiconductor module of the present invention, in the above configuration, the high potential side main terminal and the low potential side main terminal are provided inside the semiconductor module, and the high potential side main terminal is provided. A first conductor connected to the main terminal, a second conductor connected to the low-potential main terminal, and an insulation sandwiched between the first conductor and the second conductor When the laminated bus bar configured to include a body is inserted into the semiconductor module from outside, the laminated bus bar is sandwiched between the high potential side main terminal and the low potential side main terminal. It is characterized by.
　上記の構成において、前記高電位側の主端子および前記低電位側の主端子の少なくとも何れか一方が、半導体から発生する熱を放熱する主たる放熱板に絶縁体を介して接触した構造を有するようにしてもよい。 In the above configuration, at least one of the main terminal on the high potential side and the main terminal on the low potential side has a structure in contact with a main heat radiating plate that radiates heat generated from the semiconductor via an insulator. It may be.
　また、上記の構成において、前記高電位側の主端子および前記低電位側の主端子のそれぞれが、少なくとも２つ以上の面で、前記第一の導電体および前記第二の導電体と接触する面を有するようにしてもよい。 In the above configuration, each of the high potential side main terminal and the low potential side main terminal is in contact with the first conductor and the second conductor on at least two surfaces. You may make it have a surface.
　また、上記の構成において、前記高電位側の主端子および前記低電位側の主端子のそれぞれが、テーパー角を持って、前記第一の導電体および前記第二の導電体と接触する面を有するようにしてもよい。 In the above configuration, each of the main terminal on the high potential side and the main terminal on the low potential side has a taper angle and is in contact with the first conductor and the second conductor. You may make it have.
　また、上記の構成において、前記高電位側の主端子および前記低電位側の主端子のそれぞれが、主端子を形成する面に対し垂直な面で、前記第一の導電体および前記第二の導電体と接触する面を有するようにしてもよい。 In the above configuration, each of the high-potential side main terminal and the low-potential side main terminal is a plane perpendicular to a plane forming the main terminal, and the first conductor and the second potential You may make it have a surface which contacts a conductor.
　また、上記の構成において、前記半導体モジュール内の前記高電位側の主端子と前記低電位側の主端子とで前記ラミネートブスバーを挟み込む構造を、前記ラミネートブスバーの両側から押さえ板をボルトで締め付ける構造としてもよい。その場合、前記押さえ板の表面に複数の凸部が設けられるのが好適である。 Further, in the above configuration, a structure in which the laminated bus bar is sandwiched between the high potential side main terminal and the low potential side main terminal in the semiconductor module, and a structure in which the pressing plate is fastened with bolts from both sides of the laminated bus bar. It is good. In that case, it is preferable that a plurality of convex portions are provided on the surface of the pressing plate.
　また、上記の通り、本発明の電力変換器は、本発明の半導体モジュールを備えて構成されることを特徴とする。 Further, as described above, the power converter of the present invention is characterized by including the semiconductor module of the present invention.
　以下、本発明の実施形態の例を、各実施例として図面を使用して詳細に説明する。 Hereinafter, examples of embodiments of the present invention will be described in detail with reference to the drawings as examples.
　図１は、本発明の実施例１のパワーモジュールの断面構成のイメージ図の例である。５aはＩＧＢＴやＭＯＳＦＥＴなどのスイッチング用半導体素子である。本実施例では、スイッチング用半導体素子５ａにＭＯＳＦＥＴを用いた場合を例に説明する。５ｂは還流用ダイオードである。接続層６ａはスイッチング用半導体素子５ａのドレインと第１の配線層１との電気的及び熱的接続を、また、接続層６ｂは５ｂのカソードと第１の配線層１との電気的及び熱的接続を担っている。配線層１は絶縁層３を介して、放熱ベースを兼ねるハウジング４に繋がり、主な放熱経路を構成する。接続層７ａは、スイッチング用半導体素子５ａのソースと第２の配線層２に接続され、接続層７ｂは、５ｂのアノードと第２の配線層２に接続され電気的及び熱的接続を担っている。接続層７ｃは、スイッチング用半導体素子５ａのゲートと制御信号用配線２ｃとの電気的接続を担っている。 FIG. 1 is an example of an image diagram of a cross-sectional configuration of a power module according to a first embodiment of the present invention. Reference numeral 5a denotes a switching semiconductor element such as an IGBT or a MOSFET. In the present embodiment, a case where a MOSFET is used as the switching semiconductor element 5a will be described as an example. Reference numeral 5b denotes a reflux diode. The connection layer 6a is an electrical and thermal connection between the drain of the switching semiconductor element 5a and the first wiring layer 1, and the connection layer 6b is an electrical and thermal connection between the cathode of 5b and the first wiring layer 1. Responsible connection. The wiring layer 1 is connected via an insulating layer 3 to a housing 4 that also serves as a heat dissipation base, and constitutes a main heat dissipation path. The connection layer 7a is connected to the source of the switching semiconductor element 5a and the second wiring layer 2, and the connection layer 7b is connected to the anode of 5b and the second wiring layer 2 to carry out electrical and thermal connection. Yes. The connection layer 7c is responsible for electrical connection between the gate of the switching semiconductor element 5a and the control signal wiring 2c.
　０は半導体モジュールであり、図中左の開口部に外部からのバスバー１０が接続される。バスバー１０の１１は半導体モジュールの第１の配線層１につながる、配線層１１で、１２は半導体モジュールの第２の配線層２につながる、配線層１２である。１３は絶縁層であり、配線層１１と配線層１２間の絶縁を担っている。 0 is a semiconductor module, and an external bus bar 10 is connected to the left opening in the figure. 11 of the bus bar 10 is a wiring layer 11 connected to the first wiring layer 1 of the semiconductor module, and 12 is a wiring layer 12 connected to the second wiring layer 2 of the semiconductor module. Reference numeral 13 denotes an insulating layer, which provides insulation between the wiring layer 11 and the wiring layer 12.
　バスバー１０は半導体モジュール０に挿入され、図示されていない接触部の抵抗を低減するための挟み込む手段を用いて電気的に良好な接続を実現する。また、半導体素子５ａ，５ｂ周囲の図示が無い部分は、例えば、シリコンゲル等の絶縁物が充填されており、高耐圧の半導体素子の絶縁を担っている。 The bus bar 10 is inserted into the semiconductor module 0 and realizes an electrically good connection by using a sandwiching means (not shown) for reducing the resistance of the contact portion. Further, the portions not shown around the semiconductor elements 5a and 5b are filled with, for example, an insulator such as silicon gel, and are responsible for the insulation of the high breakdown voltage semiconductor elements.
　本実施例によれば、半導体モジュールと外部のバスバーを接続する部分が近接した対向する面で形成されるため、寄生インダクタンスの低減が可能になる。また、半導体モジュールの外部に主端子などの突起物が無くなり実装時の取り回しがし易くなる。 According to the present embodiment, since the portion connecting the semiconductor module and the external bus bar is formed by the adjacent opposing surfaces, the parasitic inductance can be reduced. Further, protrusions such as main terminals are eliminated from the outside of the semiconductor module, which facilitates handling during mounting.
　図２は、本発明の実施例２のパワーモジュールの断面構成のイメージ図の例である。主に図1の実施例との差異について説明する。この実施例では半導体素子５ａ、５ｂがフリップチップ実装されており、半導体素子の最も発熱する表面を主たる放熱経路側に向けた構造となっている。また、高電位の電源に接続される第１の配線層２は、図中の右端で折り返された構造になっている。これにより、半導体素子５ａ，５ｂを交互にマトリックス状に配置して、半導体モジュールの大容量化した際に、並列接続された各半導体素子の電流経路長が均質化でき電流ばらつきの低減が期待できる。 FIG. 2 is an example of an image diagram of a cross-sectional configuration of the power module according to the second embodiment of the present invention. Differences from the embodiment of FIG. 1 will be mainly described. In this embodiment, the semiconductor elements 5a and 5b are flip-chip mounted and have a structure in which the most heat-generating surface of the semiconductor element is directed to the main heat dissipation path side. Further, the first wiring layer 2 connected to the high potential power source has a structure folded at the right end in the drawing. As a result, when the semiconductor elements 5a and 5b are alternately arranged in a matrix and the capacity of the semiconductor module is increased, the current path lengths of the semiconductor elements connected in parallel can be homogenized and a reduction in current variation can be expected. .
　外部バスバーとの接続部においては、テーパーとノッチを設けることで挿入のし易さと抜け防止の効果が期待できる。 ¡By providing a taper and a notch at the connection with the external bus bar, it can be easily inserted and prevented from coming off.
　本実施例では半導体モジュール内で絶縁層を介したラミネートバスバー構成になった主端子と外部のバスバーとの接続部の構造の例を図３ａ、３ｂ、３ｃに示し説明する。図３ａは、配線層にテーパーを付けて勘合の際の挿入をし易くした構成を示している。図３ｂは、短冊状に重ねられた端子同士を幾重にも重ねた構成を示している。このように構成することで、接触面積を大幅に増やすと共に、短冊状の両面で接触するため接触の質を向上できる。図３ｃは、各端子がテーパー状に成型した２面以上の面で接触する構成を示している。このように構成すると、２面以上の面で接触するため、接触抵抗の低減が期待できる。このように、薄い絶縁層を介したラミネート構造のバスバー同士を接続する際には、沿面距離を稼ぐために、接続部では絶縁層が２層以上重なる部分を設ける必要がある。 In this embodiment, an example of the structure of a connection portion between a main terminal having a laminated bus bar configuration and an external bus bar through an insulating layer in a semiconductor module will be described with reference to FIGS. 3a, 3b, and 3c. FIG. 3a shows a configuration in which the wiring layer is tapered to facilitate insertion during fitting. FIG. 3b shows a configuration in which terminals stacked in a strip shape are stacked several times. By comprising in this way, while making a contact area increase significantly, since it contacts on both sides of strip shape, the quality of contact can be improved. FIG. 3c shows a configuration in which each terminal contacts at two or more surfaces formed into a tapered shape. If comprised in this way, since it contacts on 2 or more surfaces, reduction of contact resistance can be anticipated. Thus, when connecting bus bars having a laminated structure via a thin insulating layer, it is necessary to provide a portion where two or more insulating layers overlap in the connecting portion in order to increase a creepage distance.
　本実施例によれば、電位の異なる双方の接続部が薄い絶縁層を介して面で対向するため寄生インダクタンスを大幅に軽減できる。 According to this embodiment, since both connection portions having different potentials face each other through the thin insulating layer, the parasitic inductance can be greatly reduced.
　図４は半導体モジュールと外部バスバーの接続部を電流経路面に対して垂直方向から見たイメージ図である。例えば、１は半導体モジュール側に接続端子部で１１は外部バスバー側の接続端子部である。本実施例は、前述までの実施例とは異なり、接続部の接触抵抗を低減するための圧縮方向が電流経路面に対して垂直方向となる。このため、圧縮力が掛かる線上に絶縁層を介しないために、圧縮による絶縁層へのストレスが無く、絶縁層の信頼性の劣化などを考慮する必要がない。 FIG. 4 is an image view of the connecting portion between the semiconductor module and the external bus bar as viewed from the direction perpendicular to the current path surface. For example, 1 is a connection terminal portion on the semiconductor module side, and 11 is a connection terminal portion on the external bus bar side. In the present embodiment, unlike the embodiments described above, the compression direction for reducing the contact resistance of the connection portion is a direction perpendicular to the current path surface. For this reason, since there is no insulating layer on the line where the compressive force is applied, there is no stress on the insulating layer due to compression, and there is no need to consider deterioration of the reliability of the insulating layer.
　図５は本発明の主端子接続部の接触抵抗を低減するための押さえ板の構造の一例を示す構造図である。３１，３２は押さえ板で、この２枚の押さえ板の間に図示していないモジュール側のバスバーと外部からのバスバーの主端子接続部が挟まる。押さえ板は、ボルト３３で上下から挟み込んで、ボルト３３で締め付けることにより接続部の接触抵抗を低減する。押さえ板の挟みこむ部分には突起部３４を設けて接触加重が大きくなる部分をマトリクス状に設けて接触抵抗の更なる低減を図っている。 FIG. 5 is a structural diagram showing an example of the structure of the pressing plate for reducing the contact resistance of the main terminal connecting portion of the present invention. 31 and 32 are pressing plates, and a module-side bus bar (not shown) and a main terminal connecting portion of an external bus bar are sandwiched between the two pressing plates. The holding plate is sandwiched from above and below with bolts 33 and tightened with bolts 33 to reduce the contact resistance of the connecting portion. Protruding portions 34 are provided in the portion where the pressing plate is sandwiched, and portions where the contact load is increased are provided in a matrix to further reduce the contact resistance.
　図６は本発明の半導体モジュールを電力変換器に適用した場合のインバータ回路の一例を示す図である。４０は３相（Ｕ，Ｖ，Ｗ）のインバータである。４１はスイッチング素子４２と還流用ダイオード素子４３とで構成された、本発明の半導体モジュールである。４４は平滑用のフィルタコンデンサであり、５０は負荷となる電動機である。 FIG. 6 is a diagram showing an example of an inverter circuit when the semiconductor module of the present invention is applied to a power converter. Reference numeral 40 denotes a three-phase (U, V, W) inverter. Reference numeral 41 denotes a semiconductor module according to the present invention, which includes a switching element 42 and a reflux diode element 43. Reference numeral 44 denotes a smoothing filter capacitor, and reference numeral 50 denotes an electric motor serving as a load.
　本実施例によれば、インバータに主端子接続部の寄生インダクタンスを低減できる本発明の半導体モジュールを用いることにより、スイッチング時の跳ね上がり電圧を抑制することができるため、定格電圧が１クラス下の損失を抑えた半導体モジュールを用いることができる。そのため、インバータの損失とコストを低減できる。 According to this embodiment, since the jumping voltage at the time of switching can be suppressed by using the semiconductor module of the present invention that can reduce the parasitic inductance of the main terminal connection portion in the inverter, the rated voltage is a loss under one class. It is possible to use a semiconductor module that suppresses the above. Therefore, the loss and cost of the inverter can be reduced.
　０…半導体モジュール、
　１…第１の配線層、
　２…第２の配線層、
　３…絶縁層、
　４…ハウジング、
　５…半導体素子、
　６，７…接続層、
　８…押さえ板、
　１０…バスバー、
　１１，１２…配線層、
　１３…絶縁層、
　４０…電力変換器 0 ... Semiconductor module,
1 ... 1st wiring layer,
2 ... second wiring layer,
3. Insulating layer,
4 ... Housing,
5 ... Semiconductor element,
6, 7 ... connection layer,
8 ... Presser plate,
10 ... Bus bar,
11, 12 ... wiring layer,
13: Insulating layer,
40 ... Power converter

Claims (11)

  1. 　複数の半導体スイッチング素子を内蔵した半導体モジュールであって、
    　前記半導体モジュールの高電位側の主端子と、前記半導体モジュールの低電位側の主端子とが、前記半導体モジュール内で、主な接続面が対向した面で構成される
    ことを特徴とする半導体モジュール。     A semiconductor module incorporating a plurality of semiconductor switching elements,
    A semiconductor module characterized in that a main terminal on the high potential side of the semiconductor module and a main terminal on the low potential side of the semiconductor module are constituted by faces facing main connection surfaces in the semiconductor module. .
  2. 　請求項１において、
    　前記高電位側の主端子と、前記低電位側の主端子とが前記半導体モジュールの内側に設けられ、
    　前記高電位側の主端子に繋ぎ込む第一の導電体と、前記低電位側の主端子に繋ぎ込む第二の導電体と、前記第一の導電体と前記第二の導電体との間に挟まれた絶縁体とを備えて構成されるラミネートブスバーが外部から前記半導体モジュール内に挿入された場合に、前記高電位側の主端子と前記低電位側の主端子とで前記ラミネートブスバーを挟み込む構造を有する
    ことを特徴とする半導体モジュール。     In claim 1,
    The main terminal on the high potential side and the main terminal on the low potential side are provided inside the semiconductor module,
    Between the first conductor connected to the main terminal on the high potential side, the second conductor connected to the main terminal on the low potential side, and between the first conductor and the second conductor When the laminated bus bar configured to include an insulator sandwiched between the high potential side main terminal and the low potential side main terminal is inserted into the semiconductor module from the outside, the laminated bus bar is A semiconductor module having a sandwiching structure.
  3. 　請求項２において、
    　前記高電位側の主端子および前記低電位側の主端子のそれぞれが、テーパー角を持って、前記第一の導電体および前記第二の導電体と接触する面を有する
    ことを特徴とする半導体モジュール。     In claim 2,
    Each of the main terminal on the high potential side and the main terminal on the low potential side has a taper angle and has a surface in contact with the first conductor and the second conductor. module.
  4. 　請求項２において、
    　前記高電位側の主端子および前記低電位側の主端子の少なくとも何れか一方が、半導体から発生する熱を放熱する主たる放熱板に絶縁体を介して接触した構造を有する
    ことを特徴とする半導体モジュール     In claim 2,
    A semiconductor having a structure in which at least one of the main terminal on the high potential side and the main terminal on the low potential side is in contact with a main heat radiating plate that radiates heat generated from the semiconductor via an insulator. module
  5. 　請求項４において、
    　前記高電位側の主端子および前記低電位側の主端子のそれぞれが、テーパー角を持って、前記第一の導電体および前記第二の導電体と接触する面を有する
    ことを特徴とする半導体モジュール。     In claim 4,
    Each of the main terminal on the high potential side and the main terminal on the low potential side has a taper angle and has a surface in contact with the first conductor and the second conductor. module.
  6. 　請求項２において、
    　前記高電位側の主端子および前記低電位側の主端子のそれぞれが、少なくとも２つ以上の面で、前記第一の導電体および前記第二の導電体と接触する面を有する
    ことを特徴とする半導体モジュール。     In claim 2,
    Each of the main terminal on the high potential side and the main terminal on the low potential side has a surface in contact with the first conductor and the second conductor on at least two or more surfaces. Semiconductor module.
  7. 　請求項６において、
    　前記高電位側の主端子および前記低電位側の主端子のそれぞれが、テーパー角を持って、前記第一の導電体および前記第二の導電体と接触する面を有する
    ことを特徴とする半導体モジュール。     In claim 6,
    Each of the main terminal on the high potential side and the main terminal on the low potential side has a taper angle and has a surface in contact with the first conductor and the second conductor. module.
  8. 　請求項２において、
    　前記高電位側の主端子および前記低電位側の主端子のそれぞれが、主端子を形成する面に対し垂直な面で、前記第一の導電体および前記第二の導電体と接触する面を有する
    ことを特徴とする半導体モジュール。     In claim 2,
    Each of the main terminal on the high potential side and the main terminal on the low potential side is a surface perpendicular to the surface forming the main terminal, and the surface in contact with the first conductor and the second conductor. A semiconductor module comprising:
  9. 　請求項２において、
    　前記半導体モジュール内の前記高電位側の主端子と前記低電位側の主端子とで前記ラミネートブスバーを挟み込む構造は、前記ラミネートブスバーの両側から押さえ板をボルトで締め付ける構造である
    ことを特徴とする半導体モジュール。     In claim 2,
    The structure in which the laminated bus bar is sandwiched between the main terminal on the high potential side and the main terminal on the low potential side in the semiconductor module is a structure in which a pressing plate is fastened with bolts from both sides of the laminated bus bar. Semiconductor module.
  10. 　請求項９において、
    　前記押さえ板の表面に複数の凸部が設けられている
    ことを特徴とする半導体モジュール。     In claim 9,
    A semiconductor module, wherein a plurality of convex portions are provided on a surface of the pressing plate.
  11. 　請求項１乃至１０のいずれか１項に記載の半導体モジュールを備えて構成される
    ことを特徴とする電力変換器。     A power converter comprising the semiconductor module according to claim 1.
PCT/JP2014/061355 2014-04-23 2014-04-23 Semiconductor module and power converter using same WO2015162712A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2014/061355 WO2015162712A1 (en) 2014-04-23 2014-04-23 Semiconductor module and power converter using same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2014/061355 WO2015162712A1 (en) 2014-04-23 2014-04-23 Semiconductor module and power converter using same

Publications (1)

Publication Number Publication Date
WO2015162712A1 true WO2015162712A1 (en) 2015-10-29

Family

ID=54331904

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/061355 WO2015162712A1 (en) 2014-04-23 2014-04-23 Semiconductor module and power converter using same

Country Status (1)

Country Link
WO (1) WO2015162712A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018067998A (en) * 2016-10-18 2018-04-26 三菱電機株式会社 Power converter
JP2018186686A (en) * 2017-04-27 2018-11-22 富士電機株式会社 Power conversion device
JP2019096718A (en) * 2017-11-22 2019-06-20 三菱電機株式会社 Semiconductor device
WO2019239771A1 (en) * 2018-06-11 2019-12-19 ローム株式会社 Semiconductor module
US10720378B2 (en) 2017-08-31 2020-07-21 Delta Electronics (Shanghai) Co., Ltd Component structure, power module and power module assembly structure

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003218554A (en) * 2001-11-14 2003-07-31 Yazaki Corp Power supply distribution box, and power device module
JP2006148098A (en) * 2004-11-24 2006-06-08 General Electric Co <Ge> Power module, phase-leg power module assembly, and three-phase inverter assembly
JP2006294849A (en) * 2005-04-11 2006-10-26 Mitsubishi Electric Corp Semiconductor device
JP2010056206A (en) * 2008-08-27 2010-03-11 Toyota Motor Corp Semiconductor module
JP2010104135A (en) * 2008-10-23 2010-05-06 Hitachi Ltd Power conversion apparatus and electrical machine system for mobile
JP2011135737A (en) * 2009-12-25 2011-07-07 Denso Corp Power converter
JP2013215071A (en) * 2012-04-04 2013-10-17 Denso Corp Power converter
JP2014013826A (en) * 2012-07-04 2014-01-23 Yazaki Corp Electronic component mounting board

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003218554A (en) * 2001-11-14 2003-07-31 Yazaki Corp Power supply distribution box, and power device module
JP2006148098A (en) * 2004-11-24 2006-06-08 General Electric Co <Ge> Power module, phase-leg power module assembly, and three-phase inverter assembly
JP2006294849A (en) * 2005-04-11 2006-10-26 Mitsubishi Electric Corp Semiconductor device
JP2010056206A (en) * 2008-08-27 2010-03-11 Toyota Motor Corp Semiconductor module
JP2010104135A (en) * 2008-10-23 2010-05-06 Hitachi Ltd Power conversion apparatus and electrical machine system for mobile
JP2011135737A (en) * 2009-12-25 2011-07-07 Denso Corp Power converter
JP2013215071A (en) * 2012-04-04 2013-10-17 Denso Corp Power converter
JP2014013826A (en) * 2012-07-04 2014-01-23 Yazaki Corp Electronic component mounting board

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018067998A (en) * 2016-10-18 2018-04-26 三菱電機株式会社 Power converter
JP2018186686A (en) * 2017-04-27 2018-11-22 富士電機株式会社 Power conversion device
US10720378B2 (en) 2017-08-31 2020-07-21 Delta Electronics (Shanghai) Co., Ltd Component structure, power module and power module assembly structure
JP2019096718A (en) * 2017-11-22 2019-06-20 三菱電機株式会社 Semiconductor device
WO2019239771A1 (en) * 2018-06-11 2019-12-19 ローム株式会社 Semiconductor module
CN112352314A (en) * 2018-06-11 2021-02-09 罗姆股份有限公司 Semiconductor module
JPWO2019239771A1 (en) * 2018-06-11 2021-07-08 ローム株式会社 Semiconductor module
US11328985B2 (en) 2018-06-11 2022-05-10 Rohm Co., Ltd. Semiconductor module
JP7228587B2 (en) 2018-06-11 2023-02-24 ローム株式会社 semiconductor module
US11664298B2 (en) 2018-06-11 2023-05-30 Rohm Co., Ltd. Semiconductor module
CN112352314B (en) * 2018-06-11 2023-11-28 罗姆股份有限公司 Semiconductor module
US11923278B2 (en) 2018-06-11 2024-03-05 Rohm Co., Ltd. Semiconductor module

Similar Documents

Publication Publication Date Title
US10153708B2 (en) Three-level power converter
US9660356B1 (en) Semiconductor device
KR101522089B1 (en) Semiconductor unit
US9129932B2 (en) Semiconductor module
JP5169353B2 (en) Power module
WO2015162712A1 (en) Semiconductor module and power converter using same
US9780684B2 (en) Power converter
WO2015072105A1 (en) Power module
US10027094B2 (en) Power module, power converter and drive arrangement with a power module
US11587921B2 (en) Semiconductor device
US10438872B2 (en) Semiconductor device and lead frame
US9209099B1 (en) Power semiconductor module
JP5817702B2 (en) Semiconductor module
US11088630B2 (en) Power converter
US10438865B2 (en) Semiconductor device
US11495527B2 (en) Semiconductor module
US11901837B2 (en) Power control unit
US11450647B2 (en) Semiconductor module and semiconductor device including the same
US10103096B2 (en) Semiconductor device
US20190229040A1 (en) Semiconductor device and method of manufacturing the same
US11901836B2 (en) Power control unit
JP2014127582A (en) Semiconductor module
CN111799581B (en) Electronic circuit unit
JP2013222886A (en) Semiconductor module
US20230307332A1 (en) Power Semiconductor Module and Method for Producing a Power Semiconductor Module

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14889946

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14889946

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP