WO2015131853A1 - 高速缓冲存储器Cache地址的映射处理方法和装置 - Google Patents

高速缓冲存储器Cache地址的映射处理方法和装置 Download PDF

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Publication number
WO2015131853A1
WO2015131853A1 PCT/CN2015/073789 CN2015073789W WO2015131853A1 WO 2015131853 A1 WO2015131853 A1 WO 2015131853A1 CN 2015073789 W CN2015073789 W CN 2015073789W WO 2015131853 A1 WO2015131853 A1 WO 2015131853A1
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Prior art keywords
cache
address
page
pseudo
set index
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PCT/CN2015/073789
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English (en)
French (fr)
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崔泽汉
陈荔城
陈明宇
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华为技术有限公司
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Publication of WO2015131853A1 publication Critical patent/WO2015131853A1/zh
Priority to US15/257,506 priority Critical patent/US9984003B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
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    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
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    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
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    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
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    • G06F2212/657—Virtual address space management

Definitions

  • Embodiments of the present invention relate to data storage technologies, and in particular, to a mapping processing method and apparatus for a cache cache address.
  • TLB translation table lookup buffer
  • cache cache
  • Cache cache memory
  • TLB competition problem In most computer architectures, each time you access the memory, you need to query the page table (Page Table), convert the virtual address VA (Virtual Address) to the physical address PA (Physical Address), and then use the physical address as an index. Look for the Cache to find the data that needs to be fetched in the Cache.
  • the page table is usually large and the tier is stored in memory.
  • the TLB caches a small number of frequently used page table entries and stores them in a location close to the CPU core. Therefore, if the virtual and real mapping relationship to be queried is stored in the TLB, that is, the TLB access hit (Hit), the TLB access can be greatly accelerated. Virtual real address translation process.
  • LLC Last Level Cache
  • the number of page table items required by the process is the working set (the working set is the memory required by a process in a specific time period) size/page size, and the working set of the process will continuously increase with the application requirements.
  • Increasing the page size can significantly reduce the number of page tables required by the process.
  • the normal page is 4KB, and the large page size of 2MB can reduce the number of page tables required by the process by 512 times, greatly reducing the competitive pressure of TLB and reducing TLB Miss, thereby improving performance.
  • FIG. 1 is a schematic diagram of a principle of a coloring partitioning cache of a prior art page. As shown in FIG. 1, FIG. 1 shows a principle of a page coloring partitioning Cache.
  • the physical address PA can be divided into two parts: the physical page number (Physical Page Number; PPN) and the page offset (Page Offset); from the perspective of the Cache, the physical address (Physical Address; PA) can be divided into There are three parts: Cache Tag, Cache Set Index, and Cache Block Offset.
  • the operating system can control the PPN, but cannot control the Page Offset. If the number of Page Offset bits is N, then 2N is the page size. The intersection of the PPN and the Cache Set Index is called a color bit.
  • the operating system can map addresses to a specified Cache Set by controlling the PPN (ie, controlling the coloring bits). In this way, different processes are assigned different coloring bits, that is, they can be mapped to different Cache Sets to achieve mutual isolation.
  • FIG. 2 is a schematic diagram of the contradiction between the large page and the page coloring Cache in the prior art.
  • the number of bits in the Page Offset field of the large page is increased (because the page is larger, more bits are needed to indicate the intra-page bias). Move), and the number of bits in the PPN field becomes smaller and no longer intersects with the Cache set index.
  • the absence of a colored bit makes it impossible for the operating system to control the Cache Set Index by controlling the PPN. Therefore, under the existing hardware architecture, there is a contradiction between the large page technology and the page coloring Cache technology, which makes it impossible to use both at the same time.
  • the embodiments of the present invention provide a mapping processing method and device for a cache Cache address, which is a defect that the large page technology and the page coloring Cache technology cannot be simultaneously used in the prior art.
  • An embodiment of the present invention provides a method for mapping a cache cache address, including:
  • mapping the physical address to a Cache address where the Cache address includes a first cache set index Cache Set Index 1, a cache tag Cache Tag, a second cache set index Cache Set Index 2, and a cache block in sequence.
  • Offset Cache Block Offset wherein the Cache Set Index1 located at the upper position and the Cache Set Index2 located at the lower position together constitute a cache set index Cache Set Index, and the Cache Set Index1 is located within the coverage of the PPN .
  • Another embodiment of the present invention provides another method for mapping a cache cache address, including:
  • the pseudo physical address includes a pseudo physical page number and a pseudo page offset; wherein the pseudo physical page number includes a first address portion, and the pseudo page bias Shifting includes a second address portion, the first address portion being the same size as the second address portion;
  • the physical address is mapped to a real physical address, where the real physical address includes a real physical page number PPN and a page offset; wherein the PPN includes the second address portion, and the page offset includes the first address portion;
  • mapping the real physical address to a Cache address where the Cache address includes a cache tag Cache Tag, a cache set index Cache Set Index, and a cache block offset Cache Block Offset; wherein the first address Partially located within the coverage of the Cache Set Index.
  • mapping processing device for a cache cache address including:
  • a first acquiring module configured to acquire a physical address corresponding to an access address sent by the processing core, where the physical address includes a physical page number PPN and a page offset;
  • a first mapping module configured to map the physical address into a Cache address, where the Cache address includes a first cache set index Cache Set Index1, a cache tag Cache Tag, and a second cache set index Cache Set. Index2, and a cache block offset Cache Block Offset; wherein the Cache Set Index1 located at the upper position and the Cache Set Index2 located at the lower position together constitute a cache set index Cache Set Index, and the Cache Set Index1 is located Within the coverage of the PPN.
  • Another embodiment of the present invention provides another mapping processing device for a cache cache address, including:
  • a second acquiring module configured to acquire a pseudo physical address corresponding to an access address sent by the processing core, where the pseudo physical address includes a pseudo physical page number and a pseudo page offset; wherein the pseudo physical page number includes a first address portion, The pseudo page offset includes a second address portion, the first address portion being the same size as the second address portion;
  • a second mapping module configured to map the pseudo physical address to a real physical address by exchanging the first address portion with the second address portion, where the real physical address includes a real physical page number PPN And a page offset; wherein the PPN includes the second address portion, The page offset includes the first address portion;
  • a third mapping module configured to map the real physical address into a Cache address, where the Cache address includes a cache tag Cache Tag, a cache set index Cache Set Index, and a cache block offset Cache Block Offset; The first address portion is located within a coverage of the Cache Set Index.
  • mapping processing method and device for the cache Cache address provided by the embodiment of the present invention can be used by the operating system to color the certain page of the large page PPN by mapping it to the Cache Set Index, thereby satisfying the simultaneous use of the large page technology. And page coloring to divide the requirements of Cache technology, and get the performance improvement of large page and page coloring Cache.
  • FIG. 1 is a schematic diagram of a principle of a coloring partitioning cache of a prior art page
  • FIG. 2 is a schematic diagram of a contradiction between a large page and a page coloring partition Cache in the prior art
  • FIG. 3 is a flowchart of an embodiment of a method for mapping a cache cache address according to the present invention
  • FIG. 4 is a schematic diagram of an application scenario of Embodiment 1 of a method according to the present invention.
  • FIG. 5 is a schematic diagram of another application scenario of an embodiment of a method according to the present invention.
  • FIG. 6 is a flowchart of another embodiment of a method for mapping a cache cache address according to the present invention.
  • FIG. 7 is a schematic diagram of still another application scenario of an embodiment of a method according to the present invention.
  • FIG. 8 is a schematic diagram of a method for mapping a pseudo physical address to a real physical address according to an embodiment of the present invention
  • FIG. 9 is a schematic diagram of an embodiment of a mapping processing device for a cache cache address according to the present invention.
  • FIG. 10 is a schematic diagram of another embodiment of a mapping processing device for a cache cache address according to the present invention.
  • the PPN and the Cache Set Index of the large page do not overlap, and the page coloring Cache cannot be implemented by controlling the PPN of the large page.
  • the root cause of the contradiction is the physical address and the index cache of the operating system operation.
  • the physical address is the same address, so when using a large page, it must not meet the needs of page coloring.
  • Embodiments of the present invention provide a solution that satisfies the need to simultaneously use a large page technology and a page coloring Cache technology.
  • FIG. 3 is a flowchart of a method for processing a cache cache address according to an embodiment of the present invention. As shown in FIG. 3, the method includes:
  • Step 301 Acquire a physical address corresponding to an access address sent by the processing core, where the physical address includes a physical page number PPN and a page offset.
  • Step 302 Map the physical address to a Cache address, where the Cache address includes a first cache set index Cache Set Index1, a cache tag Cache Tag, a second cache set index Cache Set Index2, and a cache block offset Cache Block Offset. Where the high place is located The Cache Set Index 1 and the Cache Set Index 2 located at the lower level together form a cache set index Cache Set Index, and the Cache Set Index 1 is located within the coverage of the PPN.
  • FIG. 4 is a schematic diagram of an application scenario of the method according to the embodiment of the present invention.
  • the application scenario of the method embodiment of the present invention is a multi-core processor, and the multi-core processor includes: Processor core, TLB, multi-level private Cache, shared LLC, memory, etc., as shown in Figure 4:
  • the access address issued by the processing core is the virtual address VA, which is composed of the virtual physical page number VPN and the virtual page offset Page Offset.
  • the physical address PA is obtained by querying the TLB, and the physical page number PPN and the page offset Page Offset composition.
  • the physical address PA obtains the address of the Cache at each level by mapping, some of which are used as Set Index to find all Cache Lines in the corresponding Set, and then some bits of the PA are compared as tags in the Cache Line. Determine if the Cache hits. If the Cache does not hit, the physical address PA is passed to the next level Cache until it is passed to memory.
  • the physical address index Cache is improved, that is, the mapping relationship between the physical address and the Cache address is changed, and the Set Index is composed of two parts: a part is the same as the existing mode, and some are close to the Block Offset.
  • the address bits are configured so that consecutive Cache lines have different Cache Sets to avoid Cache conflicts during continuous access; the other part is composed of some address bits of the physical address high, which is part of the large page PPN.
  • the Cache address mapped by the physical address PA includes a first cache set index Cache Set Index1, a cache tag Cache Tag, a second cache set index Cache Set Index2, and a cache block offset Cache Block Offset.
  • the Cache Set Index 1 located at the upper position and the Cache Set Index 2 located at the lower position together constitute a cache set index Cache Set Index, and the Cache Set Index 1 is located in the coverage of the PPN, and the Cache Set Index 1 is used as a coloring bit, and the operation is performed.
  • the system can control the mapping relationship between the VPN and the PPN, control the coloring bits, and map the pages to a specified set of settings, thereby realizing the page coloring of the large pages.
  • the size of the Cache Set Index1 and the Cache Set Index2 may be Same, it can be different.
  • FIG. 5 is a schematic diagram of another application scenario of the method embodiment of the present invention.
  • the difference between the Cache address and the Cache address of the mapped Cache address may be different.
  • the Cache Tag includes a first cache tag Cache Tag1 located at a high level and a second cache tag Cache Tag2 located at a lower position; and the Cache Set Index1 is located in the Cache Tag1 and the Cache. Between Tag2. Further, the sizes of Cache Tag1 and Cache Tag2 may be equal or different.
  • mapping the physical address to the Cache address may occur on a mapping relationship of a certain level of Cache or all Caches, and may be completed by using programmable register control.
  • FIG. 6 is a flowchart of another embodiment of a method for processing a cache cache address according to the present invention. As shown in FIG. 6, the method includes:
  • Step 601 Acquire a pseudo physical address corresponding to the access address sent by the processing core, where the pseudo physical address includes a pseudo physical page number and a pseudo page offset, where the pseudo physical page number includes a first address part, The pseudo page offset includes a second address portion, the first address portion being the same size as the second address portion;
  • Step 602 Perform mapping of the pseudo physical address to a real physical address by exchanging the location of the first address portion with the second address portion, where the real physical address includes a real physical page number PPN and a page offset Wherein the PPN includes the second address portion, and the page offset includes the first address portion;
  • Step 603 Mapping the real physical address to a Cache address, where the Cache address includes a cache tag Cache Tag, a cache set index Cache Set Index, and a cache block offset Cache Block Offset; wherein the first address part is located at the location Within the coverage of the Cache Set Index.
  • FIG. 7 is a schematic diagram of another application scenario of the method embodiment of the present invention.
  • the application scenario of the method embodiment of the present invention is a multi-core processor, and the multi-core processor includes: Multi-core, TLB, multi-level private Cache, shared LLC, Memory, etc., as shown in Figure 7:
  • the access address issued by the processing core is the virtual address VA, which is composed of the virtual physical page number VPN and the virtual page offset Page Offset.
  • the pseudo physical address pseudo-PA is obtained by querying the TLB, and the pseudo physical page number PPN and pseudo are obtained.
  • the page offset consists of a Page Offset. Wherein, the first address portion of the predetermined size is included in the pseudo physical page number, the second address portion is included in the pseudo page offset, and the first address portion and the second address portion are the same size.
  • a pseudo-physical address space pseudo-PA is added before the Cache, and the operating system manages the pseudo physical address space, and performs large page management and page coloring management.
  • the pseudo physical address pseudo-PA is mapped to the real physical address PA, and the physical address PA is mapped to obtain the addresses of the caches at all levels, some of which are used as Set Index to find all the corresponding Sets.
  • Cache Line then some bits of the PA are compared in parallel with the tags in these Cache Lines to determine if the Cache hits. If the Cache does not hit, the physical address PA is passed to the next level Cache until it is passed to memory.
  • FIG. 8 is a schematic diagram of a method for mapping a pseudo physical address to a real physical address according to an embodiment of the present invention.
  • some bits are selected from the pseudo physical address page number pseudo-PPN as a coloring bit, that is, a first address portion, and then Select the same number of bits from the Page Offset (located in the Cache Set Index), that is, the second address part, and change the position of the two.
  • the coloring bits are located in the Page Offset, and finally pass the physics.
  • the mapping relationship between the address PA and the Cache address is mapped to the Cache Set Index.
  • the mapping component before the index cache, the mapping component first converts the pseudo physical address pseudo-PA into a real physical address PA for indexing the cache and the memory.
  • the mapping relationship maps the coloring bits of the operating system (eg, the lower bits of the PPN) to the location of the Cache Set Index.
  • the operating system manages the pseudo physical address space pseudo-PA, and the TLB is filled with the mapping relationship between the virtual address VA and the pseudo physical address pseudo-PA.
  • the L1 Cache in Figure 7 still uses the pseudo-physical address pseudo-PA access, and only converts the pseudo-physical address pseudo-PA to the real physical address PA when the memory access reaches the last-level cache (LLC).
  • LLC last-level cache
  • pseudo The location of the physical address pseudo-PA to the real physical address PA conversion is not limited to the LLC shown in FIG. 7, and may be located before the L1Cache or before L2.
  • the mapping relationship between the pseudo physical address pseudo-PA and the real physical address PA in FIG. 7 achieves the following effects: the colored bits of the large page of the pseudo physical address space (part of the pseudo-PPN) are mapped and mapped to the real physical address. The low bit is finally mapped to the Set Index of the Cache address.
  • mapping the pseudo physical address to the real physical address may specifically occur on a mapping relationship of a certain level of Cache or all Caches, and may be completed by programmable register control.
  • the mapping processing method of the cache cache address provided by the embodiment of the present invention maps some bits of the large page PPN to the Set Index of the cache, so that it can be used by the operating system for coloring, and the large page technology and page are simultaneously used. Coloring the requirements of the Cache technology, and gaining the performance of large page and page coloring Cache; and all the changes are only the change of the address mapping relationship, without adding additional circuits; the address mapping changes can guarantee one-to-one mapping, no need Operating system management.
  • FIG. 9 is a schematic diagram of an embodiment of a mapping processing device for a cache cache address according to the present invention.
  • the device includes a first obtaining module 901 and a first mapping module 902, where the first obtaining module 901 is configured to obtain Processing a physical address corresponding to the access address sent by the core, where the physical address includes a physical page number PPN and a page offset; the first mapping module 902 is configured to map the physical address into a Cache address, where the Cache address includes the first a cache set index Cache Set Index1, a cache tag Cache Tag, a second cache set index Cache Set Index2, and a cache block offset Cache Block Offset; wherein the Cache Set Index1 located at the upper position and the Cache Set Index2 located at the lower position
  • the cache set index Cache Set Index is jointly formed, and the Cache Set Index1 is located in the coverage of the PPN.
  • the sizes of Cache Set Index1 and Cache Set Index2 may be equal or unequal.
  • the first mapping module 902 is further configured to divide the Cache Tag into a first cache tag Cache Tag1 located at a high position and a second cache tag Cache Tag2 located at a lower position; and the Cache Set Index1 is located between the Cache Tag1 and the Cache Tag2.
  • the size of the Cache Tag1 and the Cache Tag2 may be equal or different.
  • the device embodiment of the present invention may specifically perform the foregoing methods as shown in FIG. 3, FIG. 4 and FIG. 5, and specific functions are not described herein again.
  • FIG. 10 is a schematic diagram of another embodiment of a mapping processing device for a cache cache address according to the present invention.
  • the apparatus includes a second obtaining module 101, a second mapping module 102, and a third mapping module 103, wherein The second obtaining module 101 acquires a pseudo physical address corresponding to the access address sent by the processing core, where the pseudo physical address includes a pseudo physical page number and a pseudo page offset; wherein the pseudo physical page number includes the first address part, The pseudo page offset includes a second address portion, the first address portion being the same size as the second address portion; and the second mapping module 102 is configured to mutually interact the first address portion and the second address portion Transmitting a location to complete mapping the pseudo physical address to a real physical address, the real physical address including a real physical page number PPN and a page offset; wherein the PPN includes the second address portion, the page offset The first address part is included; the third mapping module 103 is configured to map the real physical address into a Cache address, where the Cache address
  • the device embodiment of the present invention may specifically perform the foregoing methods as shown in FIG. 6, 7, and 8, and specific functions are not described herein again.
  • the mapping processing device of the cache cache address provided by the embodiment of the present invention maps some bits of the large page PPN to the Set Index of the cache, so that it can be used by the operating system for coloring, and the large page technology and page are simultaneously used. Coloring the requirements of the Cache technology, and gaining the performance of large page and page coloring Cache; and all the changes are only the change of the address mapping relationship, without adding additional circuits; the address mapping changes can guarantee one-to-one mapping, no need Operating system management.
  • the disclosed apparatus and method can be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the above-described integrated unit implemented in the form of a software functional unit can be stored in a computer readable storage medium.
  • the above software functional unit is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to perform the methods of the various embodiments of the present invention. Part of the steps.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes. .

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

提供一种高速缓冲存储器Cache地址的映射处理方法和装置。该方法实施例包括获取处理核发送的访问地址所对应的物理地址，物理地址包括物理页面号PPN和页偏移（301）；将物理地址映射成Cache地址，Cache地址依次包括Cache Set Index1、Cache Tag、Cache Set Index2，以及Cache Block Offset；其中，位于高位的Cache Set Index1和位于低位的Cache Set Index2共同组成Cache Set Index，且Cache Set Index1位于PPN的覆盖范围内（302）。通过将大页面PPN的某些位映射到Cache的Set Index中，可以被操作系统用来着色，满足同时使用大页面技术和页着色划分Cache技术的需求，并获得大页面和页着色划分Cache的性能提升。

Description

高速缓冲存储器Cache地址的映射处理方法和装置
本申请要求于2014年3月6日提交中国专利局、申请号为201410080762.7、发明名称为“高速缓冲存储器Cache地址的映射处理方法和装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明实施例涉及数据存储技术，尤其涉及一种高速缓冲存储器Cache地址的映射处理方法和装置。
背景技术
随着数据集(Data Set，即数据的集合)的增大和处理器核数的增多，页表缓冲(Translation Lookaside Buffer；简称TLB)和高速缓冲存储器(如下中文简称：缓存，英文：Cache)面临着更严峻的挑战。
TLB竞争问题：在多数计算机体系结构中，每次访存都需要先查询页表(Page Table)，把虚拟地址VA(Virtual Address)转换为物理地址PA(Physical Address)，然后用物理地址作为索引去查找Cache，从而找到Cache中的访存所需要获取的数据。页表通常很大，分级存储在内存中。TLB作为页表的缓冲，缓存少量经常使用的页表项，存储在离CPU核很近的位置，这样如果要查询的虚实映射关系存储在TLB中，即TLB访问命中(Hit)，可以大大加速虚实地址转换过程。但是如果TLB经常访问缺失(Miss)，仍然需要到内存中分多级查找页表得到对应的页表项，需要经历很长的访问延迟。随着大数据时代数据集的不断增大，这种TLB的竞争只会越来越激烈，从而导致更大比例的TLB访问缺失，严重影响性能。
Cache竞争问题：在大多数的多核体系结构中，最后一级Cache(Last Level Cache；简称LLC)为多核所共享，这样核与核之间就会对LLC产生竞争，导 致进程之间相互替换cache，使cache利用率下降。特别是，有些程序的局部性比较差，但是访问频繁、工作集很大，这样就会占用较多的LLC容量，从而严重影响其他进程的性能。随着核数的增多，LLC的竞争问题会越来越严重。
现有技术中一般通过大页面(Huge Page)和页着色划分Cache(Page-Coloring based Cache Partition)技术进行性能优化。其中，进程需要的页表项数为工作集(工作集为在一个特定的时间段内一个进程所需要的内存)大小/页面大小，进程的工作集随着应用需求会不断增大，这时候增大页面大小，可以显著的减少进程所需要的页表数目。比如，普通页面为4KB，使用2MB的大页面，可以把进程需要的页表数目降低512倍，大大减轻TLB的竞争压力，减少TLB Miss，从而提高性能。
一种减少LLC竞争的方法是，静态或动态的把LLC划分给不同的核或者进程，使之相互隔离，不产生竞争，这种技术称为划分cache(Cache Partition)。页着色(page-coloring)是一种软件实现划分cache的方法，具有易于使用、不需要修改硬件的优点。图1为现有技术页着色划分Cache的原理示意图，如图1所示，图1显示了页着色划分Cache的原理。从操作系统的角度，物理地址PA可以分为两部分：物理页面号(Physical Page Number；PPN)和页偏移(Page Offset)；从Cache的角度，物理地址(Physical Address；简称PA)可以分为三部分：高速缓冲存储器标签(Cache Tag)、高速缓冲存储器集合索引(Cache Set Index)和高速缓冲存储器块偏移(Cache Block Offset)。其中操作系统可以控制PPN，但是不能控制Page Offset，假设Page Offset的位数为N，则2N即为页面大小。PPN和Cache Set Index的交集称为着色位(color bits)。操作系统通过控制PPN(即控制着色位)，可以使地址映射到指定的Cache Set中。这样，给不同的进程分配不同的着色位，即可以使其映射到不同的Cache Set中，从而实现相互隔离。
图2为现有技术中大页面与页着色划分Cache的矛盾示意图，如图2所示，大页面的Page Offset域的位数变多(因为页面更大，需要更多位来表示页内偏 移)，而PPN域的位数变少，并不再与Cache set index相交。没有着色位的存在，使得操作系统不能再通过控制PPN的方式，控制Cache Set Index。因此在现有的硬件体系结构下，大页面技术和页着色划分Cache技术存在矛盾，导致两者无法同时使用。
发明内容
本发明各实施例针对现有技术中大页面技术和页着色划分Cache技术无法同时使用的缺陷，提供一种高速缓冲存储器Cache地址的映射处理方法和装置。
本发明实施例一方面提供一种高速缓冲存储器Cache地址的映射处理方法，包括：
获取处理核发送的访问地址所对应的物理地址，所述物理地址包括物理页面号PPN和页偏移；
将所述物理地址映射成Cache地址，所述Cache地址依次包括第一高速缓冲存储器集合索引Cache Set Index1、高速缓冲存储器标签Cache Tag、第二高速缓冲存储器集合索引Cache Set Index2，以及高速缓冲存储器块偏移Cache Block Offset；其中，位于高位的所述Cache Set Index1和位于低位的所述Cache Set Index2共同组成高速缓冲存储器集合索引Cache Set Index，且所述Cache Set Index1位于所述PPN的覆盖范围内。
本发明实施例另一方面还提供另一种高速缓冲存储器Cache地址的映射处理方法，包括：
获取处理核发送的访问地址所对应的伪物理地址，所述伪物理地址包括伪物理页面号和伪页偏移；其中，所述伪物理页面号中包括第一地址部分，所述伪页偏移包括第二地址部分，所述第一地址部分与所述第二地址部分大小相同；
通过将所述第一地址部分与所述第二地址部分互换位置以完成将所述伪 物理地址映射成真实物理地址，所述真实物理地址包括真实物理页面号PPN和页偏移；其中，所述PPN包括所述第二地址部分，所述页偏移包括所述第一地址部分；
将所述真实物理地址映射成Cache地址，所述Cache地址包括高速缓冲存储器标签Cache Tag、高速缓冲存储器集合索引Cache Set Index，以及高速缓冲存储器块偏移Cache Block Offset；其中，所述第一地址部分位于所述Cache Set Index的覆盖范围内。
本发明实施例另一方面提供一种高速缓冲存储器Cache地址的映射处理装置，包括：
第一获取模块，用于获取处理核发送的访问地址所对应的物理地址，所述物理地址包括物理页面号PPN和页偏移；
第一映射模块，用于将所述物理地址映射成Cache地址，所述Cache地址依次包括第一高速缓冲存储器集合索引Cache Set Index1、高速缓冲存储器标签Cache Tag、第二高速缓冲存储器集合索引Cache Set Index2，以及高速缓冲存储器块偏移Cache Block Offset；其中，位于高位的所述Cache Set Index1和位于低位的所述Cache Set Index2共同组成高速缓冲存储器集合索引Cache Set Index，且所述Cache Set Index1位于所述PPN的覆盖范围内。
本发明实施例另一方面还提供另一种高速缓冲存储器Cache地址的映射处理装置，包括：
第二获取模块，获取处理核发送的访问地址所对应的伪物理地址，所述伪物理地址包括伪物理页面号和伪页偏移；其中，所述伪物理页面号中包括第一地址部分，所述伪页偏移包括第二地址部分，所述第一地址部分与所述第二地址部分大小相同；
第二映射模块，用于通过将所述第一地址部分与所述第二地址部分互换位置以完成将所述伪物理地址映射成真实物理地址，所述真实物理地址包括真实物理页面号PPN和页偏移；其中，所述PPN包括所述第二地址部分，所 述页偏移包括所述第一地址部分；
第三映射模块，用于将所述真实物理地址映射成Cache地址，所述Cache地址包括高速缓冲存储器标签Cache Tag、高速缓冲存储器集合索引Cache Set Index，以及高速缓冲存储器块偏移Cache Block Offset；其中，所述第一地址部分位于所述Cache Set Index的覆盖范围内。
本发明实施例提供的高速缓冲存储器Cache地址的映射处理方法和装置，通过将大页面PPN的某些位映射到Cache的Set Index中，因此可以被操作系统用来着色，满足同时使用大页面技术和页着色划分Cache技术的需求，并获得大页面和页着色划分Cache的性能提升。
附图说明
为了更清楚地说明本发明的技术方案，下面将对本发明实施例中所需要使用的附图做简单地介绍，显而易见地，下面所描述的附图仅仅是本发明的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术页着色划分Cache的原理示意图；
图2为现有技术中大页面与页着色划分Cache的矛盾示意图；
图3为本发明高速缓冲存储器Cache地址的映射处理方法一实施例流程图；
图4为本发明方法实施例一应用场景示意图；
图5为本发明方法实施例另一应用场景示意图；
图6为本发明高速缓冲存储器Cache地址的映射处理方法另一实施例流程图；
图7为本发明方法实施例再一应用场景示意图；
图8为本发明方法实施例伪物理地址到真实物理地址的映射方法示意图；
图9为本发明高速缓冲存储器Cache地址的映射处理装置一实施例示意 图；
图10为本发明高速缓冲存储器Cache地址的映射处理装置另一实施例示意图。
具体实施方式
以下将参考附图详细说明本发明的各种示例性实施例、特征和方面。附图中相同的附图标记表示功能相同或相似的元件。尽管在附图中示出了实施例的各种方面，但是除非特别指出，不必按比例绘制附图。
在这里专用的词“示例性”意为“用作例子、实施例或说明性”。这里作为“示例性”所说明的任何实施例不必解释为优于或好于其它实施例。
另外，为了更好的说明本发明，在下文的具体实施方式中给出了众多的具体细节。本领域技术人员应当理解，没有某些具体细节，本发明同样可以实施。在另外一些实例中，对于本领域技术人员熟知的方法、手段、元件和电路未作详细描述，以便于凸显本发明的主旨。
由于现有技术中，大页面的PPN和Cache Set Index没有重叠，导致无法通过控制大页面的PPN来实现页着色划分Cache，出现这种矛盾的根本原因是，操作系统操作的物理地址和索引cache的物理地址是同一个地址，因此使用大页面时，必然不能满足页着色的需求。本发明各实施例提供一种解决方案，满足同时使用大页面技术和页着色划分Cache技术的需求。
图3为本发明高速缓冲存储器Cache地址的映射处理方法一实施例流程图，如图3所示，该方法包括：
步骤301，获取处理核发送的访问地址所对应的物理地址，所述物理地址包括物理页面号PPN和页偏移；
步骤302，将所述物理地址映射成Cache地址，所述Cache地址依次包括第一缓存集合索引Cache Set Index1、缓存标签Cache Tag、第二缓存集合索引Cache Set Index2，以及缓存块偏移Cache Block Offset；其中，位于高位的所 述Cache Set Index1和位于低位的所述Cache Set Index2共同组成缓存集合索引Cache Set Index，且所述Cache Set Index1位于所述PPN的覆盖范围内。
以下结合具体硬件的应用场景来对该方法实施例进行详细的介绍，图4为本发明方法实施例一应用场景示意图，本发明方法实施例的应用场景为多核处理器，多核处理器包含：多个处理器核、TLB、多级私有Cache、共享的LLC、内存(Memory)等，如图4所示：
处理核(例如Core0)发出的访存地址为虚拟地址VA，由虚拟物理页面号VPN和虚拟页偏移Page Offset组成，通过查询TLB得到物理地址PA，由物理页面号PPN和页偏移Page Offset组成。物理地址PA通过映射(map)得到索引各级Cache的地址，其中一些位作为Set Index，找到对应Set中的所有Cache Line，然后PA的一些位作为Tag与这些Cache Line中的tag进行并行比较，确定是否Cache命中。如果Cache不命中，物理地址PA被传递给更下一级Cache，直至传递给内存。
本方法实施例对物理地址索引Cache的方式进行了改进，即改变物理地址到Cache地址的映射关系，将Set Index改为由两部分构成：一部分与现有方式相同，由紧挨Block Offset的一些地址位构成，这样可以使连续的Cache line具有不同的Cache Set，避免连续访问时造成Cache冲突；另一部分由物理地址高位的一些地址位构成，为大页面PPN的一部分。
如图4所示的，物理地址PA映射成的Cache地址依次包括第一缓存集合索引Cache Set Index1、缓存标签Cache Tag、第二缓存集合索引Cache Set Index2，以及缓存块偏移Cache Block Offset；其中，位于高位的所述Cache Set Index1和位于低位的所述Cache Set Index2共同组成缓存集合索引Cache Set Index，且所述Cache Set Index1位于所述PPN的覆盖范围内，Cache Set Index1作为着色位，操作系统可以控制VPN到PPN的映射关系，控制着色位，使页面映射到指定的一组set中，从而实现大页面的页着色划分cache。
在上述方法实施例中，Cache Set Index1和Cache Set Index2的大小可以相 同，也可以不同。
图5为本发明方法实施例另一应用场景示意图，与图4的区别仅在于，物理地址PA映射成的Cache地址不同，作为另一种实现方式，映射后的Cache地址中的Cache Tag也可以分成两部分，具体地如图5所示，Cache Tag包括位于高位的第一缓存标签Cache Tag1和位于低位的第二缓存标签Cache Tag2；且所述Cache Set Index1位于所述Cache Tag1和所述Cache Tag2之间。进一步地，Cache Tag1和Cache Tag2的大小可以相等，也可以不等。
上述方法实施例中，将物理地址映射成Cache地址具体可以发生在某一级Cache或所有Cache的映射关系上，并且可以通过可编程寄存器控制完成。
图6为本发明缓存Cache地址的映射处理方法另一实施例流程图，如图6所示，该方法包括：
步骤601，获取处理核发送的访问地址所对应的伪物理地址，所述伪物理地址包括伪物理页面号和伪页偏移；其中，所述伪物理页面号中包括第一地址部分，所述伪页偏移包括第二地址部分，所述第一地址部分与所述第二地址部分大小相同；
步骤602，通过将所述第一地址部分与所述第二地址部分互换位置以完成将所述伪物理地址映射成真实物理地址，所述真实物理地址包括真实物理页面号PPN和页偏移；其中，所述PPN包括所述第二地址部分，所述页偏移包括所述第一地址部分；
步骤603，将所述真实物理地址映射成Cache地址，所述Cache地址包括缓存标签Cache Tag、缓存集合索引Cache Set Index，以及缓存块偏移Cache Block Offset；其中，所述第一地址部分位于所述Cache Set Index的覆盖范围内。
以下结合具体硬件的应用场景来对该方法实施例进行详细的介绍，图7为本发明方法实施例再一应用场景示意图，本发明方法实施例的应用场景为多核处理器，多核处理器包含：多核、TLB、多级私有Cache、共享的LLC、 内存(Memory)等，如图7所示：
处理核(例如Core0)发出的访存地址为虚拟地址VA，由虚拟物理页面号VPN和虚拟页偏移Page Offset组成，通过查询TLB得到伪物理地址pseudo-PA，由伪物理页面号PPN和伪页偏移Page Offset组成。其中，在伪物理页面号中包括预定大小的第一地址部分，在伪页偏移包括第二地址部分，且第一地址部分与第二地址部分大小相同。
本发明实施例在Cache之前增加一层伪物理地址空间pseudo-PA，操作系统管理伪物理地址空间，对其进行大页面管理和页着色管理。在索引Cache之前，先对伪物理地址pseudo-PA进行映射真正的物理地址PA，物理地址PA通过映射(map)得到索引各级Cache的地址，其中一些位作为Set Index，找到对应Set中的所有Cache Line，然后PA的一些位作为Tag与这些Cache Line中的tag进行并行比较，确定是否Cache命中。如果Cache不命中，物理地址PA被传递给更下一级Cache，直至传递给内存。
图8为本发明方法实施例伪物理地址到真实物理地址的映射方法示意图，如图8所示，从伪物理地址页面号pseudo-PPN中选出一些位作为着色位即第一地址部分，再从Page Offset中选出同样多的位(位于Cache Set Index内)即第二地址部分，把两者进行位置换，在得到的真实物理地址PA中，着色位位于Page Offset中，并最终通过物理地址PA到Cache地址的映射关系，映射到Cache Set Index中。
本发明方法实施例在索引Cache之前，映射部件先将伪物理地址pseudo-PA转换为真实物理地址PA，用于索引Cache和内存。映射关系将操作系统的着色位(例如位于PPN的低位)映射到Cache Set Index所在的位置。
在图7中，操作系统管理的是伪物理地址空间pseudo-PA，TLB中填充的是虚拟地址VA到伪物理地址pseudo-PA的映射关系。特殊的，图7中的L1 Cache仍然使用伪物理地址pseudo-PA访问，只有当访存到达最后一级cache(LLC)时，才将伪物理地址pseudo-PA转换为真实物理地址PA。当然，伪 物理地址pseudo-PA到真实物理地址PA转换的位置不局限于图7所示的LLC前，也可以位于L1Cache前，或L2前。图7中伪物理地址pseudo-PA到真实物理地址PA的映射关系实现如下效果：使伪物理地址空间的大页面的着色位(pseudo-PPN的一部分)，经过映射后，映射到真实物理地址的低位，并最终映射到Cache地址的Set Index中。
上述方法实施例中，将伪物理地址映射成真实的物理地址具体可以发生在某一级Cache或所有Cache的映射关系上，并且可以通过可编程寄存器控制完成。
本发明实施例提供的高速缓冲存储器Cache地址的映射处理方法，通过将大页面PPN的某些位映射到Cache的Set Index中，因此可以被操作系统用来着色，满足同时使用大页面技术和页着色划分Cache技术的需求，并获得大页面和页着色划分Cache的性能提升；而且所有的改动都只是地址映射关系的改变，不增加额外的电路；地址映射的改动能保证一一映射，不需要操作系统管理。
图9为本发明高速缓冲存储器Cache地址的映射处理装置一实施例示意图，如图9所示，该装置包括第一获取模块901和第一映射模块902，其中，第一获取模块901用于获取处理核发送的访问地址所对应的物理地址，所述物理地址包括物理页面号PPN和页偏移；第一映射模块902用于将所述物理地址映射成Cache地址，所述Cache地址依次包括第一缓存集合索引Cache Set Index1、缓存标签Cache Tag、第二缓存集合索引Cache Set Index2，以及缓存块偏移Cache Block Offset；其中，位于高位的所述Cache Set Index1和位于低位的所述Cache Set Index2共同组成缓存集合索引Cache Set Index，且所述Cache Set Index1位于所述PPN的覆盖范围内。
在装置实施例中，Cache Set Index1和Cache Set Index2的大小可以相等，或不等。第一映射模块902还用于，将所述Cache Tag分成位于高位的第一缓存标签Cache Tag1和位于低位的第二缓存标签Cache Tag2；且所述Cache Set  Index1位于所述Cache Tag1和所述Cache Tag2之间。其中，所述Cache Tag1和所述Cache Tag2的大小可以相等，或不等。
本发明装置实施例具体可以执行上述如图3、4和5所示的方法，具体功能此处不再赘述。
图10为本发明高速缓冲存储器Cache地址的映射处理装置另一实施例示意图，如图10所示，该装置包括第二获取模块101、第二映射模块102和第三映射模块103，其中，第二获取模块101获取处理核发送的访问地址所对应的伪物理地址，所述伪物理地址包括伪物理页面号和伪页偏移；其中，所述伪物理页面号中包括第一地址部分，所述伪页偏移包括第二地址部分，所述第一地址部分与所述第二地址部分大小相同；第二映射模块102用于通过将所述第一地址部分与所述第二地址部分互换位置以完成将所述伪物理地址映射成真实物理地址，所述真实物理地址包括真实物理页面号PPN和页偏移；其中，所述PPN包括所述第二地址部分，所述页偏移包括所述第一地址部分；第三映射模块103用于将所述真实物理地址映射成Cache地址，所述Cache地址包括缓存标签Cache Tag、缓存集合索引Cache Set Index，以及缓存块偏移Cache Block Offset；其中，所述第一地址部分位于所述Cache Set Index的覆盖范围内。
本发明装置实施例具体可以执行上述如图6、7和8所示的方法，具体功能此处不再赘述。
本发明实施例提供的高速缓冲存储器Cache地址的映射处理装置，通过将大页面PPN的某些位映射到Cache的Set Index中，因此可以被操作系统用来着色，满足同时使用大页面技术和页着色划分Cache技术的需求，并获得大页面和页着色划分Cache的性能提升；而且所有的改动都只是地址映射关系的改变，不增加额外的电路；地址映射的改动能保证一一映射，不需要操作系统管理。
在本发明所提供的几个实施例中，应该理解到，所揭露的装置和方法， 可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
上述以软件功能单元的形式实现的集成的单元，可以存储在一个计算机可读取存储介质中。上述软件功能单元存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执行本发明各个实施例所述方法的部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本领域技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。上述描述的装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (13)

  1. 一种高速缓冲存储器Cache中数据的访问方法，其特征在于，包括：
    获取处理核发送的访问地址所对应的伪物理地址，所述伪物理地址是通过查询页表由所述访问地址转换得到，所述伪物理地址包括伪物理页面号和伪页偏移；其中，所述伪物理页面号中包括第一地址部分，所述伪页偏移包括第二地址部分，用来表示所述第一地址部分与所述第二地址部分的比特位数相同；
    将所述伪物理地址中的所述第一地址部分与所述第二地址部分的比特数值进行互换得到真实物理地址，所述真实物理地址包括真实物理页面号和页偏移，其中，用来表示所述真实物理页面号和所述伪物理页面号的比特位数相同，用来表示所述页偏移和所述伪页偏移的比特位数相同，所述第二地址部分位于所述真实物理页面号的比特范围内，所述第一地址部分位于所述页偏移的比特覆盖范围内；
    将所述真实物理地址转化为Cache地址，所述Cache地址包括缓存标签Cache Tag、缓存集合索引Cache Set Index，以及缓存块偏移Cache Block Offset；其中，用来表示所述第一地址部分的比特位位于所述Cache Set Index的比特覆盖范围内。
  2. 根据权利要求1所述的方法，其特征在于，所述将所述伪物理地址转换成真实物理地址具体通过可编程寄存器控制完成。
  3. 一种高速缓冲存储器Cache地址的映射处理方法，其特征在于，包括：
    获取处理核发送的访问地址所对应的物理地址，所述物理地址包括物理页面号和页偏移；
    将所述物理地址映射成Cache地址，所述Cache地址依次包括第一缓存集合索引Cache Set Index1、缓存标签Cache Tag、第二缓存集合索引Cache Set Index2，以及缓存块偏移Cache Block Offset；其中，位于高位的所述Cache Set Index1和位于低位的所述Cache Set Index2共同组成缓存集合索引Cache Set Index，且所述Cache Set Index1位于所述物理页面号的比特覆盖范围内。
  4. 根据权利要求3所述的方法，其特征在于，用来表示所述Cache Set Index1和所述Cache Set Index2的比特位数相同。
  5. 根据权利要求3或4所述的方法，其特征在于，所述方法还包括：
    所述Cache Tag包括位于高位的第一缓存标签Cache Tag1和位于低位的第二缓存标签Cache Tag2；且所述Cache Set Index1位于所述Cache Tag1和所述Cache Tag2之间。
  6. 根据权利要求5所述的方法，其特征在于，用来表示所述Cache Tag1和所述Cache Tag2的比特位数相同。
  7. 根据权利要求3所述的方法，其特征在于，所述将所述物理地址映射成Cache地址具体通过可编程寄存器控制完成。
  8. 一种高速缓冲存储器Cache地址的映射处理装置，其特征在于，包括：
    第二获取模块，获取处理核发送的访问地址所对应的伪物理地址，所述伪物理地址是通过查询页表将所述访问地址转换得到，所述伪物理地址包括伪物理页面号和伪页偏移；其中，所述伪物理页面号中包括第一地址部分，所述伪页偏移包括第二地址部分，用来表示所述第一地址部分与所述第二地址部分的比特位数相同；
    第二映射模块，用于将所述伪物理地址中的所述第一地址部分与所述第二地址部分的数值进行互换得到真实物理地址，所述真实物理地址包括真实物理页面号和页偏移；其中，用来表示所述真实物理页面号和所述伪物理页面号的比特位数相同，用来标识所述页偏移和所述伪页偏移的比特位数相同，所述第二地址部分位于所述真实物理页面号的比特范围内，所述第一地址部分位于所述页偏移的比特覆盖范围内；
    第三映射模块，用于将所述真实物理地址转化成Cache地址，所述Cache地址包括缓存标签Cache Tag、缓存集合索引Cache Set Index，以及缓存块偏移Cache Block Offset；其中，用来表示所述第一地址部分的比特位位于所述Cache Set Index的比特覆盖范围内。
  9. 根据权利要求8所述的方法，其特征在于，所述将所述伪物理地址转换成真实物理地址具体通过可编程寄存器控制完成。
  10. 高速缓冲存储器Cache地址的映射处理装置，其特征在于，包括：
    第一获取模块，用于获取处理核发送的访问地址所对应的物理地址，所述物理地址包括物理页面号和页偏移；
    第一映射模块，用于将所述物理地址映射成Cache地址，所述Cache地址依次包括第一缓存集合索引Cache Set Index1、缓存标签Cache Tag、第二缓存集合索引Cache Set Index2，以及缓存块偏移Cache Block Offset；其中，位于高位的所述Cache Set Index1和位于低位的所述Cache Set Index2共同组成缓存集合索引Cache Set Index，且所述Cache Set Index1位于所述物理页面号的比特覆盖范围内。
  11. 根据权利要求10所述的装置，其特征在于，用来表示所述Cache Set Index1和所述Cache Set Index2的比特位数相同。
  12. 根据权利要求10或11所述的装置，其特征在于，所述第一映射模块还用于，将所述Cache Tag分成位于高位的第一缓存标签Cache Tag1和位于低位的第二缓存标签Cache Tag2；且所述Cache Set Index1位于所述Cache Tag1和所述Cache Tag2之间。
  13. 根据权利要求12所述的装置，其特征在于，用来表示所述Cache Tag1和所述Cache Tag2的比特位数相同。
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