WO2015128168A1 - Procédé et dispositif de classification et/ou génération de bits aléatoires - Google Patents

Procédé et dispositif de classification et/ou génération de bits aléatoires Download PDF

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Publication number
WO2015128168A1
WO2015128168A1 PCT/EP2015/052486 EP2015052486W WO2015128168A1 WO 2015128168 A1 WO2015128168 A1 WO 2015128168A1 EP 2015052486 W EP2015052486 W EP 2015052486W WO 2015128168 A1 WO2015128168 A1 WO 2015128168A1
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WO
WIPO (PCT)
Prior art keywords
random
signal
output
bits
bit patterns
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PCT/EP2015/052486
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German (de)
English (en)
Inventor
Markus Dichtl
Original Assignee
Siemens Aktiengesellschaft
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Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO2015128168A1 publication Critical patent/WO2015128168A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators

Definitions

  • the present invention relates to an apparatus and method for classifying and / or generating one or more random bits. For example, a random bit sequence is generated, which is used as a binary random number.
  • the proposed devices and methods for generating random bits serve, for example, the implementation of random number generators.
  • the invention allows for example ⁇ as the generation of true random bits.
  • the proposed methods and devices are used in ⁇ example, the detection of random bits or Zufallsbitfol ⁇ gene, which have good random properties, and on the other hand bits that are considered not random. Random data is required at ⁇ play, in security applications, wherein the generated random bits from, for example, cryptographic Keyring ⁇ sel or the like can be derived.
  • random bit sequences are necessary as binary random numbers. It is desirable , in particular for mobile applications, to operate as little hardware as possible.
  • Known measures for generating random numbers are, for example, pseudo-random number generators, analogue random sources, ring oscillators and their modifications.
  • Seeds are used based on which deterministic Pseudozufausstage be ⁇ expects to be.
  • a physical random number generator is usually used.
  • Fibonacci and Galois ring oscillators can have chaotic vibration states and produce faster ⁇ mature waveforms as a classic ring oscillators. ⁇ all recently various digital gates such as XOR and NOT gate are used. This may result in ASICs large differences in speed of the gate types especially in the ⁇ plement isten. Often, there is a desire to generate random bit sequences using FPGAs (Field Programmable Gate Arrays). However can use periodic vibrations, which only have a low En ⁇ entropy or randomness in the signals even at these digital components. The cause of these periodic oscillations is not yet known; their presence may depend on environmental conditions such as temperature ⁇ ture, but also from chip-specific variations in manufacturing.
  • the bits generated have the same occurrence probability of 0- and 1-bits and are statistically independent of each other.
  • high entropy devices are desired.
  • the random event-are nisse can be used as random-giving properties.
  • a method for classifying and / or generating random bits comprises the steps of: providing output signals of logical elemene ⁇ th of a ring oscillator circuit, wherein the logical elements are at least partially fed back and each outputting an input signal into an output signal;
  • Classifying a selected output signal as random coincidence signal or non-randomly with a number of different bit patterns is counted in Depending ⁇ speed of the frequency of the occurring bit patterns.
  • a ring oscillator circuit is to be understood not only the classical variant of an odd number of inverters in a logical ring structure, but z.
  • generalizations such as Fibonacci or Galois ring oscillators and generally at least partially mannge ⁇ coupled oscillating logic circuits.
  • the proposed method for classifying and / or He ⁇ evidence of random bits is particularly suitable for implemen ⁇ tation as an online test to classify, for example, in FPGAs implemen ⁇ oriented ring oscillators to be used to generate random bits. Is for example detected depending on the frequency of the occurring ⁇ Bitmus ter that a sufficient coincidence exists, a Zufallsbit composition is suppressed. On the other hand, a correspondingly reliable truly random signal can be merit ⁇ attacked upon detection of random waveforms or chaotic waveforms, for example, at one of the Huaweisigna ⁇ le. In embodiments, the method further comprises: determining a number of different bit patterns which were recognized to be different ⁇ union sampling time points.
  • clocked or at predetermined Zeitab ⁇ states or at times the output signals from a selection of z. B. implemented as an inverter implemented logical Ele ⁇ elements.
  • the bit patterns are resulting preference ⁇ be stored and counted for the occurrence of frequency.
  • the method further comprises a
  • Step of comparing the number of different bit patterns with a threshold can be fixed to the effect set that, for example, if the number under ⁇ Kunststoffaji bit pattern is too small, it is concluded that no sufficient randomness of the output signals is present.
  • the excluded selected output signal is output as a random signal if ei ⁇ ne number of different sampling time points erank- ten different bit patterns is greater than a specified differently Bener threshold. It is proposed that, if the various zugeord ⁇ Neten check bits at the outputs of the logic elements, wherein ⁇ play, the inverter forming, as many different bit ⁇ pattern, ge ⁇ joined to a sufficient randomness. This can substantially excluded that static or periodic oscillatory levels at ⁇ present in the respective ring oscillator.
  • the frequency of the occurring bit pattern ⁇ over a predetermined number of sampling times can be determined. For example, the classification of the respective ring oscillator circuit having an odd number of inverters through a limited number of play determined several thousand times a bit pattern in ⁇ .
  • the number of the predetermined sampling points in time is Example ⁇ determined depending on the number of simultaneously erutz- th output signals.
  • further sampling the random signal to generate a random bit may be performed.
  • the random signal recognized as happens to have a temporally irregular shapes ⁇ ssige waveform and varies randomly between a logi ⁇ rule H and L level. Only by scanning, for example by means of a buffer element, such as a flip-flop, a fixed random bit value is generated. This results randomly a logical H or L level at the output of the respective flip-flops.
  • an apparatus for generating random bits which comprises:
  • a ring oscillator circuit having a plurality of at least partially fed-back logic elements each outputting an input signal to an output signal
  • a sampling device which is set up to simultaneously detect a plurality of the output signals and to assign a check bit to each detected output signal, the simultaneously detected check bits forming a bit pattern
  • an evaluation device which is set up to determine a frequency encountered bit patterns in a multiple simultaneous capturing, wherein the Ausenseein ⁇ direction is further adapted to count a number of Various ⁇ NEN bit patterns.
  • the device is in particular configured to carry out a method as described above and below.
  • the device comprises a ring oscillator circuit, which usually consists of an odd number of
  • Inverter is formed. Some of the feedback paths ⁇ then deliver a mostly random vibration behavior. However, it may happen that the ring oscillator circuit enters a static state or periodic oscillator circuit. pean state expires, so that the output node of the logic elements is usually not enough random Sig ⁇ nal longer be tapped.
  • the used Ringoszillatorschalt ⁇ circle can be configured in particular as a Fibonacci or Galois ring oscillator.
  • the pre ⁇ device and method allow an online test without consuming memory or computing operations.
  • the ring oscillator circuit may further comprise an output at which one of the réellesig ⁇ signals can be tapped off as a random signal.
  • the scanning device comprises a plurality of sample and hold elements for detecting the plurality of output signals of different logic elements.
  • the sample and hold members may be clocked or controlled by a controller.
  • the sample and hold elements set there ⁇ at the detected signal level in a sketchbitpegel.
  • the device is part of an FPGA device or an ASIC device.
  • the method can be implemented on or in an FPGA or ASIC device via suitable description languages, for example VHDL or Verilog.
  • a computer program product such as a computer program means can be used, for example, as a storage medium, such as a memory card, USB stick, CD-ROM, DVD or even in the form of a
  • downloadable file from a server in a network be ⁇ provided or delivered. This can be done, for example, in a wireless communication network by transmitting a corresponding file with the computer program product or the computer program means.
  • programmge ⁇ controlled device in particular a Steuereinrich ⁇ processing, such as a microprocessor for a smart card or the like out of the question.
  • the method or device may also be hardwired or implemented in configurable FPGAs or ASICSs.
  • a data carrier is provided with a stored Compu ⁇ terprogramm with commands, which cause the imple ⁇ tion of a corresponding method on a programmge ⁇ controlled device.
  • FIG. 1 is a schematic flow diagram for a method for classifying random bits
  • Fig. 2 is a schematic illustration of an embodiment of an apparatus for generating and classifying random bits
  • Fig. 1 is a schematic flow diagram for a method for classifying or generating random bits is shown, which for example with a device as ⁇ sify as a schematic representation as from ⁇ exemplary implementation of an apparatus for generating and Klas in Fig. 2 of Random bits is shown can be performed.
  • the method and apparatus are suitable for example to at random number generators that produce with the help of Ringo ⁇ zillatoren random waveforms to detect whether an unwanted oscillation occurs. In this case, a fault alarm can be triggered so that he testified ⁇ bits are not used as random bits.
  • the ring oscillator 2 comprises an odd number of inverters 2i - 2 n, which are chained together.
  • everybody the inverter 2i - has 2 n an input and an output, which is not explicitly referred to.
  • At the respective input input signals are egg - E n received, the inverted as from ⁇ output signals Ai - output A n.
  • feedback loops are provided which cause an irregular waveform within the ring oscillator circuit.
  • a feedback is provided in the exporting ⁇ approximately example of FIG. 2, for example between the pth and p + l-th inverter.
  • a Zufallssig ⁇ nal ZS can be tapped.
  • the random signal ZS corresponds to the output signal A n of the n-th inverter 2 n .
  • ring oscillators for example in the form of Galois or Fibonacci oscillators conceivable.
  • further logi ⁇ cal elements can be provided.
  • the plurality captivesig ⁇ dimensional p A q 2 are detected for generating check bits.
  • the qp check bits are generated in egg ⁇ ner scanning device 3 by means of qp sample and hold members 3 P - 3 q .
  • the sample and hold members each have a clock input to which a clock signal or Abtastsig ⁇ signal CK is supplied.
  • the sample and hold elements In response to the clock or sampling signal CK, the sample and hold elements provide 3 P - 3 q From a logical ⁇ output level, as the check bit P p - P q is used.
  • the scanning example ⁇ at predetermined times several times in succession or in response to the clock signal CK performed by a control ⁇ device 5.
  • the qp check bits P P - P q are fed to a memory device 4, which stores the check bits P P - P q for a respective sampling time as a bit pattern BMi - BMi.
  • the memory 4 is coupled to the control device 5 via control or data signals CT. Further, the control unit 5 con- trols a set or start input 7 the ringos ⁇ zillatorschalt Vietnamese 2.
  • To start a (chaotic or irregular) oscillation of the concatenated in- verter 2 i - n 2 are, for example, initially all input signals Ei ⁇ - E n first brought to a predetermined well-defined level. The oscillation is triggered by a signal edge is coupled, for example, as the start input signal Ei and the remaining input signal level E 2 - E n are left freely oscillating.
  • an assignment of the simultaneously detected check bits P p -P q to a respective bit pattern BMi takes place in step S3.
  • step S40 the number of different bit patterns B lr detected at different sampling times is determined.
  • the number of different bit patterns that occur is recorded.
  • the number of different bit patterns is compared with a threshold value in a comparison step S41.
  • the threshold value can be adjusted as desired and determines, for example, the
  • Sensitivity of the test or classification process for random or non-random data It is recognized that only a few different bit patterns are present at the different output Signals A p - A n are derived, so the number is below the predetermined threshold, the ring oscillator or the output signal A n or ZS is classified as not random in step S42.
  • the control means 5 may, for example, a match of the ⁇ alarm or warning signal to a warning output A 10 out ⁇ ben.
  • the control device 5 can also prevent an output of the signal ⁇ ZS.
  • step S5 in the sequence in step S5, for example, according to FIG. Controlled by the control means 5, the corresponding n-random ⁇ signal ZS to the n-th output of the inverter 2 scanned.
  • the scanning can be done with the aid of a buffer device, such as a flip-flop 6.
  • the flip-flop 6 provides from the oszillie ⁇ leaders, with a non-defined logic level behafte ⁇ th random signal ZS a random bit with a level 1 or 0. This example random bit is output at the output. 9
  • the apparatus and method provide a reliable means of generating true random bits.
  • a Ringos ⁇ zillator 11 is reproduced, which is designed as a Fibonacci ring oscillator.
  • inverters 2i-2 7 There are seven concatenated inverters 2i-2 7 , wherein feedbacks according to the feedback polynomial x 7 + x 6 + x 3 + x 2 + x + 1 are implemented. From seven ⁇ output signals Ai are 2 7 - - A 7 tapped at the JE tinct outputs of inverters 2i. This tapped off ⁇ output signals can check bits Pi - P are assigned. 7 The seven check bits Pi - P7 form a bit pattern BM ⁇ at each sampling time.
  • FIGS. 4, 5 and 6 signal forms of the output signal A 7 are now reproduced, which can be regarded as a random signal ZS.
  • FIG. 7 shows a further embodiment of a
  • Fibonacci ring oscillator 12 Essentially the same elements as in FIG. 3 are included, but with the feedback polynomial chosen to be x 7 + x 6 + x 2 + 1. Looking now at the waveform A 7 at the output of the last inverter 2 7 results in a uniform vibration behavior. That is, as shown in FIG. 8, a periodi ⁇ shear oszillativer of the output signal A 7 to erken ⁇ NEN having hardly random properties. The ring oscillator, as shown in FIG. 7, is therefore not suitable for generating random bits.
  • bit pattern BM X over 5000 passes.
  • 5000 samples of check bits Pi-P 7 were made at intervals of 200 ns.
  • le ⁇ diglich 14 of the 128 possible bit patterns have been generated by 7 bits.
  • the number of encountered bit patterns differ completely fixed ⁇ Lich with values of 14 in the case of periodically oscillating generator and of 123 in the case of chaotic oscillations.
  • the choice of the threshold value is therefore not critical.
  • a suitable threshold may be set at 50, recognizing that there are only 14 different bit patterns, that is, the number of different bit patterns of 7 bits over 5,000 passes, or clock or sample times below the threshold of 50.
  • the exact threshold value can be adapted to the number and length of the inverter chains.
  • Fibonacci ring oscillators were the length of 16 tested with different return Kopp ⁇ lungspolynomen. For each 5000 samples spaced 2 ps, 16 bit long bit patterns BMi have been considered. Those feedback polynomials that lead to periodic oscillations ⁇ conditions, only resulted in 32, 40, 51 and 62 ver ⁇ different test bit patterns. at 26 other feedback poly ⁇ nomen that lead to chaotic oscillations, the number of different detected bit patterns between 1261 and 2154th In this respect, for example, in Fibonacci ring oscillators of length 16, a threshold for different bit patterns between 200 and 500 are selected.
  • the method provides a cost-effective online test for especially implemented in FPGA random bit generators that use ring oscillators. This results in a reliable detection of malfunctions, and thus periodic oszilla ⁇ toric behavior of the ring oscillator used. It is required only a small memory requirements, as the 2 p ⁇ only one bit location will be for each compels ⁇ q possible bit patterns. By a suitable choice of the decoupled check bits, the method and the hardware expenditure can be scaled. It is also possible, for example Fibonacci Ringoszil ⁇ simulators with 16 inverters used only a selection of output signals, for example, the first eight administratsig ⁇ dimensional Ai - to use A 8.
  • Fibonacci ring oscillators were tested in the above examples, this can be applied equally to at ⁇ wider complicated ring oscillators.
  • the method can be used in particular for Galois ring oscillators for Zufallsbiterzeugung.

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Abstract

L'invention concerne un procédé et un dispositif (1) permettant la classification et/ou la génération de bits aléatoires (ZB). Ledit procédé comprend les étapes suivantes : la préparation (S1) de signaux de sortie (A1 - An) d'éléments logiques (21 - 2n) d'un circuit d'oscillateur annulaire (2), les éléments logiques (21 - 2m) étant au moins en partie réinjectés et chaque signal d'entrée (E1 - En) donnant en sortie un signal de sortie (A1 - An); la détection simultanée (S2) de plusieurs signaux de sortie (Ap - Aq) de différents éléments logiques (2p - 2q) du circuit d'oscillateur annulaire (2) afin de générer des bits de vérification (Pp - Pq); l'attribution (S3) des bits de vérification (Pp - Pq) détectés simultanément à un modèle de bits respectif (BMi); et la classification (S4) d'un signal de sortie sélectionné (An) en tant que signal aléatoire (ZS) aléatoire ou non aléatoire en fonction d'une fréquence d'apparition du modèle de bits (Bi).
PCT/EP2015/052486 2014-02-28 2015-02-06 Procédé et dispositif de classification et/ou génération de bits aléatoires WO2015128168A1 (fr)

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DE102014203649.6 2014-02-28
DE201410203649 DE102014203649A1 (de) 2014-02-28 2014-02-28 Verfahren und Vorrichtung zum Klassifizieren und/oder Erzeugen von Zufallsbits

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Publication number Priority date Publication date Assignee Title
DE102014224423A1 (de) * 2014-11-28 2016-06-02 Siemens Aktiengesellschaft Verfahren und Vorrichtung zum Messen eines Jitters
DE102014226996A1 (de) * 2014-12-29 2016-06-30 Siemens Aktiengesellschaft Verfahren und Vorrichtung zum Erzeugen von Zufallsbits

Citations (3)

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US20040205095A1 (en) * 2003-04-14 2004-10-14 M-Systems Flash Disk Pioneers Ltd. Random number slip and swap generators
EP1686458A1 (fr) * 2005-01-28 2006-08-02 Infineon Technologies AG Générateur de numéros aléatoires basé sur des oscillateurs
DE102012210361A1 (de) * 2012-06-20 2013-12-24 Robert Bosch Gmbh Verfahren zum Überwachen einer Ausgabe eines Zufallsgenerators

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040205095A1 (en) * 2003-04-14 2004-10-14 M-Systems Flash Disk Pioneers Ltd. Random number slip and swap generators
EP1686458A1 (fr) * 2005-01-28 2006-08-02 Infineon Technologies AG Générateur de numéros aléatoires basé sur des oscillateurs
DE102012210361A1 (de) * 2012-06-20 2013-12-24 Robert Bosch Gmbh Verfahren zum Überwachen einer Ausgabe eines Zufallsgenerators

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BOHL E ET AL: "A fault attack robust TRNG", ON-LINE TESTING SYMPOSIUM (IOLTS), 2012 IEEE 18TH INTERNATIONAL, IEEE, 27 June 2012 (2012-06-27), pages 114 - 117, XP032243089, ISBN: 978-1-4673-2082-5, DOI: 10.1109/IOLTS.2012.6313851 *

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