WO2015128015A1 - Dispositif et procédé de génération de bits aléatoires - Google Patents

Dispositif et procédé de génération de bits aléatoires Download PDF

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Publication number
WO2015128015A1
WO2015128015A1 PCT/EP2014/077152 EP2014077152W WO2015128015A1 WO 2015128015 A1 WO2015128015 A1 WO 2015128015A1 EP 2014077152 W EP2014077152 W EP 2014077152W WO 2015128015 A1 WO2015128015 A1 WO 2015128015A1
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Prior art keywords
input
signal
signals
imaging
combinatorial
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PCT/EP2014/077152
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German (de)
English (en)
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Markus Dichtl
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Siemens Aktiengesellschaft
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Publication of WO2015128015A1 publication Critical patent/WO2015128015A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/588—Random number generators, i.e. based on natural stochastic processes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/004—Counters counting in a non-natural counting order, e.g. random counters

Definitions

  • the present invention relates to an apparatus and method for generating one or more random bits. For example, a random bit sequence is generated which is used as a binary random number.
  • the proposed pre ⁇ devices and methods for generating random bits are used, for example, the implementation of random number generator ⁇ ren.
  • the invention enables the generation of a true random bits.
  • random bit ⁇ are necessarily follow as a binary random numbers. It is desirable , in particular for mobile applications, to operate as little hardware as possible.
  • Known measures for generating random numbers are, for example, pseudo-random number generators, analogue random sources, ring oscillators and their modifications.
  • pseudo-random number generators seeds are used, from which deterministic pseudo-random numbers are calculated. To create the seed, a physical random number generator is usually used.
  • analog event sources to be ⁇ noise sources, such as the noise of Zener diodes, amplified and digitized. The Ver ⁇ connection is usually only be realized by consuming digital with analog circuitry.
  • ring oscillators which are composed of an odd number of inverters connected back ⁇ behind the other, there are random jitter from fluctuating transit times of the signals through the inverter.
  • This jitter thus a irr ⁇ moderate time variation in state changes of the sent signals by the inverters, can at multiple
  • Fibonacci and Galois ring oscillators generate faster ⁇ due waveforms as a classic ring oscillators.
  • ⁇ all recently various digital gates such as XOR and NOT gate are used.
  • FPGAs Field Programmable Gate Arrays
  • FPGAs Field Programmable Gate Arrays
  • the power consumption in the materiality ⁇ union depends on the number of switching operations per time. In the case of corresponding digital oscillating circuits, this must take place continuously, so that a rather unfavorable energy consumption arises in the case of ring oscillator-based random number generators. In particular in mobile applications, it is Wanting ⁇ 's worth keeping the energy consumption and power consumption of the hardware circuits implemented small. However, a statistically good physical random should be ent ⁇ . It is therefore an object of the present invention to provide an improved apparatus and / or a method for generating random bits.
  • an apparatus for generating random bits which comprises: a plurality of concatenated imaging devices, wherein a respective Ab Struktursein- is set up direction, a predetermined number n image a ⁇ output signals by means of a combinatorial image into a predetermined number p output signals.
  • Minim ⁇ least a combinatorial figure is configured such that a change in state of an input signal of a jewei ⁇ time imaging device to an average of more than one from ⁇ output signal of the respective imaging means is displayed.
  • a Starteinrich ⁇ tung is adapted to couple a first imaging device of the plurality of concatenated imaging devices well-defined logic level change as input start signals.
  • a detection device is particularly since ⁇ be configured to output one or more output signals to off ⁇ transitions of one or more imaging devices, which are different from the first imaging means to scan, and as a respective random bits. Since ⁇ wherein the device is for example arranged such that different random bits are recorded in directly successive level changes of at least one input start signal with the aid of Er chargedsvorrich ⁇ processing.
  • a sensing takes place for example by sampling, game as clocked at ⁇ or at predetermined different time points and used to derive a bit value H or L, the up- Due to the highly fluctuating random signal having a high entropy or randomness En ⁇ .
  • the resulting bit value (s) may be understood as a random bit. Due to the predetermined level changes, for example, from a logic low level (0) to a logic high level (1) or vice versa, a passage of the signal change is set in motion by the chain of imaging devices due to the logical Schmsein ⁇ directions. Due to the statistical fluctuations of the gate cycle times, jitter occurs. The sampling in each case picks up a random level, which is assigned by the detection device to a respective random bit value.
  • the Zufallsbiter ⁇ version takes place in particular both at a level change from zero to one and subsequently back to zero. One can speak of a double-stroke random number generator.
  • the detection device is turned rich ⁇ tet to detect the output signals of a final imaging means of the plurality of concatenated Ab Strukturseinrich ⁇ obligations as random bits.
  • a linear chain of combinatorial mapping devices is provided, wherein the chain has level changes on the input side. be signaled by signal edges, and the output side true random signals are sampled.
  • the detection device can be set up to sample an output signal as a function of another output signal.
  • the detection device has, for example, an intermediate ⁇ memory element , in particular a T-flip-flop on.
  • an intermediate ⁇ memory element in particular a T-flip-flop on.
  • flip-flops in particular T-flip-flops
  • the acquisition of the output signals and a mapping to logical random levels can be carried out with great effort.
  • one or more counters for detecting signal edges or state changes of individual signals.
  • a T-flip-flop is particularly suitable for counting rising or falling signal edges modulo 2.
  • the well-defined logical Pe ⁇ gel generated by switching from a first input bit to a second input bit. It may take such a logic level change by switching from a first input bit to a second input ⁇ bit pattern and the sampled output signals ers ⁇ th random bits are assigned.
  • a logical Pegelwech- be by switching from the second input bit pattern to the first input bit pattern second random bits are then ordered ⁇ .
  • the detection device is further configured to detect a chronological sequence of state changes of output signals at any well defined logical Pe ⁇ gel carti the input start signals.
  • the imaging devices are such MITEI ⁇ Nander concatenated, that no feedback occurs. This results in that the device is not continuously To ⁇ switching operations must take place as a digital circuit in an implementation, limiting power consumption.
  • the device developed not propagate in a circle no "Schwingun ⁇ gen" or signal change.
  • the output signals are all fed forward.
  • none of the outputs depends causally from himself off by being fed back.
  • the imaging devices are daisy-chained together such that no feedback loop is formed such that a state change is fed to at least an output signal of an imaging device as a change of state of at least one input signal a ande ⁇ ren imaging device.
  • feedback paths can be provided, which however preferably do not lead to oscillations.
  • n is not equal to p, so that the will of the input signals levels at ⁇ on states of output signals shown with the aid of a respective imaging device, wherein the number of the output signals klei ⁇ ner or greater than the number of input signals for a respective Imaging device is.
  • the imaging devices may be logical or kombinatori ⁇ cal gates in particular realizing a bijective mapping of n input signals to n output signals.
  • the input signals vary between levels, the logical supply articles, such as bits 1 and 0, or high or low associated who can ⁇ . Under a bijective mapping is understood ei ⁇ ne-one mapping between the 2 n possible logi ⁇ 's values of the input signals and the 2 n logical values of the output signals.
  • At least one kom ⁇ binatorische figure is configured such that imaged a ⁇ output signals under application of a jitter and a lo cal ⁇ function to the output signals.
  • the hardware implementation of combinatorial mapping by the imaging devices may result
  • Jitter ie fluctuations, in the temporal course of Sig ⁇ nalflanken arise. This jitter is then continued by executing the logical function, ie the mapping of the combination of n input signals or bit values to p output signals or bit values, and accumulates over the passes through the imaging devices.
  • a limited chain of imaging devices results.
  • the Abbil ⁇ training institutions can be a node or gate ⁇ be distinguished.
  • At least one of the combinatorial Some images ⁇ gene is in particular arranged such that a state change occurs in the agent at a change of state of an input signal to more than egg nem output signal. This leads to ⁇ that a respective jitter of the input signal is mapped to several ⁇ re output signals and is therefore amplified.
  • a once occurred jitter in a signal is piert with Hil ⁇ fe of the imaging devices or implemented therein combinatorial images on a plurality of output traces ko ⁇ so that jitter components hardly compensate Kgs ⁇ NEN.
  • the output signals from all the input signals of the other imaging devices are entkop ⁇ pelt.
  • this may be the last imaging device of a chain of m imaging devices that are linearly coupled to one another.
  • the result is more complete insbeson ⁇ a finite waveform.
  • This may mean that a Sig ⁇ Nal or a change of state of a signal is continued only at a predetermined time interval by the concatenated imaging devices.
  • For from a first input imaging device propagates along the concatenated imaging devices a successively with jitter and random contributions propagating random signal or more according to the respective bit width of the imaging devices. Under a decoupling can be understood that the output signals are not performed on inputs other Abbil ⁇ training institutions.
  • At least some of the pictures are not com- binatorischen images which deliver only a permu ⁇ tation of the input signals to the output signals.
  • a permutation of the input signals is present in particular if the output signals are generated the input signals entspre ⁇ surfaces or by merely changing the order of the input signals. In a permutation there is no "duplication" of the jitter.
  • the imaging devices are such Knegrich- tet that their signal propagation times are equal.
  • the risk is reduced by mög ⁇ lichst same signal transit times that jitter contributions can compensate for each other.
  • an implementation in the form of ASICs or Facilitated FPGAs are adapted to all the possible state changes at the respective outputs all within a tolerance in ⁇ tervalls of 100 ps and preferably within 50 ps successes gene.
  • At least one imaging device includes a lookup table or a Nachschla ⁇ getabelle for implementing combinatorial illustration. It is also possible that all imaging devices are provided with one or more respective lookup tables. Lookup tables can be easily read and require only a small amount of hardware. Often in program ⁇ mable logic chips such as FPGAs, corresponding fields or already provided tables.
  • the lookup tables can be filled with random bit values using Zufallselemen ⁇ th.
  • the loopup tables which provide a corresponding output bit pattern at outputs in response to an input bit pattern at inputs of the mapping devices, such that the map represented by the lookup table is randomly selected from all (2 n )! Bijections of n logical signals to n logical signals is selected.
  • the lookup tables Preferably in the
  • Imaging devices each implemented different combinatorial ⁇ maps.
  • fixed levels may initially as a first input bit to the inputs of one of the imaging devices, preferably the first Abbil ⁇ -making device of the chain, are applied to start from a well-defined change of state. At least one of these fixed levels is then switched to another fixed value, resulting in a second input bit pattern. Subsequently, an n or p-bit wide random bit obtained by the concatenated appli ⁇ dung combinatorial pictures to the signals. The switch back to the first input bit pattern results in a subsequent new random bit signal.
  • the predetermined number n or p of input or output signals is at least three.
  • the bit width or the number n and p of predetermined input whiteningswei ⁇ se output signals at the imaging devices four or more.
  • the number of imaging devices in the chain is at least 25. In embodiments, however, between 20 and 1000 concatenated imaging devices are provided.
  • the device is part of an FPGA device or an ASIC device.
  • a method for generating supply moreover wherein a plurality of combinatorial From ⁇ formations concatenated successively be performed.
  • a respective combinatorial Figure forms a specified differently bene number n of input signals to a predetermined number p output signals.
  • At least one combinatorial mapping is selected in such a way that a change in state of an input signal is mapped on average by the combinatorial mappings to more than one output signal.
  • a respective input signal can illustrate ⁇ example, a bit value.
  • the combinatorial mappings can be referred to as n on p mappings.
  • the combinatorial pictures before ⁇ are preferably linked together such that no return Kopp ⁇ lung loop.
  • feedback in which a change of state of at least one input signal a different imaging device is at least an output signal of an imaging device as a change of state to ⁇ supplied to the present example sig- nalpfadaufrich in the chain are avoided.
  • combinatorial images are concatenated only forward or the imaging devices connected in series and operated without feedback.
  • true random bits are generated in the method and apparatus that are independent of the input start signal levels.
  • the waveforms have after the
  • the imaging chain usually no recognizable signal edges or well-defined level changes.
  • the method may in particular said ⁇ via suitable description, such as VHDL or Verilog, can be implemented on or in a FPGA or ASIC device.
  • the Abisersein- are devices preferably arranged such that state changes on an input signal of the n input signals in Ab ⁇ dependence of the combinatorial picture to a moving ⁇ possible time a state change in one or more of the p If possible, produce output signals at the same time.
  • Fig. 1 is a schematic representation of a first guide From ⁇ example of an apparatus for Erzeu gene of random bits
  • Fig. 2 are schematic representations of Insstartsig signals, level changes, Bitmuster patn and lent possible Taktsignalformen.
  • Fig. 3 is a schematic representation of another imple mentation example of an apparatus for Erzeu gene of random bits.
  • functionally identical elements are provided with the same reference numerals, unless stated otherwise.
  • a "well-defined level change” is understood to mean that a substantially rising or falling signal edge is generated, but the respective signal edge can not be reproducibly generated.
  • Depict imaging device to more than one output signal of each ⁇ cocking device means that all possible combinations of input changes state averaged over a réellebitmusteralaub are caused by an image.
  • all or a selection of the combinational maps are configured such that at least one input bit pattern change, for example, where q bits change state, results in an output bit change in which q + 1 bits change state.
  • Fig. 1 shows a schematic representation of a first embodiment of an apparatus for generating random bits.
  • the device 1 is in the manner of a chain of imaging devices 2i - configured 2 m.
  • seri ⁇ ell behind the other combinatorial digital circuits 2i - coupled 2 m.
  • the combinatorial digital circuits 2i - 2 m can also function as logic gates or imaging devices for a respective combinatorial Figure Ki - K m verstan ⁇ be.
  • a starting means 3 which festgeleg ⁇ te values for the input signals ESu - ESi n for the first exhaust school 2i provides and generates assuming Pe ⁇ gel Pizza for this input start signals.
  • the da ⁇ by resulting signal edges are continued through the chain of figures.
  • To the last output image direction 2 m of the chain is coupled to a detection or Abtastvor ⁇ direction 4, which detects the output signals A m i - A mn of the last imaging device 2 m .
  • the random bit signal or random bit pattern ZB thus generated can be supplied to an optional evaluation device 9.
  • the evaluation unit 9 subjects the detected random bits ⁇ example, for example, using statistical methods in a post-processing to compensate for leaning in the generated random bits. This gives the output true random bits ZB x .
  • a skew of generated random bits denotes the ratio of the components of zeros and ones. In an idea ⁇ len skewness a distribution of random bits of 1 and 0 with a probability of 0.5 is present. A skew of 2% means that a probability for an H level or a one is 0.52.
  • the inputs and outputs are not explicitly indicated.
  • An ever ⁇ stays awhile imaging device 2 in that receives En - E in input signals and outputs An - A ip output signals.
  • jitter-prone signals propagate from the first input imager 2i to the output imager. furnishing 2 m .
  • the imaging devices 2i - 2 m are ⁇ art as combinatorial pictures Ki - K m implemented that on average a change of state of present on a respective input signal e i k - e kn at a réelleswech- be in more than one of the output signals A k i - A kn leads. That is, a change in a respective input bit or logic state of an input signal E k] results, on average (for example, over a number of passes), in changes in more than one of the output bits of the respective node or imaging device.
  • the imaging devices must 2i - 2 m not necessarily the same number n of inputs and outputs have.
  • the n channels arise with random Signalfor ⁇ men, which are caused by the jitter that of the digital switching devices constituting switching elements are caused.
  • the schematically indicated device for generating random bits 1 can be realized, in particular, at low cost in FPGA or ASIC devices.
  • ionel ⁇ len ring oscillators can be at a higher data rate random bits produce because of the particular random beneficiaries ⁇ tigende jitter by means of the multiple channels is multiplied potentially n times. It is unlikely that Jitter's contributions compensate each other because of the many channels and images.
  • a Randallzah ⁇ lengenerator can be realized with a high random bit-generating frequency at low cost.
  • At least 20 imaging devices are provided with each other in a chain.
  • 50 or 100 images are sorted ⁇ but conceivable.
  • the number of concatenated images or Abbil ⁇ training institutions between 50 and 100.
  • exporting approximately ⁇ form the number devices between 100 and 1,000 imaging.
  • Fig. 2 shows schematically input start signals, Pegelwech ⁇ sel, bit pattern change and possible clock signal forms.
  • input signal levels ESu... E s4 are changed so that well-defined level changes PW occur.
  • the level change PW or the corresponding signal edge or signal edges are guided through the imaging chain as described above.
  • a possible input bit BMI is above Darge provides ⁇ in Fig. 3.
  • All input start signals ES are at logical L level, as indicated in the middle diagram.
  • the lower curve shows a possible time profile of a clock or sampling signal CK for the sampling device 4.
  • This process is repeated, so that ⁇ (BMI BM2 on the one hand and on the other hand BM2 on BMI) at two different Jump start level or nowadayssbitmus- terver sectionieux two different sets of random bits he ⁇ be generated.
  • the random bits for the Sampling times Tl and T3 are then subjected to the same or as a random bit aftertreatment.
  • Ana ⁇ log is followed by a post-treatment for the random bits from the runs with BM2 on BMI (eg at T2).
  • Randomization and heavy jittering are more likely to lack well-defined logic levels in the hardware-implemented random-bit-generating device.
  • the table can be implemented as a look-up table for forming the mapping device 2 q .
  • a bijective mapping is implemented such that every possible bit pattern consisting of four input bits or input signal states E q i, E q 2, E q3 , E q4 occurs exactly once at the outputs of the mapping device 2 q as output signal states A q i, A q2 , A q3 , A q4 occurs on ⁇ .
  • the state change of the input signal E q i from 0 to 1 is determined by means of the combinatorial mapping K q to the three output signals A q i, A q3 and A q4 " Because the output signal A qi changes from 0 to 1 due to the state change of E q i, the output signal A q3 changes from 1 to 0 and the output signal A q4 changes from 0 to 1.
  • An input bit pattern of 0010 leads to an output bit pattern 0011 (compare third row of the table).
  • bit pattern 0000 Starting from a bit pattern 0000 and a state change of the input signal E q2 from 0 to 1, therefore, state changes occur in the case of the three output signals A q i, A q2 and A q3 , although only one input-side state change has occurred in the input signal E q2 .
  • Analog can be seen for input bit 0100 and 1000 ⁇ out from 0000 that change three or all four output states.
  • the jitter which is used as a random phenomenon, is thus amplified and distributed over several channels.
  • OR is a logical OR
  • AND is a logical AND
  • NOT is a logical
  • combinatorial mappings may be used instead of a lookup
  • Table can also be realized as a logical gate connection as shown above.
  • the disjunctive normal form ⁇ representation can also be written in an algebraic normal form ⁇ which can also be used for the design of corresponding logic circuits. You can write:
  • a q4 XOR [E q i, E q3 , E q4 ]
  • a q3 NOT [XOR (E q1 , E q2 , E q4 , AND [E q4 , E q2 , E q1 ], AND [E q4 , E q3 , E q2 ])]
  • a q2 XOR [E q2 , E q3 , E q4 , AND (E q3 , E q1 ), AND (E q4 , E q3 )]
  • a q i XOR [E q i, E q2 , E q3 , E q4 , AND (E q3 , E q i), AND (E q3 , E q2 , E ql )
  • Output signal depends on as many input signals. It would be particularly preferable that each output signal of a combinatorial mapping of all input signals for the Figure is dependent. Then, jitter would multiply particularly well in the Signa ⁇ len and reinforce.
  • each combinatorial pictures shows m ex forming apparatuses 2i Ki - implement K m where the bit width of the pictures is not constant example, the Ab ⁇ forming apparatuses 2i and 2k -.. 2 m implemented as combinatorial From ⁇ formations, which represent four input signals on four output signals.
  • the starting device 3 may toggle between input bit patterns, as indicated in FIG. 2, to generate level changes.
  • the implemented in the third imaging device 2 3 combinatorial image K 3 maps five input signals to five output signals.
  • the fourth combinational mapping K 4 implemented by means of the imaging device 2 4 maps five input to four output signals.
  • the output signal An is inverted by means of an inverter 8 into an input signal E 2 i for the second imaging device 2 2 .
  • the two output signals Ai 3 and A i4 of the first imaging device 2i are using a logical
  • Gates 7 rounded together and as input signal E 2 3 of the second imaging device 2 2 supplied.
  • the output signals A m -A i m4 are supplied to a Er fertilsvorrich ⁇ tung 4, comprising four toggle flip-flop 6.
  • the respective toggle flip-flop 6 counts the rising signal ⁇ flanks than 0 to 1 passages modulo 2.
  • the respective random example are then tapped.
  • the output of the random bits ZB is clock-controlled.
  • the proposed device and the underlying method are particularly suitable for implementation in ASICs.
  • the logical functions of the imaging devices preferably have the same logical depth in order to achieve the same signal transit time of the combinatorial mappings. In this respect, lookup tables can also be dispensed with. So that He ⁇ invention also enabling fast random ⁇ bit generation with low hardware cost.

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Abstract

L'invention concerne un dispositif (1) servant à la génération de bits aléatoires (ZB) qui comprend plusieurs systèmes de représentation (21 - 2m). Chaque système de représentation (21 - 2m) est configuré pour représenter un nombre prédéfini n de signaux d'entrée (E11 - Emn) à l'aide d'une représentation combinatoire (K1 - Km) en un nombre prédéfini p de signaux de sortie (A11 - Amp). Les systèmes de représentation (21 - 2m) sont chaînés les uns à la suite des autres et au moins une représentation combinatoire (K1 - Km) est configurée de telle manière qu'une modification d'état d'un signal d'entrée (E11 - Emn) d'un système de représentation (21 - 2m) est représentée en moyenne sur plus d'un signal de sortie (A11 - Amp) dudit système de représentation (21 - 2m). Aucune boucle de réinjection n'est présente de telle manière qu'une modification d'état d'au moins un signal de sortie de réinjection (Aij) d'un certain système de représentation (2i) est exécutée en tant que modification d'état d'au moins un signal d'entrée (Ekl) d'un autre système de représentation (2k) de telle manière qu'un ou plusieurs signaux de sortie (Ai1 - Aip) du certain système de représentation (2i) sont influencés par la modification d'état du signal de sortie de réinjection (A11). Un système de démarrage (3) est configuré afin de coupler à un premier système de représentation (21) de la pluralité des systèmes de représentations chaînés les uns à la suite des autres (21 - 2m) des changements de niveaux logiques entièrement définis (PW) en tant que signaux de démarrage d'entrée (ES11 - ES1n). Et un dispositif de détection (4) est configuré pour échantillonner un ou plusieurs signaux de sortie (A11 - Amp) aux sorties d'un ou de plusieurs systèmes de représentation (21 - 2m), qui sont différents du premier système de représentation (21), et pour les délivrer en sortie en tant que dit bit aléatoire (ZB). Le dispositif est configuré de telle manière qu'en cas de changements de niveaux successifs (PW) d'au moins un signal de démarrage d'entrée, différents bits aléatoires (ZB) sont détectés à l'aide du dispositif de détection (4).
PCT/EP2014/077152 2014-02-28 2014-12-10 Dispositif et procédé de génération de bits aléatoires WO2015128015A1 (fr)

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WO2007087559A2 (fr) * 2006-01-24 2007-08-02 Pufco, Inc. Sécurité de dispositif à base de générateur de signaux
EP2525489A1 (fr) * 2010-01-15 2012-11-21 Mitsubishi Electric Corporation Dispositif de génération de séquence binaire et procédé de génération de séquence binaire

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WO2007087559A2 (fr) * 2006-01-24 2007-08-02 Pufco, Inc. Sécurité de dispositif à base de générateur de signaux
EP2525489A1 (fr) * 2010-01-15 2012-11-21 Mitsubishi Electric Corporation Dispositif de génération de séquence binaire et procédé de génération de séquence binaire

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